cleanup

boards/uniboard2/designs/unb2_test/tb/python/tc_unb2_test_ddr.py

@@ -88,8 +88,6 @@ io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
 # Control defaults
 nof_mon = 5
 start_address = 0
-#start_address = tc.number
-#nof_words = 1000 #tc.number+10
 nof_words = tc.number
 
 for rep in range(tc.repeat):
@@ -112,7 +110,6 @@ for rep in range(tc.repeat):
         
         # Set DDR controller in write mode and start writing
         io_ddr[mb].write_set_address(data=start_address, vLevel=5)
-#        print 'nof_words=',nof_words
         io_ddr[mb].write_access_size(data=nof_words, vLevel=5)
         io_ddr[mb].write_mode_write(vLevel=5)
         io_ddr[mb].write_begin_access(vLevel=5)
@@ -125,12 +122,6 @@ for rep in range(tc.repeat):
             io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
             tx_seq_ddr[mb].read_cnt(vLevel=5)
         
-#    for mb in mb_list:
-#        # Wait until controller write access is done
-#        do_until_eq(io_ddr[mb].read_done, ms_retry=3000, val=1, s_timeout=36000)        
-
-#    tc.sleep(10.0)
-
     for mb in mb_list:
         # Wait until controller write access is done
         do_until_eq(io_ddr[mb].read_done, ms_retry=3000, val=1, s_timeout=36000)        
@@ -147,7 +138,6 @@ for rep in range(tc.repeat):
             io.wait_for_time(hw_time=0.01, sim_time=(1, 'us'))
             rx_seq_ddr[mb].read_cnt(vLevel=5)
         
-#    print "2"
     for mb in mb_list:
         # Wait until controller read access is done
         do_until_eq(io_ddr[mb].read_done, ms_retry=3000, val=1, s_timeout=36000)