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Commit 83318ded authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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using ddr_4g_2000 IP

parent 15d89753
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...@@ -12,6 +12,7 @@ hdl_lib_excludes = ip_arria10_tse_sgmii_gx ...@@ -12,6 +12,7 @@ hdl_lib_excludes = ip_arria10_tse_sgmii_gx
ip_arria10_transceiver_reset_controller_1 ip_arria10_transceiver_reset_controller_1
ip_arria10_transceiver_reset_controller_24 ip_arria10_transceiver_reset_controller_24
ip_arria10_ddr4_8g_2400 ip_arria10_ddr4_8g_2400
ip_arria10_ddr4_4g_1600
synth_files = synth_files =
unb2_test_ddr_MB_I_II.vhd unb2_test_ddr_MB_I_II.vhd
...@@ -20,7 +21,7 @@ test_bench_files = ...@@ -20,7 +21,7 @@ test_bench_files =
tb_unb2_test_ddr_MB_I_II.vhd tb_unb2_test_ddr_MB_I_II.vhd
modelsim_compile_ip_files = modelsim_compile_ip_files =
$RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_1600/copy_hex_files.tcl $RADIOHDL/libraries/technology/ip_arria10/ddr4_4g_2000/copy_hex_files.tcl
modelsim_copy_files = modelsim_copy_files =
../../src/hex hex ../../src/hex hex
......
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