add ddr4_8g_1600 to packages and wrappers

libraries/technology/ddr/hdllib.cfg

@@ -9,6 +9,7 @@ hdl_lib_uses_synth = ip_stratixiv_ddr3_uphy_4g_800_master
                      ip_arria10_ddr4_4g_2000
                      ip_arria10_ddr4_8g_2400
                      ip_arria10_e3sge3_ddr4_4g_1600
+                     ip_arria10_e3sge3_ddr4_8g_1600
                      ip_arria10_e3sge3_ddr4_4g_2000
                      ip_arria10_e3sge3_ddr4_8g_2400
                      common

libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd

@@ -35,6 +35,7 @@
 
 -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
 LIBRARY ip_arria10_e3sge3_ddr4_4g_1600_altera_emif_151;
+LIBRARY ip_arria10_e3sge3_ddr4_8g_1600_altera_emif_151;
 LIBRARY ip_arria10_e3sge3_ddr4_4g_2000_altera_emif_151;
 
 LIBRARY IEEE, technology_lib, common_lib;
@@ -204,4 +205,61 @@ BEGIN
     
   END GENERATE;
   
+  gen_ip_arria10_e3sge3_ddr4_8g_1600 : IF g_tech_ddr.name="DDR4" AND c_gigabytes=8 AND g_tech_ddr.mts=1600 GENERATE
+
+    phy_ou.cs_n(1) <= '1';
+    phy_ou.cke(1)  <= '0';
+    phy_ou.odt(1)  <= '0';
+
+    u_ip_arria10_e3sge3_ddr4_8g_1600 : ip_arria10_e3sge3_ddr4_8g_1600
+    PORT MAP (
+      amm_ready_0         => ctlr_miso.waitrequest_n,                                   --     ctrl_amm_avalon_slave_0.waitrequest_n
+      amm_read_0          => ctlr_mosi.rd,                                              --                            .read
+      amm_write_0         => ctlr_mosi.wr,                                              --                            .write
+      amm_address_0       => ctlr_mosi.address(c_ctlr_address_w-1 DOWNTO 0),            --                            .address
+      amm_readdata_0      => ctlr_miso.rddata(c_ctlr_data_w-1 DOWNTO 0),                --                            .readdata
+      amm_writedata_0     => ctlr_mosi.wrdata(c_ctlr_data_w-1 DOWNTO 0),                --                            .writedata
+      amm_burstcount_0    => ctlr_mosi.burstsize(g_tech_ddr.maxburstsize_w-1 DOWNTO 0), --                            .burstcount
+      amm_byteenable_0    => (OTHERS=>'1'),                                             --                            .byteenable
+      amm_readdatavalid_0 => ctlr_miso.rdval,                                           --                            .readdatavalid
+      emif_usr_clk        => i_ctlr_gen_clk,                                            --   emif_usr_clk_clock_source.clk
+      emif_usr_reset_n    => ctlr_gen_rst_n,                                            -- emif_usr_reset_reset_source.reset_n
+      global_reset_n      => ref_rst_n,                                                 --     global_reset_reset_sink.reset_n
+      mem_ck              => phy_ou.ck(g_tech_ddr.ck_w-1 DOWNTO 0),                     --             mem_conduit_end.mem_ck
+      mem_ck_n            => phy_ou.ck_n(g_tech_ddr.ck_w-1 DOWNTO 0),                   --                            .mem_ck_n
+      mem_a               => phy_ou.a(g_tech_ddr.a_w-1 DOWNTO 0),                       --                            .mem_a
+   sl(mem_act_n)          => phy_ou.act_n,                                              --                            .mem_act_n
+      mem_ba              => phy_ou.ba(g_tech_ddr.ba_w-1 DOWNTO 0),                     --                            .mem_ba
+      mem_bg              => phy_ou.bg(g_tech_ddr.bg_w-1 DOWNTO 0),                     --                            .mem_bg
+      mem_cke             => phy_ou.cke(g_tech_ddr.cke_w-1 DOWNTO 0),                   --                            .mem_cke
+      mem_cs_n            => phy_ou.cs_n(g_tech_ddr.cs_w-1 DOWNTO 0),                   --                            .mem_cs_n
+      mem_odt             => phy_ou.odt(g_tech_ddr.odt_w-1 DOWNTO 0),                   --                            .mem_odt
+   sl(mem_reset_n)        => phy_ou.reset_n,                                            --                            .mem_reset_n
+   sl(mem_par)            => phy_ou.par,                                                --                            .mem_par
+      mem_alert_n         => slv(phy_in.alert_n),                                       --                            .mem_alert_n
+      mem_dqs             => phy_io.dqs(g_tech_ddr.dqs_w-1 DOWNTO 0),                   --                            .mem_dqs
+      mem_dqs_n           => phy_io.dqs_n(g_tech_ddr.dqs_w-1 DOWNTO 0),                 --                            .mem_dqs_n
+      mem_dq              => phy_io.dq(g_tech_ddr.dq_w-1 DOWNTO 0),                     --                            .mem_dq
+      mem_dbi_n           => phy_io.dbi_n(g_tech_ddr.dbi_w-1 DOWNTO 0),                 --                            .mem_dbi_n
+      oct_rzqin           => phy_in.oct_rzqin,                                          --             oct_conduit_end.oct_rzqin
+      pll_ref_clk         => ref_clk,                                                   --      pll_ref_clk_clock_sink.clk
+      local_cal_success   => local_cal_success,                                         --          status_conduit_end.local_cal_success
+      local_cal_fail      => local_cal_fail                                             --                            .local_cal_fail
+    );
+    
+    -- Signals in DDR3 that are not available with DDR4:
+    --
+    --avl_burstbegin             => ctlr_mosi.burstbegin,                               --             .beginbursttransfer
+    --   beginbursttransfer is obselete for new Avalon designs, because the slave can count valid data itself to know when a new burst starts
+    --
+    --local_init_done            => ctlr_miso.done,                                     --       status.local_init_done
+    --   local_init_done = ctlr_init_done originally and mapped to ctlr_miso.done for the DDR3 IP. For the DDR4 IP the local_cal_success and
+    --   NOT local_cal_fail seem  to serve as local_init_done
+    
+    ctlr_miso.done     <= local_cal_success AND NOT local_cal_fail WHEN rising_edge(i_ctlr_gen_clk);
+    ctlr_miso.cal_ok   <= local_cal_success;
+    ctlr_miso.cal_fail <= local_cal_fail;
+    
+  END GENERATE;
+
 END str;

libraries/technology/ddr/tech_ddr_component_pkg.vhd

@@ -411,6 +411,44 @@ PACKAGE tech_ddr_component_pkg IS
   );
   END COMPONENT;
 
+  -- Dual rank version of ip_arria10_e3sge3_ddr4_4g_1600.vhd
+  COMPONENT ip_arria10_e3sge3_ddr4_8g_1600 IS
+  PORT (
+    amm_ready_0         : out   std_logic;                                         --     ctrl_amm_avalon_slave_0.waitrequest_n
+    amm_read_0          : in    std_logic                      := '0';             --                            .read
+    amm_write_0         : in    std_logic                      := '0';             --                            .write
+    amm_address_0       : in    std_logic_vector(26 downto 0)  := (others => '0'); --                            .address
+    amm_readdata_0      : out   std_logic_vector(575 downto 0);                    --                            .readdata
+    amm_writedata_0     : in    std_logic_vector(575 downto 0) := (others => '0'); --                            .writedata
+    amm_burstcount_0    : in    std_logic_vector(6 downto 0)   := (others => '0'); --                            .burstcount
+    amm_byteenable_0    : in    std_logic_vector(71 downto 0)  := (others => '0'); --                            .byteenable
+    amm_readdatavalid_0 : out   std_logic;                                         --                            .readdatavalid
+    emif_usr_clk        : out   std_logic;                                         --   emif_usr_clk_clock_source.clk
+    emif_usr_reset_n    : out   std_logic;                                         -- emif_usr_reset_reset_source.reset_n
+    global_reset_n      : in    std_logic                      := '0';             --     global_reset_reset_sink.reset_n
+    mem_ck              : out   std_logic_vector(1 downto 0);                      --             mem_conduit_end.mem_ck
+    mem_ck_n            : out   std_logic_vector(1 downto 0);                      --                            .mem_ck_n
+    mem_a               : out   std_logic_vector(16 downto 0);                     --                            .mem_a
+    mem_act_n           : out   std_logic_vector(0 downto 0);                      --                            .mem_act_n
+    mem_ba              : out   std_logic_vector(1 downto 0);                      --                            .mem_ba
+    mem_bg              : out   std_logic_vector(1 downto 0);                      --                            .mem_bg
+    mem_cke             : out   std_logic_vector(1 downto 0);                      --                            .mem_cke
+    mem_cs_n            : out   std_logic_vector(1 downto 0);                      --                            .mem_cs_n
+    mem_odt             : out   std_logic_vector(1 downto 0);                      --                            .mem_odt
+    mem_reset_n         : out   std_logic_vector(0 downto 0);                      --                            .mem_reset_n
+    mem_par             : out   std_logic_vector(0 downto 0);                      --                            .mem_par
+    mem_alert_n         : in    std_logic_vector(0 downto 0)   := (others => '0'); --                            .mem_alert_n
+    mem_dqs             : inout std_logic_vector(8 downto 0)   := (others => '0'); --                            .mem_dqs
+    mem_dqs_n           : inout std_logic_vector(8 downto 0)   := (others => '0'); --                            .mem_dqs_n
+    mem_dq              : inout std_logic_vector(71 downto 0)  := (others => '0'); --                            .mem_dq
+    mem_dbi_n           : inout std_logic_vector(8 downto 0)   := (others => '0'); --                            .mem_dbi_n
+    oct_rzqin           : in    std_logic                      := '0';             --             oct_conduit_end.oct_rzqin
+    pll_ref_clk         : in    std_logic                      := '0';             --      pll_ref_clk_clock_sink.clk
+    local_cal_success   : out   std_logic;                                         --          status_conduit_end.local_cal_success
+    local_cal_fail      : out   std_logic                                          --                            .local_cal_fail
+  );
+  END COMPONENT;
+
   -- Manually derived VHDL entity from VHDL file $RADIOHDL/libraries/technology/ip_arria10_e3sge3/ddr4_4g_2000/generated/sim/ip_arria10_e3sge3_ddr4_4g_2000.vhd
   COMPONENT ip_arria10_e3sge3_ddr4_4g_2000 IS
   PORT (

libraries/technology/ddr/tech_ddr_pkg.vhd

@@ -92,6 +92,7 @@ PACKAGE tech_ddr_pkg IS
   CONSTANT c_tech_ddr4_sim_1m                     : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 10,  9, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);  -- use a_row to set nof ctrl addr = 2**(cs_w + ba + a_row + a_col + bg_w - rsl_w)
   
   CONSTANT c_tech_ddr4_4g_1600m                   : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);
+  CONSTANT c_tech_ddr4_8g_1600m                   : t_c_tech_ddr := ("DDR4", 1600,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 2, 2,  2, 0,   2,   0,  8,  3,    8,  64,   7);
   CONSTANT c_tech_ddr4_4g_2000m                   : t_c_tech_ddr := ("DDR4", 2000,  TRUE, "DUAL  ", 17, 15, 10, 2, 72, 9,  0, 9,  2, 1, 1,  1, 0,   1,   0,  8,  3,    8,  64,   7);
 
   -- PHY in, inout and out signal records