From ed5fdb060af4a917a2152efa5b82f93b185785b4 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Thu, 2 Apr 2015 09:43:18 +0000
Subject: [PATCH] update
---
libraries/io/ddr3/hdllib.cfg | 23 +-
libraries/io/ddr3/src/tcl/compile_ip.tcl | 681 ++++++++++++++++++
libraries/io/ddr3/src/vhdl/ddr3.vhd | 490 +++++++++++++
libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd | 288 ++++++++
.../io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd | 417 +++++++++++
libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd | 387 ++++++++++
libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd | 371 ++++++++++
7 files changed, 2641 insertions(+), 16 deletions(-)
create mode 100644 libraries/io/ddr3/src/tcl/compile_ip.tcl
create mode 100644 libraries/io/ddr3/src/vhdl/ddr3.vhd
create mode 100644 libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
create mode 100644 libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
create mode 100644 libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
create mode 100644 libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
diff --git a/libraries/io/ddr3/hdllib.cfg b/libraries/io/ddr3/hdllib.cfg
index f19a821aa2..ebfa926bb2 100644
--- a/libraries/io/ddr3/hdllib.cfg
+++ b/libraries/io/ddr3/hdllib.cfg
@@ -8,8 +8,8 @@ hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR
build_dir_synth = $HDL_BUILD_DIR
-#modelsim_compile_ip_files =
-# $RADIOHDL/libraries/technology/ip_stratixiv/ddr3_uphy_4g_800_master/copy_hex_files.tcl
+modelsim_compile_ip_files =
+ $RADIOHDL/libraries/io/ddr3/src/tcl/compile_ip.tcl
synth_files =
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -17,12 +17,7 @@ synth_files =
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_seq.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_driver.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
- $UNB/Firmware/modules/ddr3/src/ip/megawizard/aphy_4g_1066.vhd
- $UNB/Firmware/modules/ddr3/src/ip/megawizard/aphy_4g_800.vhd
- $UNB/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_master.v
- $UNB/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_master_sim/uphy_4g_800_master.v
-
- $UNB/Firmware/modules/ddr3/src/vhdl/ddr3.vhd
+ src/vhdl/ddr3.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/ddr3_transpose.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3.vhd
$UNB/Firmware/modules/ddr3/src/vhdl/mms_ddr3_capture.vhd
@@ -30,14 +25,10 @@ synth_files =
test_bench_files =
#$UNB/Firmware/modules/ddr3/tb/vhdl/ddr3_mem_model.vhd
- $UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_800_mem_model.vhd
- $UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_800_full_mem_model.vhd
- $UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_1066_mem_model.vhd
- $UNB/Firmware/modules/ddr3/src/ip/megawizard/generated/testbench/aphy_4g_1066_full_mem_model.vhd
- $UNB/Firmware/modules/ddr3/tb/vhdl/tb_ddr3.vhd
- $UNB/Firmware/modules/ddr3/tb/vhdl/tb_mms_ddr3.vhd
- $UNB/Firmware/modules/ddr3/tb/vhdl/tb_seq_ddr3.vhd
- $UNB/Firmware/modules/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
+ tb/vhdl/tb_ddr3.vhd
+ tb/vhdl/tb_mms_ddr3.vhd
+ tb/vhdl/tb_seq_ddr3.vhd
+ tb/vhdl/tb_ddr3_transpose.vhd
modelsim_search_libraries =
# stratixiv only
diff --git a/libraries/io/ddr3/src/tcl/compile_ip.tcl b/libraries/io/ddr3/src/tcl/compile_ip.tcl
new file mode 100644
index 0000000000..75cd8f458c
--- /dev/null
+++ b/libraries/io/ddr3/src/tcl/compile_ip.tcl
@@ -0,0 +1,681 @@
+
+# (C) 2001-2014 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and
+# other software and tools, and its AMPP partner logic functions, and
+# any output files any of the foregoing (including device programming
+# or simulation files), and any associated documentation or information
+# are expressly subject to the terms and conditions of the Altera
+# Program License Subscription Agreement, Altera MegaCore Function
+# License Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by Altera
+# or its authorized distributors. Please refer to the applicable
+# agreement for further details.
+
+# Files created by the megawizard will be compiled intop the work library
+# and other libraries with this script.
+#
+# Be sure you run "unb_mgw ddr3" first.
+#
+# Currently it handles:
+# -UPHY_4G_800_MASTER
+# -UPHY_4G_800_SLAVE
+# -UPHY_4G_1066_MASTER
+# -UPHY_4G_1066_SLAVE
+# -Memory model
+
+######################
+# UPHY_4G_800_MASTER #
+######################
+
+set IP_DIR "$env(UNB)/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_master_sim/"
+
+# Create compilation libraries
+proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
+
+ensure_lib ./work/
+vmap work ./work/
+ensure_lib ./uphy_4g_800_master_a0/
+vmap uphy_4g_800_master_a0 ./uphy_4g_800_master_a0/
+ensure_lib ./uphy_4g_800_master_ng0/
+vmap uphy_4g_800_master_ng0 ./uphy_4g_800_master_ng0/
+ensure_lib ./uphy_4g_800_master_dll0/
+vmap uphy_4g_800_master_dll0 ./uphy_4g_800_master_dll0/
+ensure_lib ./uphy_4g_800_master_oct0/
+vmap uphy_4g_800_master_oct0 ./uphy_4g_800_master_oct0/
+ensure_lib ./uphy_4g_800_master_c0/
+vmap uphy_4g_800_master_c0 ./uphy_4g_800_master_c0/
+ensure_lib ./uphy_4g_800_master_s0/
+vmap uphy_4g_800_master_s0 ./uphy_4g_800_master_s0/
+ensure_lib ./uphy_4g_800_master_m0/
+vmap uphy_4g_800_master_m0 ./uphy_4g_800_master_m0/
+ensure_lib ./uphy_4g_800_master_p0/
+vmap uphy_4g_800_master_p0 ./uphy_4g_800_master_p0/
+ensure_lib ./uphy_4g_800_master_pll0/
+vmap uphy_4g_800_master_pll0 ./uphy_4g_800_master_pll0/
+ensure_lib ./uphy_4g_800_master_uphy_4g_800_master/
+vmap uphy_4g_800_master_uphy_4g_800_master ./uphy_4g_800_master_uphy_4g_800_master/
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+file copy -force $IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_sequencer_mem.hex ./
+file copy -force $IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_AC_ROM.hex ./
+file copy -force $IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_inst_ROM.hex ./
+
+# ----------------------------------------
+# Compile the design files in correct order
+vlog "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_mm_st_converter.v" -work uphy_4g_800_master_a0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_addr_cmd.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_addr_cmd_wrap.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_ddr2_odt_gen.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_ddr3_odt_gen.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_lpddr2_addr_cmd.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_odt_gen.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_rdwr_data_tmg.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_arbiter.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_burst_gen.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_cmd_gen.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_csr.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_buffer.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_buffer_manager.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_burst_tracking.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_dataid_manager.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_fifo.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_list.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_rdata_path.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_wdata_path.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_ecc_decoder.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_ecc_decoder_32_syn.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_ecc_decoder_64_syn.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_ecc_encoder.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_ecc_encoder_32_syn.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_ecc_encoder_64_syn.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_axi_st_converter.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_input_if.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_rank_timer.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_sideband.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_tbp.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_timing_param.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_controller.v" -work uphy_4g_800_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_ddrx_controller_st_top.v" -work uphy_4g_800_master_ng0
+vlog -sv +incdir+$IP_DIR/uphy_4g_800_master/ "$IP_DIR/uphy_4g_800_master/alt_mem_if_nextgen_ddr3_controller_core.sv" -work uphy_4g_800_master_ng0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altera_mem_if_dll_stratixiv.sv" -work uphy_4g_800_master_dll0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altera_mem_if_oct_stratixiv.sv" -work uphy_4g_800_master_oct0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_c0.v" -work uphy_4g_800_master_c0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_inst_ROM_reg.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_id_router.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_data_decoder.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_ram_csr.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_datamux.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_inst_ROM_no_ifdef_params.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_ac_ROM_reg.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_cmd_xbar_demux.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_addr_router_001.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_di_buffer.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_data_broadcast.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_bitcheck.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_ac_ROM_no_ifdef_params.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_cmd_xbar_demux_001.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/sequencer_phy_mgr.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_irq_mapper.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/altera_reset_controller.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/sequencer_scc_sv_wrapper.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_rsp_xbar_demux_003.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_addr_router.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/altera_avalon_sc_fifo.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_ddr3.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/sequencer_data_mgr.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_lfsr72.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altera_merlin_master_agent.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_ram.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/sequencer_scc_acv_wrapper.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/sequencer_scc_siii_phase_decode.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/sequencer_scc_sv_phase_decode.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altera_mem_if_sequencer_mem_no_ifdef_params.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_id_router_003.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_lfsr36.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/rw_manager_generic.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/sequencer_scc_siii_wrapper.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_cmd_xbar_mux_003.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/sequencer_scc_mgr.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_lfsr12.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altera_merlin_master_translator.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/sequencer_scc_reg_file.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/sequencer_reg_file.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_pattern_fifo.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_read_datapath.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/rw_manager_core.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altera_merlin_arbitrator.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/altera_reset_synchronizer.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_jumplogic.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altera_merlin_slave_translator.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_dm_decoder.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/sequencer_scc_acv_phase_decode.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_write_decoder.v" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/rw_manager_di_buffer_wrap.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altera_merlin_burst_uncompressor.sv" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_s0_rsp_xbar_mux.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.v" -work uphy_4g_800_master_s0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altera_merlin_slave_agent.sv" -work uphy_4g_800_master_s0
+vlog "$IP_DIR/uphy_4g_800_master/afi_mux_ddr3_ddrx.v" -work uphy_4g_800_master_m0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_clock_pair_generator.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_read_valid_selector.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_addr_cmd_datapath.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_reset.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_acv_ldc.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_addr_cmd_pads.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_addr_cmd_ldc_pads.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_addr_cmd_ldc_pad.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/addr_cmd_non_ldc_pad.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_memphy.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_reset_sync.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_new_io_pads.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_fr_cycle_shifter.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_read_datapath.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_write_datapath.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_hr_to_fr.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_simple_ddio_out.v" -work uphy_4g_800_master_p0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_sequencer_mux_bridge.sv" -work uphy_4g_800_master_p0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_phy_csr.sv" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_iss_probe.v" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_flop_mem.v" -work uphy_4g_800_master_p0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0.sv" -work uphy_4g_800_master_p0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_p0_altdqdqs.v" -work uphy_4g_800_master_p0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altdq_dqs2_ddio_3reg_stratixiv.sv" -work uphy_4g_800_master_p0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altdq_dqs2_abstract.sv" -work uphy_4g_800_master_p0
+vlog -sv "$IP_DIR/uphy_4g_800_master/altdq_dqs2_cal_delays.sv" -work uphy_4g_800_master_p0
+vlog -sv "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_pll0.sv" -work uphy_4g_800_master_pll0
+vlog "$IP_DIR/uphy_4g_800_master/uphy_4g_800_master_0002.v" -work uphy_4g_800_master_uphy_4g_800_master
+vlog "$IP_DIR/uphy_4g_800_master.v"
+
+########################################################################################
+# Get the memory model for the uphy_4g_* from the uphy_4g_master design example: #
+########################################################################################
+
+set IP_DIR "$env(UNB)/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_master_example_design/simulation/vhdl/submodules/"
+
+vlog -sv "$IP_DIR/alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv" - work work
+vlog -sv "$IP_DIR/alt_mem_if_common_ddr_mem_model_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en.sv" - work work
+
+######################
+# UPHY_4G_800_SLAVE #
+######################
+
+set IP_DIR "$env(UNB)/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_800_slave_sim/"
+
+ensure_lib ./uphy_4g_800_slave_a0/
+vmap uphy_4g_800_slave_a0 ./uphy_4g_800_slave_a0/
+ensure_lib ./uphy_4g_800_slave_ng0/
+vmap uphy_4g_800_slave_ng0 ./uphy_4g_800_slave_ng0/
+ensure_lib ./uphy_4g_800_slave_dll0/
+vmap uphy_4g_800_slave_dll0 ./uphy_4g_800_slave_dll0/
+ensure_lib ./uphy_4g_800_slave_oct0/
+vmap uphy_4g_800_slave_oct0 ./uphy_4g_800_slave_oct0/
+ensure_lib ./uphy_4g_800_slave_c0/
+vmap uphy_4g_800_slave_c0 ./uphy_4g_800_slave_c0/
+ensure_lib ./uphy_4g_800_slave_s0/
+vmap uphy_4g_800_slave_s0 ./uphy_4g_800_slave_s0/
+ensure_lib ./uphy_4g_800_slave_m0/
+vmap uphy_4g_800_slave_m0 ./uphy_4g_800_slave_m0/
+ensure_lib ./uphy_4g_800_slave_p0/
+vmap uphy_4g_800_slave_p0 ./uphy_4g_800_slave_p0/
+ensure_lib ./uphy_4g_800_slave_pll0/
+vmap uphy_4g_800_slave_pll0 ./uphy_4g_800_slave_pll0/
+ensure_lib ./uphy_4g_800_slave_uphy_4g_800_slave/
+vmap uphy_4g_800_slave_uphy_4g_800_slave ./uphy_4g_800_slave_uphy_4g_800_slave/
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+file copy -force $IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_sequencer_mem.hex ./
+file copy -force $IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_AC_ROM.hex ./
+file copy -force $IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_inst_ROM.hex ./
+
+# ----------------------------------------
+# Compile the design files in correct order
+vlog "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_mm_st_converter.v" -work uphy_4g_800_slave_a0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_addr_cmd.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_addr_cmd_wrap.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_ddr2_odt_gen.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_ddr3_odt_gen.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_lpddr2_addr_cmd.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_odt_gen.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_rdwr_data_tmg.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_arbiter.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_burst_gen.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_cmd_gen.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_csr.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_buffer.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_buffer_manager.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_burst_tracking.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_dataid_manager.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_fifo.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_list.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_rdata_path.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_wdata_path.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_ecc_decoder.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_ecc_decoder_32_syn.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_ecc_decoder_64_syn.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_ecc_encoder.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_ecc_encoder_32_syn.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_ecc_encoder_64_syn.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_axi_st_converter.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_input_if.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_rank_timer.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_sideband.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_tbp.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_timing_param.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_controller.v" -work uphy_4g_800_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_ddrx_controller_st_top.v" -work uphy_4g_800_slave_ng0
+vlog -sv +incdir+$IP_DIR/uphy_4g_800_slave/ "$IP_DIR/uphy_4g_800_slave/alt_mem_if_nextgen_ddr3_controller_core.sv" -work uphy_4g_800_slave_ng0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altera_mem_if_dll_stratixiv.sv" -work uphy_4g_800_slave_dll0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_c0.v" -work uphy_4g_800_slave_c0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_inst_ROM_reg.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_data_decoder.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_ram_csr.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_datamux.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_rsp_xbar_demux_003.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_inst_ROM_no_ifdef_params.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_ac_ROM_reg.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_addr_router_001.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_di_buffer.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_data_broadcast.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_bitcheck.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_ac_ROM_no_ifdef_params.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/sequencer_phy_mgr.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_addr_router.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/altera_reset_controller.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/sequencer_scc_sv_wrapper.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/altera_avalon_sc_fifo.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_ddr3.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/sequencer_data_mgr.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_lfsr72.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altera_merlin_master_agent.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_cmd_xbar_demux.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_ram.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_cmd_xbar_mux_003.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/sequencer_scc_acv_wrapper.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_cmd_xbar_demux_001.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/sequencer_scc_siii_phase_decode.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/sequencer_scc_sv_phase_decode.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altera_mem_if_sequencer_mem_no_ifdef_params.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_lfsr36.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/rw_manager_generic.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/sequencer_scc_siii_wrapper.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_irq_mapper.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/sequencer_scc_mgr.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_lfsr12.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altera_merlin_master_translator.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/sequencer_scc_reg_file.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/sequencer_reg_file.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_pattern_fifo.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_read_datapath.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/rw_manager_core.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altera_merlin_arbitrator.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/altera_reset_synchronizer.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_id_router_003.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_jumplogic.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altera_merlin_slave_translator.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_id_router.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_dm_decoder.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/sequencer_scc_acv_phase_decode.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_write_decoder.v" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/rw_manager_di_buffer_wrap.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altera_merlin_burst_uncompressor.sv" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_s0_rsp_xbar_mux.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.v" -work uphy_4g_800_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altera_merlin_slave_agent.sv" -work uphy_4g_800_slave_s0
+vlog "$IP_DIR/uphy_4g_800_slave/afi_mux_ddr3_ddrx.v" -work uphy_4g_800_slave_m0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_clock_pair_generator.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_read_valid_selector.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_addr_cmd_datapath.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_reset.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_acv_ldc.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_addr_cmd_pads.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_addr_cmd_ldc_pads.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_addr_cmd_ldc_pad.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/addr_cmd_non_ldc_pad.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_memphy.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_reset_sync.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_new_io_pads.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_fr_cycle_shifter.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_read_datapath.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_write_datapath.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_hr_to_fr.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_simple_ddio_out.v" -work uphy_4g_800_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_sequencer_mux_bridge.sv" -work uphy_4g_800_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_phy_csr.sv" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_iss_probe.v" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_flop_mem.v" -work uphy_4g_800_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0.sv" -work uphy_4g_800_slave_p0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_p0_altdqdqs.v" -work uphy_4g_800_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altdq_dqs2_ddio_3reg_stratixiv.sv" -work uphy_4g_800_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altdq_dqs2_abstract.sv" -work uphy_4g_800_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/altdq_dqs2_cal_delays.sv" -work uphy_4g_800_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_pll0.sv" -work uphy_4g_800_slave_pll0
+vlog "$IP_DIR/uphy_4g_800_slave/uphy_4g_800_slave_0002.v" -work uphy_4g_800_slave_uphy_4g_800_slave
+vlog "$IP_DIR/uphy_4g_800_slave.v"
+
+########################
+# UPHY_4G_1066_MASTER #
+########################
+
+set IP_DIR "$env(UNB)/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_1066_master_sim/"
+
+# Copy ROM/RAM files to simulation directory
+file copy -force $IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_sequencer_mem.hex ./
+file copy -force $IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_AC_ROM.hex ./
+file copy -force $IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_inst_ROM.hex ./
+
+ensure_lib ./uphy_4g_1066_master_a0/
+vmap uphy_4g_1066_master_a0 ./uphy_4g_1066_master_a0/
+ensure_lib ./uphy_4g_1066_master_ng0/
+vmap uphy_4g_1066_master_ng0 ./uphy_4g_1066_master_ng0/
+ensure_lib ./uphy_4g_1066_master_dll0/
+vmap uphy_4g_1066_master_dll0 ./uphy_4g_1066_master_dll0/
+ensure_lib ./uphy_4g_1066_master_oct0/
+vmap uphy_4g_1066_master_oct0 ./uphy_4g_1066_master_oct0/
+ensure_lib ./uphy_4g_1066_master_c0/
+vmap uphy_4g_1066_master_c0 ./uphy_4g_1066_master_c0/
+ensure_lib ./uphy_4g_1066_master_s0/
+vmap uphy_4g_1066_master_s0 ./uphy_4g_1066_master_s0/
+ensure_lib ./uphy_4g_1066_master_m0/
+vmap uphy_4g_1066_master_m0 ./uphy_4g_1066_master_m0/
+ensure_lib ./uphy_4g_1066_master_p0/
+vmap uphy_4g_1066_master_p0 ./uphy_4g_1066_master_p0/
+ensure_lib ./uphy_4g_1066_master_pll0/
+vmap uphy_4g_1066_master_pll0 ./uphy_4g_1066_master_pll0/
+ensure_lib ./uphy_4g_1066_master_uphy_4g_1066_master/
+vmap uphy_4g_1066_master_uphy_4g_1066_master ./uphy_4g_1066_master_uphy_4g_1066_master/
+
+vlog "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_mm_st_converter.v" -work uphy_4g_1066_master_a0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_addr_cmd.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_addr_cmd_wrap.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_ddr2_odt_gen.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_ddr3_odt_gen.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_lpddr2_addr_cmd.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_odt_gen.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_rdwr_data_tmg.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_arbiter.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_burst_gen.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_cmd_gen.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_csr.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_buffer.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_buffer_manager.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_burst_tracking.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_dataid_manager.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_fifo.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_list.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_rdata_path.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_wdata_path.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_ecc_decoder.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_ecc_decoder_32_syn.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_ecc_decoder_64_syn.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_ecc_encoder.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_ecc_encoder_32_syn.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_ecc_encoder_64_syn.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_axi_st_converter.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_input_if.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_rank_timer.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_sideband.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_tbp.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_timing_param.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_controller.v" -work uphy_4g_1066_master_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_ddrx_controller_st_top.v" -work uphy_4g_1066_master_ng0
+vlog -sv +incdir+$IP_DIR/uphy_4g_1066_master/ "$IP_DIR/uphy_4g_1066_master/alt_mem_if_nextgen_ddr3_controller_core.sv" -work uphy_4g_1066_master_ng0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altera_mem_if_dll_stratixiv.sv" -work uphy_4g_1066_master_dll0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altera_mem_if_oct_stratixiv.sv" -work uphy_4g_1066_master_oct0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_c0.v" -work uphy_4g_1066_master_c0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_rsp_xbar_mux.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_inst_ROM_reg.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_data_decoder.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_ram_csr.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_datamux.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_inst_ROM_no_ifdef_params.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_ac_ROM_reg.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_di_buffer.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_data_broadcast.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_bitcheck.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_ac_ROM_no_ifdef_params.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/sequencer_phy_mgr.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/altera_reset_controller.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/sequencer_scc_sv_wrapper.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/altera_avalon_sc_fifo.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_ddr3.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/sequencer_data_mgr.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_lfsr72.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altera_merlin_master_agent.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_cmd_xbar_demux_001.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_addr_router.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_ram.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_cmd_xbar_demux.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/sequencer_scc_acv_wrapper.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_irq_mapper.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/sequencer_scc_siii_phase_decode.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/sequencer_scc_sv_phase_decode.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altera_mem_if_sequencer_mem_no_ifdef_params.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_lfsr36.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_id_router.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/rw_manager_generic.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/sequencer_scc_siii_wrapper.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/sequencer_scc_mgr.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_lfsr12.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altera_merlin_master_translator.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/sequencer_scc_reg_file.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/sequencer_reg_file.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_pattern_fifo.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_read_datapath.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/rw_manager_core.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altera_merlin_arbitrator.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/altera_reset_synchronizer.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_cmd_xbar_mux_003.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_id_router_003.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_jumplogic.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altera_merlin_slave_translator.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_rsp_xbar_demux_003.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_dm_decoder.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/sequencer_scc_acv_phase_decode.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_write_decoder.v" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/rw_manager_di_buffer_wrap.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altera_merlin_burst_uncompressor.sv" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_s0_addr_router_001.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.v" -work uphy_4g_1066_master_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altera_merlin_slave_agent.sv" -work uphy_4g_1066_master_s0
+vlog "$IP_DIR/uphy_4g_1066_master/afi_mux_ddr3_ddrx.v" -work uphy_4g_1066_master_m0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_clock_pair_generator.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_read_valid_selector.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_addr_cmd_datapath.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_reset.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_acv_ldc.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_addr_cmd_pads.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_addr_cmd_ldc_pads.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_addr_cmd_ldc_pad.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/addr_cmd_non_ldc_pad.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_memphy.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_reset_sync.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_new_io_pads.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_fr_cycle_shifter.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_read_datapath.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_write_datapath.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_hr_to_fr.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_simple_ddio_out.v" -work uphy_4g_1066_master_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_sequencer_mux_bridge.sv" -work uphy_4g_1066_master_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_phy_csr.sv" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_iss_probe.v" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_flop_mem.v" -work uphy_4g_1066_master_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0.sv" -work uphy_4g_1066_master_p0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_p0_altdqdqs.v" -work uphy_4g_1066_master_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altdq_dqs2_ddio_3reg_stratixiv.sv" -work uphy_4g_1066_master_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altdq_dqs2_abstract.sv" -work uphy_4g_1066_master_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/altdq_dqs2_cal_delays.sv" -work uphy_4g_1066_master_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_pll0.sv" -work uphy_4g_1066_master_pll0
+vlog "$IP_DIR/uphy_4g_1066_master/uphy_4g_1066_master_0002.v" -work uphy_4g_1066_master_uphy_4g_1066_master
+vlog "$IP_DIR/uphy_4g_1066_master.v"
+
+########################
+# UPHY_4G_1066_SLAVE #
+########################
+
+set IP_DIR "$env(UNB)/Firmware/modules/ddr3/src/ip/megawizard/uphy_4g_1066_slave_sim/"
+
+# ----------------------------------------
+# Copy ROM/RAM files to simulation directory
+file copy -force $IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_sequencer_mem.hex ./
+file copy -force $IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_AC_ROM.hex ./
+file copy -force $IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_inst_ROM.hex ./
+
+ensure_lib ./uphy_4g_1066_slave_a0/
+vmap uphy_4g_1066_slave_a0 ./uphy_4g_1066_slave_a0/
+ensure_lib ./uphy_4g_1066_slave_ng0/
+vmap uphy_4g_1066_slave_ng0 ./uphy_4g_1066_slave_ng0/
+ensure_lib ./uphy_4g_1066_slave_dll0/
+vmap uphy_4g_1066_slave_dll0 ./uphy_4g_1066_slave_dll0/
+ensure_lib ./uphy_4g_1066_slave_c0/
+vmap uphy_4g_1066_slave_c0 ./uphy_4g_1066_slave_c0/
+ensure_lib ./uphy_4g_1066_slave_s0/
+vmap uphy_4g_1066_slave_s0 ./uphy_4g_1066_slave_s0/
+ensure_lib ./uphy_4g_1066_slave_m0/
+vmap uphy_4g_1066_slave_m0 ./uphy_4g_1066_slave_m0/
+ensure_lib ./uphy_4g_1066_slave_p0/
+vmap uphy_4g_1066_slave_p0 ./uphy_4g_1066_slave_p0/
+ensure_lib ./uphy_4g_1066_slave_pll0/
+vmap uphy_4g_1066_slave_pll0 ./uphy_4g_1066_slave_pll0/
+ensure_lib ./uphy_4g_1066_slave_uphy_4g_1066_slave/
+vmap uphy_4g_1066_slave_uphy_4g_1066_slave ./uphy_4g_1066_slave_uphy_4g_1066_slave/
+
+# ----------------------------------------
+# Compile the design files in correct order
+vlog "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_mm_st_converter.v" -work uphy_4g_1066_slave_a0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_addr_cmd.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_addr_cmd_wrap.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_ddr2_odt_gen.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_ddr3_odt_gen.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_lpddr2_addr_cmd.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_odt_gen.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_rdwr_data_tmg.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_arbiter.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_burst_gen.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_cmd_gen.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_csr.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_buffer.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_buffer_manager.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_burst_tracking.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_dataid_manager.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_fifo.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_list.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_rdata_path.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_wdata_path.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_ecc_decoder.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_ecc_decoder_32_syn.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_ecc_decoder_64_syn.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_ecc_encoder.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_ecc_encoder_32_syn.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_ecc_encoder_64_syn.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_axi_st_converter.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_input_if.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_rank_timer.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_sideband.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_tbp.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_timing_param.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_controller.v" -work uphy_4g_1066_slave_ng0
+vlog +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_ddrx_controller_st_top.v" -work uphy_4g_1066_slave_ng0
+vlog -sv +incdir+$IP_DIR/uphy_4g_1066_slave/ "$IP_DIR/uphy_4g_1066_slave/alt_mem_if_nextgen_ddr3_controller_core.sv" -work uphy_4g_1066_slave_ng0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altera_mem_if_dll_stratixiv.sv" -work uphy_4g_1066_slave_dll0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_c0.v" -work uphy_4g_1066_slave_c0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_inst_ROM_reg.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_data_decoder.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_ram_csr.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_datamux.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_cmd_xbar_demux.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_inst_ROM_no_ifdef_params.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_ac_ROM_reg.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_di_buffer.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_data_broadcast.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_bitcheck.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_ac_ROM_no_ifdef_params.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/sequencer_phy_mgr.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/altera_reset_controller.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/sequencer_scc_sv_wrapper.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/altera_avalon_sc_fifo.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_ddr3.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/sequencer_data_mgr.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_lfsr72.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altera_merlin_master_agent.sv" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_addr_router_001.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_ram.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_rsp_xbar_demux_003.sv" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_id_router.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_cmd_xbar_mux_003.sv" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/sequencer_scc_acv_wrapper.sv" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_addr_router.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/sequencer_scc_siii_phase_decode.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/sequencer_scc_sv_phase_decode.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altera_mem_if_sequencer_mem_no_ifdef_params.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_lfsr36.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/rw_manager_generic.sv" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_cmd_xbar_demux_001.sv" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/sequencer_scc_siii_wrapper.sv" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/sequencer_scc_mgr.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_lfsr12.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altera_merlin_master_translator.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/sequencer_scc_reg_file.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/sequencer_reg_file.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_pattern_fifo.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_read_datapath.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/rw_manager_core.sv" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altera_merlin_arbitrator.sv" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_irq_mapper.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/altera_reset_synchronizer.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_id_router_003.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_jumplogic.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altera_merlin_slave_translator.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_dm_decoder.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_s0_rsp_xbar_mux.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/sequencer_scc_acv_phase_decode.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_write_decoder.v" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/rw_manager_di_buffer_wrap.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altera_merlin_burst_uncompressor.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst.v" -work uphy_4g_1066_slave_s0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altera_merlin_slave_agent.sv" -work uphy_4g_1066_slave_s0
+vlog "$IP_DIR/uphy_4g_1066_slave/afi_mux_ddr3_ddrx.v" -work uphy_4g_1066_slave_m0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_clock_pair_generator.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_read_valid_selector.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_addr_cmd_datapath.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_reset.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_acv_ldc.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_addr_cmd_pads.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_addr_cmd_ldc_pads.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_addr_cmd_ldc_pad.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/addr_cmd_non_ldc_pad.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_memphy.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_reset_sync.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_new_io_pads.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_fr_cycle_shifter.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_read_datapath.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_write_datapath.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_hr_to_fr.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_simple_ddio_out.v" -work uphy_4g_1066_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_sequencer_mux_bridge.sv" -work uphy_4g_1066_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_phy_csr.sv" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_iss_probe.v" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_flop_mem.v" -work uphy_4g_1066_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0.sv" -work uphy_4g_1066_slave_p0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_p0_altdqdqs.v" -work uphy_4g_1066_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altdq_dqs2_ddio_3reg_stratixiv.sv" -work uphy_4g_1066_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altdq_dqs2_abstract.sv" -work uphy_4g_1066_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/altdq_dqs2_cal_delays.sv" -work uphy_4g_1066_slave_p0
+vlog -sv "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_pll0.sv" -work uphy_4g_1066_slave_pll0
+vlog "$IP_DIR/uphy_4g_1066_slave/uphy_4g_1066_slave_0002.v" -work uphy_4g_1066_slave_uphy_4g_1066_slave
+vlog "$IP_DIR/uphy_4g_1066_slave.v"
+
diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
new file mode 100644
index 0000000000..249cc7e367
--- /dev/null
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -0,0 +1,490 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.NUMERIC_STD.ALL;
+USE common_lib.common_pkg.ALL;
+USE work.ddr3_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+ENTITY ddr3 IS
+ GENERIC(
+ g_phy : NATURAL := 1; -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
+ g_ddr : t_c_ddr3_phy;
+ g_mts : NATURAL := 800; -- Megatransfers per second
+ g_wr_data_w : NATURAL := c_ddr3_ctlr_data_w;
+ g_wr_use_ctrl : BOOLEAN := FALSE; -- TRUE to allow filling the WR FIFO (by disabling flush) after an EOP
+ g_wr_fifo_depth : NATURAL := 128; -- >=16 AND >c_ddr3_ctlr_maxburstsize , defined at read side of write FIFO.
+ g_rd_fifo_depth : NATURAL := 256; -- >=16 AND >c_ddr3_ctlr_maxburstsize > c_ddr3_ctrl_nof_latent_reads, defined at write side of read FIFO.
+ g_rd_data_w : NATURAL := c_ddr3_ctlr_data_w;
+ g_flush_wr_fifo : BOOLEAN := FALSE; -- TRUE instantiates a dp_flush + controller to flush the write fifo when the driver is not ready to write
+ g_flush_ext_ena : BOOLEAN := FALSE; -- TRUE enables the external flush_ena signal and discards flushing when driver is not ready. FALSE enables flushing when driver is not ready
+ g_flush_sop : BOOLEAN := FALSE; -- When FALSE, flushing is stopped by valid data. When TRUE flushing is stopped by SOP
+ g_flush_sop_sync : BOOLEAN := FALSE; -- When TRUE, flushing is stopped by receiving SOP and SYNC
+ g_flush_sop_channel : BOOLEAN := FALSE; -- WHEN TRUE, flushing is stopped by receiving SOP and specified channel.
+ g_flush_sop_start_channel : NATURAL := 0;
+ g_flush_nof_channels : NATURAL := 0
+ );
+ PORT (
+ ctlr_ref_clk : IN STD_LOGIC;
+ ctlr_rst : IN STD_LOGIC; -- asynchronous reset input to controller
+
+ ctlr_gen_clk : OUT STD_LOGIC; -- Controller generated clock
+ ctlr_gen_rst : OUT STD_LOGIC;
+ ctlr_gen_clk_2x : OUT STD_LOGIC; -- Controller generated double frequency clock
+ ctlr_gen_rst_2x : OUT STD_LOGIC; -- ctlr_gen_rst synchronized to ctlr_gen_clk_2x
+
+ ctlr_init_done : OUT STD_LOGIC;
+ ctlr_rdy : OUT STD_LOGIC;
+
+ dvr_start_addr : IN t_ddr3_addr;
+ dvr_end_addr : IN t_ddr3_addr;
+
+ dvr_en : IN STD_LOGIC;
+ dvr_wr_not_rd : IN STD_LOGIC;
+ dvr_done : OUT STD_LOGIC;
+
+ wr_clk : IN STD_LOGIC;
+ wr_rst : IN STD_LOGIC;
+
+ flush_ena : IN STD_LOGIC; -- When toggled '1' the write-fifo flusher is enabled and stops flushing when configured trigger condition is met.
+
+ wr_sosi : IN t_dp_sosi;
+ wr_siso : OUT t_dp_siso;
+
+ rd_sosi : OUT t_dp_sosi;
+ rd_siso : IN t_dp_siso;
+
+ rd_clk : IN STD_LOGIC;
+ rd_rst : IN STD_LOGIC;
+
+ rd_fifo_usedw : OUT STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (c_ddr3_ctlr_data_w/g_rd_data_w) )-1 DOWNTO 0);
+
+ ser_term_ctrl_out : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
+ par_term_ctrl_out : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
+
+ ser_term_ctrl_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
+ par_term_ctrl_in : IN STD_LOGIC_VECTOR(13 DOWNTO 0) := (OTHERS => '0');
+
+ phy_in : IN t_ddr3_phy_in;
+ phy_io : INOUT t_ddr3_phy_io;
+ phy_ou : OUT t_ddr3_phy_ou
+ );
+END ddr3;
+
+
+ARCHITECTURE str OF ddr3 IS
+
+ CONSTANT c_wr_fifo_depth : NATURAL := g_wr_fifo_depth * (c_ddr3_ctlr_data_w/g_wr_data_w); -- Multiply fifo depth by the fifo's rd/wr width ratio to get write side depth
+
+ CONSTANT c_latency : NATURAL := 1;
+
+ SIGNAL ctlr_burst : STD_LOGIC;
+ SIGNAL ctlr_burst_size : STD_LOGIC_VECTOR(c_ddr3_ctlr_maxburstsize_w-1 DOWNTO 0);
+ SIGNAL ctlr_address : STD_LOGIC_VECTOR(ceil_log2(g_ddr.cs_w-1) + g_ddr.ba_w + g_ddr.a_w + g_ddr.a_col_w - c_ddr3_ctlr_rsl_w-1 DOWNTO 0); -- ceil_log2(..-1) because the chip select lines are converted to a logical address
+ SIGNAL ctlr_rd_req : STD_LOGIC;
+ SIGNAL ctlr_wr_req : STD_LOGIC;
+
+ SIGNAL ctlr_rst_n : STD_LOGIC;
+ SIGNAL ctlr_gen_rst_n : STD_LOGIC;
+
+ SIGNAL i_ctlr_gen_clk : STD_LOGIC;
+ SIGNAL i_ctlr_gen_rst : STD_LOGIC;
+ SIGNAL i_ctlr_gen_clk_2x : STD_LOGIC;
+ SIGNAL i_ctlr_init_done : STD_LOGIC;
+ SIGNAL i_ctlr_rdy : STD_LOGIC;
+ SIGNAL i_dvr_done : STD_LOGIC;
+
+ SIGNAL dvr_cur_addr : t_ddr3_addr;
+ SIGNAL dvr_flush : STD_LOGIC := '0';
+
+ SIGNAL ctlr_wr_siso : t_dp_siso := c_dp_siso_rdy; -- default xon='1'
+ SIGNAL ctlr_wr_sosi : t_dp_sosi;
+
+ SIGNAL flush_wr_siso : t_dp_siso;
+ SIGNAL flush_wr_sosi : t_dp_sosi;
+
+ SIGNAL ctlr_rd_siso : t_dp_siso;
+ SIGNAL ctlr_rd_sosi : t_dp_sosi;
+
+ SIGNAL wr_fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(g_wr_fifo_depth)-1 DOWNTO 0); -- read side depth of the write FIFO
+
+BEGIN
+
+ dvr_done <= i_dvr_done;
+
+ ctlr_rst_n <= NOT(ctlr_rst);
+ i_ctlr_gen_rst <= NOT(ctlr_gen_rst_n);
+
+ ctlr_gen_clk <= i_ctlr_gen_clk;
+ ctlr_gen_rst <= i_ctlr_gen_rst;
+ ctlr_gen_clk_2x <= i_ctlr_gen_clk_2x;
+ ctlr_rdy <= i_ctlr_rdy;
+ ctlr_init_done <= i_ctlr_init_done;
+
+ u_wr_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
+ GENERIC MAP (
+ g_wr_data_w => g_wr_data_w,
+ g_rd_data_w => c_ddr3_ctlr_data_w,
+ g_use_ctrl => g_wr_use_ctrl,
+ g_wr_fifo_size => c_wr_fifo_depth,
+ g_wr_fifo_af_margin => 4 + c_latency, --default (4) + c_latency to compensate for latency introduced by registering wr_siso.ready
+ g_rd_fifo_rl => 0
+ )
+ PORT MAP (
+ wr_rst => wr_rst,
+ wr_clk => wr_clk,
+ rd_rst => i_ctlr_gen_rst,
+ rd_clk => i_ctlr_gen_clk,
+
+ snk_out => wr_siso,
+ snk_in => wr_sosi,
+
+ wr_usedw => OPEN,
+ rd_usedw => wr_fifo_usedw,
+ rd_emp => OPEN,
+
+ src_in => flush_wr_siso,
+ src_out => flush_wr_sosi
+ );
+
+ u_dp_flush : ENTITY dp_lib.dp_flush -- Always instantiate the flusher as it also contains a RL adapter
+ GENERIC MAP (
+ g_ready_latency => 0,
+ g_framed_xon => g_wr_use_ctrl, -- stop flushing when dvr_flush is low and a sop has arrived
+ g_framed_xoff => FALSE -- immediately start flushing when dvr_flush goes high
+ )
+ PORT MAP (
+ rst => i_ctlr_gen_rst,
+ clk => i_ctlr_gen_clk,
+
+ snk_in => flush_wr_sosi,
+ snk_out => flush_wr_siso,
+
+ src_out => ctlr_wr_sosi,
+ src_in => ctlr_wr_siso, -- fixed streaming xon='1'
+
+ flush_en => dvr_flush -- memory mapped xon/xoff control
+ );
+
+ gen_flush : IF g_flush_wr_fifo = TRUE GENERATE
+ u_flush_ctrl : ENTITY work.ddr3_flush_ctrl
+ GENERIC MAP (
+ g_ext_ena => g_flush_ext_ena,
+ g_sop => g_flush_sop,
+ g_sop_sync => g_flush_sop_sync,
+ g_sop_channel => g_flush_sop_channel,
+ g_sop_start_channel => g_flush_sop_start_channel,
+ g_nof_channels => g_flush_nof_channels
+ )
+ PORT MAP (
+ rst => wr_rst,
+ clk => wr_clk,
+
+ dvr_en => dvr_en,
+ dvr_wr_not_rd => dvr_wr_not_rd,
+ dvr_done => i_dvr_done,
+
+ wr_sosi => wr_sosi,
+ flush_ena => flush_ena,
+
+ dvr_flush => dvr_flush
+ );
+ END GENERATE;
+
+ u_rd_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
+ GENERIC MAP (
+ g_wr_data_w => c_ddr3_ctlr_data_w,
+ g_rd_data_w => g_rd_data_w,
+ g_use_ctrl => FALSE,
+ g_wr_fifo_size => g_rd_fifo_depth,
+ g_wr_fifo_af_margin => c_ddr3_ctrl_nof_latent_reads, -- >=4 (required by dp_fifo)
+ g_rd_fifo_rl => 1
+ )
+ PORT MAP (
+ wr_rst => i_ctlr_gen_rst,
+ wr_clk => i_ctlr_gen_clk,
+ rd_rst => rd_rst,
+ rd_clk => rd_clk,
+
+ snk_out => ctlr_rd_siso,
+ snk_in => ctlr_rd_sosi,
+
+ wr_usedw => OPEN,
+ rd_usedw => rd_fifo_usedw,
+ rd_emp => OPEN,
+
+ src_in => rd_siso,
+ src_out => rd_sosi
+ );
+
+ u_ddr3_driver : ENTITY work.ddr3_driver
+ GENERIC MAP (
+ g_wr_fifo_depth => g_wr_fifo_depth,
+ g_ddr => g_ddr
+ )
+ PORT MAP (
+ rst => i_ctlr_gen_rst,
+ clk => i_ctlr_gen_clk,
+
+ ctlr_rdy => i_ctlr_rdy,
+ ctlr_init_done => i_ctlr_init_done,
+ ctlr_wr_req => ctlr_wr_req,
+ ctlr_rd_req => ctlr_rd_req,
+ ctlr_burst => ctlr_burst,
+ ctlr_burst_size => ctlr_burst_size,
+
+ wr_val => ctlr_wr_sosi.valid,
+ wr_rdy => ctlr_wr_siso.ready,
+ rd_rdy => ctlr_rd_siso.ready,
+
+ cur_addr => dvr_cur_addr,
+ start_addr => dvr_start_addr,
+ end_addr => dvr_end_addr,
+
+ dvr_en => dvr_en,
+ dvr_wr_not_rd => dvr_wr_not_rd,
+ dvr_done => i_dvr_done,
+
+ wr_fifo_usedw => wr_fifo_usedw
+ );
+
+ ctlr_address <= dvr_cur_addr.chip & dvr_cur_addr.bank & dvr_cur_addr.row(g_ddr.a_w-1 DOWNTO 0) & dvr_cur_addr.column(g_ddr.a_col_w -1 DOWNTO c_ddr3_ctlr_rsl_w);
+
+ gen_uphy_4g_800_master : IF g_mts = 800 AND g_phy = 1 GENERATE
+ u_uphy_4g_800_master : COMPONENT uphy_4g_800_master
+ PORT MAP (
+ pll_ref_clk => ctlr_ref_clk,
+ global_reset_n => ctlr_rst_n,
+ soft_reset_n => '1',
+ afi_clk => i_ctlr_gen_clk,
+ afi_half_clk => OPEN,
+ afi_reset_n => ctlr_gen_rst_n,
+ mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0),
+ mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0),
+ mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0),
+ mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0),
+ mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0),
+ mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0),
+ mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0),
+ mem_ras_n => phy_ou.ras_n,
+ mem_cas_n => phy_ou.cas_n,
+ mem_we_n => phy_ou.we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0),
+ mem_dqs => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0),
+ mem_dqs_n => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0),
+ mem_odt => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0),
+ avl_ready => i_ctlr_rdy,
+ avl_burstbegin => ctlr_burst,
+ avl_addr => ctlr_address,
+ avl_rdata_valid => ctlr_rd_sosi.valid,
+ avl_rdata => ctlr_rd_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),
+ avl_wdata => ctlr_wr_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),
+ avl_be => (OTHERS => '1'),
+ avl_read_req => ctlr_rd_req,
+ avl_write_req => ctlr_wr_req,
+ avl_size => ctlr_burst_size,
+ local_init_done => i_ctlr_init_done,
+ local_cal_success => OPEN,
+ local_cal_fail => OPEN,
+ oct_rdn => phy_in.oct_rdn,
+ oct_rup => phy_in.oct_rup,
+ seriesterminationcontrol => ser_term_ctrl_out,
+ parallelterminationcontrol => par_term_ctrl_out,
+ pll_mem_clk => i_ctlr_gen_clk_2x,
+ pll_write_clk => OPEN,
+ pll_write_clk_pre_phy_clk => OPEN,
+ pll_addr_cmd_clk => OPEN,
+ pll_locked => OPEN,
+ pll_avl_clk => OPEN,
+ pll_config_clk => OPEN,
+ dll_delayctrl => OPEN
+ );
+ END GENERATE;
+
+ gen_uphy_4g_800_slave : IF g_mts = 800 AND g_phy = 2 GENERATE
+ u_uphy_4g_800_slave : COMPONENT uphy_4g_800_slave
+ PORT MAP (
+ pll_ref_clk => ctlr_ref_clk,
+ global_reset_n => ctlr_rst_n,
+ soft_reset_n => '1',
+ afi_clk => i_ctlr_gen_clk,
+ afi_half_clk => OPEN,
+ afi_reset_n => ctlr_gen_rst_n,
+ mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0),
+ mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0),
+ mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0),
+ mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0),
+ mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0),
+ mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0),
+ mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0),
+ mem_ras_n => phy_ou.ras_n,
+ mem_cas_n => phy_ou.cas_n,
+ mem_we_n => phy_ou.we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0),
+ mem_dqs => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0),
+ mem_dqs_n => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0),
+ mem_odt => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0),
+ avl_ready => i_ctlr_rdy,
+ avl_burstbegin => ctlr_burst,
+ avl_addr => ctlr_address,
+ avl_rdata_valid => ctlr_rd_sosi.valid,
+ avl_rdata => ctlr_rd_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),
+ avl_wdata => ctlr_wr_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),
+ avl_be => (OTHERS => '1'),
+ avl_read_req => ctlr_rd_req,
+ avl_write_req => ctlr_wr_req,
+ avl_size => ctlr_burst_size,
+ local_init_done => i_ctlr_init_done,
+ local_cal_success => OPEN,
+ local_cal_fail => OPEN,
+ seriesterminationcontrol => ser_term_ctrl_in,
+ parallelterminationcontrol => par_term_ctrl_in,
+ pll_mem_clk => i_ctlr_gen_clk_2x,
+ pll_write_clk => OPEN,
+ pll_write_clk_pre_phy_clk => OPEN,
+ pll_addr_cmd_clk => OPEN,
+ pll_locked => OPEN,
+ pll_avl_clk => OPEN,
+ pll_config_clk => OPEN,
+ dll_delayctrl => OPEN
+ );
+ END GENERATE;
+
+ gen_uphy_4g_1066_master : IF g_mts = 1066 AND g_phy = 1 GENERATE
+ u_uphy_4g_1066_master : COMPONENT uphy_4g_1066_master
+ PORT MAP (
+ pll_ref_clk => ctlr_ref_clk,
+ global_reset_n => ctlr_rst_n,
+ soft_reset_n => '1',
+ afi_clk => i_ctlr_gen_clk,
+ afi_half_clk => OPEN,
+ afi_reset_n => ctlr_gen_rst_n,
+ mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0),
+ mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0),
+ mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0),
+ mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0),
+ mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0),
+ mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0),
+ mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0),
+ mem_ras_n => phy_ou.ras_n,
+ mem_cas_n => phy_ou.cas_n,
+ mem_we_n => phy_ou.we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0),
+ mem_dqs => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0),
+ mem_dqs_n => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0),
+ mem_odt => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0),
+ avl_ready => i_ctlr_rdy,
+ avl_burstbegin => ctlr_burst,
+ avl_addr => ctlr_address,
+ avl_rdata_valid => ctlr_rd_sosi.valid,
+ avl_rdata => ctlr_rd_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),
+ avl_wdata => ctlr_wr_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),
+ avl_be => (OTHERS => '1'),
+ avl_read_req => ctlr_rd_req,
+ avl_write_req => ctlr_wr_req,
+ avl_size => ctlr_burst_size,
+ local_init_done => i_ctlr_init_done,
+ local_cal_success => OPEN,
+ local_cal_fail => OPEN,
+ oct_rdn => phy_in.oct_rdn,
+ oct_rup => phy_in.oct_rup,
+ seriesterminationcontrol => ser_term_ctrl_out,
+ parallelterminationcontrol => par_term_ctrl_out,
+ pll_mem_clk => i_ctlr_gen_clk_2x,
+ pll_write_clk => OPEN,
+ pll_write_clk_pre_phy_clk => OPEN,
+ pll_addr_cmd_clk => OPEN,
+ pll_locked => OPEN,
+ pll_avl_clk => OPEN,
+ pll_config_clk => OPEN,
+ dll_delayctrl => OPEN
+ );
+ END GENERATE;
+
+ gen_uphy_4g_1066_slave : IF g_mts = 1066 AND g_phy = 2 GENERATE
+ u_uphy_4g_1066_slave : COMPONENT uphy_4g_1066_slave
+ PORT MAP (
+ pll_ref_clk => ctlr_ref_clk,
+ global_reset_n => ctlr_rst_n,
+ soft_reset_n => '1',
+ afi_clk => i_ctlr_gen_clk,
+ afi_half_clk => OPEN,
+ afi_reset_n => ctlr_gen_rst_n,
+ mem_a => phy_ou.a(g_ddr.a_w-1 DOWNTO 0),
+ mem_ba => phy_ou.ba(g_ddr.ba_w-1 DOWNTO 0),
+ mem_ck => phy_io.clk(g_ddr.clk_w-1 DOWNTO 0),
+ mem_ck_n => phy_io.clk_n(g_ddr.clk_w-1 DOWNTO 0),
+ mem_cke => phy_ou.cke(g_ddr.clk_w-1 DOWNTO 0),
+ mem_cs_n => phy_ou.cs_n(g_ddr.cs_w-1 DOWNTO 0),
+ mem_dm => phy_ou.dm(g_ddr.dm_w-1 DOWNTO 0),
+ mem_ras_n => phy_ou.ras_n,
+ mem_cas_n => phy_ou.cas_n,
+ mem_we_n => phy_ou.we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq(g_ddr.dq_w-1 DOWNTO 0),
+ mem_dqs => phy_io.dqs(g_ddr.dqs_w-1 DOWNTO 0),
+ mem_dqs_n => phy_io.dqs_n(g_ddr.dqs_w-1 DOWNTO 0),
+ mem_odt => phy_ou.odt(g_ddr.cs_w-1 DOWNTO 0),
+ avl_ready => i_ctlr_rdy,
+ avl_burstbegin => ctlr_burst,
+ avl_addr => ctlr_address,
+ avl_rdata_valid => ctlr_rd_sosi.valid,
+ avl_rdata => ctlr_rd_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),
+ avl_wdata => ctlr_wr_sosi.data(c_ddr3_ctlr_data_w-1 DOWNTO 0),
+ avl_be => (OTHERS => '1'),
+ avl_read_req => ctlr_rd_req,
+ avl_write_req => ctlr_wr_req,
+ avl_size => ctlr_burst_size,
+ local_init_done => i_ctlr_init_done,
+ local_cal_success => OPEN,
+ local_cal_fail => OPEN,
+ seriesterminationcontrol => ser_term_ctrl_in,
+ parallelterminationcontrol => par_term_ctrl_in,
+ pll_mem_clk => i_ctlr_gen_clk_2x,
+ pll_write_clk => OPEN,
+ pll_write_clk_pre_phy_clk => OPEN,
+ pll_addr_cmd_clk => OPEN,
+ pll_locked => OPEN,
+ pll_avl_clk => OPEN,
+ pll_config_clk => OPEN,
+ dll_delayctrl => OPEN
+ );
+ END GENERATE;
+
+ u_async_ctlr_gen_rst_2x: ENTITY common_lib.common_async
+ GENERIC MAP(
+ g_rst_level => '0'
+ )
+ PORT MAP(
+ rst => ctlr_rst,
+ clk => i_ctlr_gen_clk_2x,
+ din => i_ctlr_gen_rst,
+ dout => ctlr_gen_rst_2x
+ );
+
+END str;
+
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
new file mode 100644
index 0000000000..7c14461517
--- /dev/null
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
@@ -0,0 +1,288 @@
+--------------------------------------------------------------------------------
+--
+-- Copyright (C) 2011
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+--------------------------------------------------------------------------------
+
+-- This testbench tests the different type of DDR controllers:
+--
+-- - aphy_4g_800
+-- - aphy_4g_1066
+-- - uphy_4g_800_master
+-- - uphy_4g_1066_master
+-- - uphy_4g_800_slave
+-- - uphy_4g_1066_slave
+--
+-- The DUT can be selected, using the c_phy and c_mts constants.
+--
+-- Testbench is selftesting:
+--
+-- > run -all
+--
+-- Known issues: The memory model used for the aphy_4g_1066 simulation
+-- gives an error at the end of the write cyclus.
+--
+
+LIBRARY IEEE, common_lib, dp_lib, diagnostics_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE work.ddr3_pkg.ALL;
+
+ENTITY tb_ddr3 IS
+END ENTITY tb_ddr3;
+
+ARCHITECTURE str of tb_ddr3 IS
+
+ CONSTANT c_phy : NATURAL := 1; -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
+ CONSTANT c_mts : NATURAL := 800; -- Available options: 800 and 1066
+
+ CONSTANT c_ctlr_ref_clk_per : TIME := 5 ns; --200 MHz
+ CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
+
+ CONSTANT c_data_w : NATURAL := 256; --32;
+
+ SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
+ SIGNAL ctlr_rst : STD_LOGIC := '1';
+ SIGNAL tb_end : STD_LOGIC := '0';
+ SIGNAL ctlr_gen_clk : STD_LOGIC;
+ SIGNAL ctlr_gen_rst : STD_LOGIC;
+
+ SIGNAL ctlr_rdy : STD_LOGIC;
+ SIGNAL ctlr_init_done : STD_LOGIC;
+
+ SIGNAL dvr_start_addr : t_ddr3_addr;
+ SIGNAL dvr_end_addr : t_ddr3_addr;
+
+ SIGNAL dvr_en : STD_LOGIC;
+ SIGNAL dvr_wr_not_rd : STD_LOGIC;
+ SIGNAL dvr_done : STD_LOGIC;
+
+ SIGNAL wr_siso : t_dp_siso;
+ SIGNAL wr_sosi : t_dp_sosi;
+
+ SIGNAL wr_siso_pre_fifo : t_dp_siso;
+ SIGNAL wr_sosi_pre_fifo : t_dp_sosi;
+
+ SIGNAL rd_siso : t_dp_siso;
+ SIGNAL rd_sosi : t_dp_sosi;
+
+ SIGNAL src_diag_en : STD_LOGIC;
+ SIGNAL src_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+ SIGNAL snk_diag_en : STD_LOGIC;
+ SIGNAL snk_diag_res : STD_LOGIC;
+ SIGNAL snk_diag_res_val : STD_LOGIC;
+ SIGNAL snk_val_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0);
+
+ SIGNAL phy_in : t_ddr3_phy_in;
+ SIGNAL phy_io : t_ddr3_phy_io;
+ SIGNAL phy_ou : t_ddr3_phy_ou;
+
+ SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+ SIGNAL flush_ena : STD_LOGIC;
+
+BEGIN
+
+ ctlr_ref_clk <= NOT(ctlr_ref_clk) OR tb_end AFTER c_ctlr_ref_clk_per/2;
+ ctlr_rst <= '0' AFTER 100 ns;
+
+ dvr_start_addr <= c_ddr3_addr_lo;
+ dvr_end_addr <= c_ddr3_addr_hi_sim;
+
+ flush_ena <= '0';
+
+ p_stimuli : PROCESS
+ BEGIN
+ tb_end <= '0';
+ dvr_en <= '0';
+ src_diag_en <= '0';
+ dvr_wr_not_rd <= '0';
+ snk_diag_en <= '0';
+
+ WAIT UNTIL ctlr_init_done = '1';
+ FOR i IN 0 TO 1 LOOP
+ WAIT UNTIL rising_edge(ctlr_gen_clk); -- Give the driver FSM a cycle to go into idle mode
+ END LOOP;
+
+ -- START WRITE
+ src_diag_en <= '1';
+ dvr_wr_not_rd <= '1';
+ dvr_en <= '1';
+
+ WAIT UNTIL rising_edge(ctlr_gen_clk);
+
+ dvr_en <= '0';
+
+ -- WRITE DONE
+ WAIT UNTIL dvr_done = '1';
+
+ src_diag_en <= '0';
+
+ -- START READ
+ snk_diag_en <= '1';
+ dvr_wr_not_rd <= '0';
+ dvr_en <= '1';
+
+ WAIT UNTIL rising_edge(ctlr_gen_clk);
+
+ dvr_en <= '0';
+
+ -- READ DONE
+ WAIT UNTIL dvr_done = '1';
+
+ WAIT FOR 2 us; -- 'Done' means all requests are posted. Wait for the last read data to arrive.
+
+ ASSERT snk_diag_res_val = '1' REPORT "[ERROR] DIAG_RES INVALID!" SEVERITY FAILURE;
+ ASSERT snk_diag_res = '0' REPORT "[ERROR] NON-ZERO DIAG_RES!" SEVERITY FAILURE;
+ ASSERT FALSE REPORT "[OK] Test passed." SEVERITY NOTE;
+ tb_end <= '1';
+
+ WAIT;
+ END PROCESS;
+
+ u_diagnostics: ENTITY diagnostics_lib.diagnostics
+ GENERIC MAP (
+ g_dat_w => c_data_w,
+ g_nof_streams => 1
+ )
+ PORT MAP (
+ rst => ctlr_gen_rst,
+ clk => ctlr_gen_clk,
+
+ snk_out_arr(0) => rd_siso,
+ snk_in_arr(0) => rd_sosi,
+ snk_diag_en(0) => snk_diag_en,
+ snk_diag_md(0) => '1',
+ snk_diag_res(0) => snk_diag_res,
+ snk_diag_res_val(0) => snk_diag_res_val,
+ snk_val_cnt(0) => snk_val_cnt,
+
+ src_out_arr(0) => wr_sosi,
+ src_in_arr(0) => wr_siso,
+ src_diag_en(0) => src_diag_en,
+ src_diag_md(0) => '1',
+ src_val_cnt(0) => src_val_cnt
+ );
+
+
+ gen_uphy_4g_model : IF c_phy > 0 GENERATE
+ u_4gb_ddr3_model : COMPONENT alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
+ GENERIC MAP (
+ MEM_IF_ADDR_WIDTH => 15,
+ MEM_IF_ROW_ADDR_WIDTH => 15,
+ MEM_IF_COL_ADDR_WIDTH => 10,
+ MEM_IF_CS_PER_RANK => 1,
+ MEM_IF_CONTROL_WIDTH => 1,
+ MEM_IF_DQS_WIDTH => 8,
+ MEM_IF_CS_WIDTH => 2,
+ MEM_IF_BANKADDR_WIDTH => 3,
+ MEM_IF_DQ_WIDTH => 64,
+ MEM_IF_CK_WIDTH => 2,
+ MEM_IF_CLK_EN_WIDTH => 2,
+ DEVICE_WIDTH => 1,
+ MEM_TRCD => 6,
+ MEM_TRTP => 3,
+ MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+ MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+ MEM_IF_ODT_WIDTH => 2,
+ MEM_MIRROR_ADDRESSING_DEC => 0,
+ MEM_REGDIMM_ENABLED => false,
+ DEVICE_DEPTH => 1,
+ MEM_GUARANTEED_WRITE_INIT => false,
+ MEM_VERBOSE => true,
+ MEM_INIT_EN => false,
+ MEM_INIT_FILE => "",
+ DAT_DATA_WIDTH => 32
+ )
+ PORT MAP (
+ mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0), -- memory.mem_a
+ mem_ba => phy_ou.ba, -- .mem_ba
+ mem_ck => phy_io.clk, -- .mem_ck
+ mem_ck_n => phy_io.clk_n, -- .mem_ck_n
+ mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm, -- .mem_dm
+ mem_ras_n => ras_n, -- .mem_ras_n
+ mem_cas_n => cas_n, -- .mem_cas_n
+ mem_we_n => we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq, -- .mem_dq
+ mem_dqs => phy_io.dqs, -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n, -- .mem_dqs_n
+ mem_odt => phy_ou.odt -- .mem_odt
+ );
+
+ ras_n(0) <= phy_ou.ras_n;
+ cas_n(0) <= phy_ou.cas_n;
+ we_n(0) <= phy_ou.we_n;
+ END GENERATE;
+
+ u_ddr3_module: ENTITY work.ddr3
+ GENERIC MAP(
+ g_phy => c_phy,
+ g_mts => c_mts,
+ g_ddr => c_ddr,
+ g_wr_data_w => c_data_w,
+ g_rd_data_w => c_data_w
+ )
+ PORT MAP (
+ ctlr_ref_clk => ctlr_ref_clk,
+ ctlr_rst => ctlr_rst,
+
+ ctlr_gen_clk => ctlr_gen_clk,
+ ctlr_gen_rst => ctlr_gen_rst,
+
+ ctlr_init_done => ctlr_init_done,
+ ctlr_rdy => ctlr_rdy,
+
+ dvr_start_addr => dvr_start_addr,
+ dvr_end_addr => dvr_end_addr,
+ dvr_en => dvr_en,
+ dvr_wr_not_rd => dvr_wr_not_rd,
+ dvr_done => dvr_done,
+
+ wr_clk => ctlr_gen_clk,
+ wr_rst => ctlr_gen_rst,
+
+ wr_sosi => wr_sosi,
+ wr_siso => wr_siso,
+
+ flush_ena => flush_ena,
+
+ rd_sosi => rd_sosi,
+ rd_siso => rd_siso,
+
+ rd_clk => ctlr_gen_clk,
+ rd_rst => ctlr_gen_rst,
+
+ phy_ou => phy_ou,
+ phy_io => phy_io,
+ phy_in => phy_in
+ );
+
+END ARCHITECTURE str;
+
+
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
new file mode 100644
index 0000000000..f9d51e4b12
--- /dev/null
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
@@ -0,0 +1,417 @@
+
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+--
+-- Purpose: Testbench for the ddr3_transpose unit
+-- To be used in conjunction with python testscript: ../python/tc_transpose_ddr3.py
+--
+--
+-- Usage:
+-- > as 8
+-- > run -all
+-- > run python script in separate terminal: "python tc_transpose_ddr3.py --unb 0 --fn 0 --sim"
+-- > Stop the simulation manually in Modelsim by pressing the stop-button.
+-- > Evalute the WAVE window.
+
+LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE work.ddr3_pkg.ALL;
+
+ENTITY tb_ddr3_transpose IS
+ GENERIC (
+ g_wr_chunksize : POSITIVE := 64;
+ g_wr_nof_chunks : POSITIVE := 1;
+ g_rd_chunksize : POSITIVE := 16;
+ g_rd_nof_chunks : POSITIVE := 4;
+ g_gapsize : NATURAL := 0;
+ g_nof_blocks : POSITIVE := 4;
+ g_nof_blk_per_sync : POSITIVE := 64
+ );
+END tb_ddr3_transpose;
+
+ARCHITECTURE tb OF tb_ddr3_transpose IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ ----------------------------------------------------------------------------
+ -- Clocks and resets
+ ----------------------------------------------------------------------------
+ CONSTANT c_mm_clk_period : TIME := 100 ps;
+ CONSTANT c_dp_clk_period : TIME := 5 ns;
+ CONSTANT c_dp_pps_period : NATURAL := 64;
+
+ SIGNAL dp_pps : STD_LOGIC;
+
+ SIGNAL mm_rst : STD_LOGIC := '1';
+ SIGNAL mm_clk : STD_LOGIC := '0';
+
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC := '0';
+
+ ----------------------------------------------------------------------------
+ -- MM buses
+ ----------------------------------------------------------------------------
+ -- TB
+ SIGNAL reg_diag_bg_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_miso : t_mem_miso;
+
+ SIGNAL ram_diag_bg_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_re_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_re_miso : t_mem_miso;
+
+ SIGNAL reg_diag_data_buf_re_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_re_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_im_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_im_miso : t_mem_miso;
+
+ SIGNAL reg_diag_data_buf_im_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_im_miso : t_mem_miso;
+
+ -- DUT
+ SIGNAL ram_ss_ss_transp_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL ram_ss_ss_transp_miso : t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------------------------------------
+ -- Component declaration of mm_file
+ ----------------------------------------------------------------------------
+ COMPONENT mm_file
+ GENERIC(
+ g_file_prefix : STRING;
+ g_update_on_change : BOOLEAN := FALSE
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi;
+ mm_master_in : IN t_mem_miso
+ );
+ END COMPONENT;
+
+ -- Compose the Constants for the DUT
+ CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (g_wr_chunksize,
+ g_wr_nof_chunks,
+ g_rd_chunksize,
+ g_rd_nof_chunks,
+ g_gapsize,
+ g_nof_blocks);
+
+ CONSTANT c_blocksize : POSITIVE := g_wr_nof_chunks * g_wr_chunksize;
+ CONSTANT c_page_size : POSITIVE := c_blocksize * g_nof_blocks;
+
+ CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
+ CONSTANT c_mts : NATURAL := 800;--1066; --800
+ CONSTANT c_phy : NATURAL := 1;
+ CONSTANT c_data_w : NATURAL := 64;
+
+ CONSTANT c_ctrl_ref_clk_period : TIME := 5000 ps;
+
+ -- Custom definitions of constants
+ CONSTANT c_bg_block_len : NATURAL := c_blocksize * g_rd_chunksize;
+ CONSTANT c_db_block_len : NATURAL := c_blocksize * g_rd_chunksize;
+
+ -- Configuration of the block generator:
+ CONSTANT c_bg_nof_output_streams : POSITIVE := 4;
+ CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*8;
+ CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
+ CONSTANT c_bg_data_file_prefix : STRING := "UNUSED"; -- "../../../src/hex/tb_bg_dat";
+ CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 128, 1);
+
+ -- Configuration of the databuffers:
+ CONSTANT c_db_nof_streams : POSITIVE := 4;
+ CONSTANT c_db_data_w : POSITIVE := c_diag_db_max_data_w;
+ CONSTANT c_db_buf_nof_data : POSITIVE := c_db_block_len;
+ CONSTANT c_db_buf_use_sync : BOOLEAN := FALSE;
+ CONSTANT c_db_data_type_re : t_diag_data_type_enum := e_real;
+ CONSTANT c_db_data_type_im : t_diag_data_type_enum := e_imag;
+
+ SIGNAL bg_siso_arr : t_dp_siso_arr(c_bg_nof_output_streams -1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL bg_sosi_arr : t_dp_sosi_arr(c_bg_nof_output_streams -1 DOWNTO 0);
+
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(c_bg_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL out_siso_arr : t_dp_siso_arr(c_bg_nof_output_streams-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+ -- Siganls to connect the memory driver with the mm register interface
+ SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
+ SIGNAL ctlr_rst : STD_LOGIC := '1';
+ SIGNAL ctlr_gen_clk : STD_LOGIC;
+ SIGNAL ctlr_gen_rst : STD_LOGIC;
+
+ SIGNAL ctlr_rdy : STD_LOGIC;
+ SIGNAL ctlr_init_done : STD_LOGIC;
+
+ SIGNAL dvr_start_addr : t_ddr3_addr;
+ SIGNAL dvr_end_addr : t_ddr3_addr;
+
+ SIGNAL dvr_en : STD_LOGIC;
+ SIGNAL dvr_wr_not_rd : STD_LOGIC;
+ SIGNAL dvr_done : STD_LOGIC;
+
+
+ -- Signals to interface with the DDR3 memory model.
+ SIGNAL phy_in : t_ddr3_phy_in;
+ SIGNAL phy_io : t_ddr3_phy_io;
+ SIGNAL phy_ou : t_ddr3_phy_ou;
+
+ SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- Clock and reset generation
+ ----------------------------------------------------------------------------
+ mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
+ mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
+
+ dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
+ dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
+
+ ctlr_ref_clk <= NOT ctlr_ref_clk AFTER c_ctrl_ref_clk_period/2;
+ ctlr_rst <= '1', '0' AFTER c_ctrl_ref_clk_period*5;
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
+
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ ----------------------------------------------------------------------------
+ -- MM buses
+ ----------------------------------------------------------------------------
+ -- TB
+ u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+
+ u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+
+ u_mm_file_ram_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_REAL")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_re_mosi, ram_diag_data_buf_re_miso);
+
+ u_mm_file_reg_diag_data_buf_re : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_REAL")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_re_mosi, reg_diag_data_buf_re_miso);
+
+ u_mm_file_ram_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER_IMAG")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_im_mosi, ram_diag_data_buf_im_miso);
+
+ u_mm_file_reg_diag_data_buf_im : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER_IMAG")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_im_mosi, reg_diag_data_buf_im_miso);
+
+ u_mm_file_ram_ss_ss_transp : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_SS_SS_WIDE")
+ PORT MAP(mm_rst, mm_clk, ram_ss_ss_transp_mosi, ram_ss_ss_transp_miso);
+
+ ----------------------------------------------------------------------------
+ -- Source: block generator
+ ----------------------------------------------------------------------------
+ u_bg : ENTITY diag_lib.mms_diag_block_gen
+ GENERIC MAP(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ PORT MAP(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
+
+ ----------------------------------------------------------------------------
+ -- DUT: Device Under Test
+ ----------------------------------------------------------------------------
+ u_dut: ENTITY work.ddr3_transpose
+ GENERIC MAP(
+ g_sim => TRUE,
+ g_nof_streams => c_bg_nof_output_streams,
+ g_in_dat_w => c_bg_buf_dat_w/c_nof_complex,
+ g_frame_size_in => g_wr_chunksize,
+ g_frame_size_out => g_wr_chunksize,
+ g_nof_blk_per_sync => g_nof_blk_per_sync,
+ g_use_complex => TRUE,
+ g_ena_pre_transp => FALSE,
+ g_phy => c_phy,
+ g_mts => c_mts,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+
+ snk_out_arr => bg_siso_arr,
+ snk_in_arr => bg_sosi_arr,
+ -- ST source
+ src_in_arr => out_siso_arr,
+ src_out_arr => out_sosi_arr,
+
+ ram_ss_ss_transp_mosi => ram_ss_ss_transp_mosi,
+ ram_ss_ss_transp_miso => ram_ss_ss_transp_miso,
+
+ ser_term_ctrl_out => OPEN,
+ par_term_ctrl_out => OPEN,
+
+ ser_term_ctrl_in => OPEN,
+ par_term_ctrl_in => OPEN,
+
+ phy_in => phy_in,
+ phy_io => phy_io,
+ phy_ou => phy_ou
+ );
+
+ u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
+ generic map (
+ MEM_IF_ADDR_WIDTH => 15,
+ MEM_IF_ROW_ADDR_WIDTH => 15,
+ MEM_IF_COL_ADDR_WIDTH => 10,
+ MEM_IF_CS_PER_RANK => 1,
+ MEM_IF_CONTROL_WIDTH => 1,
+ MEM_IF_DQS_WIDTH => 8,
+ MEM_IF_CS_WIDTH => 2,
+ MEM_IF_BANKADDR_WIDTH => 3,
+ MEM_IF_DQ_WIDTH => 64,
+ MEM_IF_CK_WIDTH => 2,
+ MEM_IF_CLK_EN_WIDTH => 2,
+ DEVICE_WIDTH => 1,
+ MEM_TRCD => 6,
+ MEM_TRTP => 3,
+ MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+ MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+ MEM_IF_ODT_WIDTH => 2,
+ MEM_MIRROR_ADDRESSING_DEC => 0,
+ MEM_REGDIMM_ENABLED => false,
+ DEVICE_DEPTH => 1,
+ MEM_GUARANTEED_WRITE_INIT => false,
+ MEM_VERBOSE => true,
+ MEM_INIT_EN => false,
+ MEM_INIT_FILE => "",
+ DAT_DATA_WIDTH => 32
+ )
+ port map (
+ mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
+ mem_ba => phy_ou.ba,
+ mem_ck => phy_io.clk,
+ mem_ck_n => phy_io.clk_n,
+ mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
+ mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
+ mem_dm => phy_ou.dm,
+ mem_ras_n => ras_n,
+ mem_cas_n => cas_n,
+ mem_we_n => we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq,
+ mem_dqs => phy_io.dqs,
+ mem_dqs_n => phy_io.dqs_n,
+ mem_odt => phy_ou.odt
+ );
+
+ ras_n(0) <= phy_ou.ras_n;
+ cas_n(0) <= phy_ou.cas_n;
+ we_n(0) <= phy_ou.we_n;
+
+ ----------------------------------------------------------------------------
+ -- Sink: data buffer real
+ ----------------------------------------------------------------------------
+ u_data_buf_re : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_re,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ PORT MAP (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_re_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_re_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_re_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_re_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
+
+ ----------------------------------------------------------------------------
+ -- Sink: data buffer imag
+ ----------------------------------------------------------------------------
+ u_data_buf_im : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type_im,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ PORT MAP (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_im_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_im_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_im_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_im_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
+
+END tb;
diff --git a/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
new file mode 100644
index 0000000000..379cdef1ac
--- /dev/null
+++ b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
@@ -0,0 +1,387 @@
+
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+--
+-- Purpose: Testbench for the seq_ddr3 unit
+-- To be used in conjunction with python testscript: ../python/tc_seq_ddr3.py
+--
+--
+-- Usage:
+-- > as 8
+-- > run -all
+-- > run python script in separate terminal: "python tc_seq_ddr3.py --unb 0 --fn 0 --sim"
+-- > Stop the simulation manually in Modelsim by pressing the stop-button.
+-- > Evalute the WAVE window.
+
+LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE work.ddr3_pkg.ALL;
+
+ENTITY tb_mms_ddr3 IS
+END tb_mms_ddr3;
+
+ARCHITECTURE tb OF tb_mms_ddr3 IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ ----------------------------------------------------------------------------
+ -- Clocks and resets
+ ----------------------------------------------------------------------------
+ CONSTANT c_mm_clk_period : TIME := 8 ns; -- 200 ps;
+ CONSTANT c_dp_clk_period : TIME := 5 ns;
+ CONSTANT c_dp_pps_period : NATURAL := 64;
+
+ SIGNAL dp_pps : STD_LOGIC;
+
+ SIGNAL mm_rst : STD_LOGIC := '1';
+ SIGNAL mm_clk : STD_LOGIC := '0';
+
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC := '0';
+
+ ----------------------------------------------------------------------------
+ -- MM buses
+ ----------------------------------------------------------------------------
+ -- TB
+ SIGNAL reg_diag_bg_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_miso : t_mem_miso;
+
+ SIGNAL ram_diag_bg_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_miso : t_mem_miso;
+
+ SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_miso : t_mem_miso;
+
+ -- DUT
+ SIGNAL reg_ddr3_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_ddr3_miso : t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------------------------------------
+ -- Component declaration of mm_file
+ ----------------------------------------------------------------------------
+ COMPONENT mm_file
+ GENERIC(
+ g_file_prefix : STRING;
+ g_update_on_change : BOOLEAN := FALSE
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi;
+ mm_master_in : IN t_mem_miso
+ );
+ END COMPONENT;
+
+ -- Compose the Constants for the DUT
+ CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
+ CONSTANT c_mts : NATURAL := 800;--1066; --800
+ CONSTANT c_phy : NATURAL := 1;
+ CONSTANT c_wr_data_w : NATURAL := 64;
+ CONSTANT c_wr_use_ctrl : BOOLEAN := FALSE;
+ CONSTANT c_wr_fifo_depth : NATURAL := 1024;
+ CONSTANT c_rd_fifo_depth : NATURAL := 256;
+ CONSTANT c_rd_data_w : NATURAL := 64;
+ CONSTANT c_flush_wr_fifo : BOOLEAN := FALSE;
+ CONSTANT c_flush_sop : BOOLEAN := FALSE;
+ CONSTANT c_flush_sop_channel : BOOLEAN := FALSE;
+ CONSTANT c_flush_sop_start_channel : NATURAL := 0;
+ CONSTANT c_flush_nof_channels : NATURAL := 0;
+
+ CONSTANT c_ctrl_ref_clk_period : TIME := 5000 ps;
+
+ -- Custom definitions of constants
+ CONSTANT c_bg_block_len : NATURAL := 1024;
+ CONSTANT c_db_block_len : NATURAL := 1024;
+
+ -- Configuration of the block generator:
+ CONSTANT c_bg_nof_output_streams : POSITIVE := 1;
+ CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*8;
+ CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
+ CONSTANT c_bg_data_file_prefix : STRING := "../../../src/hex/tb_bg_dat";
+ CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 1, 1);
+
+ -- Configuration of the databuffers:
+ CONSTANT c_db_nof_streams : POSITIVE := 1;
+ CONSTANT c_db_data_w : POSITIVE := c_diag_db_max_data_w;
+ CONSTANT c_db_buf_nof_data : POSITIVE := c_db_block_len;
+ CONSTANT c_db_buf_use_sync : BOOLEAN := FALSE;
+ CONSTANT c_db_data_type_re : t_diag_data_type_enum := e_real;
+ CONSTANT c_db_data_type_im : t_diag_data_type_enum := e_imag;
+
+ SIGNAL bg_siso_arr : t_dp_siso_arr(1 -1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL bg_sosi_arr : t_dp_sosi_arr(1 -1 DOWNTO 0);
+
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(1-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL out_siso_arr : t_dp_siso_arr(1-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+ -- Siganls to connect the memory driver with the mm register interface
+ SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
+ SIGNAL ctlr_rst : STD_LOGIC := '1';
+ SIGNAL ctlr_gen_clk : STD_LOGIC;
+ SIGNAL ctlr_gen_rst : STD_LOGIC;
+
+ SIGNAL ctlr_rdy : STD_LOGIC;
+ SIGNAL ctlr_init_done : STD_LOGIC;
+
+ SIGNAL dvr_start_addr : t_ddr3_addr;
+ SIGNAL dvr_end_addr : t_ddr3_addr;
+
+ SIGNAL dvr_en : STD_LOGIC;
+ SIGNAL dvr_wr_not_rd : STD_LOGIC;
+ SIGNAL dvr_done : STD_LOGIC;
+
+
+ -- Signals to interface with the DDR3 memory model.
+ SIGNAL phy_in : t_ddr3_phy_in;
+ SIGNAL phy_io : t_ddr3_phy_io;
+ SIGNAL phy_ou : t_ddr3_phy_ou;
+
+ SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+ SIGNAL flush_ena : STD_LOGIC;
+
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- Clock and reset generation
+ ----------------------------------------------------------------------------
+ mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
+ mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
+
+ dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
+ dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
+
+ ctlr_ref_clk <= NOT ctlr_ref_clk AFTER c_ctrl_ref_clk_period/2;
+ ctlr_rst <= '1', '0' AFTER c_ctrl_ref_clk_period*5;
+
+ flush_ena <= '0';
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
+
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ ----------------------------------------------------------------------------
+ -- MM buses
+ ----------------------------------------------------------------------------
+ -- TB
+ u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+
+ u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+
+ u_mm_file_ram_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+
+ u_mm_file_reg_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+
+ u_mm_file_reg_ddr3_0 : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DDR3_0")
+ PORT MAP(mm_rst, mm_clk, reg_ddr3_mosi, reg_ddr3_miso );
+
+
+ ----------------------------------------------------------------------------
+ -- Source: block generator
+ ----------------------------------------------------------------------------
+ u_bg : ENTITY diag_lib.mms_diag_block_gen
+ GENERIC MAP(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ PORT MAP(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
+
+ ----------------------------------------------------------------------------
+ -- DUT: Device Under Test
+ ----------------------------------------------------------------------------
+ u_dut: ENTITY work.mms_ddr3
+ GENERIC MAP(
+ g_sim => c_sim,
+ g_ddr => c_ddr,
+ g_mts => c_mts,
+ g_phy => c_phy,
+ g_wr_data_w => c_wr_data_w,
+ g_wr_use_ctrl => c_wr_use_ctrl,
+ g_wr_fifo_depth => c_wr_fifo_depth,
+ g_rd_fifo_depth => c_rd_fifo_depth,
+ g_rd_data_w => c_rd_data_w,
+ g_flush_wr_fifo => c_flush_wr_fifo,
+ g_flush_sop => c_flush_sop,
+ g_flush_sop_channel => c_flush_sop_channel,
+ g_flush_sop_start_channel => c_flush_sop_start_channel,
+ g_flush_nof_channels => c_flush_nof_channels
+ )
+ PORT MAP (
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+
+ -- MM registers
+ ctrl_mosi => reg_ddr3_mosi,
+ ctrl_miso => reg_ddr3_miso,
+
+ ctlr_ref_clk => ctlr_ref_clk,
+ ctlr_rst => ctlr_rst,
+
+ ctlr_gen_clk => open,
+ ctlr_gen_rst => open,
+
+ wr_clk => dp_clk,
+ wr_rst => dp_rst,
+
+ wr_sosi => bg_sosi_arr(0),
+ wr_siso => bg_siso_arr(0),
+
+ flush_ena => flush_ena,
+
+ rd_sosi => out_sosi_arr(0),
+ rd_siso => out_siso_arr(0),
+
+ rd_clk => dp_clk,
+ rd_rst => dp_rst,
+
+ rd_fifo_usedw => open, -- relative to FIFO wr side
+
+ ddr3_in => phy_in,
+ ddr3_io => phy_io,
+ ddr3_ou => phy_ou
+ );
+
+ gen_u_800_model : IF c_phy > 0 GENERATE
+ u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
+ generic map (
+ MEM_IF_ADDR_WIDTH => 15,
+ MEM_IF_ROW_ADDR_WIDTH => 15,
+ MEM_IF_COL_ADDR_WIDTH => 10,
+ MEM_IF_CS_PER_RANK => 1,
+ MEM_IF_CONTROL_WIDTH => 1,
+ MEM_IF_DQS_WIDTH => 8,
+ MEM_IF_CS_WIDTH => 2,
+ MEM_IF_BANKADDR_WIDTH => 3,
+ MEM_IF_DQ_WIDTH => 64,
+ MEM_IF_CK_WIDTH => 2,
+ MEM_IF_CLK_EN_WIDTH => 2,
+ DEVICE_WIDTH => 1,
+ MEM_TRCD => 6,
+ MEM_TRTP => 3,
+ MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+ MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+ MEM_IF_ODT_WIDTH => 2,
+ MEM_MIRROR_ADDRESSING_DEC => 0,
+ MEM_REGDIMM_ENABLED => false,
+ DEVICE_DEPTH => 1,
+ MEM_GUARANTEED_WRITE_INIT => false,
+ MEM_VERBOSE => true,
+ MEM_INIT_EN => false,
+ MEM_INIT_FILE => "",
+ DAT_DATA_WIDTH => 32
+ )
+ port map (
+ mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
+ mem_ba => phy_ou.ba,
+ mem_ck => phy_io.clk,
+ mem_ck_n => phy_io.clk_n,
+ mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
+ mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
+ mem_dm => phy_ou.dm,
+ mem_ras_n => ras_n,
+ mem_cas_n => cas_n,
+ mem_we_n => we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq,
+ mem_dqs => phy_io.dqs,
+ mem_dqs_n => phy_io.dqs_n,
+ mem_odt => phy_ou.odt
+ );
+
+ ras_n(0) <= phy_ou.ras_n;
+ cas_n(0) <= phy_ou.cas_n;
+ we_n(0) <= phy_ou.we_n;
+
+ END GENERATE;
+
+ ----------------------------------------------------------------------------
+ -- Sink: data buffer
+ ----------------------------------------------------------------------------
+ u_data_buf : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => e_data,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ PORT MAP (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
+
+END tb;
diff --git a/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
new file mode 100644
index 0000000000..2fa60459d7
--- /dev/null
+++ b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
@@ -0,0 +1,371 @@
+
+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2012
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program. If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+--
+-- Purpose: Testbench for the seq_ddr3 unit
+-- To be used in conjunction with python testscript: ../python/tc_seq_ddr3.py
+--
+--
+-- Usage:
+-- > as 8
+-- > run -all
+-- > run python script in separate terminal: "python tc_seq_ddr3.py --unb 0 --fn 0 --sim"
+-- > Stop the simulation manually in Modelsim by pressing the stop-button.
+-- > Evalute the WAVE window.
+
+LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE common_lib.common_str_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+USE common_lib.tb_common_mem_pkg.ALL;
+USE mm_lib.mm_file_unb_pkg.ALL;
+USE mm_lib.mm_file_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+USE diag_lib.diag_pkg.ALL;
+USE work.ddr3_pkg.ALL;
+
+ENTITY tb_seq_ddr3 IS
+ GENERIC (
+ g_wr_chunksize : POSITIVE := 240;
+ g_wr_nof_chunks : POSITIVE := 1;
+ g_rd_chunksize : POSITIVE := 16;
+ g_rd_nof_chunks : POSITIVE := 15;
+ g_gapsize : NATURAL := 16;
+ g_nof_blocks : POSITIVE := 5
+ );
+END tb_seq_ddr3;
+
+ARCHITECTURE tb OF tb_seq_ddr3 IS
+
+ CONSTANT c_sim : BOOLEAN := TRUE;
+
+ ----------------------------------------------------------------------------
+ -- Clocks and resets
+ ----------------------------------------------------------------------------
+ CONSTANT c_mm_clk_period : TIME := 8 ns; -- 200 ps;
+ CONSTANT c_dp_clk_period : TIME := 5 ns;
+ CONSTANT c_dp_pps_period : NATURAL := 64;
+
+ SIGNAL dp_pps : STD_LOGIC;
+
+ SIGNAL mm_rst : STD_LOGIC := '1';
+ SIGNAL mm_clk : STD_LOGIC := '0';
+
+ SIGNAL dp_rst : STD_LOGIC;
+ SIGNAL dp_clk : STD_LOGIC := '0';
+
+ ----------------------------------------------------------------------------
+ -- MM buses
+ ----------------------------------------------------------------------------
+ -- TB
+ SIGNAL reg_diag_bg_mosi : t_mem_mosi;
+ SIGNAL reg_diag_bg_miso : t_mem_miso;
+
+ SIGNAL ram_diag_bg_mosi : t_mem_mosi;
+ SIGNAL ram_diag_bg_miso : t_mem_miso;
+
+ SIGNAL ram_diag_data_buf_mosi : t_mem_mosi;
+ SIGNAL ram_diag_data_buf_miso : t_mem_miso;
+
+ SIGNAL reg_diag_data_buf_mosi : t_mem_mosi;
+ SIGNAL reg_diag_data_buf_miso : t_mem_miso;
+
+ -- DUT
+ SIGNAL reg_ddr3_mosi : t_mem_mosi := c_mem_mosi_rst;
+ SIGNAL reg_ddr3_miso : t_mem_miso := c_mem_miso_rst;
+
+ ----------------------------------------------------------------------------
+ -- Component declaration of mm_file
+ ----------------------------------------------------------------------------
+ COMPONENT mm_file
+ GENERIC(
+ g_file_prefix : STRING;
+ g_update_on_change : BOOLEAN := FALSE
+ );
+ PORT (
+ mm_rst : IN STD_LOGIC;
+ mm_clk : IN STD_LOGIC;
+ mm_master_out : OUT t_mem_mosi;
+ mm_master_in : IN t_mem_miso
+ );
+ END COMPONENT;
+
+ -- Compose the Constants for the DUT
+ CONSTANT c_ddr3_seq_conf : t_ddr3_seq := (g_wr_chunksize,
+ g_wr_nof_chunks,
+ g_rd_chunksize,
+ g_rd_nof_chunks,
+ g_gapsize,
+ g_nof_blocks);
+
+ CONSTANT c_blocksize : POSITIVE := g_wr_nof_chunks * g_wr_chunksize;
+ CONSTANT c_page_size : POSITIVE := c_blocksize * g_nof_blocks;
+
+ CONSTANT c_ddr : t_c_ddr3_phy := c_ddr3_phy_4g;
+ CONSTANT c_mts : NATURAL := 1066;--1066; --800
+ CONSTANT c_phy : NATURAL := 1;
+ CONSTANT c_data_w : NATURAL := 64;
+
+ CONSTANT c_ctrl_ref_clk_period : TIME := 5000 ps;
+
+ -- Custom definitions of constants
+ CONSTANT c_bg_block_len : NATURAL := c_page_size;
+ CONSTANT c_db_block_len : NATURAL := c_page_size;
+
+ -- Configuration of the block generator:
+ CONSTANT c_bg_nof_output_streams : POSITIVE := 1;
+ CONSTANT c_bg_buf_dat_w : POSITIVE := c_nof_complex*8;
+ CONSTANT c_bg_buf_adr_w : POSITIVE := ceil_log2(c_bg_block_len);
+ CONSTANT c_bg_data_file_prefix : STRING := "../../../src/hex/tb_bg_dat";
+ CONSTANT c_bg_data_file_index_arr : t_nat_natural_arr := array_init(0, 1, 1);
+
+ -- Configuration of the databuffers:
+ CONSTANT c_db_nof_streams : POSITIVE := 1;
+ CONSTANT c_db_data_w : POSITIVE := c_diag_db_max_data_w;
+ CONSTANT c_db_buf_nof_data : POSITIVE := c_db_block_len;
+ CONSTANT c_db_buf_use_sync : BOOLEAN := FALSE;
+ CONSTANT c_db_data_type : t_diag_data_type_enum := e_data;
+
+
+ SIGNAL bg_siso_arr : t_dp_siso_arr(1 -1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+ SIGNAL bg_sosi_arr : t_dp_sosi_arr(1 -1 DOWNTO 0);
+
+ SIGNAL out_sosi_arr : t_dp_sosi_arr(1-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
+ SIGNAL out_siso_arr : t_dp_siso_arr(1-1 DOWNTO 0) := (OTHERS => c_dp_siso_rdy);
+
+ -- Siganls to connect the memory driver with the mm register interface
+ SIGNAL ctlr_ref_clk : STD_LOGIC := '0';
+ SIGNAL ctlr_rst : STD_LOGIC := '1';
+ SIGNAL ctlr_gen_clk : STD_LOGIC;
+ SIGNAL ctlr_gen_rst : STD_LOGIC;
+
+ SIGNAL ctlr_rdy : STD_LOGIC;
+ SIGNAL ctlr_init_done : STD_LOGIC;
+
+ SIGNAL dvr_start_addr : t_ddr3_addr;
+ SIGNAL dvr_end_addr : t_ddr3_addr;
+
+ SIGNAL dvr_en : STD_LOGIC;
+ SIGNAL dvr_wr_not_rd : STD_LOGIC;
+ SIGNAL dvr_done : STD_LOGIC;
+
+
+ -- Signals to interface with the DDR3 memory model.
+ SIGNAL phy_in : t_ddr3_phy_in;
+ SIGNAL phy_io : t_ddr3_phy_io;
+ SIGNAL phy_ou : t_ddr3_phy_ou;
+
+ SIGNAL ras_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL cas_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+ SIGNAL we_n : STD_LOGIC_VECTOR(0 DOWNTO 0);
+
+
+BEGIN
+
+ ----------------------------------------------------------------------------
+ -- Clock and reset generation
+ ----------------------------------------------------------------------------
+ mm_clk <= NOT mm_clk AFTER c_mm_clk_period/2;
+ mm_rst <= '1', '0' AFTER c_mm_clk_period*5;
+
+ dp_clk <= NOT dp_clk AFTER c_dp_clk_period/2;
+ dp_rst <= '1', '0' AFTER c_dp_clk_period*5;
+
+ ctlr_ref_clk <= NOT ctlr_ref_clk AFTER c_ctrl_ref_clk_period/2;
+ ctlr_rst <= '1', '0' AFTER c_ctrl_ref_clk_period*5;
+
+ ------------------------------------------------------------------------------
+ -- External PPS
+ ------------------------------------------------------------------------------
+ proc_common_gen_pulse(1, c_dp_pps_period, '1', dp_clk, dp_pps);
+
+ ----------------------------------------------------------------------------
+ -- Procedure that polls a sim control file that can be used to e.g. get
+ -- the simulation time in ns
+ ----------------------------------------------------------------------------
+ mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
+
+ ----------------------------------------------------------------------------
+ -- MM buses
+ ----------------------------------------------------------------------------
+ -- TB
+ u_mm_file_reg_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, reg_diag_bg_mosi, reg_diag_bg_miso);
+
+ u_mm_file_ram_diag_bg : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_BG")
+ PORT MAP(mm_rst, mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso);
+
+ u_mm_file_ram_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "RAM_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, mm_clk, ram_diag_data_buf_mosi, ram_diag_data_buf_miso);
+
+ u_mm_file_reg_diag_data_buf : mm_file GENERIC MAP(mmf_unb_file_prefix(0, 0, "FN") & "REG_DIAG_DATA_BUFFER")
+ PORT MAP(mm_rst, mm_clk, reg_diag_data_buf_mosi, reg_diag_data_buf_miso);
+
+ ----------------------------------------------------------------------------
+ -- Source: block generator
+ ----------------------------------------------------------------------------
+ u_bg : ENTITY diag_lib.mms_diag_block_gen
+ GENERIC MAP(
+ g_nof_streams => c_bg_nof_output_streams,
+ g_buf_dat_w => c_bg_buf_dat_w,
+ g_buf_addr_w => c_bg_buf_adr_w,
+ g_file_index_arr => c_bg_data_file_index_arr,
+ g_file_name_prefix => c_bg_data_file_prefix
+ )
+ PORT MAP(
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ en_sync => dp_pps,
+ -- MM interface
+ reg_bg_ctrl_mosi => reg_diag_bg_mosi,
+ reg_bg_ctrl_miso => reg_diag_bg_miso,
+ ram_bg_data_mosi => ram_diag_bg_mosi,
+ ram_bg_data_miso => ram_diag_bg_miso,
+ -- ST interface
+ out_siso_arr => bg_siso_arr,
+ out_sosi_arr => bg_sosi_arr
+ );
+
+ ----------------------------------------------------------------------------
+ -- DUT: Device Under Test
+ ----------------------------------------------------------------------------
+ u_dut: ENTITY work.seq_ddr3
+ GENERIC MAP(
+ g_ddr => c_ddr,
+ g_mts => c_mts,
+ g_phy => c_phy,
+ g_data_w => c_data_w,
+ g_ddr3_seq => c_ddr3_seq_conf
+ )
+ PORT MAP (
+ ctlr_ref_clk => ctlr_ref_clk,
+ ctlr_rst => ctlr_rst,
+
+ ctlr_gen_clk => open,
+ ctlr_gen_rst => open,
+
+ wr_clk => dp_clk,
+ wr_rst => dp_rst,
+
+ wr_sosi => bg_sosi_arr(0),
+ wr_siso => bg_siso_arr(0),
+
+ flush_ena => '0',
+
+ rd_sosi => out_sosi_arr(0),
+ rd_siso => out_siso_arr(0),
+
+ rd_clk => dp_clk,
+ rd_rst => dp_rst,
+
+ ddr3_in => phy_in,
+ ddr3_io => phy_io,
+ ddr3_ou => phy_ou
+ );
+
+ gen_u_800_model : IF c_phy > 0 GENERATE
+ u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
+ generic map (
+ MEM_IF_ADDR_WIDTH => 15,
+ MEM_IF_ROW_ADDR_WIDTH => 15,
+ MEM_IF_COL_ADDR_WIDTH => 10,
+ MEM_IF_CS_PER_RANK => 1,
+ MEM_IF_CONTROL_WIDTH => 1,
+ MEM_IF_DQS_WIDTH => 8,
+ MEM_IF_CS_WIDTH => 2,
+ MEM_IF_BANKADDR_WIDTH => 3,
+ MEM_IF_DQ_WIDTH => 64,
+ MEM_IF_CK_WIDTH => 2,
+ MEM_IF_CLK_EN_WIDTH => 2,
+ DEVICE_WIDTH => 1,
+ MEM_TRCD => 6,
+ MEM_TRTP => 3,
+ MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+ MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+ MEM_IF_ODT_WIDTH => 2,
+ MEM_MIRROR_ADDRESSING_DEC => 0,
+ MEM_REGDIMM_ENABLED => false,
+ DEVICE_DEPTH => 1,
+ MEM_GUARANTEED_WRITE_INIT => false,
+ MEM_VERBOSE => true,
+ MEM_INIT_EN => false,
+ MEM_INIT_FILE => "",
+ DAT_DATA_WIDTH => 32
+ )
+ port map (
+ mem_a => phy_ou.a(c_ddr.a_w-1 DOWNTO 0),
+ mem_ba => phy_ou.ba,
+ mem_ck => phy_io.clk,
+ mem_ck_n => phy_io.clk_n,
+ mem_cke => phy_ou.cke(c_ddr.cs_w-1 DOWNTO 0),
+ mem_cs_n => phy_ou.cs_n(c_ddr.cs_w-1 DOWNTO 0),
+ mem_dm => phy_ou.dm,
+ mem_ras_n => ras_n,
+ mem_cas_n => cas_n,
+ mem_we_n => we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq,
+ mem_dqs => phy_io.dqs,
+ mem_dqs_n => phy_io.dqs_n,
+ mem_odt => phy_ou.odt
+ );
+
+ ras_n(0) <= phy_ou.ras_n;
+ cas_n(0) <= phy_ou.cas_n;
+ we_n(0) <= phy_ou.we_n;
+
+ END GENERATE;
+
+ ----------------------------------------------------------------------------
+ -- Sink: data buffer real
+ ----------------------------------------------------------------------------
+ u_data_buf : ENTITY diag_lib.mms_diag_data_buffer
+ GENERIC MAP (
+ g_nof_streams => c_db_nof_streams,
+ g_data_type => c_db_data_type,
+ g_data_w => c_db_data_w,
+ g_buf_nof_data => c_db_buf_nof_data,
+ g_buf_use_sync => c_db_buf_use_sync
+ )
+ PORT MAP (
+ -- System
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ dp_rst => dp_rst,
+ dp_clk => dp_clk,
+ -- MM interface
+ ram_data_buf_mosi => ram_diag_data_buf_mosi,
+ ram_data_buf_miso => ram_diag_data_buf_miso,
+ reg_data_buf_mosi => reg_diag_data_buf_mosi,
+ reg_data_buf_miso => reg_diag_data_buf_miso,
+ -- ST interface
+ in_sync => OPEN,
+ in_sosi_arr => out_sosi_arr
+ );
+
+
+END tb;
--
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