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Commit ec2c7eae authored by Reinier van der Walle's avatar Reinier van der Walle
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replaced bsn sched + sync_insert with bsn_sync_scheduler

parent d57ed6b1
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1 merge request!144Resolve L2SDP-425
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applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.fpga.yaml
+ 2
− 6
View file @ ec2c7eae
......@@ -214,14 +214,10 @@ peripherals:
# Xsub = Subband Correlator (from node_sdp_correlator.vhd)
#############################################################################
- peripheral_name: dp/dp_bsn_scheduler
- peripheral_name: dp/dp_bsn_sync_scheduler
peripheral_group: xsub
mm_port_names:
- REG_BSN_SCHEDULER_XSUB
- peripheral_name: dp/dp_sync_insert_v2
mm_port_names:
- REG_DP_SYNC_INSERT_V2
- REG_BSN_SYNC_SCHEDULER_XSUB
- peripheral_name: st/st_xst_for_sdp
parameter_overrides:
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_cpu_0.ip
+ 2
− 2
View file @ ec2c7eae
......@@ -2218,7 +2218,7 @@
<spirit:parameter>
<spirit:name>dataSlaveMapParam</spirit:name>
<spirit:displayName>dataSlaveMapParam</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /><slave name='reg_bsn_scheduler_xsub.mem' start='0xB4170' end='0xB4178' datawidth='32' /><slave name='reg_dp_sync_insert_v2.mem' start='0xB4178' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB4180' end='0xB4188' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB4188' end='0xB4190' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB4190' end='0xB4198' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB4198' end='0xB41A0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /><slave name='reg_si.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
<spirit:value spirit:format="string" spirit:id="dataSlaveMapParam"><![CDATA[<address-map><slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /><slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /><slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /><slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /><slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /><slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /><slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /><slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /><slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /><slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /><slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /><slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /><slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3040' end='0x3080' datawidth='32' /><slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /><slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /><slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /><slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /><slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /><slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /><slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /><slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /><slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /><slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /><slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /><slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /><slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /><slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /><slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /><slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /><slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /><slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /><slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /><slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /><slave name='avs_eth_0.mms_reg' start='0xB4000' end='0xB4040' datawidth='32' /><slave name='reg_crosslets_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /><slave name='reg_sdp_info.mem' start='0xB4080' end='0xB40C0' datawidth='32' /><slave name='reg_fpga_voltage_sens.mem' start='0xB40C0' end='0xB4100' datawidth='32' /><slave name='reg_bsn_source_v2.mem' start='0xB4100' end='0xB4120' datawidth='32' /><slave name='reg_fpga_temp_sens.mem' start='0xB4120' end='0xB4140' datawidth='32' /><slave name='reg_epcs.mem' start='0xB4140' end='0xB4160' datawidth='32' /><slave name='reg_remu.mem' start='0xB4160' end='0xB4180' datawidth='32' /><slave name='reg_stat_enable_bst.mem' start='0xB4180' end='0xB4190' datawidth='32' /><slave name='reg_dp_xonoff.mem' start='0xB4190' end='0xB41A0' datawidth='32' /><slave name='reg_bf_scale.mem' start='0xB41A0' end='0xB41B0' datawidth='32' /><slave name='pio_pps.mem' start='0xB41B0' end='0xB41C0' datawidth='32' /><slave name='reg_stat_enable_sst.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /><slave name='pio_jesd_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /><slave name='reg_nw_10gbe_eth10g.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /><slave name='reg_dp_selector.mem' start='0xB41D8' end='0xB41E0' datawidth='32' /><slave name='reg_bsn_scheduler.mem' start='0xB41E0' end='0xB41E8' datawidth='32' /><slave name='reg_si.mem' start='0xB41E8' end='0xB41F0' datawidth='32' /><slave name='reg_mmdp_data.mem' start='0xB41F0' end='0xB41F8' datawidth='32' /><slave name='reg_mmdp_ctrl.mem' start='0xB41F8' end='0xB4200' datawidth='32' /><slave name='reg_dpmm_data.mem' start='0xB4200' end='0xB4208' datawidth='32' /><slave name='reg_dpmm_ctrl.mem' start='0xB4208' end='0xB4210' datawidth='32' /><slave name='jtag_uart_0.avalon_jtag_slave' start='0xB4210' end='0xB4218' datawidth='32' /><slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /></address-map>]]></spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>tightlyCoupledDataMaster0MapParam</spirit:name>
......@@ -3489,7 +3489,7 @@
<suppliedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0xB4000' end='0xB4040' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xB4080' end='0xB40C0' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0xB40C0' end='0xB40E0' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0xB40E0' end='0xB4100' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0xB4100' end='0xB4120' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0xB4120' end='0xB4140' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0xB4140' end='0xB4150' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0xB4150' end='0xB4160' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0xB4160' end='0xB4170' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler_xsub.mem' start='0xB4170' end='0xB4178' datawidth='32' /&gt;&lt;slave name='reg_dp_sync_insert_v2.mem' start='0xB4178' end='0xB4180' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0xB4180' end='0xB4188' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0xB4188' end='0xB4190' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0xB4190' end='0xB4198' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0xB4198' end='0xB41A0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0xB41A0' end='0xB41A8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0xB41A8' end='0xB41B0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0xB41B0' end='0xB41B8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0xB41B8' end='0xB41C0' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0xB41D8' end='0xB41E0' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
<value>&lt;address-map&gt;&lt;slave name='pio_system_info.mem' start='0x0' end='0x80' datawidth='32' /&gt;&lt;slave name='reg_diag_data_buffer_bsn.mem' start='0x80' end='0x100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_xst.mem' start='0x100' end='0x200' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_bst.mem' start='0x200' end='0x400' datawidth='32' /&gt;&lt;slave name='reg_bsn_monitor_input.mem' start='0x400' end='0x800' datawidth='32' /&gt;&lt;slave name='ram_scrap.mem' start='0x800' end='0x1000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_tse' start='0x1000' end='0x2000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_ram' start='0x2000' end='0x3000' datawidth='32' /&gt;&lt;slave name='reg_wdi.mem' start='0x3000' end='0x3008' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_xst.mem' start='0x3008' end='0x3010' datawidth='32' /&gt;&lt;slave name='pio_wdi.s1' start='0x3010' end='0x3020' datawidth='32' /&gt;&lt;slave name='timer_0.s1' start='0x3020' end='0x3040' datawidth='16' /&gt;&lt;slave name='reg_bsn_sync_scheduler_xsub.mem' start='0x3040' end='0x3080' datawidth='32' /&gt;&lt;slave name='reg_dp_shiftram.mem' start='0x3080' end='0x3100' datawidth='32' /&gt;&lt;slave name='reg_stat_hdr_dat_sst.mem' start='0x3100' end='0x3200' datawidth='32' /&gt;&lt;slave name='reg_hdr_dat.mem' start='0x3200' end='0x3400' datawidth='32' /&gt;&lt;slave name='reg_wg.mem' start='0x3400' end='0x3500' datawidth='32' /&gt;&lt;slave name='reg_aduh_monitor.mem' start='0x3500' end='0x3600' datawidth='32' /&gt;&lt;slave name='reg_unb_pmbus.mem' start='0x3600' end='0x3700' datawidth='32' /&gt;&lt;slave name='reg_unb_sens.mem' start='0x3700' end='0x3800' datawidth='32' /&gt;&lt;slave name='cpu_0.debug_mem_slave' start='0x3800' end='0x4000' datawidth='32' /&gt;&lt;slave name='ram_st_bst.mem' start='0x4000' end='0x8000' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_mac.mem' start='0x8000' end='0x10000' datawidth='32' /&gt;&lt;slave name='rom_system_info.mem' start='0x10000' end='0x18000' datawidth='32' /&gt;&lt;slave name='ram_equalizer_gains.mem' start='0x18000' end='0x20000' datawidth='32' /&gt;&lt;slave name='onchip_memory2_0.s1' start='0x20000' end='0x40000' datawidth='32' /&gt;&lt;slave name='ram_bf_weights.mem' start='0x40000' end='0x60000' datawidth='32' /&gt;&lt;slave name='ram_st_xsq.mem' start='0x60000' end='0x70000' datawidth='32' /&gt;&lt;slave name='ram_ss_ss_wide.mem' start='0x70000' end='0x80000' datawidth='32' /&gt;&lt;slave name='ram_wg.mem' start='0x80000' end='0x90000' datawidth='32' /&gt;&lt;slave name='ram_fil_coefs.mem' start='0x90000' end='0xA0000' datawidth='32' /&gt;&lt;slave name='ram_st_sst.mem' start='0xA0000' end='0xB0000' datawidth='32' /&gt;&lt;slave name='jesd204b.mem' start='0xB0000' end='0xB4000' datawidth='32' /&gt;&lt;slave name='avs_eth_0.mms_reg' start='0xB4000' end='0xB4040' datawidth='32' /&gt;&lt;slave name='reg_crosslets_info.mem' start='0xB4040' end='0xB4080' datawidth='32' /&gt;&lt;slave name='reg_sdp_info.mem' start='0xB4080' end='0xB40C0' datawidth='32' /&gt;&lt;slave name='reg_fpga_voltage_sens.mem' start='0xB40C0' end='0xB4100' datawidth='32' /&gt;&lt;slave name='reg_bsn_source_v2.mem' start='0xB4100' end='0xB4120' datawidth='32' /&gt;&lt;slave name='reg_fpga_temp_sens.mem' start='0xB4120' end='0xB4140' datawidth='32' /&gt;&lt;slave name='reg_epcs.mem' start='0xB4140' end='0xB4160' datawidth='32' /&gt;&lt;slave name='reg_remu.mem' start='0xB4160' end='0xB4180' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_bst.mem' start='0xB4180' end='0xB4190' datawidth='32' /&gt;&lt;slave name='reg_dp_xonoff.mem' start='0xB4190' end='0xB41A0' datawidth='32' /&gt;&lt;slave name='reg_bf_scale.mem' start='0xB41A0' end='0xB41B0' datawidth='32' /&gt;&lt;slave name='pio_pps.mem' start='0xB41B0' end='0xB41C0' datawidth='32' /&gt;&lt;slave name='reg_stat_enable_sst.mem' start='0xB41C0' end='0xB41C8' datawidth='32' /&gt;&lt;slave name='pio_jesd_ctrl.mem' start='0xB41C8' end='0xB41D0' datawidth='32' /&gt;&lt;slave name='reg_nw_10gbe_eth10g.mem' start='0xB41D0' end='0xB41D8' datawidth='32' /&gt;&lt;slave name='reg_dp_selector.mem' start='0xB41D8' end='0xB41E0' datawidth='32' /&gt;&lt;slave name='reg_bsn_scheduler.mem' start='0xB41E0' end='0xB41E8' datawidth='32' /&gt;&lt;slave name='reg_si.mem' start='0xB41E8' end='0xB41F0' datawidth='32' /&gt;&lt;slave name='reg_mmdp_data.mem' start='0xB41F0' end='0xB41F8' datawidth='32' /&gt;&lt;slave name='reg_mmdp_ctrl.mem' start='0xB41F8' end='0xB4200' datawidth='32' /&gt;&lt;slave name='reg_dpmm_data.mem' start='0xB4200' end='0xB4208' datawidth='32' /&gt;&lt;slave name='reg_dpmm_ctrl.mem' start='0xB4208' end='0xB4210' datawidth='32' /&gt;&lt;slave name='jtag_uart_0.avalon_jtag_slave' start='0xB4210' end='0xB4218' datawidth='32' /&gt;&lt;slave name='ram_diag_data_buffer_bsn.mem' start='0x800000' end='0x1000000' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.ip → applications/lofar2/designs/lofar2_unb2b_sdp_station/quartus/ip/qsys_lofar2_unb2b_sdp_station/qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.ip
+ 28
− 20
View file @ ec2c7eae
<?xml version="1.0" ?>
<spirit:component xmlns:altera="http://www.altera.com/XMLSchema/IPXact/extensions" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009">
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:library>
<spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:name>
<spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</spirit:library>
<spirit:name>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:busInterfaces>
<spirit:busInterface>
......@@ -129,7 +129,7 @@
<spirit:parameter>
<spirit:name>addressSpan</spirit:name>
<spirit:displayName>Address span</spirit:displayName>
<spirit:value spirit:format="string" spirit:id="addressSpan">8</spirit:value>
<spirit:value spirit:format="string" spirit:id="addressSpan">64</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>addressUnits</spirit:name>
......@@ -605,6 +605,10 @@
<spirit:name>avs_mem_address</spirit:name>
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
......@@ -697,6 +701,10 @@
<spirit:name>coe_address_export</spirit:name>
<spirit:wire>
<spirit:direction>out</spirit:direction>
<spirit:vector>
<spirit:left>0</spirit:left>
<spirit:right>3</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>STD_LOGIC_VECTOR</spirit:typeName>
......@@ -766,7 +774,7 @@
<spirit:vendorExtensions>
<altera:entity_info>
<spirit:vendor>ASTRON</spirit:vendor>
<spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub</spirit:library>
<spirit:library>qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub</spirit:library>
<spirit:name>avs_common_mm</spirit:name>
<spirit:version>1.0</spirit:version>
</altera:entity_info>
......@@ -775,7 +783,7 @@
<spirit:parameter>
<spirit:name>g_adr_w</spirit:name>
<spirit:displayName>g_adr_w</spirit:displayName>
<spirit:value spirit:format="long" spirit:id="g_adr_w">1</spirit:value>
<spirit:value spirit:format="long" spirit:id="g_adr_w">4</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>g_dat_w</spirit:name>
......@@ -838,7 +846,7 @@
<name>coe_address_export</name>
<role>export</role>
<direction>Output</direction>
<width>1</width>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
......@@ -902,7 +910,7 @@
<name>avs_mem_address</name>
<role>address</role>
<direction>Input</direction>
<width>1</width>
<width>4</width>
<lowerBound>0</lowerBound>
<vhdlType>STD_LOGIC_VECTOR</vhdlType>
</port>
......@@ -971,7 +979,7 @@
</entry>
<entry>
<key>addressSpan</key>
<value>8</value>
<value>64</value>
</entry>
<entry>
<key>addressUnits</key>
......@@ -1366,11 +1374,11 @@
<consumedSystemInfos>
<entry>
<key>ADDRESS_MAP</key>
<value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x8' datawidth='32' /&gt;&lt;/address-map&gt;</value>
<value>&lt;address-map&gt;&lt;slave name='mem' start='0x0' end='0x40' datawidth='32' /&gt;&lt;/address-map&gt;</value>
</entry>
<entry>
<key>ADDRESS_WIDTH</key>
<value>3</value>
<value>6</value>
</entry>
<entry>
<key>MAX_SLAVE_DATA_WIDTH</key>
......@@ -1398,38 +1406,38 @@
</spirit:parameters>
</altera:altera_system_parameters>
<altera:altera_interface_boundary>
<altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.address" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="address" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.address" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_address_export" altera:internal="coe_address_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="clk" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.clk" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_clk_export" altera:internal="coe_clk_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:interface_mapping altera:name="mem" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.mem" altera:type="avalon" altera:dir="end">
<altera:port_mapping altera:name="avs_mem_address" altera:internal="avs_mem_address"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_read" altera:internal="avs_mem_read"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_readdata" altera:internal="avs_mem_readdata"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_write" altera:internal="avs_mem_write"></altera:port_mapping>
<altera:port_mapping altera:name="avs_mem_writedata" altera:internal="avs_mem_writedata"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.read" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="read" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.read" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_read_export" altera:internal="coe_read_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="readdata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.readdata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_readdata_export" altera:internal="coe_readdata_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.reset" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_reset_export" altera:internal="coe_reset_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.system" altera:type="clock" altera:dir="end">
<altera:interface_mapping altera:name="system" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.system" altera:type="clock" altera:dir="end">
<altera:port_mapping altera:name="csi_system_clk" altera:internal="csi_system_clk"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:interface_mapping altera:name="system_reset" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.system_reset" altera:type="reset" altera:dir="end">
<altera:port_mapping altera:name="csi_system_reset" altera:internal="csi_system_reset"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.write" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="write" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.write" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_write_export" altera:internal="coe_write_export"></altera:port_mapping>
</altera:interface_mapping>
<altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_scheduler_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:interface_mapping altera:name="writedata" altera:internal="qsys_lofar2_unb2b_sdp_station_reg_bsn_sync_scheduler_xsub.writedata" altera:type="conduit" altera:dir="end">
<altera:port_mapping altera:name="coe_writedata_export" altera:internal="coe_writedata_export"></altera:port_mapping>
</altera:interface_mapping>
</altera:altera_interface_boundary>
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+ 1
− 1
View file @ ec2c7eae
......@@ -89,7 +89,7 @@ ARCHITECTURE tb OF tb_lofar2_unb2b_sdp_station_fsub IS
-- WG
CONSTANT c_full_scale_ampl : REAL := REAL(2**(14-1)-1); -- = full scale of WG
CONSTANT c_bsn_start_wg : NATURAL := 2; -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/2; -- in number of lsb
CONSTANT c_ampl_sp_0 : NATURAL := 2**(c_sdp_W_adc-1)/1; -- in number of lsb
CONSTANT c_wg_subband_freq_unit : REAL := c_diag_wg_freq_unit/REAL(c_sdp_N_fft); -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
CONSTANT c_wg_freq_offset : REAL := 0.0/11.0; -- in freq_unit
CONSTANT c_subband_sp_0 : REAL := 102.0; -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+ 6
− 14
View file @ ec2c7eae
......@@ -274,17 +274,13 @@ ARCHITECTURE str OF lofar2_unb2b_sdp_station IS
----------------------------------------------
-- XSUB
----------------------------------------------
-- dp_sync_insert_v2
SIGNAL reg_dp_sync_insert_v2_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_dp_sync_insert_v2_miso : t_mem_miso := c_mem_miso_rst;
-- crosslets_info
SIGNAL reg_crosslets_info_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_crosslets_info_miso : t_mem_miso := c_mem_miso_rst;
-- bsn_scheduler_xsub
SIGNAL reg_bsn_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_bsn_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL reg_bsn_sync_scheduler_xsub_mosi : t_mem_mosi := c_mem_mosi_rst;
SIGNAL reg_bsn_sync_scheduler_xsub_miso : t_mem_miso := c_mem_miso_rst;
-- st_xsq
SIGNAL ram_st_xsq_mosi : t_mem_mosi := c_mem_mosi_rst;
......@@ -640,12 +636,10 @@ BEGIN
reg_stat_enable_bst_miso => reg_stat_enable_bst_miso,
reg_stat_hdr_dat_bst_mosi => reg_stat_hdr_dat_bst_mosi,
reg_stat_hdr_dat_bst_miso => reg_stat_hdr_dat_bst_miso,
reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso
);
......@@ -739,12 +733,10 @@ BEGIN
reg_sdp_info_miso => reg_sdp_info_miso,
-- XSUB
reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso,
reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi,
reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso,
reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso,
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+ 12
− 27
View file @ ec2c7eae
......@@ -206,17 +206,13 @@ ENTITY mmm_lofar2_unb2b_sdp_station IS
reg_stat_hdr_dat_bst_mosi : OUT t_mem_mosi;
reg_stat_hdr_dat_bst_miso : IN t_mem_miso;
-- dp_sync_insert_v2
reg_dp_sync_insert_v2_mosi : OUT t_mem_mosi;
reg_dp_sync_insert_v2_miso : IN t_mem_miso;
-- crosslets_info
reg_crosslets_info_mosi : OUT t_mem_mosi;
reg_crosslets_info_miso : IN t_mem_miso;
-- bsn_scheduler_xsub
reg_bsn_scheduler_xsub_mosi : OUT t_mem_mosi;
reg_bsn_scheduler_xsub_miso : IN t_mem_miso;
-- bsn_sync_scheduler_xsub
reg_bsn_sync_scheduler_xsub_mosi : OUT t_mem_mosi;
reg_bsn_sync_scheduler_xsub_miso : IN t_mem_miso;
-- st_xsq (XST)
ram_st_xsq_mosi : OUT t_mem_mosi;
......@@ -365,14 +361,11 @@ BEGIN
u_mm_file_reg_stat_hdr_info_bst : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_STAT_HDR_DAT_BST")
PORT MAP(mm_rst, mm_clk, reg_stat_hdr_dat_bst_mosi, reg_stat_hdr_dat_bst_miso);
u_mm_file_reg_dp_sync_insert_v2 : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DP_SYNC_INSERT_V2")
PORT MAP(mm_rst, mm_clk, reg_dp_sync_insert_v2_mosi, reg_dp_sync_insert_v2_miso);
u_mm_file_reg_crosslets_info : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_CROSSLETS_INFO")
PORT MAP(mm_rst, mm_clk, reg_crosslets_info_mosi, reg_crosslets_info_miso);
u_mm_file_reg_bsn_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SCHEDULER_XSUB")
PORT MAP(mm_rst, mm_clk, reg_bsn_scheduler_xsub_mosi, reg_bsn_scheduler_xsub_miso);
u_mm_file_reg_bsn_sync_scheduler_xsub : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_SYNC_SCHEDULER_XSUB")
PORT MAP(mm_rst, mm_clk, reg_bsn_sync_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_miso);
u_mm_file_ram_st_xsq : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_ST_XSQ")
PORT MAP(mm_rst, mm_clk, ram_st_xsq_mosi, ram_st_xsq_miso);
......@@ -775,14 +768,6 @@ BEGIN
reg_stat_hdr_dat_bst_read_export => reg_stat_hdr_dat_bst_mosi.rd,
reg_stat_hdr_dat_bst_readdata_export => reg_stat_hdr_dat_bst_miso.rddata(c_word_w-1 DOWNTO 0),
reg_dp_sync_insert_v2_clk_export => OPEN,
reg_dp_sync_insert_v2_reset_export => OPEN,
reg_dp_sync_insert_v2_address_export => reg_dp_sync_insert_v2_mosi.address(c_sdp_reg_dp_sync_insert_v2_addr_w-1 DOWNTO 0),
reg_dp_sync_insert_v2_write_export => reg_dp_sync_insert_v2_mosi.wr,
reg_dp_sync_insert_v2_writedata_export => reg_dp_sync_insert_v2_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_dp_sync_insert_v2_read_export => reg_dp_sync_insert_v2_mosi.rd,
reg_dp_sync_insert_v2_readdata_export => reg_dp_sync_insert_v2_miso.rddata(c_word_w-1 DOWNTO 0),
reg_crosslets_info_clk_export => OPEN,
reg_crosslets_info_reset_export => OPEN,
reg_crosslets_info_address_export => reg_crosslets_info_mosi.address(c_sdp_reg_crosslets_info_addr_w-1 DOWNTO 0),
......@@ -791,13 +776,13 @@ BEGIN
reg_crosslets_info_read_export => reg_crosslets_info_mosi.rd,
reg_crosslets_info_readdata_export => reg_crosslets_info_miso.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_scheduler_xsub_clk_export => OPEN,
reg_bsn_scheduler_xsub_reset_export => OPEN,
reg_bsn_scheduler_xsub_address_export => reg_bsn_scheduler_xsub_mosi.address(c_sdp_reg_bsn_scheduler_xsub_addr_w-1 DOWNTO 0),
reg_bsn_scheduler_xsub_write_export => reg_bsn_scheduler_xsub_mosi.wr,
reg_bsn_scheduler_xsub_writedata_export => reg_bsn_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_scheduler_xsub_read_export => reg_bsn_scheduler_xsub_mosi.rd,
reg_bsn_scheduler_xsub_readdata_export => reg_bsn_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
reg_bsn_sync_scheduler_xsub_clk_export => OPEN,
reg_bsn_sync_scheduler_xsub_reset_export => OPEN,
reg_bsn_sync_scheduler_xsub_address_export => reg_bsn_sync_scheduler_xsub_mosi.address(c_sdp_reg_bsn_sync_scheduler_xsub_addr_w-1 DOWNTO 0),
reg_bsn_sync_scheduler_xsub_write_export => reg_bsn_sync_scheduler_xsub_mosi.wr,
reg_bsn_sync_scheduler_xsub_writedata_export => reg_bsn_sync_scheduler_xsub_mosi.wrdata(c_word_w-1 DOWNTO 0),
reg_bsn_sync_scheduler_xsub_read_export => reg_bsn_sync_scheduler_xsub_mosi.rd,
reg_bsn_sync_scheduler_xsub_readdata_export => reg_bsn_sync_scheduler_xsub_miso.rddata(c_word_w-1 DOWNTO 0),
ram_st_xsq_clk_export => OPEN,
ram_st_xsq_reset_export => OPEN,
......
applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+ 7
− 14
View file @ ec2c7eae
......@@ -329,13 +329,6 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_stat_hdr_dat_bst_reset_export : out std_logic; -- export
reg_stat_hdr_dat_bst_write_export : out std_logic; -- export
reg_stat_hdr_dat_bst_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_dp_sync_insert_v2_address_export : out std_logic_vector(0 downto 0); -- export
reg_dp_sync_insert_v2_clk_export : out std_logic; -- export
reg_dp_sync_insert_v2_read_export : out std_logic; -- export
reg_dp_sync_insert_v2_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_dp_sync_insert_v2_reset_export : out std_logic; -- export
reg_dp_sync_insert_v2_write_export : out std_logic; -- export
reg_dp_sync_insert_v2_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_crosslets_info_address_export : out std_logic_vector(3 downto 0); -- export
reg_crosslets_info_clk_export : out std_logic; -- export
reg_crosslets_info_read_export : out std_logic; -- export
......@@ -343,13 +336,13 @@ PACKAGE qsys_lofar2_unb2b_sdp_station_pkg IS
reg_crosslets_info_reset_export : out std_logic; -- export
reg_crosslets_info_write_export : out std_logic; -- export
reg_crosslets_info_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_scheduler_xsub_address_export : out std_logic_vector(0 downto 0); -- export
reg_bsn_scheduler_xsub_clk_export : out std_logic; -- export
reg_bsn_scheduler_xsub_read_export : out std_logic; -- export
reg_bsn_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_bsn_scheduler_xsub_reset_export : out std_logic; -- export
reg_bsn_scheduler_xsub_write_export : out std_logic; -- export
reg_bsn_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
reg_bsn_sync_scheduler_xsub_address_export : out std_logic_vector(3 downto 0); -- export
reg_bsn_sync_scheduler_xsub_clk_export : out std_logic; -- export
reg_bsn_sync_scheduler_xsub_read_export : out std_logic; -- export
reg_bsn_sync_scheduler_xsub_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
reg_bsn_sync_scheduler_xsub_reset_export : out std_logic; -- export
reg_bsn_sync_scheduler_xsub_write_export : out std_logic; -- export
reg_bsn_sync_scheduler_xsub_writedata_export : out std_logic_vector(31 downto 0); -- export
ram_st_xsq_address_export : out std_logic_vector(13 downto 0); -- export
ram_st_xsq_clk_export : out std_logic; -- export
ram_st_xsq_read_export : out std_logic; -- export
......
applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+ 3
− 4
View file @ ec2c7eae
......@@ -329,10 +329,9 @@ PACKAGE sdp_pkg is
CONSTANT c_sdp_xst_nof_blk_per_sync_min : NATURAL := 19530;
-- XSUB MM address widths
CONSTANT c_sdp_reg_dp_sync_insert_v2_addr_w : NATURAL := 1;
CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
CONSTANT c_sdp_reg_bsn_scheduler_xsub_addr_w : NATURAL := 1;
CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
CONSTANT c_sdp_reg_crosslets_info_addr_w : NATURAL := c_sdp_mm_reg_crosslets_info.adr_w;
CONSTANT c_sdp_reg_bsn_sync_scheduler_xsub_addr_w : NATURAL := 4;
CONSTANT c_sdp_ram_st_xsq_addr_w : NATURAL := ceil_log2(c_sdp_P_sq) + ceil_log2(c_sdp_N_crosslets * c_sdp_X_sq * c_nof_complex * (c_longword_sz/c_word_sz) );
END PACKAGE sdp_pkg;
......
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