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Commit d57ed6b1 authored by Reinier van der Walle's avatar Reinier van der Walle
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replace dp_bsn_scheduler / sync insert with dp_bsn_sync_scheduler in

VHDL
parent ce87e7c0
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1 merge request!144Resolve L2SDP-425
...@@ -54,12 +54,10 @@ ENTITY node_sdp_correlator IS ...@@ -54,12 +54,10 @@ ENTITY node_sdp_correlator IS
mm_rst : IN STD_LOGIC; mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC; mm_clk : IN STD_LOGIC;
reg_dp_bsn_sync_scheduler_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_dp_bsn_sync_scheduler_miso : OUT t_mem_miso; reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso;
reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_crosslets_info_miso : OUT t_mem_miso; reg_crosslets_info_miso : OUT t_mem_miso;
reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_bsn_scheduler_xsub_miso : OUT t_mem_miso;
ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst; ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
ram_st_xsq_miso : OUT t_mem_miso; ram_st_xsq_miso : OUT t_mem_miso;
reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_stat_enable_mosi : IN t_mem_mosi := c_mem_mosi_rst;
...@@ -89,16 +87,12 @@ ARCHITECTURE str OF node_sdp_correlator IS ...@@ -89,16 +87,12 @@ ARCHITECTURE str OF node_sdp_correlator IS
SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst); SIGNAL master_miso_arr : t_mem_miso_arr(0 TO c_nof_masters-1) := (OTHERS=>c_mem_miso_rst);
SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); SIGNAL quant_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL dp_bsn_sync_scheduler_snk_in : t_dp_sosi := c_dp_sosi_rst;
SIGNAL dp_bsn_sync_scheduler_src_out : t_dp_sosi := c_dp_sosi_rst; SIGNAL dp_bsn_sync_scheduler_src_out : t_dp_sosi := c_dp_sosi_rst;
SIGNAL xin_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst; SIGNAL xsel_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL crosslets_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); SIGNAL crosslets_sosi_arr : t_dp_sosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst); SIGNAL crosslets_mosi_arr : t_mem_mosi_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_mosi_rst);
SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst); SIGNAL crosslets_miso_arr : t_mem_miso_arr(g_P_sq-1 DOWNTO 0) := (OTHERS => c_mem_miso_rst);
SIGNAL dp_bsn_sync_scheduler_out_start : STD_LOGIC;
SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0); SIGNAL crosslets_info : STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0);
BEGIN BEGIN
--------------------------------------------------------------- ---------------------------------------------------------------
...@@ -126,42 +120,6 @@ BEGIN ...@@ -126,42 +120,6 @@ BEGIN
); );
END GENERATE; END GENERATE;
---------------------------------------------------------------
-- mmp_dp_bsn_sync_scheduler
---------------------------------------------------------------
dp_bsn_sync_scheduler_snk_in <= quant_sosi_arr(0);
p_bsn_sync : PROCESS(dp_bsn_sync_scheduler_src_out)
BEGIN
xin_sosi_arr <= quant_sosi_arr;
FOR I IN 0 TO c_sdp_P_pfb-1 LOOP
xin_sosi_arr(I).sop <= dp_bsn_sync_scheduler_src_out.sop;
xin_sosi_arr(I).eop <= dp_bsn_sync_scheduler_src_out.eop;
xin_sosi_arr(I).valid <= dp_bsn_sync_scheduler_src_out.valid;
xin_sosi_arr(I).sync <= dp_bsn_sync_scheduler_src_out.sync;
END LOOP;
END PROCESS;
u_mmp_dp_bsn_sync_scheduler : ENTITY dp_lib.mmp_dp_bsn_sync_scheduler
GENERIC MAP (
g_block_size => c_sdp_N_fft,
g_ctrl_interval_size_min => c_sdp_xst_nof_blk_per_sync_min
)
PORT MAP (
dp_rst => dp_rst,
dp_clk => dp_clk,
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mosi => reg_dp_bsn_sync_scheduler_mosi,
reg_miso => reg_dp_bsn_sync_scheduler_miso,
in_sosi => dp_bsn_sync_scheduler_snk_in,
out_sosi => dp_bsn_sync_scheduler_src_out,
out_start => dp_bsn_sync_scheduler_out_start
);
--------------------------------------------------------------- ---------------------------------------------------------------
-- Crosslet Subband Select -- Crosslet Subband Select
--------------------------------------------------------------- ---------------------------------------------------------------
...@@ -173,7 +131,7 @@ BEGIN ...@@ -173,7 +131,7 @@ BEGIN
dp_clk => dp_clk, dp_clk => dp_clk,
dp_rst => dp_rst, dp_rst => dp_rst,
in_sosi_arr => xin_sosi_arr, in_sosi_arr => quant_sosi_arr,
out_sosi => xsel_sosi, out_sosi => xsel_sosi,
mm_rst => mm_rst, mm_rst => mm_rst,
...@@ -182,10 +140,9 @@ BEGIN ...@@ -182,10 +140,9 @@ BEGIN
reg_crosslets_info_mosi => reg_crosslets_info_mosi, reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso, reg_crosslets_info_miso => reg_crosslets_info_miso,
reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso, reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
start_trigger => dp_bsn_sync_scheduler_out_start,
out_crosslets_info => crosslets_info out_crosslets_info => crosslets_info
); );
......
...@@ -41,7 +41,8 @@ USE work.sdp_pkg.ALL; ...@@ -41,7 +41,8 @@ USE work.sdp_pkg.ALL;
ENTITY sdp_crosslets_subband_select IS ENTITY sdp_crosslets_subband_select IS
GENERIC ( GENERIC (
g_N_crosslets : NATURAL := c_sdp_N_crosslets g_N_crosslets : NATURAL := c_sdp_N_crosslets;
g_ctrl_interval_size_min : NATURAL := c_sdp_xst_nof_blk_per_sync_min
); );
PORT ( PORT (
dp_clk : IN STD_LOGIC; dp_clk : IN STD_LOGIC;
...@@ -56,8 +57,8 @@ ENTITY sdp_crosslets_subband_select IS ...@@ -56,8 +57,8 @@ ENTITY sdp_crosslets_subband_select IS
reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst; reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_bsn_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst; reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0) out_crosslets_info : OUT STD_LOGIC_VECTOR(c_sdp_crosslets_info_reg_w-1 DOWNTO 0)
...@@ -96,6 +97,7 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS ...@@ -96,6 +97,7 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS
SIGNAL col_select_miso : t_mem_miso := c_mem_miso_rst; SIGNAL col_select_miso : t_mem_miso := c_mem_miso_rst;
SIGNAL row_select_slv : STD_LOGIC_VECTOR(c_row_select_slv_w-1 DOWNTO 0); SIGNAL row_select_slv : STD_LOGIC_VECTOR(c_row_select_slv_w-1 DOWNTO 0);
SIGNAL dp_bsn_sync_scheduler_src_out_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL col_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0); SIGNAL col_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0);
SIGNAL row_sosi : t_dp_sosi; SIGNAL row_sosi : t_dp_sosi;
...@@ -104,27 +106,27 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS ...@@ -104,27 +106,27 @@ ARCHITECTURE str OF sdp_crosslets_subband_select IS
BEGIN BEGIN
--------------------------------------------------------------- ---------------------------------------------------------------
-- BSN scheduler -- BSN sync scheduler
--------------------------------------------------------------- ---------------------------------------------------------------
u_bsn_scheduler : ENTITY dp_lib.mms_dp_bsn_scheduler u_mmp_dp_bsn_sync_scheduler_arr : ENTITY dp_lib.mmp_dp_bsn_sync_scheduler_arr
GENERIC MAP ( GENERIC MAP (
g_cross_clock_domain => TRUE, g_nof_streams => c_sdp_P_pfb,
g_bsn_w => c_dp_stream_bsn_w g_block_size => c_sdp_N_fft,
g_ctrl_interval_size_min => g_ctrl_interval_size_min
) )
PORT MAP ( PORT MAP (
-- Memory-mapped clock domain dp_rst => dp_rst,
dp_clk => dp_clk,
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
reg_mosi => reg_bsn_scheduler_xsub_mosi, reg_mosi => reg_bsn_sync_scheduler_xsub_mosi,
reg_miso => reg_bsn_scheduler_xsub_miso, reg_miso => reg_bsn_sync_scheduler_xsub_miso,
-- Streaming clock domain in_sosi_arr => in_sosi_arr,
dp_rst => dp_rst, out_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
dp_clk => dp_clk,
snk_in => in_sosi_arr(0), -- only uses eop (= block sync), bsn[] out_start => start_trigger
trigger_out => start_trigger
); );
--------------------------------------------------------------- ---------------------------------------------------------------
...@@ -161,7 +163,7 @@ BEGIN ...@@ -161,7 +163,7 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
p_comb_crosslets_control : PROCESS(r, start_trigger, crosslets_info_reg, in_sosi_arr, col_select_miso) p_comb_crosslets_control : PROCESS(r, start_trigger, crosslets_info_reg, dp_bsn_sync_scheduler_src_out_arr, col_select_miso)
VARIABLE v : t_crosslets_control_reg; VARIABLE v : t_crosslets_control_reg;
-- Use extra variable to simplify col_select_mosi address selection. -- Use extra variable to simplify col_select_mosi address selection.
-- Also using v_offsets instead of v.offsets to clearly indicate we do not only use this variable on the left side but also on the right side of assignments. -- Also using v_offsets instead of v.offsets to clearly indicate we do not only use this variable on the left side but also on the right side of assignments.
...@@ -178,7 +180,8 @@ BEGIN ...@@ -178,7 +180,8 @@ BEGIN
v.row_index := 0; v.row_index := 0;
v.col_index := 0; v.col_index := 0;
v.sync_detected := '0'; -- set sync_detected to 0 in the case that a sync has been detected before the initial start_trigger. v.sync_detected := '0'; -- set sync_detected to 0 in the case that a sync has been detected before the initial start_trigger.
-- start_trigger is active on the eop so we can immediatly reset the offsets/step such that they are used in the next packet.
-- start_trigger is active on the sync so we can immediatly reset the offsets/step such that they are used in the next packet.
-- It is up to the user to schedule the start trigger on a BSN that coincides with a sync interval if that is desired. -- It is up to the user to schedule the start trigger on a BSN that coincides with a sync interval if that is desired.
v.step := TO_UINT(crosslets_info_reg(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w)); v.step := TO_UINT(crosslets_info_reg(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w));
FOR I IN 0 TO g_N_crosslets-1 LOOP FOR I IN 0 TO g_N_crosslets-1 LOOP
...@@ -186,21 +189,18 @@ BEGIN ...@@ -186,21 +189,18 @@ BEGIN
END LOOP; END LOOP;
END IF; END IF;
IF in_sosi_arr(0).sync = '1' THEN -- Do not set sync_detected if start_trigger = 1 because the first sync interval after (re)start
-- already has set the indices for the first interval and we do not want to increase them with the step.
IF dp_bsn_sync_scheduler_src_out_arr(0).sync = '1' AND start_trigger = '0' THEN
v.sync_detected := '1'; v.sync_detected := '1';
END IF; END IF;
IF r.started = '1' THEN -- Once started r.started remains active. IF r.started = '1' THEN -- Once started r.started remains active.
-- add step to offsets -- add step to offsets
IF in_sosi_arr(0).eop = '1' AND r.sync_detected = '1' THEN -- using r.sync_detected to change offsets 1 packet after the sync due to the buffered packet in reorder_col_wide_select IF dp_bsn_sync_scheduler_src_out_arr(0).eop = '1' AND r.sync_detected = '1' THEN -- using r.sync_detected to change offsets 1 packet after the sync due to the buffered packet in reorder_col_wide_select
v.sync_detected := '0'; v.sync_detected := '0';
FOR I IN 0 TO g_N_crosslets-1 LOOP FOR I IN 0 TO g_N_crosslets-1 LOOP
IF start_trigger = '1' THEN
-- Using the crosslets_info_reg directly instead of r.step when start trigger coincides with the current eop as step can have a new value.
v_offsets(I) := r.offsets(I) + TO_UINT(crosslets_info_reg(c_sdp_crosslets_info_reg_w-1 DOWNTO c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w));
ELSE
v_offsets(I) := r.offsets(I) + r.step; v_offsets(I) := r.offsets(I) + r.step;
END IF;
END LOOP; END LOOP;
END IF; END IF;
...@@ -265,7 +265,7 @@ BEGIN ...@@ -265,7 +265,7 @@ BEGIN
col_select_miso => col_select_miso, col_select_miso => col_select_miso,
-- Streaming -- Streaming
input_sosi_arr => in_sosi_arr, input_sosi_arr => dp_bsn_sync_scheduler_src_out_arr,
output_sosi_arr => col_sosi_arr output_sosi_arr => col_sosi_arr
); );
......
...@@ -170,17 +170,13 @@ ENTITY sdp_station IS ...@@ -170,17 +170,13 @@ ENTITY sdp_station IS
---------------------------------------------- ----------------------------------------------
-- XSUB -- XSUB
---------------------------------------------- ----------------------------------------------
-- dp_sync_insert_v2
reg_dp_sync_insert_v2_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_dp_sync_insert_v2_miso : OUT t_mem_miso := c_mem_miso_rst;
-- crosslets_info -- crosslets_info
reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_crosslets_info_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst; reg_crosslets_info_miso : OUT t_mem_miso := c_mem_miso_rst;
-- bsn_scheduler_xsub -- bsn_scheduler_xsub
reg_bsn_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst; reg_bsn_sync_scheduler_xsub_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_bsn_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst; reg_bsn_sync_scheduler_xsub_miso : OUT t_mem_miso := c_mem_miso_rst;
-- st_xsq -- st_xsq
ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst; ram_st_xsq_mosi : IN t_mem_mosi := c_mem_mosi_rst;
...@@ -517,12 +513,10 @@ BEGIN ...@@ -517,12 +513,10 @@ BEGIN
mm_rst => mm_rst, mm_rst => mm_rst,
mm_clk => mm_clk, mm_clk => mm_clk,
reg_dp_sync_insert_v2_mosi => reg_dp_sync_insert_v2_mosi,
reg_dp_sync_insert_v2_miso => reg_dp_sync_insert_v2_miso,
reg_crosslets_info_mosi => reg_crosslets_info_mosi, reg_crosslets_info_mosi => reg_crosslets_info_mosi,
reg_crosslets_info_miso => reg_crosslets_info_miso, reg_crosslets_info_miso => reg_crosslets_info_miso,
reg_bsn_scheduler_xsub_mosi => reg_bsn_scheduler_xsub_mosi, reg_bsn_sync_scheduler_xsub_mosi => reg_bsn_sync_scheduler_xsub_mosi,
reg_bsn_scheduler_xsub_miso => reg_bsn_scheduler_xsub_miso, reg_bsn_sync_scheduler_xsub_miso => reg_bsn_sync_scheduler_xsub_miso,
ram_st_xsq_mosi => ram_st_xsq_mosi, ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso, ram_st_xsq_miso => ram_st_xsq_miso,
......
...@@ -65,7 +65,9 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS ...@@ -65,7 +65,9 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
CONSTANT c_ch_sel_step : NATURAL := 3; -- offset step size to increase per sync interval CONSTANT c_ch_sel_step : NATURAL := 3; -- offset step size to increase per sync interval
CONSTANT c_nof_ch_sel : NATURAL := c_N_crosslets*c_nof_ch_sel_col*c_nof_ch_sel_row; CONSTANT c_nof_ch_sel : NATURAL := c_N_crosslets*c_nof_ch_sel_col*c_nof_ch_sel_row;
CONSTANT scheduled_bsn : NATURAL := 11; CONSTANT c_ctrl_interval_size : NATURAL := c_nof_block_per_sync * c_nof_ch_in;
CONSTANT c_scheduled_bsn : NATURAL := 11;
CONSTANT c_nof_block_dly : NATURAL := c_nof_block_per_sync;
SIGNAL rst : STD_LOGIC; SIGNAL rst : STD_LOGIC;
SIGNAL clk : STD_LOGIC := '1'; SIGNAL clk : STD_LOGIC := '1';
...@@ -83,7 +85,7 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS ...@@ -83,7 +85,7 @@ ARCHITECTURE tb OF tb_sdp_crosslets_subband_select IS
SIGNAL st_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); SIGNAL st_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
SIGNAL exp_sosi : t_dp_sosi := c_dp_sosi_rst; SIGNAL exp_sosi : t_dp_sosi := c_dp_sosi_rst;
SIGNAL bsn : NATURAL := scheduled_bsn-1; SIGNAL bsn : NATURAL := c_scheduled_bsn - c_nof_block_dly;
SIGNAL in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); SIGNAL in_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst);
...@@ -105,8 +107,11 @@ BEGIN ...@@ -105,8 +107,11 @@ BEGIN
proc_common_wait_until_low(mm_clk, rst); proc_common_wait_until_low(mm_clk, rst);
proc_common_wait_some_cycles(mm_clk, 50); -- Give dut some time to start proc_common_wait_some_cycles(mm_clk, 50); -- Give dut some time to start
-- BSN Scheduler -- BSN Scheduler
proc_mem_mm_bus_wr(0, scheduled_bsn, mm_clk, mm_trigger_miso, mm_trigger_mosi); proc_mem_mm_bus_wr(1, c_ctrl_interval_size, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(1, 0, mm_clk, mm_trigger_miso, mm_trigger_mosi); proc_mem_mm_bus_wr(2, c_scheduled_bsn, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(3, 0, mm_clk, mm_trigger_miso, mm_trigger_mosi);
proc_mem_mm_bus_wr(0, 1, mm_clk, mm_trigger_miso, mm_trigger_mosi); --enable
-- crosslet info -- crosslet info
FOR I IN 0 TO c_N_crosslets-1 LOOP FOR I IN 0 TO c_N_crosslets-1 LOOP
...@@ -198,8 +203,8 @@ BEGIN ...@@ -198,8 +203,8 @@ BEGIN
exp_sosi.eop <= '1'; exp_sosi.eop <= '1';
END IF; END IF;
exp_sosi.re <= TO_DP_DSP_DATA( I * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5); exp_sosi.re <= TO_DP_DSP_DATA( (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
exp_sosi.im <= TO_DP_DSP_DATA(1+ I * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5); exp_sosi.im <= TO_DP_DSP_DATA(1+ (I + c_nof_block_dly) * c_nof_ch_in + v_k + c_nof_ch_sel_col*c_ch_sel_offsets(v_offset) + v_col + v_row*2**5);
proc_common_wait_some_cycles(clk, 1); proc_common_wait_some_cycles(clk, 1);
END LOOP; END LOOP;
...@@ -225,7 +230,8 @@ BEGIN ...@@ -225,7 +230,8 @@ BEGIN
u_dut : ENTITY work.sdp_crosslets_subband_select u_dut : ENTITY work.sdp_crosslets_subband_select
GENERIC MAP ( GENERIC MAP (
g_N_crosslets => c_N_crosslets g_N_crosslets => c_N_crosslets,
g_ctrl_interval_size_min => 1
) )
PORT MAP ( PORT MAP (
dp_rst => rst, dp_rst => rst,
...@@ -237,8 +243,8 @@ BEGIN ...@@ -237,8 +243,8 @@ BEGIN
reg_crosslets_info_mosi => mm_mosi, reg_crosslets_info_mosi => mm_mosi,
reg_crosslets_info_miso => mm_miso, reg_crosslets_info_miso => mm_miso,
reg_bsn_scheduler_xsub_mosi => mm_trigger_mosi, reg_bsn_sync_scheduler_xsub_mosi => mm_trigger_mosi,
reg_bsn_scheduler_xsub_miso => mm_trigger_miso, reg_bsn_sync_scheduler_xsub_miso => mm_trigger_miso,
-- Streaming -- Streaming
in_sosi_arr => in_sosi_arr, in_sosi_arr => in_sosi_arr,
......
...@@ -93,6 +93,7 @@ synth_files = ...@@ -93,6 +93,7 @@ synth_files =
src/vhdl/mms_dp_bsn_scheduler.vhd src/vhdl/mms_dp_bsn_scheduler.vhd
src/vhdl/dp_bsn_sync_scheduler.vhd src/vhdl/dp_bsn_sync_scheduler.vhd
src/vhdl/mmp_dp_bsn_sync_scheduler.vhd src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
src/vhdl/dp_bsn_delay.vhd src/vhdl/dp_bsn_delay.vhd
src/vhdl/dp_bsn_align.vhd src/vhdl/dp_bsn_align.vhd
src/vhdl/dp_bsn_align_reg.vhd src/vhdl/dp_bsn_align_reg.vhd
......
...@@ -64,7 +64,7 @@ ENTITY mmp_dp_bsn_sync_scheduler IS ...@@ -64,7 +64,7 @@ ENTITY mmp_dp_bsn_sync_scheduler IS
GENERIC ( GENERIC (
g_bsn_w : NATURAL := c_dp_stream_bsn_w; g_bsn_w : NATURAL := c_dp_stream_bsn_w;
g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2 g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
g_ctrl_interval_size_min : NATURAL := 19530 -- Minimum interval size to use if MM write interval size is set too small. g_ctrl_interval_size_min : NATURAL := 1 -- Minimum interval size to use if MM write interval size is set too small.
); );
PORT ( PORT (
-- Clocks and reset -- Clocks and reset
......
-- --------------------------------------------------------------------------
-- Copyright 2021
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- --------------------------------------------------------------------------
--
-- Author : R. vd Walle
-- Purpose : Array wrapper for mmp_dp_bsn_sync_scheduler.vhd
-- Description: This component is wrapper that uses mmp_dp_bsn_sync_scheduler.vhd
-- with input 0 to determine the streaming control (sync, sop, eop, valid). So
-- it is assumed that all inputs in in_sosi_arr have identical control signals.
--
-- Remarks: See mmp_dp_bsn_sync_scheduler.vhd
LIBRARY IEEE, common_lib;
USE IEEE.STD_LOGIC_1164.ALL;
USE common_lib.common_pkg.ALL;
USE common_lib.common_mem_pkg.ALL;
USE work.dp_stream_pkg.ALL;
ENTITY mmp_dp_bsn_sync_scheduler_arr IS
GENERIC (
g_nof_streams : POSITIVE := 1;
g_bsn_w : NATURAL := c_dp_stream_bsn_w;
g_block_size : NATURAL := 256; -- = number of data valid per BSN block, must be >= 2
g_ctrl_interval_size_min : NATURAL := 1 -- Minimum interval size to use if MM write interval size is set too small.
);
PORT (
-- Clocks and reset
mm_rst : IN STD_LOGIC;
mm_clk : IN STD_LOGIC;
dp_rst : IN STD_LOGIC;
dp_clk : IN STD_LOGIC;
-- MM control
reg_mosi : IN t_mem_mosi := c_mem_mosi_rst;
reg_miso : OUT t_mem_miso;
-- Streaming
in_sosi_arr : IN t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
out_sosi_arr : OUT t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
out_start : OUT STD_LOGIC;
out_enable : OUT STD_LOGIC
);
END mmp_dp_bsn_sync_scheduler_arr;
ARCHITECTURE str OF mmp_dp_bsn_sync_scheduler_arr IS
CONSTANT c_pipeline : NATURAL := 1;
SIGNAL single_src_out : t_dp_sosi;
SIGNAL in_sosi_arr_piped : t_dp_sosi_arr(g_nof_streams-1 DOWNTO 0);
BEGIN
-- dp_bsn_sync_scheduler
u_mmp_dp_bsn_sync_scheduler : ENTITY work.mmp_dp_bsn_sync_scheduler
GENERIC MAP (
g_bsn_w => g_bsn_w,
g_block_size => g_block_size,
g_ctrl_interval_size_min => g_ctrl_interval_size_min
)
PORT MAP (
dp_rst => dp_rst,
dp_clk => dp_clk,
mm_rst => mm_rst,
mm_clk => mm_clk,
reg_mosi => reg_mosi,
reg_miso => reg_miso,
in_sosi => in_sosi_arr(0),
out_sosi => single_src_out,
out_start => out_start,
out_enable => out_enable
);
-- Pipeline in_sosi_arr to compensate for the latency in mmp_dp_bsn_sync_scheduler
u_dp_pipeline_arr : ENTITY work.dp_pipeline_arr
GENERIC MAP (
g_nof_streams => g_nof_streams,
g_pipeline => c_pipeline
)
PORT MAP (
rst => dp_rst,
clk => dp_clk,
-- ST sink
snk_in_arr => in_sosi_arr,
-- ST source
src_out_arr => in_sosi_arr_piped
);
p_streams : PROCESS(in_sosi_arr_piped, single_src_out)
BEGIN
out_sosi_arr <= in_sosi_arr_piped;
FOR I IN 0 TO g_nof_streams-1 LOOP
out_sosi_arr(I).sop <= single_src_out.sop;
out_sosi_arr(I).eop <= single_src_out.eop;
out_sosi_arr(I).valid <= single_src_out.valid;
out_sosi_arr(I).sync <= single_src_out.sync;
END LOOP;
END PROCESS;
END str;
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