removed hdlilb.cfg

applications/compaan/designs/compaan_unb1_dp_offload/hdllib.cfg

-hdl_lib_name = compaan_unb1_dp_offload
-hdl_library_clause_name = compaan_unb1_dp_offload_lib
-hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag ipcore
-hdl_lib_technology = ip_stratixiv
-
-synth_files =
-    $HDL_BUILD_DIR/quartus/compaan_unb1_dp_offload/sopc_compaan_unb1_dp_offload.vhd
-    src/vhdl/pkg_signals.vhd
-    src/vhdl/compaan_design.vhd
-    src/vhdl/mmm_compaan_unb1_dp_offload.vhd
-    src/vhdl/compaan_unb1_dp_offload.vhd
-
-test_bench_files = 
-    tb/vhdl/tb_compaan_unb1_dp_offload.vhd
-    tb/vhdl/tb_compaan_unb1_dp_offload_2ins.vhd
-    tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
-    tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
-
-    
-

applications/compaan/designs/compaan_unb1_dp_offload/src/vhdl/mmm_compaan_unb1_dp_offload.vhd

@@ -167,7 +167,7 @@ ARCHITECTURE str OF mmm_compaan_unb1_dp_offload IS
   CONSTANT c_reg_compaan_w                         : NATURAL := 19;
 
   -- Simulation
-  CONSTANT c_mm_clk_period                         : TIME := 500 ps; --8 ns; 
+  CONSTANT c_mm_clk_period                         : TIME := 8 ns; --500 ps; --8 ns; 
   CONSTANT c_tech_tse_clk_period                   : TIME := 8 ns;
   CONSTANT c_dp_clk_period                         : TIME := 5 ns;