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Commit f832d3e6 authored by Pepping's avatar Pepping
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-Removed "mother" hdllib.cfg. There are ONLY revisions to work with.

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applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_bg/compaan_unb1_dp_offload_bg.vhd
+ 2
− 2
View file @ f832d3e6
......@@ -24,7 +24,7 @@
-- . Create a block generator and databuffer in a node.
-- Description:
LIBRARY IEEE, unb1_board_lib, compaan_unb1_dp_offload_lib;
LIBRARY IEEE, unb1_board_lib;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
......@@ -69,7 +69,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload_bg IS
BEGIN
u_revision : ENTITY compaan_unb1_dp_offload_lib.compaan_unb1_dp_offload
u_revision : ENTITY work.compaan_unb1_dp_offload
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
......
applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_bg/hdllib.cfg
+ 13
− 5
View file @ f832d3e6
hdl_lib_name = compaan_unb1_dp_offload_bg
hdl_library_clause_name = compaan_unb1_dp_offload_bg_lib
hdl_lib_uses_synth = unb1_board compaan_unb1_dp_offload
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag ipcore
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
......@@ -9,9 +8,19 @@ build_dir_synth = $HDL_BUILD_DIR
synth_top_level_entity =
synth_files = compaan_unb1_dp_offload_bg.vhd
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_bg/sopc_compaan_unb1_dp_offload.vhd
../../src/vhdl/pkg_signals.vhd
../../src/vhdl/compaan_design.vhd
../../src/vhdl/mmm_compaan_unb1_dp_offload.vhd
../../src/vhdl/compaan_unb1_dp_offload.vhd
compaan_unb1_dp_offload_bg.vhd
test_bench_files =
../../tb/vhdl/tb_compaan_unb1_dp_offload.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_2ins.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
quartus_copy_files = ../../quartus/sopc_compaan_unb1_dp_offload.sopc .
......@@ -21,5 +30,4 @@ quartus_qsf_files =
quartus_tcl_files =
../../quartus/compaan_unb1_dp_offload_pins.tcl
quartus_qip_files =
$HDL_BUILD_DIR/quartus/compaan_unb1_dp_offload_bg/sopc_compaan_unb1_dp_offload.qip
quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_bg/sopc_compaan_unb1_dp_offload.qip
applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_co/compaan_unb1_dp_offload_co.vhd
+ 2
− 2
View file @ f832d3e6
......@@ -24,7 +24,7 @@
-- . Creates image with compaan functionality
-- Description:
LIBRARY IEEE, unb1_board_lib, compaan_unb1_dp_offload_lib;
LIBRARY IEEE, unb1_board_lib;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
......@@ -69,7 +69,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload_co IS
BEGIN
u_revision : ENTITY compaan_unb1_dp_offload_lib.compaan_unb1_dp_offload
u_revision : ENTITY work.compaan_unb1_dp_offload
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
......
applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_co/hdllib.cfg
+ 13
− 5
View file @ f832d3e6
hdl_lib_name = compaan_unb1_dp_offload_co
hdl_library_clause_name = compaan_unb1_dp_offload_co_lib
hdl_lib_uses_synth = unb1_board compaan_unb1_dp_offload
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag ipcore
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
......@@ -9,9 +8,19 @@ build_dir_synth = $HDL_BUILD_DIR
synth_top_level_entity =
synth_files = compaan_unb1_dp_offload_co.vhd
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_co/sopc_compaan_unb1_dp_offload.vhd
../../src/vhdl/pkg_signals.vhd
../../src/vhdl/compaan_design.vhd
../../src/vhdl/mmm_compaan_unb1_dp_offload.vhd
../../src/vhdl/compaan_unb1_dp_offload.vhd
compaan_unb1_dp_offload_co.vhd
test_bench_files =
../../tb/vhdl/tb_compaan_unb1_dp_offload.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_2ins.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
quartus_copy_files = ../../quartus/sopc_compaan_unb1_dp_offload.sopc .
......@@ -21,5 +30,4 @@ quartus_qsf_files =
quartus_tcl_files =
../../quartus/compaan_unb1_dp_offload_pins.tcl
quartus_qip_files =
$HDL_BUILD_DIR/quartus/compaan_unb1_dp_offload_co/sopc_compaan_unb1_dp_offload.qip
quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_co/sopc_compaan_unb1_dp_offload.qip
applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_lb/compaan_unb1_dp_offload_lb.vhd
+ 2
− 2
View file @ f832d3e6
......@@ -25,7 +25,7 @@
-- Loopback.
-- Description:
LIBRARY IEEE, unb1_board_lib, compaan_unb1_dp_offload_lib;
LIBRARY IEEE, unb1_board_lib;
use IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE unb1_board_lib.unb1_board_pkg.ALL;
......@@ -70,7 +70,7 @@ ARCHITECTURE str OF compaan_unb1_dp_offload_lb IS
BEGIN
u_revision : ENTITY compaan_unb1_dp_offload_lib.compaan_unb1_dp_offload
u_revision : ENTITY work.compaan_unb1_dp_offload
GENERIC MAP (
g_design_name => g_design_name,
g_design_note => g_design_note,
......
applications/compaan/designs/compaan_unb1_dp_offload/revisions/compaan_unb1_dp_offload_lb/hdllib.cfg
+ 13
− 5
View file @ f832d3e6
hdl_lib_name = compaan_unb1_dp_offload_lb
hdl_library_clause_name = compaan_unb1_dp_offload_lb_lib
hdl_lib_uses_synth = unb1_board compaan_unb1_dp_offload
hdl_lib_uses_synth = common unb1_board dp eth tech_tse diag ipcore
hdl_lib_technology = ip_stratixiv
build_dir_sim = $HDL_BUILD_DIR
......@@ -9,9 +8,19 @@ build_dir_synth = $HDL_BUILD_DIR
synth_top_level_entity =
synth_files = compaan_unb1_dp_offload_lb.vhd
synth_files =
$HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_lb/sopc_compaan_unb1_dp_offload.vhd
../../src/vhdl/pkg_signals.vhd
../../src/vhdl/compaan_design.vhd
../../src/vhdl/mmm_compaan_unb1_dp_offload.vhd
../../src/vhdl/compaan_unb1_dp_offload.vhd
compaan_unb1_dp_offload_lb.vhd
test_bench_files =
../../tb/vhdl/tb_compaan_unb1_dp_offload.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_2ins.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_lb.vhd
../../tb/vhdl/tb_compaan_unb1_dp_offload_bg_co.vhd
quartus_copy_files = ../../quartus/sopc_compaan_unb1_dp_offload.sopc .
......@@ -21,5 +30,4 @@ quartus_qsf_files =
quartus_tcl_files =
../../quartus/compaan_unb1_dp_offload_pins.tcl
quartus_qip_files =
$HDL_BUILD_DIR/quartus/compaan_unb1_dp_offload_lb/sopc_compaan_unb1_dp_offload.qip
quartus_qip_files = $HDL_BUILD_DIR/unb1/quartus/compaan_unb1_dp_offload_lb/sopc_compaan_unb1_dp_offload.qip
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