Skip to content
Snippets Groups Projects
Commit eb24be54 authored by Pieter Donker's avatar Pieter Donker
Browse files

Merge branch 'RTSD-154' into 'master' 

Resolve RTSD-154

Closes RTSD-154

See merge request desp/hdl!345
parents c584762f e3e65fb0
No related branches found
No related tags found
1 merge request!345Resolve RTSD-154
Pipeline #56093 passed
Stage: linting
Hide whitespace changes
Inline Side-by-side
Showing
with 0 additions and 154 deletions
applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
+ 0
− 4
View file @ eb24be54
......@@ -64,7 +64,6 @@ entity pfb2 is
end pfb2;
architecture str of pfb2 is
constant c_nof_coeffs : natural := g_pfs_nof_taps * g_nof_points;
signal pfs_in_dat_x : std_logic_vector(g_pfs_in_dat_w - 1 downto 0);
......@@ -80,9 +79,7 @@ architecture str of pfb2 is
signal pft_out_dat_im : std_logic_vector(g_pft_out_dat_w - 1 downto 0);
signal pft_out_val : std_logic;
signal pft_out_sync : std_logic;
begin
-- Delay in_sosi data with respect to sync to fit LOFAR1 sync timing
pfs_in_dat_x <= in_sosi.re(g_pfs_in_dat_w - 1 downto 0) when rising_edge(dp_clk);
pfs_in_dat_y <= in_sosi.im(g_pfs_in_dat_w - 1 downto 0) when rising_edge(dp_clk);
......@@ -153,5 +150,4 @@ begin
out_sosi.im <= RESIZE_DP_DSP_DATA(pft_out_dat_im);
out_sosi.valid <= pft_out_val;
out_sosi.sync <= pft_out_sync when rising_edge(dp_clk);
end str;
applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
+ 0
− 7
View file @ eb24be54
......@@ -73,16 +73,13 @@ entity pfb2_unit is
end pfb2_unit;
architecture str of pfb2_unit is
constant c_nof_stats : natural := g_nof_points; -- SST X and SST Y are interleaved for PFT_MODE_REAL2
signal ram_st_sst_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal ram_st_sst_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
signal pft_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
begin
---------------------------------------------------------------
-- Polyphase Filterbanks
---------------------------------------------------------------
......@@ -150,8 +147,4 @@ begin
end generate;
out_sosi_arr <= pft_sosi_arr;
end str;
applications/lofar1/RSP/pfs/src/vhdl/pfs(empty).vhd
+ 0
− 1
View file @ eb24be54
architecture empty of pfs is
begin
end empty;
applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
+ 0
− 10
View file @ eb24be54
......@@ -4,7 +4,6 @@ library common_lib;
use common_lib.common_pkg.all;
architecture str of pfs is
constant c_nof_bands_w : natural := ceil_log2(g_nof_bands);
constant c_nof_fir_taps : natural := g_nof_taps / g_nof_bands;
constant c_nof_fir_taps_w : natural := ceil_log2(c_nof_fir_taps);
......@@ -17,9 +16,7 @@ architecture str of pfs is
signal taps_out_x : std_logic_vector(g_in_dat_w * c_nof_fir_taps - 1 downto 0);
signal taps_out_y : std_logic_vector(g_in_dat_w * c_nof_fir_taps - 1 downto 0);
signal coefs : std_logic_vector(g_coef_dat_w * c_nof_fir_taps - 1 downto 0);
begin
ctrl : entity pfs_lib.pfs_ctrl
generic map (
g_nof_bands_w => c_nof_bands_w,
......@@ -46,7 +43,6 @@ begin
out_sync => out_sync
);
firx : entity pfs_lib.pfs_filter
generic map (
g_coef_w => g_coef_dat_w,
......@@ -61,7 +57,6 @@ begin
result => out_dat_x
);
firy : entity pfs_lib.pfs_filter
generic map (
g_coef_w => g_coef_dat_w,
......@@ -76,7 +71,6 @@ begin
result => out_dat_y
);
tapsbufx : entity pfs_lib.pfs_tapsbuf
generic map (
g_data_w => g_in_dat_w * c_nof_fir_taps,
......@@ -93,7 +87,6 @@ begin
rst => rst
);
tapsbufy : entity pfs_lib.pfs_tapsbuf
generic map (
g_data_w => g_in_dat_w * c_nof_fir_taps,
......@@ -110,7 +103,6 @@ begin
rst => rst
);
coefsbuf : entity pfs_lib.pfs_coefsbuf
generic map (
g_data_w => g_coef_dat_w * c_nof_fir_taps,
......@@ -123,6 +115,4 @@ begin
clk => clk,
rst => rst
);
end str;
applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
+ 0
− 11
View file @ eb24be54
......@@ -52,9 +52,7 @@ entity pfs is
);
end pfs;
architecture str of pfs is
constant c_nof_bands_w : natural := ceil_log2(g_nof_bands);
constant c_nof_fir_taps : natural := g_nof_taps / g_nof_bands;
constant c_nof_fir_taps_w : natural := ceil_log2(c_nof_fir_taps);
......@@ -67,9 +65,7 @@ architecture str of pfs is
signal taps_out_x : std_logic_vector(g_in_dat_w * c_nof_fir_taps - 1 downto 0);
signal taps_out_y : std_logic_vector(g_in_dat_w * c_nof_fir_taps - 1 downto 0);
signal coefs : std_logic_vector(g_coef_dat_w * c_nof_fir_taps - 1 downto 0);
begin
ctrl : entity work.pfs_ctrl
generic map (
g_nof_bands_w => c_nof_bands_w,
......@@ -96,7 +92,6 @@ begin
out_sync => out_sync
);
firx : entity work.pfs_filter
generic map (
g_coef_w => g_coef_dat_w,
......@@ -111,7 +106,6 @@ begin
result => out_dat_x
);
firy : entity work.pfs_filter
generic map (
g_coef_w => g_coef_dat_w,
......@@ -126,7 +120,6 @@ begin
result => out_dat_y
);
tapsbufx : entity work.pfs_tapsbuf
generic map (
g_data_w => g_in_dat_w * c_nof_fir_taps,
......@@ -143,7 +136,6 @@ begin
rst => rst
);
tapsbufy : entity work.pfs_tapsbuf
generic map (
g_data_w => g_in_dat_w * c_nof_fir_taps,
......@@ -160,7 +152,6 @@ begin
rst => rst
);
coefsbuf : entity work.pfs_coefsbuf
generic map (
g_data_w => g_coef_dat_w * c_nof_fir_taps,
......@@ -174,6 +165,4 @@ begin
clk => clk,
rst => rst
);
end str;
applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
+ 0
− 8
View file @ eb24be54
......@@ -3,17 +3,13 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_mem_pkg.all;
architecture str of pfs_coefsbuf is
constant c_coefs_rom : t_c_mem := (latency => 2,
adr_w => g_addr_w,
dat_w => g_data_w,
nof_dat => g_nof_coefs, -- <= 2**g_addr_w
init_sl => '0');
begin
rom : entity common_lib.common_rom
generic map (
g_ram => c_coefs_rom,
......@@ -26,8 +22,4 @@ begin
rd_adr => addr,
rd_dat => data
);
end str;
applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
+ 0
− 8
View file @ eb24be54
......@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
architecture stratix of pfs_coefsbuf is
component altsyncram
generic (
operation_mode : string;
......@@ -28,9 +26,7 @@ architecture stratix of pfs_coefsbuf is
q_a : out std_logic_vector(g_data_w - 1 downto 0)
);
end component;
begin
rom : altsyncram
generic map (
operation_mode => "ROM",
......@@ -52,8 +48,4 @@ begin
address_a => addr,
q_a => data
);
end stratix;
applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
+ 0
− 6
View file @ eb24be54
......@@ -28,7 +28,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_mem_pkg.all;
entity pfs_coefsbuf is
generic (
g_data_w : natural;
......@@ -45,17 +44,13 @@ entity pfs_coefsbuf is
);
end pfs_coefsbuf;
architecture str of pfs_coefsbuf is
constant c_coefs_rom : t_c_mem := (latency => 2,
adr_w => g_addr_w,
dat_w => g_data_w,
nof_dat => g_nof_coefs, -- <= 2**g_addr_w
init_sl => '0');
begin
rom : entity common_lib.common_rom
generic map (
g_ram => c_coefs_rom,
......@@ -67,5 +62,4 @@ begin
rd_adr => addr,
rd_dat => data
);
end str;
applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
+ 0
− 6
View file @ eb24be54
......@@ -2,18 +2,14 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture rtl of pfs_combine is
signal i_out_dat_x : std_logic_vector(out_dat_x'range);
signal nxt_out_dat_x : std_logic_vector(out_dat_x'range);
signal i_out_dat_y : std_logic_vector(out_dat_y'range);
signal nxt_out_dat_y : std_logic_vector(out_dat_y'range);
signal nxt_out_val : std_logic;
signal nxt_out_sync : std_logic;
begin
out_dat_x <= i_out_dat_x;
out_dat_y <= i_out_dat_y;
......@@ -35,7 +31,6 @@ begin
end if;
end process;
select_value : process (i_out_dat_x, i_out_dat_y, in_val, in_dat_x, in_dat_y,
in_sync)
begin
......@@ -53,5 +48,4 @@ begin
end if;
end loop;
end process;
end rtl;
applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
+ 0
− 2
View file @ eb24be54
library IEEE;
use IEEE.std_logic_1164.all;
entity pfs_combine is
generic (
g_nof_fir : integer;
......@@ -20,4 +19,3 @@ entity pfs_combine is
rst : in std_logic
);
end pfs_combine;
applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
+ 0
− 9
View file @ eb24be54
......@@ -2,9 +2,7 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
architecture rtl of pfs_ctrl is
-- The number of cycles that should be waited until the result that comes out
-- of the MAC block is the valid result. The ctrl block will generate a valid
-- pulse.
......@@ -23,9 +21,7 @@ architecture rtl of pfs_ctrl is
signal nxt_rdval : std_logic_vector(rdval'range);
signal i_taps_wraddr : std_logic_vector(taps_wraddr'range);
signal nxt_taps_wraddr : std_logic_vector(taps_wraddr'range);
begin
-- Output signals.
taps_rdaddr <= i_taps_rdaddr;
taps_wraddr <= i_taps_wraddr;
......@@ -59,7 +55,6 @@ begin
end if;
end process;
read_address_gen : process (restart, i_taps_rdaddr, in_val_reg, rdval)
begin
nxt_taps_rdaddr <= std_logic_vector(unsigned(i_taps_rdaddr) + 1);
......@@ -75,7 +70,6 @@ begin
end if;
end process;
write_control : process (restart, i_taps_wraddr, taps_in_x, taps_in_y, in_x_reg, rdval,
in_y_reg)
begin
......@@ -95,7 +89,4 @@ begin
taps_wren <= '1';
end if;
end process;
end rtl;
applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
+ 0
− 8
View file @ eb24be54
......@@ -27,7 +27,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pfs_ctrl is
generic (
g_nof_bands_w : natural;
......@@ -55,9 +54,7 @@ entity pfs_ctrl is
);
end pfs_ctrl;
architecture rtl of pfs_ctrl is
-- The number of cycles that should be waited until the result that comes out
-- of the MAC block is the valid result. The ctrl block will generate a valid
-- pulse.
......@@ -76,9 +73,7 @@ architecture rtl of pfs_ctrl is
signal nxt_rdval : std_logic_vector(rdval'range);
signal i_taps_wraddr : std_logic_vector(taps_wraddr'range);
signal nxt_taps_wraddr : std_logic_vector(taps_wraddr'range);
begin
-- Output signals.
taps_rdaddr <= i_taps_rdaddr;
taps_wraddr <= i_taps_wraddr;
......@@ -112,7 +107,6 @@ begin
end if;
end process;
read_address_gen : process (restart, i_taps_rdaddr, in_val_reg, rdval)
begin
nxt_taps_rdaddr <= std_logic_vector(unsigned(i_taps_rdaddr) + 1);
......@@ -128,7 +122,6 @@ begin
end if;
end process;
write_control : process (restart, i_taps_wraddr, taps_in_x, taps_in_y, in_x_reg, rdval,
in_y_reg)
begin
......@@ -148,5 +141,4 @@ begin
taps_wren <= '1';
end if;
end process;
end rtl;
applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
+ 0
− 8
View file @ eb24be54
......@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
architecture rtl of pfs_filter is
type type_res is array (0 to 7) of std_logic_vector(g_coef_w + g_taps_w + 1 - 1 downto 0);
signal res : type_res;
......@@ -16,9 +14,7 @@ architecture rtl of pfs_filter is
signal add_a : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_b : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_c : std_logic_vector(g_coef_w + g_taps_w + 4 - 1 downto 0);
begin
registers : process (clk)
begin
if rising_edge(clk) then
......@@ -28,7 +24,6 @@ begin
end if;
end process;
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
-- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
......@@ -62,7 +57,4 @@ begin
res_3 <= std_logic_vector(resize(signed(res(6)),res_0'length) + resize(signed(res(7)),res_0'length));
end if;
end process;
end rtl;
applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
+ 0
− 12
View file @ eb24be54
......@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
architecture stratix of pfs_filter is
component altmult_add
generic (
input_register_b2 : string := "CLOCK0";
......@@ -79,7 +77,6 @@ architecture stratix of pfs_filter is
);
end component;
signal res_0 : std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0);
signal res_1 : std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0);
signal res_2 : std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0);
......@@ -87,9 +84,7 @@ architecture stratix of pfs_filter is
signal add_a : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_b : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_c : std_logic_vector(g_coef_w + g_taps_w + 4 - 1 downto 0);
begin
registers : process (clk, rst)
begin
if rst = '1' then
......@@ -103,11 +98,9 @@ begin
end if;
end process;
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
-- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
ALTMULT_ADD_0 : altmult_add
port map (
dataa => taps(47 downto 0),
......@@ -117,7 +110,6 @@ begin
result => res_0
);
ALTMULT_ADD_1 : altmult_add
port map (
dataa => taps(95 downto 48),
......@@ -136,7 +128,6 @@ begin
result => res_2
);
ALTMULT_ADD_3 : altmult_add
port map (
dataa => taps(191 downto 144),
......@@ -145,7 +136,4 @@ begin
aclr3 => rst,
result => res_3
);
end stratix;
applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
+ 0
− 7
View file @ eb24be54
......@@ -28,7 +28,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
entity pfs_filter is
generic (
g_coef_w : natural;
......@@ -44,9 +43,7 @@ entity pfs_filter is
);
end pfs_filter;
architecture rtl of pfs_filter is
type type_res is array (0 to 7) of std_logic_vector(g_coef_w + g_taps_w + 1 - 1 downto 0);
signal res : type_res;
......@@ -57,9 +54,7 @@ architecture rtl of pfs_filter is
signal add_a : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_b : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_c : std_logic_vector(g_coef_w + g_taps_w + 4 - 1 downto 0);
begin
registers : process (clk)
begin
if rising_edge(clk) then
......@@ -69,7 +64,6 @@ begin
end if;
end process;
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
-- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
......@@ -103,5 +97,4 @@ begin
res_3 <= std_logic_vector(resize(signed(res(6)),res_0'length) + resize(signed(res(7)),res_0'length));
end if;
end process;
end rtl;
applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
+ 0
− 14
View file @ eb24be54
......@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
library common_lib;
use common_lib.common_pkg.all;
architecture str of pfs_fir is
constant c_nof_taps_w : natural := ceil_log2(g_nof_taps);
constant c_nof_prefilter_w : natural := ceil_log2(g_nof_prefilter);
constant c_nof_coefs : natural := g_nof_prefilter * g_nof_taps;
......@@ -25,10 +23,7 @@ architecture str of pfs_fir is
signal coefs_rden : std_logic;
signal res_clr : std_logic;
signal i_res_val : std_logic;
begin
ctrl : entity pfs_lib.pfs_fir_ctrl
generic map (
g_nof_prefilter => g_nof_prefilter,
......@@ -57,7 +52,6 @@ begin
result_sync => res_sync
);
mac_hor : entity pfs_lib.pfs_fir_mac
generic map (
g_a_in_w => g_in_dat_w,
......@@ -76,7 +70,6 @@ begin
result => res_hor
);
mac_ver : entity pfs_lib.pfs_fir_mac
generic map (
g_a_in_w => g_in_dat_w,
......@@ -95,7 +88,6 @@ begin
result => res_ver
);
coefsbuf_0 : if g_fir_nr = 0 generate
coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
generic map (
......@@ -114,7 +106,6 @@ begin
);
end generate;
coefsbuf_N : if g_fir_nr > 0 generate
coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
generic map (
......@@ -133,7 +124,6 @@ begin
);
end generate;
tapsbuf_hor : entity pfs_lib.pfs_fir_tapsbuf
generic map (
g_data_w => g_in_dat_w,
......@@ -151,7 +141,6 @@ begin
rst => rst
);
tapsbuf_ver : entity pfs_lib.pfs_fir_tapsbuf
generic map (
g_data_w => g_in_dat_w,
......@@ -170,7 +159,4 @@ begin
);
res_val <= i_res_val;
end str;
applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
+ 0
− 3
View file @ eb24be54
......@@ -2,7 +2,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pfs_fir is
generic (
g_in_dat_w : natural;
......@@ -28,5 +27,3 @@ entity pfs_fir is
res_sync : out std_logic
);
end pfs_fir;
applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
+ 0
− 8
View file @ eb24be54
......@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
architecture stratix of pfs_fir_coefsbuf is
component altsyncram
generic (
operation_mode : string;
......@@ -28,9 +26,7 @@ architecture stratix of pfs_fir_coefsbuf is
q_a : out std_logic_vector(g_data_w - 1 downto 0)
);
end component;
begin
rom : altsyncram
generic map (
operation_mode => "ROM",
......@@ -52,8 +48,4 @@ begin
address_a => addr,
q_a => data
);
end stratix;
applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
+ 0
− 2
View file @ eb24be54
......@@ -17,5 +17,3 @@ entity pfs_fir_coefsbuf is
rst : in std_logic
);
end pfs_fir_coefsbuf;
applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
+ 0
− 20
View file @ eb24be54
......@@ -2,9 +2,7 @@ library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of pfs_fir_ctrl is
-- The number of cycles that should be waited until the result that comes out
-- of the MAC block is the valid result. The ctrl block will generate a valid
-- pulse.
......@@ -13,13 +11,11 @@ architecture rtl of pfs_fir_ctrl is
-- start with the next FIR calculation.
constant c_mac_clr_delay : integer := 4;
type fir_state_enum is (
idle,
calc
);
signal fir_state : fir_state_enum;
signal nxt_fir_state : fir_state_enum;
signal taps_cnt : std_logic_vector(g_nof_taps_w - 1 downto 0);
......@@ -46,9 +42,7 @@ architecture rtl of pfs_fir_ctrl is
signal sync_delay : std_logic_vector(c_mac_res_delay + g_nof_taps * 2 - 1 downto 0);
signal nxt_sync_delay : std_logic_vector(sync_delay'range);
signal last_tap : std_logic;
begin
-- Output signals.
result_val <= mac_res_delay(mac_res_delay'high);
result_sync <= sync_delay(sync_delay'high);
......@@ -58,7 +52,6 @@ begin
sample_data_ver <= i_sample_data_ver;
sample_addr <= i_sample_addr;
registers_proc : process (clk, rst)
begin
if rst = '1' then
......@@ -100,7 +93,6 @@ begin
end if;
end process;
-- The state machine will stay in idle until it receives an input sample. At
-- that time it will start the FIR filter operation. It will return to idle
-- unless another sample is received at the time the calculation is ready.
......@@ -122,13 +114,11 @@ begin
end case;
end process;
-- Pulse when the tap counter reaches it maximum.
last_tap <= '1' when unsigned(taps_cnt) = (g_nof_taps - 1) else '0';
res_clr <= '1' when unsigned(taps_cnt) = c_mac_clr_delay - 1 else '0';
-- Counter that will be used for addressing various RAMs, and to indicate
-- to the state machine when a FIR operation is finished.
tap_counter_proc : process (taps_cnt, input_val, fir_state, last_tap)
......@@ -141,7 +131,6 @@ begin
end if;
end process;
-- Keep track of the current logical FIR operation. This counter will be used
-- for addressing of the memories.
prefilter_counter_proc : process (prefilter_cnt, last_tap)
......@@ -156,7 +145,6 @@ begin
end if;
end process;
-- Generate address and read enable for the coefficient memory.
coefficient_control_proc : process (prefilter_cnt, taps_cnt, fir_state)
begin
......@@ -169,7 +157,6 @@ begin
end if;
end process;
-- Generate write signals for the taps memories. The received samples will
-- be written into this memory at the end of the FIR calculation cycle.
sample_ram_control_proc : process (taps_cnt, input_val, i_sample_data_hor,
......@@ -194,7 +181,6 @@ begin
end if;
end process;
-- Generate read signals for the taps memories. Also, the base address of the
-- current logical FIR operation will be generated here. The base address will
-- change in time to emulate a shift register using memories.
......@@ -216,11 +202,9 @@ begin
end if;
end process;
taps_addr_offset <= std_logic_vector(unsigned(taps_addr_base)
+ unsigned(taps_cnt));
-- The MAC delay register is used to generate a valid pulse for the MAC output
-- when the FIR calculation is done, and to generate a reset pulse to set the
-- intermediate result of the MAC to 0.
......@@ -234,8 +218,4 @@ begin
nxt_sync_delay(0) <= input_sync;
end if;
end process;
end rtl;
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment