diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
index 38d1546d526fbb2b4de0fef765739bf618f7ecb3..7e61500080ecdcf9914fef4f36789b46790da87b 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2.vhd
@@ -64,7 +64,6 @@ entity pfb2 is
end pfb2;
architecture str of pfb2 is
-
constant c_nof_coeffs : natural := g_pfs_nof_taps * g_nof_points;
signal pfs_in_dat_x : std_logic_vector(g_pfs_in_dat_w - 1 downto 0);
@@ -80,9 +79,7 @@ architecture str of pfb2 is
signal pft_out_dat_im : std_logic_vector(g_pft_out_dat_w - 1 downto 0);
signal pft_out_val : std_logic;
signal pft_out_sync : std_logic;
-
begin
-
-- Delay in_sosi data with respect to sync to fit LOFAR1 sync timing
pfs_in_dat_x <= in_sosi.re(g_pfs_in_dat_w - 1 downto 0) when rising_edge(dp_clk);
pfs_in_dat_y <= in_sosi.im(g_pfs_in_dat_w - 1 downto 0) when rising_edge(dp_clk);
@@ -153,5 +150,4 @@ begin
out_sosi.im <= RESIZE_DP_DSP_DATA(pft_out_dat_im);
out_sosi.valid <= pft_out_val;
out_sosi.sync <= pft_out_sync when rising_edge(dp_clk);
-
end str;
diff --git a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
index 776304c928959332102356ed628dd3f9408a48ab..424b49e6e684b57931790f725b8111ca58123d8c 100644
--- a/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
+++ b/applications/lofar1/RSP/pfb2/src/vhdl/pfb2_unit.vhd
@@ -73,16 +73,13 @@ entity pfb2_unit is
end pfb2_unit;
architecture str of pfb2_unit is
-
constant c_nof_stats : natural := g_nof_points; -- SST X and SST Y are interleaved for PFT_MODE_REAL2
signal ram_st_sst_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal ram_st_sst_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
signal pft_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
---------------------------------------------------------------
-- Polyphase Filterbanks
---------------------------------------------------------------
@@ -150,8 +147,4 @@ begin
end generate;
out_sosi_arr <= pft_sosi_arr;
-
end str;
-
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs(empty).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs(empty).vhd
index cfe07966cd68a1d848a753b4886b7466abee36e4..db798f9feb7d11e4bc06bdcf5264f541a7366801 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs(empty).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs(empty).vhd
@@ -1,4 +1,3 @@
architecture empty of pfs is
begin
end empty;
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
index 30b483a481ab2260a990124f057d3ba0bdaea23f..09cb45d5da45fd5f9956ede23c99fc12c3d2e0d4 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs(str).vhd
@@ -4,7 +4,6 @@ library common_lib;
use common_lib.common_pkg.all;
architecture str of pfs is
-
constant c_nof_bands_w : natural := ceil_log2(g_nof_bands);
constant c_nof_fir_taps : natural := g_nof_taps / g_nof_bands;
constant c_nof_fir_taps_w : natural := ceil_log2(c_nof_fir_taps);
@@ -17,9 +16,7 @@ architecture str of pfs is
signal taps_out_x : std_logic_vector(g_in_dat_w * c_nof_fir_taps - 1 downto 0);
signal taps_out_y : std_logic_vector(g_in_dat_w * c_nof_fir_taps - 1 downto 0);
signal coefs : std_logic_vector(g_coef_dat_w * c_nof_fir_taps - 1 downto 0);
-
begin
-
ctrl : entity pfs_lib.pfs_ctrl
generic map (
g_nof_bands_w => c_nof_bands_w,
@@ -46,7 +43,6 @@ begin
out_sync => out_sync
);
-
firx : entity pfs_lib.pfs_filter
generic map (
g_coef_w => g_coef_dat_w,
@@ -61,7 +57,6 @@ begin
result => out_dat_x
);
-
firy : entity pfs_lib.pfs_filter
generic map (
g_coef_w => g_coef_dat_w,
@@ -76,7 +71,6 @@ begin
result => out_dat_y
);
-
tapsbufx : entity pfs_lib.pfs_tapsbuf
generic map (
g_data_w => g_in_dat_w * c_nof_fir_taps,
@@ -93,7 +87,6 @@ begin
rst => rst
);
-
tapsbufy : entity pfs_lib.pfs_tapsbuf
generic map (
g_data_w => g_in_dat_w * c_nof_fir_taps,
@@ -110,7 +103,6 @@ begin
rst => rst
);
-
coefsbuf : entity pfs_lib.pfs_coefsbuf
generic map (
g_data_w => g_coef_dat_w * c_nof_fir_taps,
@@ -123,6 +115,4 @@ begin
clk => clk,
rst => rst
);
-
end str;
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
index 3a59bc50333e71677c6b5e44b78d2406babb119e..ffdeb470a07fcd58c59d2c230f970b5e9fe0af0f 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs.vhd
@@ -52,9 +52,7 @@ entity pfs is
);
end pfs;
-
architecture str of pfs is
-
constant c_nof_bands_w : natural := ceil_log2(g_nof_bands);
constant c_nof_fir_taps : natural := g_nof_taps / g_nof_bands;
constant c_nof_fir_taps_w : natural := ceil_log2(c_nof_fir_taps);
@@ -67,9 +65,7 @@ architecture str of pfs is
signal taps_out_x : std_logic_vector(g_in_dat_w * c_nof_fir_taps - 1 downto 0);
signal taps_out_y : std_logic_vector(g_in_dat_w * c_nof_fir_taps - 1 downto 0);
signal coefs : std_logic_vector(g_coef_dat_w * c_nof_fir_taps - 1 downto 0);
-
begin
-
ctrl : entity work.pfs_ctrl
generic map (
g_nof_bands_w => c_nof_bands_w,
@@ -96,7 +92,6 @@ begin
out_sync => out_sync
);
-
firx : entity work.pfs_filter
generic map (
g_coef_w => g_coef_dat_w,
@@ -111,7 +106,6 @@ begin
result => out_dat_x
);
-
firy : entity work.pfs_filter
generic map (
g_coef_w => g_coef_dat_w,
@@ -126,7 +120,6 @@ begin
result => out_dat_y
);
-
tapsbufx : entity work.pfs_tapsbuf
generic map (
g_data_w => g_in_dat_w * c_nof_fir_taps,
@@ -143,7 +136,6 @@ begin
rst => rst
);
-
tapsbufy : entity work.pfs_tapsbuf
generic map (
g_data_w => g_in_dat_w * c_nof_fir_taps,
@@ -160,7 +152,6 @@ begin
rst => rst
);
-
coefsbuf : entity work.pfs_coefsbuf
generic map (
g_data_w => g_coef_dat_w * c_nof_fir_taps,
@@ -174,6 +165,4 @@ begin
clk => clk,
rst => rst
);
-
end str;
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
index 461af4d42a799e24bdc0b18ec9ff874f17debe64..257754314c9c4fb000af3c2034c2080e988d1750 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(str).vhd
@@ -3,17 +3,13 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_mem_pkg.all;
-
architecture str of pfs_coefsbuf is
-
constant c_coefs_rom : t_c_mem := (latency => 2,
adr_w => g_addr_w,
dat_w => g_data_w,
nof_dat => g_nof_coefs, -- <= 2**g_addr_w
init_sl => '0');
-
begin
-
rom : entity common_lib.common_rom
generic map (
g_ram => c_coefs_rom,
@@ -26,8 +22,4 @@ begin
rd_adr => addr,
rd_dat => data
);
-
end str;
-
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
index 8a18fea17ac82b480a0d65f32b99fa3f1e764fec..2983acb7242e17968f0beb65dad4bd95a9a44b98 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf(stratix).vhd
@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
architecture stratix of pfs_coefsbuf is
-
component altsyncram
generic (
operation_mode : string;
@@ -28,9 +26,7 @@ architecture stratix of pfs_coefsbuf is
q_a : out std_logic_vector(g_data_w - 1 downto 0)
);
end component;
-
begin
-
rom : altsyncram
generic map (
operation_mode => "ROM",
@@ -52,8 +48,4 @@ begin
address_a => addr,
q_a => data
);
-
end stratix;
-
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
index f68e6c99e3a3c078d1426ea5ed303206c5d11034..d28621875de50bba54bae8ff7dbb1cbcfd9ce970 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_coefsbuf.vhd
@@ -28,7 +28,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_mem_pkg.all;
-
entity pfs_coefsbuf is
generic (
g_data_w : natural;
@@ -45,17 +44,13 @@ entity pfs_coefsbuf is
);
end pfs_coefsbuf;
-
architecture str of pfs_coefsbuf is
-
constant c_coefs_rom : t_c_mem := (latency => 2,
adr_w => g_addr_w,
dat_w => g_data_w,
nof_dat => g_nof_coefs, -- <= 2**g_addr_w
init_sl => '0');
-
begin
-
rom : entity common_lib.common_rom
generic map (
g_ram => c_coefs_rom,
@@ -67,5 +62,4 @@ begin
rd_adr => addr,
rd_dat => data
);
-
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
index 2f4d1cce6b99c5dfed081b92cc47a0295abc5e41..63fc7c73471a552a4a428a166707c13976e98ceb 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine(rtl).vhd
@@ -2,18 +2,14 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
architecture rtl of pfs_combine is
-
signal i_out_dat_x : std_logic_vector(out_dat_x'range);
signal nxt_out_dat_x : std_logic_vector(out_dat_x'range);
signal i_out_dat_y : std_logic_vector(out_dat_y'range);
signal nxt_out_dat_y : std_logic_vector(out_dat_y'range);
signal nxt_out_val : std_logic;
signal nxt_out_sync : std_logic;
-
begin
-
out_dat_x <= i_out_dat_x;
out_dat_y <= i_out_dat_y;
@@ -35,7 +31,6 @@ begin
end if;
end process;
-
select_value : process (i_out_dat_x, i_out_dat_y, in_val, in_dat_x, in_dat_y,
in_sync)
begin
@@ -53,5 +48,4 @@ begin
end if;
end loop;
end process;
-
end rtl;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
index 58d73db25ddc241ac2d7f94e85ca260cd4d5532b..6c921d33b654b58e4ae42d7c793b191d4c8f3a68 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_combine.vhd
@@ -1,7 +1,6 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity pfs_combine is
generic (
g_nof_fir : integer;
@@ -20,4 +19,3 @@ entity pfs_combine is
rst : in std_logic
);
end pfs_combine;
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
index 111e9267bf7fe2e8de9e8dabc86906a6e43f2e2a..315298a5ae8096c295e9af10fb55e0ba4234a6b1 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl(rtl).vhd
@@ -2,9 +2,7 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
architecture rtl of pfs_ctrl is
-
-- The number of cycles that should be waited until the result that comes out
-- of the MAC block is the valid result. The ctrl block will generate a valid
-- pulse.
@@ -23,9 +21,7 @@ architecture rtl of pfs_ctrl is
signal nxt_rdval : std_logic_vector(rdval'range);
signal i_taps_wraddr : std_logic_vector(taps_wraddr'range);
signal nxt_taps_wraddr : std_logic_vector(taps_wraddr'range);
-
begin
-
-- Output signals.
taps_rdaddr <= i_taps_rdaddr;
taps_wraddr <= i_taps_wraddr;
@@ -59,7 +55,6 @@ begin
end if;
end process;
-
read_address_gen : process (restart, i_taps_rdaddr, in_val_reg, rdval)
begin
nxt_taps_rdaddr <= std_logic_vector(unsigned(i_taps_rdaddr) + 1);
@@ -75,7 +70,6 @@ begin
end if;
end process;
-
write_control : process (restart, i_taps_wraddr, taps_in_x, taps_in_y, in_x_reg, rdval,
in_y_reg)
begin
@@ -95,7 +89,4 @@ begin
taps_wren <= '1';
end if;
end process;
-
end rtl;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
index 703f337882376a05c5a61d2ae7a35b298c824cdd..ab0bcedb05208d4f158befcd644b567dc9509d8b 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_ctrl.vhd
@@ -27,7 +27,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity pfs_ctrl is
generic (
g_nof_bands_w : natural;
@@ -55,9 +54,7 @@ entity pfs_ctrl is
);
end pfs_ctrl;
-
architecture rtl of pfs_ctrl is
-
-- The number of cycles that should be waited until the result that comes out
-- of the MAC block is the valid result. The ctrl block will generate a valid
-- pulse.
@@ -76,9 +73,7 @@ architecture rtl of pfs_ctrl is
signal nxt_rdval : std_logic_vector(rdval'range);
signal i_taps_wraddr : std_logic_vector(taps_wraddr'range);
signal nxt_taps_wraddr : std_logic_vector(taps_wraddr'range);
-
begin
-
-- Output signals.
taps_rdaddr <= i_taps_rdaddr;
taps_wraddr <= i_taps_wraddr;
@@ -112,7 +107,6 @@ begin
end if;
end process;
-
read_address_gen : process (restart, i_taps_rdaddr, in_val_reg, rdval)
begin
nxt_taps_rdaddr <= std_logic_vector(unsigned(i_taps_rdaddr) + 1);
@@ -128,7 +122,6 @@ begin
end if;
end process;
-
write_control : process (restart, i_taps_wraddr, taps_in_x, taps_in_y, in_x_reg, rdval,
in_y_reg)
begin
@@ -148,5 +141,4 @@ begin
taps_wren <= '1';
end if;
end process;
-
end rtl;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
index 2b024f225669c8b00ab4ace5f78463b17b1b2889..c17e494eb6f07d436f9ae722f90652f4642090fe 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(rtl).vhd
@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
architecture rtl of pfs_filter is
-
type type_res is array (0 to 7) of std_logic_vector(g_coef_w + g_taps_w + 1 - 1 downto 0);
signal res : type_res;
@@ -16,9 +14,7 @@ architecture rtl of pfs_filter is
signal add_a : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_b : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_c : std_logic_vector(g_coef_w + g_taps_w + 4 - 1 downto 0);
-
begin
-
registers : process (clk)
begin
if rising_edge(clk) then
@@ -28,7 +24,6 @@ begin
end if;
end process;
-
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
-- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
@@ -62,7 +57,4 @@ begin
res_3 <= std_logic_vector(resize(signed(res(6)),res_0'length) + resize(signed(res(7)),res_0'length));
end if;
end process;
-
end rtl;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
index eb483ea066f3b0cbe85c37cf8eb9362810d9718e..d551fa62270d140d88209eb96a728e47634e08c8 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter(stratix).vhd
@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
architecture stratix of pfs_filter is
-
component altmult_add
generic (
input_register_b2 : string := "CLOCK0";
@@ -79,7 +77,6 @@ architecture stratix of pfs_filter is
);
end component;
-
signal res_0 : std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0);
signal res_1 : std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0);
signal res_2 : std_logic_vector(g_coef_w + g_taps_w + 2 - 1 downto 0);
@@ -87,9 +84,7 @@ architecture stratix of pfs_filter is
signal add_a : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_b : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_c : std_logic_vector(g_coef_w + g_taps_w + 4 - 1 downto 0);
-
begin
-
registers : process (clk, rst)
begin
if rst = '1' then
@@ -103,11 +98,9 @@ begin
end if;
end process;
-
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
-- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
-
ALTMULT_ADD_0 : altmult_add
port map (
dataa => taps(47 downto 0),
@@ -117,7 +110,6 @@ begin
result => res_0
);
-
ALTMULT_ADD_1 : altmult_add
port map (
dataa => taps(95 downto 48),
@@ -136,7 +128,6 @@ begin
result => res_2
);
-
ALTMULT_ADD_3 : altmult_add
port map (
dataa => taps(191 downto 144),
@@ -145,7 +136,4 @@ begin
aclr3 => rst,
result => res_3
);
-
end stratix;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
index de5108589952d5046e84dfc9f9a421ed329d41dc..ba25c7ab38656b7edf7bf6ce78db76ffb66da00d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_filter.vhd
@@ -28,7 +28,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity pfs_filter is
generic (
g_coef_w : natural;
@@ -44,9 +43,7 @@ entity pfs_filter is
);
end pfs_filter;
-
architecture rtl of pfs_filter is
-
type type_res is array (0 to 7) of std_logic_vector(g_coef_w + g_taps_w + 1 - 1 downto 0);
signal res : type_res;
@@ -57,9 +54,7 @@ architecture rtl of pfs_filter is
signal add_a : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_b : std_logic_vector(g_coef_w + g_taps_w + 3 - 1 downto 0);
signal add_c : std_logic_vector(g_coef_w + g_taps_w + 4 - 1 downto 0);
-
begin
-
registers : process (clk)
begin
if rising_edge(clk) then
@@ -69,7 +64,6 @@ begin
end if;
end process;
-
add_c <= std_logic_vector(SHIFT_LEFT((resize(signed(add_a),add_c'length) + signed(add_b)),4));
-- nxt_result <= STD_LOGIC_VECTOR(RESIZE(SIGNED(add_c),
@@ -103,5 +97,4 @@ begin
res_3 <= std_logic_vector(resize(signed(res(6)),res_0'length) + resize(signed(res(7)),res_0'length));
end if;
end process;
-
end rtl;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
index 86711a87f57aee21a4d1c7ddd58f2b1241d470ec..abe1bfdfcd8001d60681e6c1c36120765b94dbe7 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir(str).vhd
@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
library common_lib;
use common_lib.common_pkg.all;
-
architecture str of pfs_fir is
-
constant c_nof_taps_w : natural := ceil_log2(g_nof_taps);
constant c_nof_prefilter_w : natural := ceil_log2(g_nof_prefilter);
constant c_nof_coefs : natural := g_nof_prefilter * g_nof_taps;
@@ -25,10 +23,7 @@ architecture str of pfs_fir is
signal coefs_rden : std_logic;
signal res_clr : std_logic;
signal i_res_val : std_logic;
-
-
begin
-
ctrl : entity pfs_lib.pfs_fir_ctrl
generic map (
g_nof_prefilter => g_nof_prefilter,
@@ -57,7 +52,6 @@ begin
result_sync => res_sync
);
-
mac_hor : entity pfs_lib.pfs_fir_mac
generic map (
g_a_in_w => g_in_dat_w,
@@ -76,7 +70,6 @@ begin
result => res_hor
);
-
mac_ver : entity pfs_lib.pfs_fir_mac
generic map (
g_a_in_w => g_in_dat_w,
@@ -95,7 +88,6 @@ begin
result => res_ver
);
-
coefsbuf_0 : if g_fir_nr = 0 generate
coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
generic map (
@@ -114,7 +106,6 @@ begin
);
end generate;
-
coefsbuf_N : if g_fir_nr > 0 generate
coefsbuf : entity pfs_lib.pfs_fir_coefsbuf
generic map (
@@ -133,7 +124,6 @@ begin
);
end generate;
-
tapsbuf_hor : entity pfs_lib.pfs_fir_tapsbuf
generic map (
g_data_w => g_in_dat_w,
@@ -151,7 +141,6 @@ begin
rst => rst
);
-
tapsbuf_ver : entity pfs_lib.pfs_fir_tapsbuf
generic map (
g_data_w => g_in_dat_w,
@@ -170,7 +159,4 @@ begin
);
res_val <= i_res_val;
-
end str;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
index 1d5f3219c1f8d0389dfe7b628ff3d16e365b38d2..b0c265b36f1be8d98b008da7050314745af124a7 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir.vhd
@@ -2,7 +2,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity pfs_fir is
generic (
g_in_dat_w : natural;
@@ -28,5 +27,3 @@ entity pfs_fir is
res_sync : out std_logic
);
end pfs_fir;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
index 57b0f46def479bb8970f51d3e26c54ea240d6343..75cc60eba806430d870b0a73f851b054ace794b1 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf(stratix).vhd
@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
architecture stratix of pfs_fir_coefsbuf is
-
component altsyncram
generic (
operation_mode : string;
@@ -28,9 +26,7 @@ architecture stratix of pfs_fir_coefsbuf is
q_a : out std_logic_vector(g_data_w - 1 downto 0)
);
end component;
-
begin
-
rom : altsyncram
generic map (
operation_mode => "ROM",
@@ -52,8 +48,4 @@ begin
address_a => addr,
q_a => data
);
-
end stratix;
-
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
index 7eecba00597bd65d06043efdff1d7bbdaefef840..5bd64c7a4a5eab7647529c9f694c20ab2b9b4c11 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_coefsbuf.vhd
@@ -17,5 +17,3 @@ entity pfs_fir_coefsbuf is
rst : in std_logic
);
end pfs_fir_coefsbuf;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
index 0a33653b352f3713dc30320cf391f3c03279072b..1a2fc318a95852a567b1043632652faaee2d0c06 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl(rtl).vhd
@@ -2,9 +2,7 @@ library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-
architecture rtl of pfs_fir_ctrl is
-
-- The number of cycles that should be waited until the result that comes out
-- of the MAC block is the valid result. The ctrl block will generate a valid
-- pulse.
@@ -13,13 +11,11 @@ architecture rtl of pfs_fir_ctrl is
-- start with the next FIR calculation.
constant c_mac_clr_delay : integer := 4;
-
type fir_state_enum is (
idle,
calc
);
-
signal fir_state : fir_state_enum;
signal nxt_fir_state : fir_state_enum;
signal taps_cnt : std_logic_vector(g_nof_taps_w - 1 downto 0);
@@ -46,9 +42,7 @@ architecture rtl of pfs_fir_ctrl is
signal sync_delay : std_logic_vector(c_mac_res_delay + g_nof_taps * 2 - 1 downto 0);
signal nxt_sync_delay : std_logic_vector(sync_delay'range);
signal last_tap : std_logic;
-
begin
-
-- Output signals.
result_val <= mac_res_delay(mac_res_delay'high);
result_sync <= sync_delay(sync_delay'high);
@@ -58,7 +52,6 @@ begin
sample_data_ver <= i_sample_data_ver;
sample_addr <= i_sample_addr;
-
registers_proc : process (clk, rst)
begin
if rst = '1' then
@@ -100,7 +93,6 @@ begin
end if;
end process;
-
-- The state machine will stay in idle until it receives an input sample. At
-- that time it will start the FIR filter operation. It will return to idle
-- unless another sample is received at the time the calculation is ready.
@@ -122,13 +114,11 @@ begin
end case;
end process;
-
-- Pulse when the tap counter reaches it maximum.
last_tap <= '1' when unsigned(taps_cnt) = (g_nof_taps - 1) else '0';
res_clr <= '1' when unsigned(taps_cnt) = c_mac_clr_delay - 1 else '0';
-
-- Counter that will be used for addressing various RAMs, and to indicate
-- to the state machine when a FIR operation is finished.
tap_counter_proc : process (taps_cnt, input_val, fir_state, last_tap)
@@ -141,7 +131,6 @@ begin
end if;
end process;
-
-- Keep track of the current logical FIR operation. This counter will be used
-- for addressing of the memories.
prefilter_counter_proc : process (prefilter_cnt, last_tap)
@@ -156,7 +145,6 @@ begin
end if;
end process;
-
-- Generate address and read enable for the coefficient memory.
coefficient_control_proc : process (prefilter_cnt, taps_cnt, fir_state)
begin
@@ -169,7 +157,6 @@ begin
end if;
end process;
-
-- Generate write signals for the taps memories. The received samples will
-- be written into this memory at the end of the FIR calculation cycle.
sample_ram_control_proc : process (taps_cnt, input_val, i_sample_data_hor,
@@ -194,7 +181,6 @@ begin
end if;
end process;
-
-- Generate read signals for the taps memories. Also, the base address of the
-- current logical FIR operation will be generated here. The base address will
-- change in time to emulate a shift register using memories.
@@ -216,11 +202,9 @@ begin
end if;
end process;
-
taps_addr_offset <= std_logic_vector(unsigned(taps_addr_base)
+ unsigned(taps_cnt));
-
-- The MAC delay register is used to generate a valid pulse for the MAC output
-- when the FIR calculation is done, and to generate a reset pulse to set the
-- intermediate result of the MAC to 0.
@@ -234,8 +218,4 @@ begin
nxt_sync_delay(0) <= input_sync;
end if;
end process;
-
-
end rtl;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
index 3554e9b5d834ee52579e17d868c3b41b0e1f2258..d3c70a8bb12eb819e523dbb900ac90f2e3cd9c6d 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_ctrl.vhd
@@ -1,7 +1,6 @@
library ieee;
use ieee.std_logic_1164.all;
-
entity pfs_fir_ctrl is
generic (
g_nof_prefilter : natural;
@@ -30,4 +29,3 @@ entity pfs_fir_ctrl is
result_sync : out std_logic
);
end pfs_fir_ctrl;
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
index 845d6a4ea4d91e44e379bcb3f0c7a72768ecff4b..e036325cd4a2e27cbc4ce7300d213f6d70826c5c 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac(stratix).vhd
@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
architecture stratix of pfs_fir_mac is
-
component altmult_accum
generic (
intended_device_family : string;
@@ -46,12 +44,9 @@ architecture stratix of pfs_fir_mac is
);
end component;
-
-- NOTE: although it appears otherwise, bit growth in the accumulation is accounted for!
signal acc_out : std_logic_vector(g_a_in_w + g_b_in_w - 1 downto 0);
-
begin
-
registers : process (clk, rst)
begin
if rst = '1' then
@@ -61,7 +56,6 @@ begin
end if;
end process;
-
mac : altmult_accum
generic map (
intended_device_family => c_rsp_device_family,
@@ -100,7 +94,4 @@ begin
clock0 => clk,
result => acc_out
);
-
end stratix;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
index 91a494944198d30660fd51c2216f0fc552bc34d5..a9ff53a2ccad0feca77b90310e37cf29b721715c 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_mac.vhd
@@ -2,7 +2,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity pfs_fir_mac is
generic (
g_a_in_w : natural;
@@ -21,4 +20,3 @@ entity pfs_fir_mac is
result : out std_logic_vector(g_out_w - 1 downto 0)
);
end pfs_fir_mac;
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
index fe27455ccf2eb6fbecba2f50ac700fc768c9f0e7..000968fe0ec5143ebf9c7ca9f03d6bd551ab15db 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf(stratix).vhd
@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
architecture stratix of pfs_fir_tapsbuf is
-
component altsyncram
generic (
intended_device_family : string;
@@ -35,9 +33,7 @@ architecture stratix of pfs_fir_tapsbuf is
data_a : in std_logic_vector(g_data_w - 1 downto 0)
);
end component;
-
begin
-
altsyncram_component : altsyncram
generic map (
intended_device_family => c_rsp_device_family,
@@ -67,9 +63,4 @@ begin
data_a => data_a,
q_b => data_b
);
-
end stratix;
-
-
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
index e147c4872deb33186fbe91425b0fcf33c4f16ca6..05d25645123dc0bc1a0ac4e9fa72c85f8be9b337 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_fir_tapsbuf.vhd
@@ -19,5 +19,3 @@ entity pfs_fir_tapsbuf is
rst : in std_logic
);
end pfs_fir_tapsbuf;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
index 08444d204e712c7f9b1e4e17aff73e0963aa015c..47dcc7272d22339a9cd1055c5137ac925d19c6f4 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_pkg.vhd
@@ -28,14 +28,9 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package pfs_pkg is
-
constant c_pfs_coef_w : natural := 16;
constant c_pfs_coefs_file : string := "data/pfs_coefsbuf_1024.hex";
-
end pfs_pkg;
-
package body pfs_pkg is
end pfs_pkg;
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
index b33201039c075799d66d1c5bb25fd3e3e075a976..de1f3ccf289e5afe7aefb1d5aa91533267529a74 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate(rtl).vhd
@@ -2,9 +2,7 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
architecture rtl of pfs_rotate is
-
signal i_out_dat_x : std_logic_vector(out_dat_x'range);
signal nxt_out_dat_x : std_logic_vector(out_dat_x'range);
signal i_out_dat_y : std_logic_vector(out_dat_y'range);
@@ -13,9 +11,7 @@ architecture rtl of pfs_rotate is
signal nxt_out_sync : std_logic;
signal cnt : integer range 0 to out_val'length - 1;
signal nxt_cnt : integer;
-
begin
-
out_dat_x <= i_out_dat_x;
out_dat_y <= i_out_dat_y;
@@ -36,7 +32,6 @@ begin
end if;
end process;
-
counter_proc : process (cnt, in_val)
begin
nxt_cnt <= cnt;
@@ -47,7 +42,6 @@ begin
end if;
end process;
-
interleaver_proc : process (in_val, cnt, in_dat_x, in_dat_y, in_sync,
i_out_dat_x, i_out_dat_y)
begin
@@ -62,8 +56,4 @@ begin
nxt_out_dat_y <= in_dat_y;
end if;
end process;
-
end rtl;
-
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
index d9fc8e59bc679b420a9890752bb1f6273ccd609b..96b25a28cd47f08211a9150d702b724ad41880f3 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_rotate.vhd
@@ -2,7 +2,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity pfs_rotate is
generic (
g_in_dat_w : integer;
@@ -21,4 +20,3 @@ entity pfs_rotate is
out_sync : out std_logic
);
end pfs_rotate;
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
index 07d942d7cb1302bf0a32d454837458b77b4726fd..5f59cf66fdc9ff4b49f7238087e7732de7b8b691 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
@@ -3,18 +3,14 @@ use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use common_lib.common_pkg.all;
-
architecture rtl of pfs_tapsbuf is
-
type RamType is array(0 to 2**g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
-- pfs_tapsbuf_1024.hex is empty (all zeros)
signal RAM : RamType := (others => (others => '0'));
signal read_addrb : std_logic_vector(g_addr_w - 1 downto 0);
-
begin
-
---------------------------------------------------------------
process (clk)
begin
@@ -30,7 +26,3 @@ end process;
---------------------------------------------------------------
---------------------------------------------------------------
end rtl;
-
-
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
index 416c141731f0a19cae9983f081866c80e8a048ea..c7dcd76860c71e5c9c37a712e3abb37615f6580e 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(stratix).vhd
@@ -3,9 +3,7 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
architecture stratix of pfs_tapsbuf is
-
component altsyncram
generic (
intended_device_family : string;
@@ -35,9 +33,7 @@ architecture stratix of pfs_tapsbuf is
data_a : in std_logic_vector(g_data_w - 1 downto 0)
);
end component;
-
begin
-
altsyncram_component : altsyncram
generic map (
intended_device_family => c_rsp_device_family,
@@ -66,9 +62,4 @@ begin
data_a => wrdata,
q_b => rddata
);
-
end stratix;
-
-
-
-
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
index 36a6e0916343867fbb1e05eb15417ab091785a79..fcbf46518a8a28e3d78eec83b0d5221fa2c308cf 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf.vhd
@@ -28,7 +28,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-
entity pfs_tapsbuf is
generic (
g_data_w : natural;
@@ -46,18 +45,14 @@ entity pfs_tapsbuf is
);
end pfs_tapsbuf;
-
architecture rtl of pfs_tapsbuf is
-
type RamType is array(0 to 2**g_addr_w) of std_logic_vector(g_data_w - 1 downto 0);
-- pfs_tapsbuf_1024.hex is empty (all zeros)
signal RAM : RamType := (others => (others => '0'));
signal read_addrb : std_logic_vector(g_addr_w - 1 downto 0);
-
begin
-
process (clk)
begin
if rising_edge(clk) then
@@ -68,5 +63,4 @@ begin
rddata <= RAM(conv_integer(read_addrb));
end if;
end process;
-
end rtl;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
index 663a11939660e4a8eec0a2d4c34ce99b5a25af8d..9651e9c167dd46c943f9d91e38b81a42f7bd97a0 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top(str).vhd
@@ -1,9 +1,7 @@
library IEEE, pfs_lib;
use IEEE.std_logic_1164.all;
-
architecture str of pfs_top is
-
signal reg_in_dat_x : std_logic_vector(g_in_dat_w - 1 downto 0);
signal reg_in_dat_y : std_logic_vector(g_in_dat_w - 1 downto 0);
signal reg_in_val : std_logic;
@@ -12,9 +10,7 @@ architecture str of pfs_top is
signal d_out_dat_y : std_logic_vector(g_out_dat_w - 1 downto 0);
signal d_out_val : std_logic;
signal d_out_sync : std_logic;
-
begin
-
registers : process(clk)
begin
if rising_edge(clk) then
@@ -50,5 +46,4 @@ begin
rst => rst,
restart => '0'
);
-
end str;
diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
index 7b318f2069f3345748346733a1a57052394a0a5a..a69a35d77d304525196608786a1730d395dd5a8c 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_top.vhd
@@ -1,7 +1,6 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity pfs_top is
generic (
g_nof_bands : natural := 1024;
diff --git a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
index 14758276d50e402f789ff5418b709915eb1c63b0..17cc8b68856ffcc2f6e91ce4279749b0757421ad 100644
--- a/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
+++ b/applications/lofar1/RSP/pfs/tb/vhdl/tb_pfs.vhd
@@ -35,12 +35,10 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use common_lib.tb_common_pkg.all;
-
entity tb_pfs is
end tb_pfs;
architecture tb of tb_pfs is
-
constant clk_period : time := 5.0 ns;
signal in_dat_x : std_logic_vector(11 downto 0) := (others => '0');
@@ -54,9 +52,7 @@ architecture tb of tb_pfs is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
signal tb_end : std_logic := '0';
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '0' after 3 * clk_period;
@@ -123,7 +119,4 @@ begin
tb_end <= '1';
wait;
end process;
-
end tb;
-
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(empty).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(empty).vhd
index 6a80be53096d25feaa93b6d2f5e4cb04d64be9a6..84fa87eb0c39a4f8ff2dad9f2e783c8b1d36d892 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(empty).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(empty).vhd
@@ -1,5 +1,3 @@
architecture empty of pft is
begin
end empty;
-
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
index 979b3a80a12ae95becdbd7a7241dbe7ee18c278e..20e0854462a20340b86b60b89dd1282e43f4b4ea 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(pkg).vhd
@@ -15,11 +15,7 @@ package pft_pkg is
PFT_BF1,
PFT_BF2
);
-
end pft_pkg;
-
package body pft_pkg is
end pft_pkg;
-
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
index 794c5bf7b48a1526e55d7e23db9a3f7a9370691e..47cd94497c6b680649d154a9e7abc18602d80def 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft(str).vhd
@@ -6,7 +6,6 @@ library pft2_lib;
use pft2_lib.pft_pkg.all;
architecture str of pft is
-
function pft_dat_w ( output_w : in natural; mode : in PFT_MODE_TYPE) return natural is
variable dat_w : natural;
begin
@@ -61,7 +60,6 @@ architecture str of pft is
signal unswitch_val : std_logic;
signal unswitch_sync : std_logic;
-
-- synthesis translate_off
signal bin : std_logic_vector(g_fft_size_w - 1 downto 0) := (others => '0');
signal band : std_logic_vector(g_fft_size_w - 2 downto 0);
@@ -73,14 +71,11 @@ architecture str of pft is
signal power_x : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
signal power_y : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
-- synthesis translate_on
-
begin
-
-- The pipelined fft is composed of a number of consecutive stages.
-- The output of each stage is used as input for the next stage.
-- NB. The first stage has index c_nof_stages-1, the last stage has index 0.
-
switch: entity pft2_lib.pft_switch
generic map (
g_dat_w => g_in_dat_w,
@@ -121,7 +116,6 @@ begin
);
end generate;
-
middle_gen : for i in c_nof_stages - 2 downto 1 generate
middle_stage : entity pft2_lib.pft_stage
generic map (
@@ -194,7 +188,6 @@ begin
end generate;
buf_gen : if g_mode /= PFT_MODE_BITREV generate
-
buf : entity pft2_lib.pft_buffer
generic map (
g_fft_size_w => g_fft_size_w,
@@ -217,7 +210,6 @@ begin
);
end generate;
-
reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
reverse : entity pft2_lib.pft_reverse
generic map (
@@ -240,10 +232,8 @@ begin
clk => clk,
rst => rst
);
-
end generate;
-
separate_gen : if g_mode = PFT_MODE_REAL2 generate
separate : entity pft2_lib.pft_separate
generic map (
@@ -288,7 +278,6 @@ begin
out_sync => unswitch_sync
);
-
-- calculate the power. This is intended to be used in simulations only.
-- synthesis translate_off
@@ -336,7 +325,4 @@ begin
out_im <= unswitch_im;
out_val <= unswitch_val;
out_sync <= unswitch_sync;
-
end str;
-
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
index ea022d0a49db005b1e02833ad6b81b39d5bd3ecc..167561784c506e95549ea815b4773596ec4e747e 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft.vhd
@@ -28,7 +28,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.pft_pkg.all;
-
entity pft is
generic (
g_fft_size_w : natural := 10;
@@ -52,9 +51,7 @@ entity pft is
);
end pft;
-
architecture str of pft is
-
function pft_dat_w ( output_w : in natural; mode : in PFT_MODE_TYPE) return natural is
variable dat_w : natural;
begin
@@ -108,7 +105,6 @@ architecture str of pft is
signal unswitch_val : std_logic;
signal unswitch_sync : std_logic;
-
-- synthesis translate_off
signal bin : std_logic_vector(g_fft_size_w - 1 downto 0) := (others => '0');
signal band : std_logic_vector(g_fft_size_w - 2 downto 0);
@@ -120,14 +116,11 @@ architecture str of pft is
signal power_x : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
signal power_y : std_logic_vector(2 * g_out_dat_w - 1 downto 0);
-- synthesis translate_on
-
begin
-
-- The pipelined fft is composed of a number of consecutive stages.
-- The output of each stage is used as input for the next stage.
-- NB. The first stage has index c_nof_stages-1, the last stage has index 0.
-
switch: entity work.pft_switch
generic map (
g_dat_w => g_in_dat_w,
@@ -168,7 +161,6 @@ begin
);
end generate;
-
middle_gen : for i in c_nof_stages - 2 downto 1 generate
middle_stage : entity work.pft_stage
generic map (
@@ -241,7 +233,6 @@ begin
end generate;
buf_gen : if g_mode /= PFT_MODE_BITREV generate
-
buf : entity work.pft_buffer
generic map (
g_fft_size_w => g_fft_size_w,
@@ -264,7 +255,6 @@ begin
);
end generate;
-
reverse_gen : if g_mode = PFT_MODE_COMPLEX generate
reverse : entity work.pft_reverse
generic map (
@@ -287,10 +277,8 @@ begin
clk => clk,
rst => rst
);
-
end generate;
-
separate_gen : if g_mode = PFT_MODE_REAL2 generate
separate : entity work.pft_separate
generic map (
@@ -335,7 +323,6 @@ begin
out_sync => unswitch_sync
);
-
-- calculate the power. This is intended to be used in simulations only.
-- synthesis translate_off
@@ -383,5 +370,4 @@ begin
out_im <= unswitch_im;
out_val <= unswitch_val;
out_sync <= unswitch_sync;
-
end str;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
index 5cd8e02ac4b2c6610a83dd7b1571744e98bb24d3..36e8e2a0075c428aee6e6f9a319fd30ec9a899c6 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf(rtl).vhd
@@ -6,7 +6,6 @@ library common_lib;
use common_lib.all;
architecture rtl of pft_bf is
-
constant c_read_pipeline : natural := 1;
constant c_add_pipeline : natural := 2;
constant c_write_pipeline : natural := 1;
@@ -81,9 +80,7 @@ architecture rtl of pft_bf is
signal wr_dat : std_logic_vector(2 * c_dat_w - 1 downto 0);
signal nxt_wr_dat : std_logic_vector(2 * c_dat_w - 1 downto 0);
signal rd_dat : std_logic_vector(2 * c_dat_w - 1 downto 0);
-
begin
-
out_val <= sig(0).val;
out_sync <= sig(0).sync;
wr_req <= sig(0).wr_req;
@@ -198,7 +195,6 @@ begin
end if;
end process;
-
out_proc : process (sig, add_cr,add_ci,sub_cr,sub_ci)
begin
nxt_out_re <= std_logic_vector(resize(signed(add_cr),g_out_dat_w));
@@ -213,7 +209,6 @@ begin
end if;
end process;
-
-- Adds/ Subs ------------------------------------------------------------------
-- Intel Altera lmp_add_sub carry in:
@@ -317,7 +312,6 @@ begin
);
end generate fifo_gen;
-
fifo2_gen : if c_regbank_size > c_pipeline and c_regbank_size <= 8 generate
fifo2_reg : process (clk, rst)
begin
@@ -359,6 +353,4 @@ begin
end generate;
assert c_regbank_size >= c_pipeline severity FAILURE;
-
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
index edbaf8f12ab50be37751245e34690e708d7fa527..52eebaf095bcdbb3292059b408909b75c15f7ed5 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf.vhd
@@ -29,7 +29,6 @@ use IEEE.numeric_std.all;
library common_lib;
-
entity pft_bf is
generic (
g_index : natural;
@@ -53,9 +52,7 @@ entity pft_bf is
);
end pft_bf;
-
architecture rtl of pft_bf is
-
constant c_read_pipeline : natural := 1;
constant c_add_pipeline : natural := 2;
constant c_write_pipeline : natural := 1;
@@ -130,9 +127,7 @@ architecture rtl of pft_bf is
signal wr_dat : std_logic_vector(2 * c_dat_w - 1 downto 0);
signal nxt_wr_dat : std_logic_vector(2 * c_dat_w - 1 downto 0);
signal rd_dat : std_logic_vector(2 * c_dat_w - 1 downto 0);
-
begin
-
out_val <= sig(0).val;
out_sync <= sig(0).sync;
wr_req <= sig(0).wr_req;
@@ -247,7 +242,6 @@ begin
end if;
end process;
-
out_proc : process (sig, add_cr,add_ci,sub_cr,sub_ci)
begin
nxt_out_re <= std_logic_vector(resize(signed(add_cr),g_out_dat_w));
@@ -262,7 +256,6 @@ begin
end if;
end process;
-
-- Adds/ Subs ------------------------------------------------------------------
-- Intel Altera lmp_add_sub carry in:
@@ -366,7 +359,6 @@ begin
);
end generate fifo_gen;
-
fifo2_gen : if c_regbank_size > c_pipeline and c_regbank_size <= 8 generate
fifo2_reg : process (clk, rst)
begin
@@ -408,5 +400,4 @@ begin
end generate;
assert c_regbank_size >= c_pipeline severity FAILURE;
-
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
index b0a1c3b41733a575832f96b018af4f4e474cd537..c8467e44759e8f153de12a1fc307f04e6963a553 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw(rtl).vhd
@@ -6,7 +6,6 @@ library common_lib;
use common_lib.all;
architecture rtl of pft_bf_fw is
-
constant c_add_pipeline : natural := 2;
constant c_dist : natural := 2**g_index;
constant c_pipeline : natural := c_add_pipeline + c_dist + 2;
@@ -21,7 +20,6 @@ architecture rtl of pft_bf_fw is
signal xi : reg_arr;
signal nxt_xi : reg_arr;
-
signal pipe_val : std_logic_vector(c_pipeline-1 downto 0);
signal nxt_pipe_val : std_logic_vector(pipe_val'range);
signal pipe_sync : std_logic_vector(c_pipeline-1 downto 0);
@@ -41,17 +39,13 @@ architecture rtl of pft_bf_fw is
signal yr_cry : std_logic;
signal yi_cry : std_logic;
-
signal nxt_yr_a : std_logic_vector(yr_a'range);
signal nxt_yr_b : std_logic_vector(yr_b'range);
signal nxt_yi_a : std_logic_vector(yi_a'range);
signal nxt_yi_b : std_logic_vector(yi_b'range);
signal nxt_yr_add : std_logic;
signal nxt_yi_add : std_logic;
-
-
begin
-
nxt_xr <= in_re & xr (xr 'high downto xr 'low + 1);
nxt_xi <= in_im & xi (xi 'high downto xi 'low + 1);
@@ -93,7 +87,6 @@ begin
end if;
end process;
-
counter : process (cnt, pipe_val, pipe_sync)
begin
nxt_cnt <= cnt;
@@ -104,7 +97,6 @@ begin
end if;
end process;
-
process(s0,s1,xr,xi)
variable state : std_logic_vector(1 downto 0);
begin
@@ -157,7 +149,6 @@ begin
nxt_yi_add <= '1';
nxt_yi_a <= xi(-c_dist);
nxt_yi_b <= xr(0);
-
end case;
end process;
@@ -238,6 +229,4 @@ begin
in_b => yi_b,
result => out_im
);
-
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
index 77530984b9d175557af59b11e9426031b3c2e6dd..f777f5e18d382a71341aaa2c01de40cff0f3f6e2 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_bf_fw.vhd
@@ -29,7 +29,6 @@ use IEEE.numeric_std.all;
library common_lib;
-
entity pft_bf_fw is
generic (
g_in_dat_w : natural;
@@ -53,9 +52,7 @@ entity pft_bf_fw is
);
end pft_bf_fw;
-
architecture rtl of pft_bf_fw is
-
constant c_add_pipeline : natural := 2;
constant c_dist : natural := 2**g_index;
constant c_pipeline : natural := c_add_pipeline + c_dist + 2;
@@ -70,7 +67,6 @@ architecture rtl of pft_bf_fw is
signal xi : reg_arr;
signal nxt_xi : reg_arr;
-
signal pipe_val : std_logic_vector(c_pipeline-1 downto 0);
signal nxt_pipe_val : std_logic_vector(pipe_val'range);
signal pipe_sync : std_logic_vector(c_pipeline-1 downto 0);
@@ -90,17 +86,13 @@ architecture rtl of pft_bf_fw is
signal yr_cry : std_logic;
signal yi_cry : std_logic;
-
signal nxt_yr_a : std_logic_vector(yr_a'range);
signal nxt_yr_b : std_logic_vector(yr_b'range);
signal nxt_yi_a : std_logic_vector(yi_a'range);
signal nxt_yi_b : std_logic_vector(yi_b'range);
signal nxt_yr_add : std_logic;
signal nxt_yi_add : std_logic;
-
-
begin
-
nxt_xr <= in_re & xr (xr 'high downto xr 'low + 1);
nxt_xi <= in_im & xi (xi 'high downto xi 'low + 1);
@@ -142,7 +134,6 @@ begin
end if;
end process;
-
counter : process (cnt, pipe_val, pipe_sync)
begin
nxt_cnt <= cnt;
@@ -153,7 +144,6 @@ begin
end if;
end process;
-
process(s0,s1,xr,xi)
variable state : std_logic_vector(1 downto 0);
begin
@@ -206,7 +196,6 @@ begin
nxt_yi_add <= '1';
nxt_yi_a <= xi(-c_dist);
nxt_yi_b <= xr(0);
-
end case;
end process;
@@ -287,5 +276,4 @@ begin
in_b => yi_b,
result => out_im
);
-
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
index f6fa171496b541baa2ea186fe3b46196e98d7fd1..85ff4fdba8fa3418b4ad97b1822d11048cf95d67 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer(rtl).vhd
@@ -8,7 +8,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
architecture rtl of pft_buffer is
-
constant c_latency : natural := 2;
constant c_adr_w : natural := g_fft_size_w + 1;
constant c_nof_words : natural := 2**c_adr_w;
@@ -31,7 +30,6 @@ architecture rtl of pft_buffer is
signal nxt_rd_page : std_logic;
signal wr_en : std_logic;
-
signal pipe_val : std_logic_vector(c_latency - 1 downto 0);
signal nxt_pipe_val : std_logic_vector(pipe_val'range);
@@ -43,9 +41,7 @@ architecture rtl of pft_buffer is
end loop;
return result;
end function;
-
begin
-
nxt_rd_page <= not nxt_wr_page;
rd_adr_paged <= rd_page & rd_adr;
@@ -137,6 +133,4 @@ begin
rd_adr => rd_adr_paged,
rd_dat => rd_dat
);
-
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
index 422d4c850ad1cbfc3a1b58b827f3c1e0c2ba4ca1..33f764deb9248f081270a60e9b8f988ee8ba4d68 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_buffer.vhd
@@ -53,9 +53,7 @@ entity pft_buffer is
);
end pft_buffer;
-
architecture rtl of pft_buffer is
-
constant c_latency : natural := 2;
constant c_adr_w : natural := g_fft_size_w + 1;
constant c_nof_words : natural := 2**c_adr_w;
@@ -78,7 +76,6 @@ architecture rtl of pft_buffer is
signal nxt_rd_page : std_logic;
signal wr_en : std_logic;
-
signal pipe_val : std_logic_vector(c_latency - 1 downto 0);
signal nxt_pipe_val : std_logic_vector(pipe_val'range);
@@ -90,9 +87,7 @@ architecture rtl of pft_buffer is
end loop;
return result;
end function;
-
begin
-
nxt_rd_page <= not nxt_wr_page;
rd_adr_paged <= rd_page & rd_adr;
@@ -184,5 +179,4 @@ begin
rd_adr => rd_adr_paged,
rd_dat => rd_dat
);
-
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
index 10175d10956fac3d496c1b747e7f5b748f8b700e..73c752e25b1ca2a39e139d33bf2679c903f3049f 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr(rtl).vhd
@@ -1,9 +1,7 @@
-
library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of pft_lfsr is
-
-- uses preferred pair of pritive trinomials
-- x^41 + x^20 + 1 and x^41 + x^3 + 1
-- see XAPP217
@@ -17,8 +15,6 @@ architecture rtl of pft_lfsr is
signal s2 : std_logic_vector(c_max - 1 downto 0);
signal nxt_s2 : std_logic_vector(c_max - 1 downto 0);
-
-
begin
regs: process(rst,clk)
begin
@@ -52,6 +48,4 @@ begin
nxt_s2(c2) <= s2(c_max - 1) xor s2(c2 - 1);
end if;
end process;
-
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
index f8737106856a2eebece03226c6b6db703834d6e9..c6250be5bcfe8928822af3b70a4ea08bd354f43f 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_lfsr.vhd
@@ -36,9 +36,7 @@ entity pft_lfsr is
);
end pft_lfsr;
-
architecture rtl of pft_lfsr is
-
-- uses preferred pair of pritive trinomials
-- x^41 + x^20 + 1 and x^41 + x^3 + 1
-- see XAPP217
@@ -52,8 +50,6 @@ architecture rtl of pft_lfsr is
signal s2 : std_logic_vector(c_max - 1 downto 0);
signal nxt_s2 : std_logic_vector(c_max - 1 downto 0);
-
-
begin
regs: process(rst,clk)
begin
@@ -87,6 +83,4 @@ begin
nxt_s2(c2) <= s2(c_max - 1) xor s2(c2 - 1);
end if;
end process;
-
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
index b1feb26ef2ee2e7fb08e00713fbbeb92adbc74ba..75fcb992ca37e651d4d4fac16d9fc9a089c70e99 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_pkg.vhd
@@ -28,7 +28,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package pft_pkg is
-
constant c_pft_twiddle_w : natural := 16;
constant c_pft_stage_dat_w : natural := 20;
@@ -42,11 +41,7 @@ package pft_pkg is
PFT_BF1,
PFT_BF2
);
-
end pft_pkg;
-
package body pft_pkg is
end pft_pkg;
-
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
index 38d53ce352b7d76e2573f24aad26f7a6a97218ca..86d5cdd9f8b248a002e0fb1f7400bdf123eebcbc 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse(rtl).vhd
@@ -2,18 +2,13 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
architecture rtl of pft_reverse is
-
signal i_rdaddr : std_logic_vector(rdaddr'range);
signal nxt_rdaddr : std_logic_vector(rdaddr'range);
signal i_rden : std_logic;
signal nxt_rden : std_logic;
signal rdrdy : std_logic;
-
-
begin
-
rdaddr <= i_rdaddr;
rden <= i_rden;
page_done <= rdrdy;
@@ -33,7 +28,6 @@ begin
end if;
end process;
-
read_enable_control : process (i_rden, page_rdy, rdrdy)
begin
nxt_rden <= i_rden;
@@ -44,7 +38,6 @@ begin
end if;
end process;
-
read_addr_control : process (i_rdaddr, i_rden)
begin
rdrdy <= '0';
@@ -57,10 +50,8 @@ begin
end if;
end process;
-
out_dat_re <= rddata_re when rdval = '1' else (others => '0');
out_dat_im <= rddata_im when rdval = '1' else (others => '0');
out_val <= '1' when rdval = '1' else '0';
out_sync <= '1' when rdsync = '1' else '0';
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
index c74f2d8e2904595322b29c7d02254c6da00ee391..80ebdc99694b1ed0082d0329a9a70f65f1014c96 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_reverse.vhd
@@ -33,7 +33,6 @@ entity pft_reverse is
g_fft_sz_w : natural;
g_data_w : natural
);
-
port (
rddata_re : in std_logic_vector(g_data_w - 1 downto 0);
rddata_im : in std_logic_vector(g_data_w - 1 downto 0);
@@ -52,18 +51,13 @@ entity pft_reverse is
);
end pft_reverse;
-
architecture rtl of pft_reverse is
-
signal i_rdaddr : std_logic_vector(rdaddr'range);
signal nxt_rdaddr : std_logic_vector(rdaddr'range);
signal i_rden : std_logic;
signal nxt_rden : std_logic;
signal rdrdy : std_logic;
-
-
begin
-
rdaddr <= i_rdaddr;
rden <= i_rden;
page_done <= rdrdy;
@@ -83,7 +77,6 @@ begin
end if;
end process;
-
read_enable_control : process (i_rden, page_rdy, rdrdy)
begin
nxt_rden <= i_rden;
@@ -94,7 +87,6 @@ begin
end if;
end process;
-
read_addr_control : process (i_rdaddr, i_rden)
begin
rdrdy <= '0';
@@ -107,7 +99,6 @@ begin
end if;
end process;
-
out_dat_re <= rddata_re when rdval = '1' else (others => '0');
out_dat_im <= rddata_im when rdval = '1' else (others => '0');
out_val <= '1' when rdval = '1' else '0';
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
index b5b97ee960275171a3808ae42c912b34919c91ac..885d8a147e4ce267f05bdcc4e7fbf506db9f85c8 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate(rtl).vhd
@@ -6,7 +6,6 @@ library common_lib;
use common_lib.all;
architecture rtl of pft_separate is
-
constant c_reg_delay : natural := 2;
constant c_add_delay : natural := 2;
constant c_tot_delay : natural := c_reg_delay + c_add_delay;
@@ -46,10 +45,7 @@ architecture rtl of pft_separate is
signal sub1 : std_logic_vector(rddata_re'range);
signal nxt_sub0 : std_logic_vector(rddata_re'range);
signal nxt_sub1 : std_logic_vector(rddata_re'range);
-
begin
-
-
registers : process (rst, clk)
begin
if rst = '1' then
@@ -118,7 +114,6 @@ begin
end if;
end process;
-
addr_gen : process (cnt)
begin
rdaddr <= (others => '0');
@@ -164,7 +159,6 @@ begin
end if;
end process;
-
nxt_out_dat_re <= add_out;
nxt_out_dat_im <= sub_out;
nxt_out_val <= rdval_dly(rdval_dly'high);
@@ -237,6 +231,4 @@ begin
in_b => sub1,
result => sub_out
);
-
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
index 41325aa1fa2e48c8c363f981fcdfa42527636d80..538b57aac83328aa950606c8ec148b4e48c09ae2 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_separate.vhd
@@ -34,7 +34,6 @@ entity pft_separate is
g_rd_dat_w : natural;
g_out_dat_w : natural
);
-
port (
rddata_re : in std_logic_vector(g_rd_dat_w - 1 downto 0);
rddata_im : in std_logic_vector(g_rd_dat_w - 1 downto 0);
@@ -52,9 +51,7 @@ entity pft_separate is
);
end pft_separate;
-
architecture rtl of pft_separate is
-
constant c_reg_delay : natural := 2;
constant c_add_delay : natural := 2;
constant c_tot_delay : natural := c_reg_delay + c_add_delay;
@@ -94,10 +91,7 @@ architecture rtl of pft_separate is
signal sub1 : std_logic_vector(rddata_re'range);
signal nxt_sub0 : std_logic_vector(rddata_re'range);
signal nxt_sub1 : std_logic_vector(rddata_re'range);
-
begin
-
-
registers : process (rst, clk)
begin
if rst = '1' then
@@ -166,7 +160,6 @@ begin
end if;
end process;
-
addr_gen : process (cnt)
begin
rdaddr <= (others => '0');
@@ -212,7 +205,6 @@ begin
end if;
end process;
-
nxt_out_dat_re <= add_out;
nxt_out_dat_im <= sub_out;
nxt_out_val <= rdval_dly(rdval_dly'high);
@@ -285,5 +277,4 @@ begin
in_b => sub1,
result => sub_out
);
-
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
index 6a4eb2c67ab85f6652ae6fd02be545fb70025a2b..b4069cd55e894f35425bc864e9ccead2124b2f93 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage(str).vhd
@@ -23,7 +23,6 @@ library common_lib, pft2_lib;
use common_lib.all;
architecture str of pft_stage is
-
constant c_round_pipeline_in : natural := 1;
constant c_round_pipeline_out : natural := 1;
constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
@@ -40,11 +39,8 @@ architecture str of pft_stage is
signal bf2_im : std_logic_vector(c_bf2_out_w - 1 downto 0);
signal bf2_val : std_logic;
signal bf2_sync : std_logic;
-
begin
-
gen_middle: if g_index > 0 generate
-
bf1 : entity pft2_lib.pft_bf
generic map (
g_index => 2 * g_index + 1,
@@ -106,7 +102,6 @@ begin
end generate;
gen_last: if g_index = 0 generate
-
signal reg_val : std_logic;
signal reg_sync : std_logic;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
index 80b92de2b096c821e3116399aee043e22b2482bf..08b73281a27042197d8ee89d6f075cf2c1679cfd 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_stage.vhd
@@ -26,7 +26,6 @@
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
-
entity pft_stage is
generic (
g_index : natural;
@@ -47,9 +46,7 @@ entity pft_stage is
);
end pft_stage;
-
architecture str of pft_stage is
-
constant c_round_pipeline_in : natural := 1;
constant c_round_pipeline_out : natural := 1;
constant c_round_pipeline : natural := c_round_pipeline_in + c_round_pipeline_out;
@@ -66,11 +63,8 @@ architecture str of pft_stage is
signal bf2_im : std_logic_vector(c_bf2_out_w - 1 downto 0);
signal bf2_val : std_logic;
signal bf2_sync : std_logic;
-
begin
-
gen_middle: if g_index > 0 generate
-
bf1 : entity work.pft_bf
generic map (
g_index => 2 * g_index + 1,
@@ -132,7 +126,6 @@ begin
end generate;
gen_last: if g_index = 0 generate
-
signal reg_val : std_logic;
signal reg_sync : std_logic;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
index e7243c4796e8b23b5890c6bc3ab04bf1523dbf3b..f721e586262435efb9becf043fdc10c9dacd8185 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch(rtl).vhd
@@ -6,7 +6,6 @@ library pft2_lib;
use pft2_lib.all;
architecture rtl of pft_switch is
-
signal cnt : std_logic_vector(g_fft_sz_w downto 0);
signal nxt_cnt : std_logic_vector(cnt'range);
@@ -18,9 +17,7 @@ signal nxt_out_val : std_logic;
signal nxt_out_sync : std_logic;
signal nxt_out_re : std_logic_vector(in_re'range);
signal nxt_out_im : std_logic_vector(in_im'range);
-
begin
-
registers : process (rst, clk)
begin
if rst = '1' then
@@ -83,7 +80,4 @@ begin
out_bit1 => lfsr_bit1,
out_bit2 => lfsr_bit2
);
-
-
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
index 2932e0745d73a698ab45b3d4011ca7acb6a10e36..0c6daed641bee4d02364616f52b3da4f03912ad7 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_switch.vhd
@@ -23,7 +23,6 @@
-- Description: Ported from LOFAR1, see readme_lofar1.txt
-- Remark: Put entity and architecture in same file without () in file name.
-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -33,7 +32,6 @@ entity pft_switch is
g_fft_sz_w : natural;
g_dat_w : natural
);
-
port (
in_re : in std_logic_vector(g_dat_w - 1 downto 0);
in_im : in std_logic_vector(g_dat_w - 1 downto 0);
@@ -49,9 +47,7 @@ entity pft_switch is
);
end pft_switch;
-
architecture rtl of pft_switch is
-
signal cnt : std_logic_vector(g_fft_sz_w downto 0);
signal nxt_cnt : std_logic_vector(cnt'range);
@@ -63,9 +59,7 @@ signal nxt_out_val : std_logic;
signal nxt_out_sync : std_logic;
signal nxt_out_re : std_logic_vector(in_re'range);
signal nxt_out_im : std_logic_vector(in_im'range);
-
begin
-
registers : process (rst, clk)
begin
if rst = '1' then
@@ -128,6 +122,4 @@ begin
out_bit1 => lfsr_bit1,
out_bit2 => lfsr_bit2
);
-
-
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
index d77f34405f227df3fcc4d86b5a5124459cdc1998..fc220fa98cf914dfde56a210489d62a7a3db4f9d 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult(rtl).vhd
@@ -29,7 +29,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
architecture rtl of pft_tmult is
-
constant c_nof_twids : natural := 16 * 2**(2 * (g_index - 1));
constant c_adr_w : natural := 2 + 2 * g_index;
@@ -82,9 +81,7 @@ architecture rtl of pft_tmult is
signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
-
begin
-
p_regs : process (clk, rst)
begin
if rst = '1' then
@@ -198,5 +195,4 @@ begin
out_im => out_im,
clk => clk
);
-
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
index fbe5a2b8f32fc592cabbae251f682bc4e6340bf5..e6ab7f98a95ffa1977924cc1b3b6c11e64902133 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_tmult.vhd
@@ -33,7 +33,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.pft_pkg.all;
-
entity pft_tmult is
generic (
g_in_dat_w : natural;
@@ -54,9 +53,7 @@ entity pft_tmult is
);
end pft_tmult;
-
architecture rtl of pft_tmult is
-
constant c_nof_twids : natural := 16 * 2**(2 * (g_index - 1));
constant c_adr_w : natural := 2 + 2 * g_index;
@@ -109,9 +106,7 @@ architecture rtl of pft_tmult is
signal coeff_dat : std_logic_vector(2 * c_coeff_w - 1 downto 0);
signal coeff_re : std_logic_vector(c_coeff_w - 1 downto 0);
signal coeff_im : std_logic_vector(c_coeff_w - 1 downto 0);
-
begin
-
p_regs : process (clk, rst)
begin
if rst = '1' then
@@ -225,5 +220,4 @@ begin
out_im => out_im,
clk => clk
);
-
end rtl;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
index 7eb587edd0bcbc0b62bf3f0d74cc68ece7abf8a2..6edd1a89f60db877e92ec5a3fc0c897ca8cad584 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_top(str).vhd
@@ -2,9 +2,7 @@ library IEEE, common_lib, pft2_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
architecture str of pft_top is
-
signal reg_in_re : std_logic_vector(g_in_dat_w - 1 downto 0);
signal reg_in_im : std_logic_vector(g_in_dat_w - 1 downto 0);
signal reg_in_val : std_logic;
@@ -19,9 +17,7 @@ architecture str of pft_top is
signal pfft_in_im : std_logic_vector(17 downto 0);
signal pfft_out_re : std_logic_vector(17 downto 0);
signal pfft_out_im : std_logic_vector(17 downto 0);
-
begin
-
registers : process(clk)
begin
if rising_edge(clk) then
@@ -56,5 +52,4 @@ begin
clk => clk,
rst => rst
);
-
end str;
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
index cf7f913ddbb170eb1ba274aa0adadbc500c5356d..f6d0eeb201ee792c957c8ca6152ec348f30e9341 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_top.vhd
@@ -26,4 +26,3 @@ entity pft_top is
rst : in std_logic
);
end pft_top;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
index 896495e46a6f6abe35cd9852abd88ff26713befc..e12c3622fe32f9a7f9dd5390db7f249959ea1788 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch(rtl).vhd
@@ -6,7 +6,6 @@ library pft2_lib;
use pft2_lib.all;
architecture rtl of pft_unswitch is
-
signal cnt : std_logic_vector(g_fft_sz_w downto 0);
signal nxt_cnt : std_logic_vector(cnt'range);
@@ -19,9 +18,7 @@ signal nxt_out_val : std_logic;
signal nxt_out_sync : std_logic;
signal nxt_out_re : std_logic_vector(in_re'range);
signal nxt_out_im : std_logic_vector(in_im'range);
-
begin
-
registers : process (rst, clk)
begin
if rst = '1' then
@@ -79,7 +76,4 @@ begin
out_bit1 => lfsr_bit1,
out_bit2 => lfsr_bit2
);
-
-
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
index 81add2c9817a505467689b534089547fd4dad4d5..726636e03b031b6933e1dfad0b6a0a8e589d7902 100644
--- a/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
+++ b/applications/lofar1/RSP/pft2/src/vhdl/pft_unswitch.vhd
@@ -27,13 +27,11 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity pft_unswitch is
generic (
g_fft_sz_w : natural;
g_dat_w : natural
);
-
port (
in_re : in std_logic_vector(g_dat_w - 1 downto 0);
in_im : in std_logic_vector(g_dat_w - 1 downto 0);
@@ -49,9 +47,7 @@ entity pft_unswitch is
);
end pft_unswitch;
-
architecture rtl of pft_unswitch is
-
signal cnt : std_logic_vector(g_fft_sz_w downto 0);
signal nxt_cnt : std_logic_vector(cnt'range);
@@ -64,9 +60,7 @@ signal nxt_out_val : std_logic;
signal nxt_out_sync : std_logic;
signal nxt_out_re : std_logic_vector(in_re'range);
signal nxt_out_im : std_logic_vector(in_im'range);
-
begin
-
registers : process (rst, clk)
begin
if rst = '1' then
@@ -124,7 +118,4 @@ begin
out_bit1 => lfsr_bit1,
out_bit2 => lfsr_bit2
);
-
-
end rtl;
-
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
index 3f6757eda46b4585f8069c732531225338fa4f6b..5294b0a66bf24ef523fb548d624319a6b7774459 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft.vhd
@@ -17,7 +17,6 @@ entity tb_pft is
end tb_pft;
architecture tb of tb_pft is
-
constant c_pft_in_file : string := g_tst_data_dir & "input.txt";
constant c_pft_out_file : string := g_tst_data_dir & "output.txt";
constant c_pft_ref_file : string := g_tst_data_dir & "reference.txt";
@@ -45,14 +44,12 @@ architecture tb of tb_pft is
-- SIGNAL ref_re : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
-- SIGNAL ref_im : STD_LOGIC_VECTOR(g_out_w-1 DOWNTO 0);
-- SIGNAL ref_val : STD_LOGIC;
-
begin
rst <= '0' after g_rst_period;
val <= '1' after g_rst_period + g_clk_period / 2;
clk <= not clk after g_clk_period / 2;
-
in_dat: entity tst_lib.tst_input
generic map (
g_file_name => c_pft_in_file,
@@ -92,7 +89,6 @@ begin
restart => '0'
);
-
pft : entity pft2_lib.pft
generic map (
g_fft_size_w => g_fft_size_w,
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
index 3fbd80e15ae9af7512dced48c49bbe5d148e6d9d..7c4aa160e924e499109ada8f001609d5febcfb05 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft2.vhd
@@ -92,7 +92,6 @@ entity tb_pft2 is
end tb_pft2;
architecture tb of tb_pft2 is
-
constant c_clk_period : time := 10 ns;
constant c_rst_period : natural := 20;
constant c_fft_size_w : natural := 10;
@@ -220,7 +219,6 @@ architecture tb of tb_pft2 is
signal diff_rdy : std_logic;
signal nxt_diff_rdy : std_logic;
-
-----------------------------------------------------------------------------
-- Procedures to scale and round the reference FFT results
-----------------------------------------------------------------------------
@@ -305,9 +303,7 @@ architecture tb of tb_pft2 is
end loop;
end if;
end proc_fft_real2_re;
-
begin
-
p_tb_end : process
begin
proc_common_wait_until_hi_lo(clk, out_val); -- end of test
@@ -326,7 +322,6 @@ begin
rst_sync <= '1', '0' after c_clk_period * (c_rst_period * 2 - 1); -- start in_sync pulse interval 1 clk cycle before first in_val = '1'
proc_common_gen_pulse(1, c_nof_block_per_sync * c_fft_size, '1', rst_sync, clk, in_sync);
-
-----------------------------------------------------------------------------
-- Input X, Y data
-----------------------------------------------------------------------------
@@ -363,7 +358,6 @@ begin
out_val => in_val_y
);
-
-----------------------------------------------------------------------------
-- Read expected Xre, Xim, Yre, Yim data
-----------------------------------------------------------------------------
@@ -473,7 +467,6 @@ begin
proc_fft_real2_im(ref_rdy, rd_dat_y_re, rd_dat_y_im, ref_real2_dat_y_im);
end generate;
-
-----------------------------------------------------------------------------
-- Verify
-----------------------------------------------------------------------------
@@ -486,7 +479,6 @@ begin
end if;
end process;
-
gen_diff_fft : if g_pft_mode = PFT_MODE_BITREV or g_pft_mode = PFT_MODE_COMPLEX generate
nxt_diff_cnt <= diff_cnt + 1 when out_val_dly = '1' and diff_cnt < c_fft_size-1 else
0 when out_val_dly = '1' and diff_cnt = c_fft_size-1 else
@@ -551,7 +543,6 @@ begin
diff_val <= out_val_dly;
-
-----------------------------------------------------------------------------
-- PFT
-----------------------------------------------------------------------------
@@ -578,7 +569,6 @@ begin
rst => rst
);
-
p_pft_reg : process(clk)
begin
if rising_edge(clk) then
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
index 7e4f250ff4af5a4daee1df9a045545b8b54c954e..cdc09c717a053e14a256d95aaf0a35ef34f2159d 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_pft_simple.vhd
@@ -7,13 +7,9 @@ use pft2_lib.pft_pkg.all;
use common_lib.common_pkg.all;
entity tb_pft is
-
-
end tb_pft;
-
architecture tb of tb_pft is
-
constant clk_period : time := 10 ns;
constant rst_period : time := 3 * clk_period;
constant g_in_dat_w : natural := 18;
@@ -41,9 +37,7 @@ architecture tb of tb_pft is
signal clk : std_logic := '1';
signal rst : std_logic := '1';
-
begin
-
regs : process(rst, clk)
begin
if rst = '1' then
@@ -115,7 +109,6 @@ begin
wait;
end process;
-
-- -----------------------------------------------------------------------------
-- --
-- -- X = Y is sliding impulse
@@ -139,7 +132,6 @@ begin
-- END PROCESS;
-- in_y <= in_x;
-
-----------------------------------------------------------------------------
--
-- X = sinus Fs/2 and Y = DC
@@ -160,7 +152,6 @@ begin
end if;
end process;
-
-- -----------------------------------------------------------------------------
-- --
-- -- X, Y is impulse 0, impulse 1 or DC
@@ -190,5 +181,4 @@ begin
-- END IF;
-- END IF;
-- END PROCESS;
-
end tb;
diff --git a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
index 541de50963536d8f24190cc9ff02c20ecf2e7c9f..48440aff8717881673e5e82c0fa2e71ab61d25f7 100644
--- a/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
+++ b/applications/lofar1/RSP/pft2/tb/vhdl/tb_tb_pft2.vhd
@@ -29,6 +29,7 @@ use IEEE.std_logic_1164.all;
entity tb_tb_pft2 is
end tb_tb_pft2;
+
use work.pft_pkg.all;
architecture tb of tb_tb_pft2 is
@@ -37,7 +38,6 @@ architecture tb of tb_tb_pft2 is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- >>> PFT settings
--g_switch_en : STD_LOGIC := '0';
--g_stage_dat_w : NATURAL := c_pft_stage_dat_w; -- c_pft_stage_dat_w = 20 in pft_pkg.vhd
@@ -128,5 +128,4 @@ begin
u_18_block_117_u_noise : entity work.tb_pft2 generic map(c_sw, 18, PFT_MODE_REAL2, "block_117", "u_noise", 2);
u_19_block_117_u_noise : entity work.tb_pft2 generic map(c_sw, 19, PFT_MODE_REAL2, "block_117", "u_noise", 2);
-- . for g_stage_dat_w > 20 tb result is still OK, but diff_max_* does not reduce further
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
index 824dd0c1b38a74270df9bef0867a8df581977119..36aaca529eb85f3b060a0b8c60f04698c276d2ec 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -87,14 +86,10 @@ entity lofar2_unb2b_adc_6ch_200MHz is
end lofar2_unb2b_adc_6ch_200MHz;
architecture str of lofar2_unb2b_adc_6ch_200MHz is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -111,7 +106,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
index 9a73f68341b22ec89bb94a78d4a49daabd5a48f1..d1e33a7ff0d788701309206613f646f48f8a0601 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_6ch_200MHz/tb_lofar2_unb2b_adc_6ch_200MHz.vhd
@@ -18,7 +18,6 @@
--
-------------------------------------------------------------------------------
-
-- Author: Jonathan Hargreaves
-- Purpose: Tb to show that lofar2_unb2b_adc_6ch_200MHz can simulate
-- Description:
@@ -39,7 +38,6 @@ entity tb_lofar2_unb2b_adc_6ch_200MHz is
end tb_lofar2_unb2b_adc_6ch_200MHz;
architecture tb of tb_lofar2_unb2b_adc_6ch_200MHz is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0; -- Back node 3
@@ -81,11 +79,7 @@ architecture tb of tb_lofar2_unb2b_adc_6ch_200MHz is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
-
begin
-
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -154,12 +148,10 @@ begin
JESD204B_SYNC_N => jesd204b_sync_n
);
-
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' after 1 us;
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
index bb69c74548aac01d4a11d8803a146dedc8b017c6..7e46728d34127e2043e52764741dcad8b2cd8b47 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/lofar2_unb2b_adc_full.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_adc_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,14 +85,10 @@ entity lofar2_unb2b_adc_full is
end lofar2_unb2b_adc_full;
architecture str of lofar2_unb2b_adc_full is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -110,7 +105,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_adc_lib.lofar2_unb2b_adc
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
index 09e5939db954296064b751b63b150bc8d8bbc83d..02076e8cc845c1469e638ecf7d10c6e04674db58 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_full/tb_lofar2_unb2b_adc_full.vhd
@@ -18,7 +18,6 @@
--
-------------------------------------------------------------------------------
-
-- Author: Jonathan Hargreaves
-- Purpose: Tb to show that lofar2_unb2b_adc_full can simulate
-- Description:
@@ -40,7 +39,6 @@ entity tb_lofar2_unb2b_adc_full is
end tb_lofar2_unb2b_adc_full;
architecture tb of tb_lofar2_unb2b_adc_full is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0; -- Back node 3
@@ -82,11 +80,7 @@ architecture tb of tb_lofar2_unb2b_adc_full is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
-
begin
-
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -155,12 +149,10 @@ begin
JESD204B_SYNC_N => jesd204b_sync_n
);
-
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' after 1 us;
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
index 8c022088a3b6da4b2bb1621e24ff113c0dafad0f..88acdb6b718de2b491b79f1c68a0de9a898b422f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/lofar2_unb2b_adc_one_node.vhd
@@ -18,7 +18,6 @@
--
-------------------------------------------------------------------------------\
-
-- Author : J Hargreaves
-- Purpose:
-- Wrapper for one node adc input test design
@@ -85,15 +84,11 @@ entity lofar2_unb2b_adc_one_node is
);
end lofar2_unb2b_adc_one_node;
-
architecture str of lofar2_unb2b_adc_one_node is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
index 4986bce1d00b51315eb996cb4f7e1067389fad32..768efa68b74c1bd9b3245e1b9ec0d5ee58f94def 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/revisions/lofar2_unb2b_adc_one_node/tb_lofar2_unb2b_adc_one_node.vhd
@@ -39,7 +39,6 @@ entity tb_lofar2_unb2b_adc_one_node is
end tb_lofar2_unb2b_adc_one_node;
architecture tb of tb_lofar2_unb2b_adc_one_node is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0; -- Back node 3
@@ -81,11 +80,7 @@ architecture tb of tb_lofar2_unb2b_adc_one_node is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
-
begin
-
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -154,12 +149,10 @@ begin
JESD204B_SYNC_N => jesd204b_sync_n
);
-
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' after 1 us;
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
index 81e79079929ff42b4157acada027af797b4cd2af..f23f05116a5a424ccf0273da9f2827046a750d00 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc.vhd
@@ -18,7 +18,6 @@
--
-------------------------------------------------------------------------------
-
-- Author : J Hargreaves
-- Purpose:
-- Core design for Lofar2 ADC input stage
@@ -93,9 +92,7 @@ entity lofar2_unb2b_adc is
);
end lofar2_unb2b_adc;
-
architecture str of lofar2_unb2b_adc is
-
-- Revision parameters
constant c_revision_select : t_lofar2_unb2b_adc_config := func_sel_revision_rec(g_design_name);
constant c_nof_streams : natural := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
@@ -104,7 +101,6 @@ architecture str of lofar2_unb2b_adc is
constant c_fw_version : t_unb2b_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
-
-- System
signal cs_sim : std_logic;
signal xo_ethclk : std_logic;
@@ -227,9 +223,7 @@ architecture str of lofar2_unb2b_adc is
-- JESD control
signal jesd_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
signal jesd_ctrl_miso : t_mem_miso := c_mem_miso_rst;
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -438,7 +432,6 @@ begin
reg_aduh_monitor_miso => reg_aduh_monitor_miso
);
-
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
@@ -516,6 +509,4 @@ begin
red_led_arr => qsfp_red_led_arr,
QSFP_LED => QSFP_LED
);
-
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
index 00c4a2d4265bb03d5fe5ce2559bd201eb327c63c..27c3add61508aed51f55a6e905fd5bd8f45c96ba 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/lofar2_unb2b_adc_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package lofar2_unb2b_adc_pkg is
-
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -43,12 +42,9 @@ package lofar2_unb2b_adc_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_adc_config;
-
end lofar2_unb2b_adc_pkg;
-
package body lofar2_unb2b_adc_pkg is
-
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_adc_config is
begin
if g_design_name = "lofar2_unb2b_adc_one_node" then return c_one_node;
@@ -56,8 +52,7 @@ package body lofar2_unb2b_adc_pkg is
elsif g_design_name = "lofar2_unb2b_adc_6ch_200MHz" then return c_full;
else return c_one_node;
end if;
- end;
+ end;
end lofar2_unb2b_adc_pkg;
-
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
index 3e138949c39a8af07e7cf8fa5ddda99a3259d9dc..daffa485ac9a95f2265164cc80f90ed0bb1062c9 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/mmm_lofar2_unb2b_adc.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_lofar2_unb2b_adc_pkg.all;
-
entity mmm_lofar2_unb2b_adc is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -144,19 +143,15 @@ entity mmm_lofar2_unb2b_adc is
end mmm_lofar2_unb2b_adc;
architecture str of mmm_lofar2_unb2b_adc is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -220,7 +215,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
@@ -237,7 +231,6 @@ begin
-- the_pio_wdi: toggled by NIOS II application unb_osy. Connects to WDI via ctrl_unb2b_board.
pio_wdi_external_connection_export => pout_wdi,
-
avs_eth_0_reset_export => eth1g_mm_rst,
avs_eth_0_clk_export => OPEN,
avs_eth_0_tse_address_export => eth1g_tse_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_tse_adr_w - 1 downto 0),
@@ -439,7 +432,6 @@ begin
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
ram_diag_data_buffer_bsn_clk_export => OPEN,
ram_diag_data_buffer_bsn_reset_export => OPEN,
ram_diag_data_buffer_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(21 - 1 downto 0), -- 22 = ceil_log2(12 * 256k), so maximum possible data buffer size is 256 kSamples
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
index 594eb65cf5c9af8be21c71d8cf15589c57319506..869b3d932d615a4da5f73c9a8440766d3460d248 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/node_adc_input_and_timing.vhd
@@ -55,7 +55,6 @@ entity node_adc_input_and_timing is
dp_clk : in std_logic;
dp_rst : in std_logic;
-
-- mm control buses
-- JESD
jesd204b_mosi : in t_mem_mosi := c_mem_mosi_rst;
@@ -117,9 +116,7 @@ entity node_adc_input_and_timing is
);
end node_adc_input_and_timing;
-
architecture str of node_adc_input_and_timing is
-
constant c_nof_streams_jesd204b : natural := 12; -- IP is set up for 12 streams
constant c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
@@ -146,7 +143,6 @@ architecture str of node_adc_input_and_timing is
constant c_data_w : natural := 16;
constant c_dp_fifo_dc_size : natural := 64;
-
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
@@ -170,9 +166,7 @@ architecture str of node_adc_input_and_timing is
signal mm_jesd_ctrl_reg : std_logic_vector(c_word_w - 1 downto 0);
signal jesd204b_disable_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal jesd204b_reset : std_logic;
-
begin
-
-- The node AIT is reset at power up by mm_rst and under software control by jesd204b_reset.
-- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
-- The MM jesd204b_reset is intended for node AIT resynchronisation tests of the u_jesd204b.
@@ -182,6 +176,7 @@ begin
-- complete blocks, so from sop to eop.
mm_rst_internal <= mm_rst or mm_jesd_ctrl_reg(31);
+
gen_jesd_disable : for I in 0 to c_nof_streams_jesd204b - 1 generate
jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
end generate;
@@ -221,7 +216,6 @@ begin
serial_rx_arr => JESD204B_SERIAL_DATA(c_nof_streams_jesd204b - 1 downto 0)
);
-
-----------------------------------------------------------------------------
-- Time delay: dp_shiftram
-- . copied from unb1_bn_capture_input (apertif)
@@ -237,7 +231,6 @@ begin
end process;
end generate;
-
u_dp_shiftram : entity dp_lib.dp_shiftram
generic map (
g_nof_streams => c_nof_streams_jesd204b,
@@ -309,7 +302,6 @@ begin
trigger_out => trigger_wg
);
-
-----------------------------------------------------------------------------
-- WG (Test Signal Generator)
-----------------------------------------------------------------------------
@@ -349,7 +341,6 @@ begin
out_sosi_arr => wg_sosi_arr
);
-
-----------------------------------------------------------------------------
-- ADC/WG Mux (Input Select)
-----------------------------------------------------------------------------
@@ -380,7 +371,6 @@ begin
end process;
end generate;
-
---------------------------------------------------------------------------------------
-- Diagnostics on the bsn-framed data
-- . BSN Monitor (ToDo: can be removed as not part of the spec)
@@ -388,7 +378,6 @@ begin
-- . Data Buffer (variable depth from 1k-128k)
---------------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------------
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
@@ -412,7 +401,6 @@ begin
in_sosi_arr => st_sosi_arr(0 downto 0)
);
-
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
-----------------------------------------------------------------------------
@@ -443,7 +431,6 @@ begin
in_sosi_arr => st_sosi_arr
);
-
-----------------------------------------------------------------------------
-- Diagnostic Data Buffer
-----------------------------------------------------------------------------
@@ -470,7 +457,6 @@ begin
in_sync => st_sosi_arr(0).sync
);
-
-----------------------------------------------------------------------------
-- Output Stage
-- . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
@@ -519,5 +505,4 @@ begin
out_reg => mm_jesd_ctrl_reg,
in_reg => mm_jesd_ctrl_reg
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
index 8bc5901363b4477a94d5db4e370b7472d0e30ec0..cd479c2bdbe001e2bd25df14c936a10be5cffdda 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/src/vhdl/qsys_lofar2_unb2b_adc_pkg.vhd
@@ -19,12 +19,10 @@
--
-------------------------------------------------------------------------------
-
library IEEE;
use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_adc_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
@@ -238,5 +236,5 @@ package qsys_lofar2_unb2b_adc_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_adc;
-end qsys_lofar2_unb2b_adc_pkg;
+end qsys_lofar2_unb2b_adc_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
index 1e1167a1cd7f0173ac70248cd0d2743012d5fc2b..627ac45ba488fb71a0073ea24bb1a910369afdf6 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc.vhd
@@ -41,7 +41,6 @@ entity tb_lofar2_unb2b_adc is
end tb_lofar2_unb2b_adc;
architecture tb of tb_lofar2_unb2b_adc is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0; -- Back node 3
@@ -83,11 +82,7 @@ architecture tb of tb_lofar2_unb2b_adc is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w) - 1 downto 0);
-
-
begin
-
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -158,12 +153,10 @@ begin
JESD204B_SYNC_N => jesd204b_sync_n
);
-
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' after 1 us;
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
index 6fe9a16e9b801fbe5337eb73d48efa6ecf401337..16294442b7b7a21a596125399d2de3cd0c9483c8 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_multichannel.vhd
@@ -42,7 +42,6 @@ entity tb_lofar2_unb2b_adc_multichannel is
end tb_lofar2_unb2b_adc_multichannel;
architecture tb of tb_lofar2_unb2b_adc_multichannel is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0; -- Back node 3
@@ -86,8 +85,6 @@ architecture tb of tb_lofar2_unb2b_adc_multichannel is
1000 ps); -- transport delays clock source to adc(tx)
constant c_delay_sysreftofpga : time := 10200 ps;
-
-
-- clocks and resets for the jesd204b tx
signal txlink_clk : std_logic_vector(c_nof_jesd204b_tx - 1 downto 0);
signal dev_sync_n : std_logic_vector(c_nof_jesd204b_tx - 1 downto 0);
@@ -159,10 +156,7 @@ architecture tb of tb_lofar2_unb2b_adc_multichannel is
signal avs_read : std_logic_vector(11 downto 0);
signal avs_readdata : t_slv_32_arr(11 downto 0);
signal avs_address : t_slv_8_arr(11 downto 0);
-
begin
-
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -232,7 +226,6 @@ begin
JESD204B_SYNC_N => jesd204b_sync_n_fpga
);
-
-----------------------------------------------------------------------------
-- Transport
-----------------------------------------------------------------------------
@@ -343,16 +336,12 @@ begin
jesd204b_tx_link_data_arr(i)(31 downto 16) <= TO_SVEC(data, 16);
jesd204b_tx_link_valid(i) <= '1';
end if;
-
end if;
end if;
end process;
-
-
end generate;
-
-----------------------------------------------------------------------------
-- Stimulii
-----------------------------------------------------------------------------
@@ -498,5 +487,4 @@ begin
sim_done <= '0';
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
index c1689b31e3340fc67f895d0cb3cca31b3e949c44..470c7ab17576fd1237034c445cf190d39a3004df 100644
--- a/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_adc/tb/vhdl/tb_lofar2_unb2b_adc_wg.vhd
@@ -62,7 +62,6 @@ entity tb_lofar2_unb2b_adc_wg is
end tb_lofar2_unb2b_adc_wg;
architecture tb of tb_lofar2_unb2b_adc_wg is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -114,7 +113,6 @@ architecture tb of tb_lofar2_unb2b_adc_wg is
constant c_mm_file_reg_aduh_mon : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_ADUH_MONITOR";
constant c_mm_file_ram_aduh_mon : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ADUH_MONITOR";
-
-- Tb
signal tb_end : std_logic := '0';
signal sim_done : std_logic := '0';
@@ -154,9 +152,7 @@ architecture tb of tb_lofar2_unb2b_adc_wg is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w) - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -335,5 +331,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
index cd8df535cd1533dccb1b91fcd305abd22fb9992c..90b3f265619797cda4aaf7e0ba26920a0409748c 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node/lofar2_unb2b_beamformer_one_node.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -93,14 +92,10 @@ entity lofar2_unb2b_beamformer_one_node is
end lofar2_unb2b_beamformer_one_node;
architecture str of lofar2_unb2b_beamformer_one_node is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -117,7 +112,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_beamformer_lib.lofar2_unb2b_beamformer
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
index 1fd5cbce8c6e6d2b126f439be8cdb037a7281d06..ebaa797084ef9a4b6a073ae64fc2e71cae0a060d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/revisions/lofar2_unb2b_beamformer_one_node_256MHz/lofar2_unb2b_beamformer_one_node_256MHz.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF with a DP_clk of 256MHz
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_beamformer_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -93,14 +92,10 @@ entity lofar2_unb2b_beamformer_one_node_256MHz is
end lofar2_unb2b_beamformer_one_node_256MHz;
architecture str of lofar2_unb2b_beamformer_one_node_256MHz is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -117,7 +112,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_beamformer_lib.lofar2_unb2b_beamformer
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
index 45b42b43b07a8a5dbddcc81087e80f4ab90f5caf..0d815568ee1674d47062268d8106f9c41ab9358d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer.vhd
@@ -102,9 +102,7 @@ entity lofar2_unb2b_beamformer is
);
end lofar2_unb2b_beamformer;
-
architecture str of lofar2_unb2b_beamformer is
-
-- Revision parameters
constant c_revision_select : t_lofar2_unb2b_beamformer_config := func_sel_revision_rec(g_design_name);
constant c_nof_streams : natural := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
@@ -133,14 +131,12 @@ architecture str of lofar2_unb2b_beamformer is
constant c_addr_w_reg_dp_xonoff : natural := 1;
constant c_addr_w_ram_st_bst : natural := ceil_log2(c_sdp_S_sub_bf * c_sdp_N_pol * (c_longword_sz / c_word_sz));
-
-- Read only sdp_info values
constant c_f_adc : std_logic := '1'; -- '0' => 160M, '1' => 200M
constant c_fsub_type : std_logic := '0'; -- '0' => critical sampled PFB, '1' => oversampled PFB
signal gn_id : std_logic_vector(c_sdp_W_gn_id - 1 downto 0);
signal gn_index : natural := 0;
-
-- System
signal cs_sim : std_logic;
signal xo_ethclk : std_logic;
@@ -383,7 +379,6 @@ architecture str of lofar2_unb2b_beamformer is
signal sdp_info : t_sdp_info := c_sdp_info_rst;
-
-- QSFP LEDS
signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
@@ -391,11 +386,7 @@ architecture str of lofar2_unb2b_beamformer is
signal unb2_board_qsfp_leds_snk_in_arr : t_dp_sosi_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_sosi_rst);
signal unb2_board_qsfp_leds_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_siso_rst);
signal unb2_board_qsfp_leds_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_sosi_rst);
-
-
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -732,7 +723,6 @@ begin
out_sosi_arr => ait_sosi_arr
);
-
-----------------------------------------------------------------------------
-- node_sdp_filterbank (FSUB)
-----------------------------------------------------------------------------
@@ -771,8 +761,6 @@ begin
udp_src_port => sst_udp_src_port
);
-
-
-- Beamformers
gen_bf : for beamset_id in 0 to c_sdp_N_beamsets - 1 generate
u_bf : entity lofar2_sdp_lib.node_sdp_beamformer
@@ -815,7 +803,6 @@ begin
hdr_fields_out => bf_10GbE_hdr_fields_out_arr(beamset_id)
);
-
end generate;
-- MM multiplexing
@@ -891,8 +878,6 @@ begin
miso_arr => ram_st_bst_miso_arr
);
-
-
-----------------------------------------------------------------------------
-- DP MUX
-----------------------------------------------------------------------------
@@ -919,7 +904,6 @@ begin
src_in => nw_10gbe_snk_out_arr(0)
);
-
-----------------------------------------------------------------------------
-- Interface : 10GbE
-----------------------------------------------------------------------------
@@ -947,7 +931,6 @@ begin
QSFP_LED => QSFP_LED
);
-
---------
-- PLL
---------
@@ -963,7 +946,6 @@ begin
rst_312 => open
);
-
---------------
-- nw_10GbE
---------------
@@ -1012,5 +994,4 @@ begin
hdr_fields_in_arr => nw_10GbE_hdr_fields_in_arr
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
index c9c60af0b844fc52c4086213f2e2bc1adbcd0144..5fc60b88b1e6f6c4e1072a7becc7aedb2b2dbd71 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/lofar2_unb2b_beamformer_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_beamformer_pkg is
-
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -45,20 +44,16 @@ package lofar2_unb2b_beamformer_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_beamformer_config;
-
end lofar2_unb2b_beamformer_pkg;
-
package body lofar2_unb2b_beamformer_pkg is
-
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_beamformer_config is
begin
if g_design_name = "lofar2_unb2b_beamformer_one_node" then return c_one_node;
elsif g_design_name = "lofar2_unb2b_beamformer_one_node_256MHz" then return c_one_node_256MHz;
else return c_one_node;
end if;
- end;
+ end;
end lofar2_unb2b_beamformer_pkg;
-
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
index 75fed2788b1766b75186e6eff963a25dcd9c98e8..27f912bd203d366a6d1cafe3ffe0fad8ae38d046 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/mmm_lofar2_unb2b_beamformer.vhd
@@ -205,20 +205,15 @@ entity mmm_lofar2_unb2b_beamformer is
end mmm_lofar2_unb2b_beamformer;
architecture str of mmm_lofar2_unb2b_beamformer is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -331,7 +326,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
@@ -541,7 +535,6 @@ begin
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
ram_diag_data_buf_bsn_clk_export => OPEN,
ram_diag_data_buf_bsn_reset_export => OPEN,
ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(14 - 1 downto 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
index eec711a09d8adc334307f169cc51d002e95c20db..1df2a17b4164dfe45e634bc1c67f6ca4b3a2b35b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/src/vhdl/qsys_lofar2_unb2b_beamformer_pkg.vhd
@@ -22,7 +22,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_beamformer_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
@@ -346,5 +345,5 @@ package qsys_lofar2_unb2b_beamformer_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_beamformer;
-end qsys_lofar2_unb2b_beamformer_pkg;
+end qsys_lofar2_unb2b_beamformer_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
index 64c94a7e6b1ad5d4678fe07d04d511f8c68cd8c5..aef82a89ff36116894d3267561d23df702a525e7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_beamformer/tb/vhdl/tb_lofar2_unb2b_beamformer.vhd
@@ -68,7 +68,6 @@ entity tb_lofar2_unb2b_beamformer is
end tb_lofar2_unb2b_beamformer;
architecture tb of tb_lofar2_unb2b_beamformer is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -192,9 +191,7 @@ architecture tb of tb_lofar2_unb2b_beamformer is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w) - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -314,7 +311,6 @@ begin
);
-
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
@@ -332,7 +328,6 @@ begin
proc_common_wait_until_hi_lo(ext_clk, ext_pps);
-
----------------------------------------------------------------------------
-- Enable UDP offload (dp_xonoff) of beamset 0
----------------------------------------------------------------------------
@@ -453,7 +448,6 @@ begin
proc_common_wait_some_cycles(tb_clk, 1);
-
---------------------------------------------------------------------------
-- Read 10GbE Stream
---------------------------------------------------------------------------
@@ -543,5 +537,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
index f40c7e042057c428770ffd49179b6d469022fead..bae7a2ad5adc1e17b9214db699ee4da18638515d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full/lofar2_unb2b_filterbank_full.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,14 +85,10 @@ entity lofar2_unb2b_filterbank_full is
end lofar2_unb2b_filterbank_full;
architecture str of lofar2_unb2b_filterbank_full is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -110,7 +105,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_filterbank_lib.lofar2_unb2b_filterbank
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
index 74c1bb4c1d9138c3b10927c09d0834f48c7326b5..e541eecf75e176cc2737f809a6499ac7cc2f8d40 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/revisions/lofar2_unb2b_filterbank_full_256MHz/lofar2_unb2b_filterbank_full_256MHz.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_filterbank_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,14 +85,10 @@ entity lofar2_unb2b_filterbank_full_256MHz is
end lofar2_unb2b_filterbank_full_256MHz;
architecture str of lofar2_unb2b_filterbank_full_256MHz is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -110,7 +105,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_filterbank_lib.lofar2_unb2b_filterbank
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
index 99bc1ee68fb58eed04af6237661be1500a81c757..9a0af000e4e08da7987274fa4ee76a468ce5f354 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank.vhd
@@ -98,9 +98,7 @@ entity lofar2_unb2b_filterbank is
);
end lofar2_unb2b_filterbank;
-
architecture str of lofar2_unb2b_filterbank is
-
-- Revision parameters
constant c_revision_select : t_lofar2_unb2b_filterbank_config := func_sel_revision_rec(g_design_name);
constant c_nof_streams : natural := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
@@ -285,7 +283,6 @@ architecture str of lofar2_unb2b_filterbank is
signal sdp_info : t_sdp_info := c_sdp_info_rst;
-
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
@@ -297,9 +294,7 @@ architecture str of lofar2_unb2b_filterbank is
-- JESD control
signal jesd_ctrl_mosi : t_mem_mosi := c_mem_mosi_rst;
signal jesd_ctrl_miso : t_mem_miso := c_mem_miso_rst;
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -677,5 +672,4 @@ begin
ip_src_addr => stat_ip_src_addr,
udp_src_port => sst_udp_src_port
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
index 54639dc946a470a69a6b6106204ef7a0a315c155..7b732860482965946a9be4fd98a18552c43ea78b 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/lofar2_unb2b_filterbank_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_filterbank_pkg is
-
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -45,20 +44,16 @@ package lofar2_unb2b_filterbank_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_filterbank_config;
-
end lofar2_unb2b_filterbank_pkg;
-
package body lofar2_unb2b_filterbank_pkg is
-
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_filterbank_config is
begin
if g_design_name = "lofar2_unb2b_filterbank_full" then return c_full;
elsif g_design_name = "lofar2_unb2b_filterbank_full_256MHz" then return c_full_256MHz;
else return c_full;
end if;
- end;
+ end;
end lofar2_unb2b_filterbank_pkg;
-
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
index 27c0955ee36b54a8100034d1548836098800f3c9..736f555d99d7bab483adde375befeb779fe9e9e7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/mmm_lofar2_unb2b_filterbank.vhd
@@ -185,20 +185,15 @@ entity mmm_lofar2_unb2b_filterbank is
end mmm_lofar2_unb2b_filterbank;
architecture str of mmm_lofar2_unb2b_filterbank is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -294,7 +289,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
@@ -510,7 +504,6 @@ begin
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
ram_diag_data_buf_bsn_clk_export => OPEN,
ram_diag_data_buf_bsn_reset_export => OPEN,
ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(14 - 1 downto 0),
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
index e06b06d095f55ede1ac1d6dda07e6094fcee4d74..21dc8f5640f021b9394624c55618ecaf3286de3a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/src/vhdl/qsys_lofar2_unb2b_filterbank_pkg.vhd
@@ -22,7 +22,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_filterbank_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
@@ -314,5 +313,5 @@ package qsys_lofar2_unb2b_filterbank_pkg is
pio_jesd_ctrl_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component qsys_lofar2_unb2b_filterbank;
-end qsys_lofar2_unb2b_filterbank_pkg;
+end qsys_lofar2_unb2b_filterbank_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
index 034c6ca655f66c378dd10d7d628ae74472c50e15..a0ade62951545450169b348d329fc8db6ee5de08 100644
--- a/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_filterbank/tb/vhdl/tb_lofar2_unb2b_filterbank.vhd
@@ -69,7 +69,6 @@ entity tb_lofar2_unb2b_filterbank is
end tb_lofar2_unb2b_filterbank;
architecture tb of tb_lofar2_unb2b_filterbank is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -125,7 +124,6 @@ architecture tb of tb_lofar2_unb2b_filterbank is
constant c_mm_file_ram_aduh_mon : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ADUH_MONITOR";
constant c_mm_file_ram_st_sst : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
-
-- Tb
signal tb_end : std_logic := '0';
signal sim_done : std_logic := '0';
@@ -174,9 +172,7 @@ architecture tb of tb_lofar2_unb2b_filterbank is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector((c_unb2b_board_tr_jesd204b.nof_bus * c_unb2b_board_tr_jesd204b.bus_w) - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -422,5 +418,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
index 812ae5e19ab670740b46063e9e577b13f0b6a0a5..afbced0491d2897686cfa308ee72ff868e9ab676 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/lofar2_unb2b_ring_full.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete ring design with all 8 lanes.
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -93,7 +92,6 @@ end lofar2_unb2b_ring_full;
architecture str of lofar2_unb2b_ring_full is
begin
-
u_revision : entity lofar2_unb2b_ring_lib.lofar2_unb2b_ring
generic map (
g_design_name => g_design_name,
@@ -147,5 +145,4 @@ begin
-- LEDs
QSFP_LED => QSFP_LED
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
index 1731e4fb08ee7428c6eca7357956123d16c27f50..18ccf3dd9ee22e084b529e1a948256a2e6ecd29d 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_full/tb_lofar2_unb2b_ring_full.vhd
@@ -39,7 +39,6 @@ entity tb_lofar2_unb2b_ring_full is
end tb_lofar2_unb2b_ring_full;
architecture tb of tb_lofar2_unb2b_ring_full is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
@@ -81,11 +80,7 @@ architecture tb of tb_lofar2_unb2b_ring_full is
signal i_RING_0_RX : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
signal i_RING_1_TX : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
signal i_RING_1_RX : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
-
-
begin
-
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -153,12 +148,10 @@ begin
QSFP_LED => open
);
-
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' after 1 us;
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
index b2b6bae2fc99f862829262853cf7605fb98806ce..86bb45908a0af897cc16e31e7c6369e2846ec416 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/lofar2_unb2b_ring_one.vhd
@@ -28,7 +28,6 @@
-- Note that the amount of transceivers support 2 lanes, one even and one odd.
-- However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_ring_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -96,7 +95,6 @@ end lofar2_unb2b_ring_one;
architecture str of lofar2_unb2b_ring_one is
begin
-
u_revision : entity lofar2_unb2b_ring_lib.lofar2_unb2b_ring
generic map (
g_design_name => g_design_name,
@@ -150,5 +148,4 @@ begin
-- LEDs
QSFP_LED => QSFP_LED
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
index 171687d127158814e4ecdf7d330169133d686c77..eccc9a2de90ef4ffdfb240ba21b931328522b699 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/revisions/lofar2_unb2b_ring_one/tb_lofar2_unb2b_ring_one.vhd
@@ -39,7 +39,6 @@ entity tb_lofar2_unb2b_ring_one is
end tb_lofar2_unb2b_ring_one;
architecture tb of tb_lofar2_unb2b_ring_one is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
@@ -81,11 +80,7 @@ architecture tb of tb_lofar2_unb2b_ring_one is
signal i_RING_0_RX : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
signal i_RING_1_TX : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
signal i_RING_1_RX : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
-
-
begin
-
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -153,12 +148,10 @@ begin
QSFP_LED => open
);
-
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' after 1 us;
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
index 709c0583219b127462dd8e33bd88da11b10f9b86..dbf744910f3b14dca09265aa302b51d6732d67f0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring.vhd
@@ -43,7 +43,6 @@ use work.lofar2_unb2b_ring_pkg.all;
use eth_lib.eth_pkg.all;
use ring_lib.ring_pkg.all;
-
entity lofar2_unb2b_ring is
generic (
g_design_name : string := "lofar2_unb2b_ring";
@@ -102,9 +101,7 @@ entity lofar2_unb2b_ring is
);
end lofar2_unb2b_ring;
-
architecture str of lofar2_unb2b_ring is
-
-- Revision parameters
constant c_revision_select : t_lofar2_unb2b_ring_config := func_sel_revision_rec(g_design_name);
constant c_nof_lanes : natural := c_revision_select.N_ring_lanes;
@@ -152,7 +149,6 @@ architecture str of lofar2_unb2b_ring is
constant c_addr_w_reg_dp_block_validate_err : natural := ceil_log2(c_nof_err_counts + 3);
constant c_addr_w_reg_dp_block_validate_bsn_at_sync : natural := ceil_log2(3);
-
constant c_reg_ring_input_select : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_lanes),
dat_w => 1,
@@ -248,7 +244,6 @@ architecture str of lofar2_unb2b_ring is
signal reg_tr_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
signal reg_tr_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
-
signal reg_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
signal reg_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
signal ram_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
@@ -315,7 +310,6 @@ architecture str of lofar2_unb2b_ring is
signal tr_10gbe_src_in_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
signal tr_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
-
signal bs_sosi : t_dp_sosi := c_dp_sosi_rst;
signal local_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -330,7 +324,6 @@ architecture str of lofar2_unb2b_ring is
signal i_RING_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
signal i_RING_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
-
signal tr_10gbe_serial_tx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
signal tr_10gbe_serial_rx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
@@ -345,9 +338,7 @@ architecture str of lofar2_unb2b_ring is
signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
signal unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_unb2b_board_tr_qsfp.nof_bus * c_unb2b_board_tr_qsfp.bus_w - 1 downto 0) := (others => c_dp_siso_rst);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -640,7 +631,6 @@ begin
);
bs_sosi <= local_sosi;
-
-----------------------------------------------------------------------------
-- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
@@ -699,7 +689,6 @@ begin
-- DP Mux
-----------------------------------------------------------------------------
gen_dp_mux: for I in 0 to c_nof_lanes - 1 generate
-
dp_xonoff_lane_src_in_arr(I) <= dp_mux_snk_out_2arr(I)(0);
dp_xonoff_local_src_in_arr(I) <= dp_mux_snk_out_2arr(I)(1);
dp_mux_snk_in_2arr(I)(0) <= dp_xonoff_lane_src_out_arr(I);
@@ -922,7 +911,6 @@ begin
serial_rx_arr => tr_10gbe_serial_rx_arr
);
-
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
-----------------------------------------------------------------------------
@@ -1009,5 +997,4 @@ begin
tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
index d594f682efa11c6dd17ea8853b38d9a5f6637818..d922173d669de38fbd3b051ba1e456e904460dfc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/lofar2_unb2b_ring_pkg.vhd
@@ -25,7 +25,6 @@ use common_lib.common_pkg.all;
use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_ring_pkg is
-
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -41,19 +40,15 @@ package lofar2_unb2b_ring_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_ring_config;
-
end lofar2_unb2b_ring_pkg;
-
package body lofar2_unb2b_ring_pkg is
-
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_ring_config is
begin
if g_design_name = "lofar2_unb2b_ring_one" then return c_one;
else return c_full;
end if;
- end;
+ end;
end lofar2_unb2b_ring_pkg;
-
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
index b1396c516b2bee49db46541f75319f5f5b844f28..1ae1c752c22c1e09deeff3e8e390387ec3b170b3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/mmc_lofar2_unb2b_ring.vhd
@@ -150,20 +150,15 @@ entity mmc_lofar2_unb2b_ring is
end mmc_lofar2_unb2b_ring;
architecture str of mmc_lofar2_unb2b_ring is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
@@ -234,7 +229,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
index d30654d49c54eb9402d71a29a34d829bc70be9b0..44c943c0a76371ac71bff7354db5faa72e782bba 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/src/vhdl/qsys_lofar2_unb2b_ring_pkg.vhd
@@ -22,7 +22,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_ring_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
@@ -242,5 +241,5 @@ package qsys_lofar2_unb2b_ring_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_ring;
-end qsys_lofar2_unb2b_ring_pkg;
+end qsys_lofar2_unb2b_ring_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
index d8e3d8072608ce29446817305e3c7eeeb1ace22a..a41b295e624654a5b30cfca9e41c1f014839f0b1 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_lofar2_unb2b_ring.vhd
@@ -62,11 +62,9 @@ entity tb_lofar2_unb2b_ring is
port (
tb_end : out std_logic := '0' -- For multi tb
);
-
end tb_lofar2_unb2b_ring;
architecture tb of tb_lofar2_unb2b_ring is
-
constant c_sim : boolean := true;
constant c_node_nr : natural := 0;
constant c_version : std_logic_vector(1 downto 0) := "00";
@@ -92,7 +90,6 @@ architecture tb of tb_lofar2_unb2b_ring is
constant c_exp_nof_sop : natural := g_nof_block_per_sync;
constant c_exp_nof_valid : natural := g_nof_block_per_sync * c_blocksize;
-
-- MM
constant c_mm_file_reg_ring_info : string := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_RING_INFO";
constant c_mm_file_reg_ring_lane_info : string := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_RING_LANE_INFO";
@@ -136,10 +133,7 @@ architecture tb of tb_lofar2_unb2b_ring is
signal pmbus_sda : std_logic;
signal SA_CLK : std_logic := '1';
-
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -227,12 +221,11 @@ begin
i_RING_0_RX(I + 1) <= i_RING_1_TX(I);
i_RING_1_RX(I) <= i_RING_0_TX(I + 1);
end generate;
+
-- Connect first and last nodes with QSFP interface.
i_QSFP_0_RX(0) <= i_QSFP_0_TX(g_nof_rn - 1);
i_QSFP_0_RX(g_nof_rn - 1) <= i_QSFP_0_TX(0);
-
-
------------------------------------------------------------------------------
-- MM peripeheral accesses via file IO
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
index d71e7bdcae212b57682be46913228e94fc27ea8f..d3b80ca5d9bb1acacc0877d95d9ae7ab801c8751 100644
--- a/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_ring/tb/vhdl/tb_tb_lofar2_unb2b_ring.vhd
@@ -42,7 +42,6 @@ architecture tb of tb_tb_lofar2_unb2b_ring is
signal tb_end_vec : std_logic_vector(c_nof_tb - 1 downto 0) := (others => '0');
signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
begin
-
-- g_multi_tb : BOOLEAN := FALSE;
-- g_unb_nr : NATURAL := 4;
-- g_design_name : STRING := "lofar2_unb2c_ring_one";
@@ -61,5 +60,4 @@ begin
tb_end <= vector_and(tb_end_vec);
proc_common_stop_simulation(tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
index b8a355302520c66ac1a2579b6dfaaa917c5c71b5..bd619d79329a78c77405e68e916edc70d06c6e90 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full/disturb2_unb2b_sdp_station_full.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, oversampeld FSUB, XSUB, BF and RING
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -102,14 +101,10 @@ entity disturb2_unb2b_sdp_station_full is
end disturb2_unb2b_sdp_station_full;
architecture str of disturb2_unb2b_sdp_station_full is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -126,7 +121,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
index 06248f95620a21ef6fdf40334e3ed9dd347e2208..f8d63040562e1ce27dddf1de39a6e3e71ca931cb 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/disturb2_unb2b_sdp_station_full_wg.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing of SDP using the WG.
-- Contains AIT input stage with WG, oversampled FSUB, XSUB, BF and RING, so without ADC JESD.
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_sdp_lib, wpfb_lib, lofar2_unb2b_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -37,7 +36,6 @@ use dp_lib.dp_stream_pkg.all;
use wpfb_lib.wpfb_pkg.all;
use lofar2_sdp_lib.sdp_pkg.all;
-
entity disturb2_unb2b_sdp_station_full_wg is
generic (
g_design_name : string := "disturb2_unb2b_sdp_station_full_wg";
@@ -100,9 +98,7 @@ entity disturb2_unb2b_sdp_station_full_wg is
end disturb2_unb2b_sdp_station_full_wg;
architecture str of disturb2_unb2b_sdp_station_full_wg is
-
begin
-
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
index 8b30fa74fd8b94869565bc9784339091fde2ed74..4a1080e7605e740d0ba02b7b772795396a5a6d44 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/disturb2_unb2b_sdp_station_full_wg/tb_disturb2_unb2b_sdp_station_full_wg.vhd
@@ -82,7 +82,6 @@ entity tb_disturb2_unb2b_sdp_station_full_wg is
end tb_disturb2_unb2b_sdp_station_full_wg;
architecture tb of tb_disturb2_unb2b_sdp_station_full_wg is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -221,9 +220,7 @@ architecture tb of tb_disturb2_unb2b_sdp_station_full_wg is
signal SA_CLK : std_logic := '1';
signal si_lpbk_0 : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
index e1cf5d4b90a3fbbdcab57eb1dea5c3b2534ac467..061841c5e476d3f97ddef6398e4caa6978ab842a 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/lofar2_unb2b_sdp_station_adc.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,14 +85,10 @@ entity lofar2_unb2b_sdp_station_adc is
end lofar2_unb2b_sdp_station_adc;
architecture str of lofar2_unb2b_sdp_station_adc is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -110,7 +105,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
index 415eb6e682870a5f3e21d242f548570a3456cb0c..eefec65249bc24e73d6ebd6d769fe7c3963852f0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_adc/tb_lofar2_unb2b_sdp_station_adc.vhd
@@ -62,7 +62,6 @@ entity tb_lofar2_unb2b_sdp_station_adc is
end tb_lofar2_unb2b_sdp_station_adc;
architecture tb of tb_lofar2_unb2b_sdp_station_adc is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -142,9 +141,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_adc is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -302,5 +299,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
index ee4ec32e9d9811ad6522fb2f599e4cfdd18b6751..852d977aeeeecea267480821e3338a2d5fcf37ce 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/lofar2_unb2b_sdp_station_bf.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -93,14 +92,10 @@ entity lofar2_unb2b_sdp_station_bf is
end lofar2_unb2b_sdp_station_bf;
architecture str of lofar2_unb2b_sdp_station_bf is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -117,7 +112,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
index 1d0a9613ed40dd0e86643db1540f5b9a533483e6..b941058df291306216f661588e8990cc4970ff50 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf.vhd
@@ -99,7 +99,6 @@ entity tb_lofar2_unb2b_sdp_station_bf is
end tb_lofar2_unb2b_sdp_station_bf;
architecture tb of tb_lofar2_unb2b_sdp_station_bf is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -351,9 +350,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -474,7 +471,6 @@ begin
src_in_arr(0) => tr_10GbE_src_in
);
-
u_rx : entity dp_lib.dp_offload_rx
generic map (
g_nof_streams => 1,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
index 44fb9e22305f5f7fac7be945162f48940d35ff8a..2285e92f73ce6f98e3395c146054461765d58284 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_bf/tb_lofar2_unb2b_sdp_station_bf_bst_offload.vhd
@@ -57,7 +57,6 @@ entity tb_lofar2_unb2b_sdp_station_bf_bst_offload is
end tb_lofar2_unb2b_sdp_station_bf_bst_offload;
architecture tb of tb_lofar2_unb2b_sdp_station_bf_bst_offload is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -124,9 +123,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_bf_bst_offload is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -249,5 +246,4 @@ begin
eth_serial_in => eth_txp(0),
tb_end => eth_done
);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
index 7ec3d86fa029fd86fa39e0204700b447e6927fc2..486993590125f4e5b065d84dbb19c848d0f80367 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/lofar2_unb2b_sdp_station_fsub.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,13 +85,10 @@ entity lofar2_unb2b_sdp_station_fsub is
end lofar2_unb2b_sdp_station_fsub;
architecture str of lofar2_unb2b_sdp_station_fsub is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -109,7 +105,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
index 8527173e3890df0c19cec437691b2e7858fea271..ae4d83d08ea97fa788ff42172351ba2766e67b31 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub.vhd
@@ -85,7 +85,6 @@ entity tb_lofar2_unb2b_sdp_station_fsub is
end tb_lofar2_unb2b_sdp_station_fsub;
architecture tb of tb_lofar2_unb2b_sdp_station_fsub is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -220,9 +219,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_fsub is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -526,5 +523,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
index 14f55f913c8737f18730fd9a246e900a10255c76..01701f878f46068c3a02ac7b9f690496b64f6208 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_fsub/tb_lofar2_unb2b_sdp_station_fsub_sst_offload.vhd
@@ -56,7 +56,6 @@ entity tb_lofar2_unb2b_sdp_station_fsub_sst_offload is
end tb_lofar2_unb2b_sdp_station_fsub_sst_offload;
architecture tb of tb_lofar2_unb2b_sdp_station_fsub_sst_offload is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 2;
constant c_node_nr : natural := 1;
@@ -123,9 +122,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_fsub_sst_offload is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -248,5 +245,4 @@ begin
eth_serial_in => eth_txp(0),
tb_end => eth_done
);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
index 10bb1a13294313290cfe98c3b855244a76912529..fd878bb3cf9de4a6271d3a4b340665f85b2b7383 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full/lofar2_unb2b_sdp_station_full.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -102,14 +101,10 @@ entity lofar2_unb2b_sdp_station_full is
end lofar2_unb2b_sdp_station_full;
architecture str of lofar2_unb2b_sdp_station_full is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -126,7 +121,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
index d2000d761ea6cd2540fc74f986bd969f0da167c9..5412994b0eead9bb2323560ce8d2bb771a82c8c3 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_full_wg/lofar2_unb2b_sdp_station_full_wg.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing of SDP using the WG.
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -95,9 +94,7 @@ entity lofar2_unb2b_sdp_station_full_wg is
end lofar2_unb2b_sdp_station_full_wg;
architecture str of lofar2_unb2b_sdp_station_full_wg is
-
begin
-
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
index 3fd7c6e5f7399f1114c6862ac751926661f6efc1..925e86ef84fc7f1e3f86c40c9a2c239e8e5e5992 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,13 +85,10 @@ entity lofar2_unb2b_sdp_station_xsub_one is
end lofar2_unb2b_sdp_station_xsub_one;
architecture str of lofar2_unb2b_sdp_station_xsub_one is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -109,7 +105,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
index 91392de7bb0dc6aa0929e8c1f47c3d79ed0b1a80..95899d4d5894634e6b1ab3fda7976c57cc8819e0 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one.vhd
@@ -64,7 +64,6 @@ entity tb_lofar2_unb2b_sdp_station_xsub_one is
end tb_lofar2_unb2b_sdp_station_xsub_one;
architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -125,7 +124,6 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one is
-- WPFB
signal xsub_stats_arr : t_slv_64_arr(0 to c_nof_complex * c_sdp_X_sq - 1);
-
-- DUT
signal ext_clk : std_logic := '0';
signal pps : std_logic := '0';
@@ -152,9 +150,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -367,5 +363,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
index fc89b3f07f2eeefe9184e89cc6d09c2d09656209..955572365e77b02697bb9109ae11fccf0bd528a7 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_one/tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload.vhd
@@ -57,7 +57,6 @@ entity tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload is
end tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload;
architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 2;
constant c_node_nr : natural := 1;
@@ -123,9 +122,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_one_xst_offload is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -260,5 +257,4 @@ begin
eth_serial_in => eth_txp(0),
tb_end => eth_done
);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
index bdc156ac013fe6a998372130c664465a16d50367..1cd39a4cd95fd46ed27f655314b2054711fd1046 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete SDP station design with AIT input stage with 12 ADC streams, FSUB, XSUB with ring
-
library IEEE, common_lib, unb2b_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2b_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -102,14 +101,10 @@ entity lofar2_unb2b_sdp_station_xsub_ring is
end lofar2_unb2b_sdp_station_xsub_ring;
architecture str of lofar2_unb2b_sdp_station_xsub_ring is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -126,7 +121,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2b_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2b_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2b_sdp_station_lib.lofar2_unb2b_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
index aaf28671a33032e4f0342ac9de88785260628daa..9e7401c049e4ad2d0100efebeca9f6cac2999df2 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/revisions/lofar2_unb2b_sdp_station_xsub_ring/tb_lofar2_unb2b_sdp_station_xsub_ring.vhd
@@ -65,7 +65,6 @@ entity tb_lofar2_unb2b_sdp_station_xsub_ring is
end tb_lofar2_unb2b_sdp_station_xsub_ring;
architecture tb of tb_lofar2_unb2b_sdp_station_xsub_ring is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -137,7 +136,6 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_ring is
-- WPFB
signal xsub_stats_arr : t_slv_64_arr(0 to c_P_sq * c_nof_complex * c_sdp_X_sq - 1);
-
-- DUT
signal ext_clk : std_logic := '0';
signal pps : std_logic := '0';
@@ -165,9 +163,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station_xsub_ring is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -263,11 +259,11 @@ begin
i_RING_0_RX(I + 1) <= i_RING_1_TX(I);
i_RING_1_RX(I) <= i_RING_0_TX(I + 1);
end generate;
+
-- Connect first and last nodes with QSFP interface.
i_QSFP_0_RX(0) <= i_QSFP_0_TX(c_nof_rn - 1);
i_QSFP_0_RX(c_nof_rn - 1) <= i_QSFP_0_TX(0);
-
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
@@ -361,7 +357,6 @@ begin
v_bsn := TO_UINT(current_bsn_wg) + 2;
assert v_bsn <= c_bsn_start_wg report "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) severity ERROR;
-
for RN in 0 to c_nof_rn - 1 loop
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SCHEDULER", 0, c_bsn_start_wg, tb_clk); -- first write low then high part
mmf_mm_bus_wr(mmf_unb_file_prefix(c_unb_nr + (RN / c_quad), RN mod c_quad) & "REG_BSN_SCHEDULER", 1, 0, tb_clk); -- assume v_bsn < 2**31-1
@@ -484,5 +479,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
index df3f7acae0faef2e6bdc863624caa62760fc5d77..f4947909cf7154cc6ba578469c7455de0f72074e 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station.vhd
@@ -42,7 +42,6 @@ use lofar2_sdp_lib.sdp_pkg.all;
use work.lofar2_unb2b_sdp_station_pkg.all;
use eth_lib.eth_pkg.all;
-
entity lofar2_unb2b_sdp_station is
generic (
g_design_name : string := "lofar2_unb2b_sdp_station";
@@ -116,9 +115,7 @@ entity lofar2_unb2b_sdp_station is
);
end lofar2_unb2b_sdp_station;
-
architecture str of lofar2_unb2b_sdp_station is
-
-- Revision parameters
constant c_revision_select : t_lofar2_unb2b_sdp_station_config := func_sel_revision_rec(g_design_name);
@@ -484,9 +481,7 @@ architecture str of lofar2_unb2b_sdp_station is
signal unb2_board_qsfp_leds_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_sosi_rst);
signal unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_siso_rst);
signal unb2_board_qsfp_leds_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_sosi_rst);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -801,7 +796,6 @@ begin
ram_st_xsq_cipo => ram_st_xsq_cipo
);
-
-- Use full 8 bit gn_id = ID
gn_id <= ID;
@@ -1052,5 +1046,4 @@ begin
tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
index e8670d3d4481d113e06d37e40b81aa226b70951e..dd06a93a7fe1f0af2bf646d0ab3ac55e584f2dcc 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/lofar2_unb2b_sdp_station_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use unb2b_board_lib.unb2b_board_pkg.all;
package lofar2_unb2b_sdp_station_pkg is
-
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -55,12 +54,9 @@ package lofar2_unb2b_sdp_station_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_sdp_station_config;
-
end lofar2_unb2b_sdp_station_pkg;
-
package body lofar2_unb2b_sdp_station_pkg is
-
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2b_sdp_station_config is
begin
if g_design_name = "lofar2_unb2b_sdp_station_adc" then return c_ait;
@@ -75,8 +71,7 @@ package body lofar2_unb2b_sdp_station_pkg is
elsif g_design_name = "disturb2_unb2b_sdp_station_full" then return c_full_os;
else return c_full;
end if;
- end;
+ end;
end lofar2_unb2b_sdp_station_pkg;
-
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
index feaf68b374f69fe761b29e5879a8273bd2161ce7..194e3ee4180e6c18c5a5c68184ba85ad7d511c58 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/mmm_lofar2_unb2b_sdp_station.vhd
@@ -335,20 +335,15 @@ entity mmm_lofar2_unb2b_sdp_station is
end mmm_lofar2_unb2b_sdp_station;
architecture str of mmm_lofar2_unb2b_sdp_station is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
@@ -562,7 +557,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
index d9693c5838cb5567d9a42e687a62c6befddac12a..5b73786a9702555b039c255550f2cb477f20c68f 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/src/vhdl/qsys_lofar2_unb2b_sdp_station_pkg.vhd
@@ -22,7 +22,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2b_sdp_station_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
@@ -577,5 +576,5 @@ package qsys_lofar2_unb2b_sdp_station_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2b_sdp_station;
-end qsys_lofar2_unb2b_sdp_station_pkg;
+end qsys_lofar2_unb2b_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
index bb7bc1ceff01efacd29cf05362f13f0a449972b9..a057ddef1ed45cbf28976e972f10acd299a5b213 100644
--- a/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2b_sdp_station/tb/vhdl/tb_lofar2_unb2b_sdp_station.vhd
@@ -50,7 +50,6 @@ entity tb_lofar2_unb2b_sdp_station is
end tb_lofar2_unb2b_sdp_station;
architecture tb of tb_lofar2_unb2b_sdp_station is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -120,9 +119,7 @@ architecture tb of tb_lofar2_unb2b_sdp_station is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
-- System setup
ext_clk <= (not ext_clk) or tb_end after c_ext_clk_period / 2; -- External clock (200 MHz)
eth_clk <= (not eth_clk) or tb_end after c_eth_clk_period / 2; -- Ethernet ref clock (125 MHz)
@@ -256,5 +253,4 @@ begin
eth_serial_in => eth_txp(0),
tb_end => eth_done
);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
index a40ce9956b68c3350ad0836a5ac18c648c5d4949..1556515bae9a2a48edf9c1abafa56ba96312953a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/lofar2_unb2c_ddrctrl.vhd
@@ -32,8 +32,6 @@ use tech_ddr_lib.tech_ddr_pkg.all;
use lofar2_sdp_lib.sdp_pkg.all;
use diag_lib.diag_pkg.all;
-
-
entity lofar2_unb2c_ddrctrl is
generic (
g_design_name : string := "lofar2_unb2c_ddrctrl";
@@ -82,13 +80,10 @@ entity lofar2_unb2c_ddrctrl is
--MB_II_IO : INOUT t_tech_ddr4_phy_io;
--MB_II_OU : OUT t_tech_ddr4_phy_ou;
-
);
end lofar2_unb2c_ddrctrl;
-
architecture str of lofar2_unb2c_ddrctrl is
-
-- Firmware version x.y
-- If x >= 2, rom_info starts on 0x10000 and max size = 0x8192 words
constant c_fw_version : t_unb2c_board_fw_version := (2, 0);
@@ -115,8 +110,6 @@ architecture str of lofar2_unb2c_ddrctrl is
-- diag_bsn_buffer
constant c_bsn_type : t_diag_data_type_enum := e_real;
-
-
-- System
signal cs_sim : std_logic;
signal xo_ethclk : std_logic;
@@ -250,25 +243,17 @@ architecture str of lofar2_unb2c_ddrctrl is
signal out_wr_bsn_done_arr : std_logic_vector(c_nof_streams - 1 downto 0);
signal mb_I_ref_rst : std_logic;
-
-
begin
-
out_siso.ready <= vector_and(not out_wr_data_done_arr) and vector_and(not out_wr_bsn_done_arr);
-
p_sosi_arr : process(out_sosi_arr_ddrctrl)
-
begin
-
in_sosi_arr_data_buf <= out_sosi_arr_ddrctrl;
store_bsn_in_re : for I in 0 to c_nof_streams - 1 loop
in_sosi_arr_data_buf(I).re <= out_sosi_arr_ddrctrl(I).bsn;
end loop;
-
end process;
-
u_bsn_source_v2 : entity dp_lib.mms_dp_bsn_source_v2
generic map (
g_cross_clock_domain => true,
@@ -315,7 +300,6 @@ begin
trigger_out => trigger_wg
);
-
u_wg_arr : entity diag_lib.mms_diag_wg_wideband_arr
generic map (
g_nof_streams => c_nof_streams,
@@ -351,7 +335,6 @@ begin
out_sosi_arr => wg_sosi_arr
);
-
gen_concat : for I in 0 to c_sdp_S_pn - 1 generate
p_sosi : process(wg_sosi_arr(I), bs_sosi)
begin
@@ -360,7 +343,6 @@ begin
end process;
end generate;
-
u_stop_in_reg : entity common_lib.mms_common_reg
port map (
-- Memory-mapped clock domain
@@ -378,7 +360,6 @@ begin
out_reg => stop_in_arr
);
-
u_ddrctrl_ctrl_state_reg : entity common_lib.mms_common_reg
port map (
-- Memory-mapped clock domain
@@ -396,7 +377,6 @@ begin
out_reg => open
);
-
u_ddrctrl : entity lofar2_ddrctrl_lib.ddrctrl
generic map (
g_tech_ddr => c_tech_ddr,
@@ -467,7 +447,6 @@ begin
out_wr_done_arr => out_wr_data_done_arr
);
-
u_diag_bsn_buffer : entity diag_lib.mms_diag_data_buffer_dev
generic map (
g_technology => g_technology,
@@ -503,7 +482,6 @@ begin
out_wr_done_arr => out_wr_bsn_done_arr
);
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -759,6 +737,4 @@ begin
red_led_arr => qsfp_red_led_arr,
QSFP_LED => QSFP_LED
);
-
end str;
-
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
index 7d53952914f4ad62b40f50c454b5ebee4cf568e9..bc7d3e754784cf6a70dbd23d2c0ec3c2f91c8c01 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/mmm_lofar2_unb2c_ddrctrl.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_lofar2_unb2c_ddrctrl_pkg.all;
-
entity mmm_lofar2_unb2c_ddrctrl is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -96,8 +95,6 @@ entity mmm_lofar2_unb2c_ddrctrl is
ram_scrap_mosi : out t_mem_mosi;
ram_scrap_miso : in t_mem_miso;
-
-
-- bsn_source_v2
reg_bsn_source_v2_mosi : out t_mem_mosi;
reg_bsn_source_v2_miso : in t_mem_miso;
@@ -140,24 +137,19 @@ entity mmm_lofar2_unb2c_ddrctrl is
reg_rx_seq_bsn_mosi : out t_mem_mosi;
reg_rx_seq_bsn_miso : in t_mem_miso
-
);
end mmm_lofar2_unb2c_ddrctrl;
architecture str of mmm_lofar2_unb2c_ddrctrl is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -222,15 +214,11 @@ begin
u_mm_file_reg_rx_seq_bsn : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_RX_SEQ_BSN")
port map(mm_rst, mm_clk, reg_rx_seq_bsn_mosi, reg_rx_seq_bsn_miso);
-
-
-
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
index 0b4b8cd68b8822a066cd9b42642f1ab97e3a5176..aa9cb7c67cda243aa068f6502e8a4471b38a6cee 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/src/vhdl/qsys_lofar2_unb2c_ddrctrl_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_ddrctrl_pkg is
-
----------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder
----------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
index 10f176c35f91f519566b8ba6603b79cd93925b7e..2e4ac9d8d868dd53538e960a49ef02807376189c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ddrctrl/tb/vhdl/tb_lofar2_unb2c_ddrctrl.vhd
@@ -57,7 +57,6 @@ use diag_lib.diag_pkg.all;
use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
-
entity tb_lofar2_unb2c_ddrctrl is
generic (
g_design_name : string := "lofar2_unb2c_ddrctrl";
@@ -67,7 +66,6 @@ entity tb_lofar2_unb2c_ddrctrl is
end tb_lofar2_unb2c_ddrctrl;
architecture tb of tb_lofar2_unb2c_ddrctrl is
-
constant c_sim : boolean := true;
constant c_rd_data_w : natural := 32;
@@ -108,7 +106,6 @@ architecture tb of tb_lofar2_unb2c_ddrctrl is
constant c_bim : natural := (c_max_adr * c_ctrl_data_w) / (c_block_size * c_nof_streams * c_data_w); -- the amount of whole blocks that fit in memory.
constant c_nof_st_in_mem : natural := c_bim * c_block_size;
-
constant c_check_vector : std_logic_vector(c_ctrl_data_w * c_bim * c_block_size-1 downto 0) := (others => '0'); -- the sinewave of one stream for c_bim length
-- BSN
@@ -138,10 +135,8 @@ architecture tb of tb_lofar2_unb2c_ddrctrl is
signal sosi_out_data_sin : std_logic_vector( c_data_w - 1 downto 0) := (others => '0');
signal sosi_out_not_bsn : std_logic_vector(c_rd_data_w - 1 downto 0) := (others => '0');
-
signal out_ddrctrl_ctrl_state : std_logic_vector(c_rd_data_w - 1 downto 0) := (others => '0');
-
signal WDI : std_logic;
signal INTA : std_logic;
signal INTB : std_logic;
@@ -157,10 +152,7 @@ architecture tb of tb_lofar2_unb2c_ddrctrl is
signal qsfp_led : std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
signal current_bsn_wg : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
-
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -217,23 +209,17 @@ begin
);
-
-- WG
-
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
tb_clk <= not tb_clk or tb_end after c_tb_clk_period / 2; -- Testbench MM clock
-
-
p_mm_stimuli : process
variable v_bsn : natural := 0;
-
begin
-
wait for 1 us;
----------------------------------------------------------------------------
-- Enable BSN
@@ -243,8 +229,6 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1, c_nof_clk_per_sync, tb_clk); -- nof_block_per_sync
mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0, 16#00000003#, tb_clk); -- Enable BSN at PPS
-
-
--mmf_mm_bus_rd(c_mm_file_reg_dp_selector, 0, rd_data, tb_clk);
----------------------------------------------------------------------------
@@ -304,7 +288,6 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
wait for c_mm_clk_period * 50000;
-
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
@@ -325,8 +308,6 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
wait for c_mm_clk_period * 50000;
-
-
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
@@ -347,7 +328,6 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
wait for c_mm_clk_period * 50000;
-
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
@@ -368,7 +348,6 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
wait for c_mm_clk_period * 50000;
-
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
@@ -389,7 +368,6 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_stop_in, 0, 0, tb_clk);
wait for c_mm_clk_period * 50000;
-
for I in 0 to c_bim - 1 loop
for J in 0 to c_nof_streams - 1 loop
for K in c_block_size - (c_block_size / (2**c_speed)) to c_block_size-1 loop
@@ -408,7 +386,4 @@ begin
assert false report "Test: OK" severity FAILURE;
wait;
end process;
-
-
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
index 66148b3a528ffc9bc22bbad6d580df80bb724fd0..e8ebe5092ffb6baf376b6bf33af2e15c31ae5968 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full/lofar2_unb2c_filterbank_full.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,14 +85,10 @@ entity lofar2_unb2c_filterbank_full is
end lofar2_unb2c_filterbank_full;
architecture str of lofar2_unb2c_filterbank_full is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -110,7 +105,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2c_filterbank_lib.lofar2_unb2c_filterbank
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
index 0fb7c2680775afc097c512faded4cfcc688faec4..82942a08d3a10ab712f640a73207bcb9a7d7d6b1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/revisions/lofar2_unb2c_filterbank_full_256MHz/lofar2_unb2c_filterbank_full_256MHz.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_filterbank_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,14 +85,10 @@ entity lofar2_unb2c_filterbank_full_256MHz is
end lofar2_unb2c_filterbank_full_256MHz;
architecture str of lofar2_unb2c_filterbank_full_256MHz is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA(0) <= BCK_RX(42);
@@ -110,7 +105,6 @@ begin
JESD204B_SERIAL_DATA(11) <= '0';
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2c_filterbank_lib.lofar2_unb2c_filterbank
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
index 395f52da852676b48a70086f48544729734f00c8..a8ae459ab259b858a1f6e7a89ff8c8a4f60bdde6 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank.vhd
@@ -96,9 +96,7 @@ entity lofar2_unb2c_filterbank is
);
end lofar2_unb2c_filterbank;
-
architecture str of lofar2_unb2c_filterbank is
-
-- Revision parameters
constant c_revision_select : t_lofar2_unb2c_filterbank_config := func_sel_revision_rec(g_design_name);
constant c_nof_streams : natural := c_revision_select.nof_streams_input; -- Streams actually passed through for processing
@@ -256,9 +254,7 @@ architecture str of lofar2_unb2c_filterbank is
signal ait_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
signal pfb_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0);
signal fsub_sosi_arr : t_dp_sosi_arr(c_sdp_P_pfb - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -479,7 +475,6 @@ begin
ram_scrap_miso => ram_scrap_miso
);
-
-----------------------------------------------------------------------------
-- node_adc_input_and_timing (AIT)
-- .Contains JESD receiver, bsn source and associated data buffers, diagnostics and statistics
@@ -536,7 +531,6 @@ begin
out_sosi_arr => ait_sosi_arr
);
-
u_fsub : entity lofar2_sdp_lib.node_sdp_filterbank
generic map(
g_sim => g_sim,
@@ -565,5 +559,4 @@ begin
reg_selector_mosi => reg_dp_selector_mosi,
reg_selector_miso => reg_dp_selector_miso
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
index 8bc26b1b3c49230d623a77890bb7f4140f1aec0c..617e401becaadd6ae2136b036964cb07dc2348f4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/lofar2_unb2c_filterbank_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_filterbank_pkg is
-
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -45,20 +44,16 @@ package lofar2_unb2c_filterbank_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_filterbank_config;
-
end lofar2_unb2c_filterbank_pkg;
-
package body lofar2_unb2c_filterbank_pkg is
-
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_filterbank_config is
begin
if g_design_name = "lofar2_unb2c_filterbank_full" then return c_full;
elsif g_design_name = "lofar2_unb2c_filterbank_full_256MHz" then return c_full_256MHz;
else return c_full;
end if;
- end;
+ end;
end lofar2_unb2c_filterbank_pkg;
-
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
index d9e1229f7bf58dd13822cc42a54ec24f9c882f46..fa4e12bb7ebf8ffe23157e2fa7f24779c4c37f30 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/mmm_lofar2_unb2c_filterbank.vhd
@@ -169,20 +169,15 @@ entity mmm_lofar2_unb2c_filterbank is
end mmm_lofar2_unb2c_filterbank;
architecture str of mmm_lofar2_unb2c_filterbank is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -268,7 +263,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
@@ -478,7 +472,6 @@ begin
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
ram_diag_data_buf_bsn_clk_export => OPEN,
ram_diag_data_buf_bsn_reset_export => OPEN,
ram_diag_data_buf_bsn_address_export => ram_diag_data_buf_bsn_mosi.address(c_sdp_ram_diag_data_buf_bsn_addr_w - 1 downto 0),
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
index 72f0f9eb4301601834b175f2c7a6c5da28bb899a..3193b1a4e866e50ee1b08de077a7ac83b789782d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/src/vhdl/qsys_lofar2_unb2c_filterbank_pkg.vhd
@@ -22,7 +22,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_filterbank_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
@@ -283,5 +282,5 @@ package qsys_lofar2_unb2c_filterbank_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2c_filterbank;
-end qsys_lofar2_unb2c_filterbank_pkg;
+end qsys_lofar2_unb2c_filterbank_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
index 20f124a66ec41efa46d19061fcc7581b5e95b9de..260d1427fd7440fac1f3a4aec28bf8c4a34955b3 100644
--- a/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_filterbank/tb/vhdl/tb_lofar2_unb2c_filterbank.vhd
@@ -69,7 +69,6 @@ entity tb_lofar2_unb2c_filterbank is
end tb_lofar2_unb2c_filterbank;
architecture tb of tb_lofar2_unb2c_filterbank is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -125,7 +124,6 @@ architecture tb of tb_lofar2_unb2c_filterbank is
constant c_mm_file_ram_aduh_mon : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ADUH_MONITOR";
constant c_mm_file_ram_st_sst : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "RAM_ST_SST";
-
-- Tb
signal tb_end : std_logic := '0';
signal sim_done : std_logic := '0';
@@ -174,9 +172,7 @@ architecture tb of tb_lofar2_unb2c_filterbank is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector((c_unb2c_board_tr_jesd204b.nof_bus * c_unb2c_board_tr_jesd204b.bus_w) - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -422,5 +418,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
index 9b01c6973ef8cd88783ccad4f0117db0d5b36f96..896329e2ff83779b74d415115d61552c3a367eb4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/lofar2_unb2c_ring_full.vhd
@@ -25,7 +25,6 @@
-- Unb2b version for lab testing
-- Contains complete ring design with all 8 lanes.
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -85,7 +84,6 @@ end lofar2_unb2c_ring_full;
architecture str of lofar2_unb2c_ring_full is
begin
-
u_revision : entity lofar2_unb2c_ring_lib.lofar2_unb2c_ring
generic map (
g_design_name => g_design_name,
@@ -131,5 +129,4 @@ begin
-- LEDs
QSFP_LED => QSFP_LED
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
index 9cbf1b0569c6e827e29c391f15a6a2cf00e8b8a5..17830917aa4976d86f2bd11c8a9c70e26ce0206b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_full/tb_lofar2_unb2c_ring_full.vhd
@@ -39,7 +39,6 @@ entity tb_lofar2_unb2c_ring_full is
end tb_lofar2_unb2c_ring_full;
architecture tb of tb_lofar2_unb2c_ring_full is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
@@ -81,11 +80,7 @@ architecture tb of tb_lofar2_unb2c_ring_full is
signal i_RING_0_RX : std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
signal i_RING_1_TX : std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
signal i_RING_1_RX : std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
-
-
begin
-
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -139,12 +134,10 @@ begin
QSFP_LED => open
);
-
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' after 1 us;
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
index add93416938f22e673b79cc6e8ab134cc134a467..991fdeb9228a16aadb54889827c1f81d926359e5 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/lofar2_unb2c_ring_one.vhd
@@ -28,7 +28,6 @@
-- Note that the amount of transceivers support 2 lanes, one even and one odd.
-- However only 1 ring_lane.vhd component is instantiated with lane index 0 (even).
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_ring_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -88,7 +87,6 @@ end lofar2_unb2c_ring_one;
architecture str of lofar2_unb2c_ring_one is
begin
-
u_revision : entity lofar2_unb2c_ring_lib.lofar2_unb2c_ring
generic map (
g_design_name => g_design_name,
@@ -134,5 +132,4 @@ begin
-- LEDs
QSFP_LED => QSFP_LED
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
index 375d1289ac390c8e5c84fa3ee657ad98f21ee428..0aff49975ac74650b42b8206d7c239f9c9319ed2 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/revisions/lofar2_unb2c_ring_one/tb_lofar2_unb2c_ring_one.vhd
@@ -39,7 +39,6 @@ entity tb_lofar2_unb2c_ring_one is
end tb_lofar2_unb2c_ring_one;
architecture tb of tb_lofar2_unb2c_ring_one is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0;
constant c_node_nr : natural := 0;
@@ -81,11 +80,7 @@ architecture tb of tb_lofar2_unb2c_ring_one is
signal i_RING_0_RX : std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
signal i_RING_1_TX : std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
signal i_RING_1_RX : std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
-
-
begin
-
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -139,12 +134,10 @@ begin
QSFP_LED => open
);
-
------------------------------------------------------------------------------
-- Simulation end
------------------------------------------------------------------------------
sim_done <= '0', '1' after 1 us;
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
index 781bd97de97b0e03136b3c6365b966419c2d65f1..44d0371592780c69ebd37b2599f76fa3075634f9 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring.vhd
@@ -43,7 +43,6 @@ use work.lofar2_unb2c_ring_pkg.all;
use eth_lib.eth_pkg.all;
use ring_lib.ring_pkg.all;
-
entity lofar2_unb2c_ring is
generic (
g_design_name : string := "lofar2_unb2c_ring";
@@ -94,9 +93,7 @@ entity lofar2_unb2c_ring is
);
end lofar2_unb2c_ring;
-
architecture str of lofar2_unb2c_ring is
-
-- Revision parameters
constant c_revision_select : t_lofar2_unb2c_ring_config := func_sel_revision_rec(g_design_name);
constant c_nof_lanes : natural := c_revision_select.N_ring_lanes;
@@ -144,7 +141,6 @@ architecture str of lofar2_unb2c_ring is
constant c_addr_w_reg_dp_block_validate_err : natural := ceil_log2(c_nof_err_counts + 3);
constant c_addr_w_reg_dp_block_validate_bsn_at_sync : natural := ceil_log2(3);
-
constant c_reg_ring_input_select : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_lanes),
dat_w => 1,
@@ -232,7 +228,6 @@ architecture str of lofar2_unb2c_ring is
signal reg_tr_10GbE_eth10g_copi : t_mem_copi := c_mem_copi_rst;
signal reg_tr_10GbE_eth10g_cipo : t_mem_cipo := c_mem_cipo_rst;
-
signal reg_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
signal reg_diag_bg_cipo : t_mem_cipo := c_mem_cipo_rst;
signal ram_diag_bg_copi : t_mem_copi := c_mem_copi_rst;
@@ -299,7 +294,6 @@ architecture str of lofar2_unb2c_ring is
signal tr_10gbe_src_in_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
signal tr_10gbe_snk_out_arr : t_dp_siso_arr(c_nof_mac - 1 downto 0) := (others => c_dp_siso_rdy);
-
signal bs_sosi : t_dp_sosi := c_dp_sosi_rst;
signal local_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -314,7 +308,6 @@ architecture str of lofar2_unb2c_ring is
signal i_RING_TX : t_unb2c_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
signal i_RING_RX : t_unb2c_board_qsfp_bus_2arr(c_nof_ring_bus - 1 downto 0) := (others => (others => '0'));
-
signal tr_10gbe_serial_tx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
signal tr_10gbe_serial_rx_arr : std_logic_vector(c_nof_mac - 1 downto 0) := (others => '0');
@@ -329,9 +322,7 @@ architecture str of lofar2_unb2c_ring is
signal qsfp_red_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
signal unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_unb2c_board_tr_qsfp.nof_bus * c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => c_dp_siso_rst);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -606,7 +597,6 @@ begin
);
bs_sosi <= local_sosi;
-
-----------------------------------------------------------------------------
-- MMP dp_xonoff from_lane_sosi
-----------------------------------------------------------------------------
@@ -665,7 +655,6 @@ begin
-- DP Mux
-----------------------------------------------------------------------------
gen_dp_mux: for I in 0 to c_nof_lanes - 1 generate
-
dp_xonoff_lane_src_in_arr(I) <= dp_mux_snk_out_2arr(I)(0);
dp_xonoff_local_src_in_arr(I) <= dp_mux_snk_out_2arr(I)(1);
dp_mux_snk_in_2arr(I)(0) <= dp_xonoff_lane_src_out_arr(I);
@@ -888,7 +877,6 @@ begin
serial_rx_arr => tr_10gbe_serial_rx_arr
);
-
-----------------------------------------------------------------------------
-- Seperate serial tx/rx array
-----------------------------------------------------------------------------
@@ -975,5 +963,4 @@ begin
tx_siso_arr => unb2_board_qsfp_leds_tx_siso_arr
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
index bb9c567d90bdc44119599cfcf839114c0a982781..28a9c8341d315412c0150b7a8905bc1fb0f4c6c7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/lofar2_unb2c_ring_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_ring_pkg is
-
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -42,19 +41,15 @@ package lofar2_unb2c_ring_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_ring_config;
-
end lofar2_unb2c_ring_pkg;
-
package body lofar2_unb2c_ring_pkg is
-
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_ring_config is
begin
if g_design_name = "lofar2_unb2c_ring_one" then return c_one;
else return c_full;
end if;
- end;
+ end;
end lofar2_unb2c_ring_pkg;
-
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
index 27875325897b7babb3bdb09326cc6ade7b94132a..42f7512e380976a981493559160d58b0950a99a8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/mmc_lofar2_unb2c_ring.vhd
@@ -144,20 +144,15 @@ entity mmc_lofar2_unb2c_ring is
end mmc_lofar2_unb2c_ring;
architecture str of mmc_lofar2_unb2c_ring is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
@@ -222,7 +217,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
index 6cdf83dd533c8170d7d500dc46dc2c9364984642..8c35d482f28c694e83468ddaca51cb3918516597 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/src/vhdl/qsys_lofar2_unb2c_ring_pkg.vhd
@@ -22,7 +22,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_ring_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
@@ -228,5 +227,5 @@ package qsys_lofar2_unb2c_ring_pkg is
rom_system_info_writedata_export : out std_logic_vector(31 downto 0) -- export
);
end component qsys_lofar2_unb2c_ring;
-end qsys_lofar2_unb2c_ring_pkg;
+end qsys_lofar2_unb2c_ring_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
index 2af846791dcaaf621fcd41582f09d0f5e01438cb..60dc7bbea0781615a5844d2c59e1ec938e65793a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_lofar2_unb2c_ring.vhd
@@ -62,11 +62,9 @@ entity tb_lofar2_unb2c_ring is
port (
tb_end : out std_logic := '0' -- For multi tb
);
-
end tb_lofar2_unb2c_ring;
architecture tb of tb_lofar2_unb2c_ring is
-
constant c_sim : boolean := true;
constant c_node_nr : natural := 0;
constant c_version : std_logic_vector(1 downto 0) := "00";
@@ -92,7 +90,6 @@ architecture tb of tb_lofar2_unb2c_ring is
constant c_exp_nof_sop : natural := g_nof_block_per_sync;
constant c_exp_nof_valid : natural := g_nof_block_per_sync * c_blocksize;
-
-- MM
constant c_mm_file_reg_ring_info : string := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_RING_INFO";
constant c_mm_file_reg_ring_lane_info : string := mmf_unb_file_prefix(g_unb_nr, c_node_nr) & "REG_RING_LANE_INFO";
@@ -136,10 +133,7 @@ architecture tb of tb_lofar2_unb2c_ring is
signal pmbus_sda : std_logic;
signal SA_CLK : std_logic := '1';
-
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -219,12 +213,11 @@ begin
i_RING_0_RX(I + 1) <= i_RING_1_TX(I);
i_RING_1_RX(I) <= i_RING_0_TX(I + 1);
end generate;
+
-- Connect first and last nodes with QSFP interface.
i_QSFP_0_RX(0) <= i_QSFP_0_TX(g_nof_rn - 1);
i_QSFP_0_RX(g_nof_rn - 1) <= i_QSFP_0_TX(0);
-
-
------------------------------------------------------------------------------
-- MM peripeheral accesses via file IO
------------------------------------------------------------------------------
diff --git a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
index 5646c6aacf5641e9ca50e56f5caf3e3dfaa2181c..8d8576c59fc5a8963b9b38fd9587c055aaa59e37 100644
--- a/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_ring/tb/vhdl/tb_tb_lofar2_unb2c_ring.vhd
@@ -42,7 +42,6 @@ architecture tb of tb_tb_lofar2_unb2c_ring is
signal tb_end_vec : std_logic_vector(c_nof_tb - 1 downto 0) := (others => '0');
signal tb_end : std_logic; -- declare tb_end as STD_LOGIC to avoid 'No objects found' error on 'when -label tb_end' in *.do file
begin
-
-- g_multi_tb : BOOLEAN := FALSE;
-- g_unb_nr : NATURAL := 4;
-- g_design_name : STRING := "lofar2_unb2c_ring_one";
@@ -61,5 +60,4 @@ begin
tb_end <= vector_and(tb_end_vec);
proc_common_stop_simulation(tb_end);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
index e1dcded39d5ce8a8df5952560f11c1c02666a759..0a7c377d0a2ce6f6fff31adfcae2f1efb453f3f1 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full/disturb2_unb2c_sdp_station_full.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -94,13 +93,10 @@ entity disturb2_unb2c_sdp_station_full is
end disturb2_unb2c_sdp_station_full;
architecture str of disturb2_unb2c_sdp_station_full is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA <= BCK_RX;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
index bd4765698e73bf040c888ca7a4d9b9dcedf73908..0bd6efeaed403e1242fac2f0ef8779b4507fee20 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/disturb2_unb2c_sdp_station_full_wg/disturb2_unb2c_sdp_station_full_wg.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing of SDP using the WG.
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,9 +85,7 @@ entity disturb2_unb2c_sdp_station_full_wg is
end disturb2_unb2c_sdp_station_full_wg;
architecture str of disturb2_unb2c_sdp_station_full_wg is
-
begin
-
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
index 47b939604492ac17dc8ba19c248f37b17063bfcd..cde951b9a50baab6ffdcbb9846b03923bc9b252b 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/lofar2_unb2c_sdp_station_adc.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing
-- Contains complete AIT input stage with 12 ADC streams
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -78,20 +77,15 @@ entity lofar2_unb2c_sdp_station_adc is
end lofar2_unb2c_sdp_station_adc;
architecture str of lofar2_unb2c_sdp_station_adc is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA <= BCK_RX;
JESD204B_SYNC_N(c_unb2c_board_nof_sync_jesd204b - 1 downto 0) <= jesd204b_sync_n_arr(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
-
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
index e0a8c79d03937bd4ea47541e9fa244f557bafd44..e94d9e9a29ac5f69d5f323243a791b7d0f1fb4dd 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc.vhd
@@ -62,7 +62,6 @@ entity tb_lofar2_unb2c_sdp_station_adc is
end tb_lofar2_unb2c_sdp_station_adc;
architecture tb of tb_lofar2_unb2c_sdp_station_adc is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -137,9 +136,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_adc is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -284,5 +281,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
index 48aaf313094302057a28ad82dccfd4ad0a55806f..02130ecf7708d27b33d450f0218a278e92a10272 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_adc/tb_lofar2_unb2c_sdp_station_adc_jesd.vhd
@@ -72,7 +72,6 @@ entity tb_lofar2_unb2c_sdp_station_adc_jesd is
end tb_lofar2_unb2c_sdp_station_adc_jesd;
architecture tb of tb_lofar2_unb2c_sdp_station_adc_jesd is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -271,9 +270,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_adc_jesd is
csr_dev_syncn);
end loop;
end;
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -747,5 +744,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
index 6c63cfa6b536bff9f7cc53013adc8c9ba8a1ee80..9abb13ac1daf7f49579863db07164826d96ae873 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/lofar2_unb2c_sdp_station_bf.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -85,14 +84,10 @@ entity lofar2_unb2c_sdp_station_bf is
end lofar2_unb2c_sdp_station_bf;
architecture str of lofar2_unb2c_sdp_station_bf is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA <= BCK_RX;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
index a925ba49ae0e65c0cc75b49b91ea20e17f00e487..74fa6e366d14530426c0c5a1256df0f55473062e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -177,7 +177,6 @@ entity tb_lofar2_unb2c_sdp_station_bf is
end tb_lofar2_unb2c_sdp_station_bf;
architecture tb of tb_lofar2_unb2c_sdp_station_bf is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -482,9 +481,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -595,7 +592,6 @@ begin
src_in_arr(0) => tr_10GbE_src_in
);
-
u_rx : entity dp_lib.dp_offload_rx
generic map (
g_nof_streams => 1,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
index 2e3e9aa8254e7d0f990fb1ff3418915719336740..17d6d80420055ba503fdec77b55034b2de8d537c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_lofar2_unb2c_sdp_station_bf_bst_offload.vhd
@@ -58,7 +58,6 @@ entity tb_lofar2_unb2c_sdp_station_bf_bst_offload is
end tb_lofar2_unb2c_sdp_station_bf_bst_offload;
architecture tb of tb_lofar2_unb2c_sdp_station_bf_bst_offload is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -152,9 +151,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_bst_offload is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -335,5 +332,4 @@ begin
v_bool := func_sdp_verify_stat_header("BST", rx_sdp_stat_header, exp_sdp_stat_header);
end if;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
index 1516651fc41e2630eb3e5d7b28825e8c745ba8d8..b85519e4bd8305f112efcc0135334b271e4b60b7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf/tb_tb_lofar2_unb2c_sdp_station_bf.vhd
@@ -30,17 +30,12 @@ library IEEE, lofar2_sdp_lib;
use IEEE.std_logic_1164.all;
use lofar2_sdp_lib.sdp_pkg.all;
-
entity tb_tb_lofar2_unb2c_sdp_station_bf is
end tb_tb_lofar2_unb2c_sdp_station_bf;
-
architecture tb of tb_tb_lofar2_unb2c_sdp_station_bf is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
u_bf : entity work.tb_lofar2_unb2c_sdp_station_bf
generic map (
g_sp => 3, -- WG signal path (SP) index in range(S_pn = 12)
@@ -62,5 +57,4 @@ begin
g_read_all_SST => false, -- when FALSE only read SST for g_subband, to save sim time
g_read_all_BST => false -- when FALSE only read BST for g_beamlet, to save sim time
);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
index d449e94b384b603941319701a2210afddc2c44fa..2292509910d6d2468f946f75ee0c52bb5cbb5a07 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB and BF
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -71,7 +70,6 @@ entity lofar2_unb2c_sdp_station_bf is
QSFP_0_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_0_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-
-- front transceivers
QSFP_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
QSFP_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
@@ -85,7 +83,6 @@ entity lofar2_unb2c_sdp_station_bf is
RING_1_RX : in std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0) := (others => '0');
RING_1_TX : out std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
-
-- back transceivers (note only 12 are used in unb2c)
BCK_RX : in std_logic_vector(c_unb2c_board_nof_tr_jesd204b - 1 downto 0); -- c_unb2c_board_nof_tr_jesd204b = c_sdp_S_pn = 12
BCK_REF_CLK : in std_logic; -- Use as JESD204B_REFCLK
@@ -97,14 +94,10 @@ entity lofar2_unb2c_sdp_station_bf is
end lofar2_unb2c_sdp_station_bf;
architecture str of lofar2_unb2c_sdp_station_bf is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA <= BCK_RX;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
index 879bc4cfe166f7920a74ea04833ea2cf9a8b4005..351a0af16c45536bcdb590081907ba511f696b98 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_bf_ring/tb_lofar2_unb2c_sdp_station_bf_ring.vhd
@@ -171,7 +171,6 @@ entity tb_lofar2_unb2c_sdp_station_bf_ring is
end tb_lofar2_unb2c_sdp_station_bf_ring;
architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
-
constant c_sim : boolean := true;
constant c_first_unb_nr : natural := g_first_gn / c_quad; -- c_quad = 4 FPGAs per UniBoard2
constant c_first_node_nr : natural := g_first_gn mod c_quad; -- first node_nr in range(c_quad) = [0:3] on c_first_unb_nr
@@ -486,9 +485,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_bf_ring is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -622,7 +619,6 @@ begin
src_in_arr(0) => tr_10GbE_src_in
);
-
u_rx : entity dp_lib.dp_offload_rx
generic map (
g_nof_streams => 1,
@@ -1475,5 +1471,4 @@ begin
-- To view the 64 bit 10GbE offload data more easily in the Wave window
rx_beamlet_data <= rx_beamlet_sosi.data(c_longword_w - 1 downto 0);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
index 0beac1eb37c12e7831d38e25df8ff0461995a23b..10853a63baf3dd229888366c988e34cc04299429 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/lofar2_unb2c_sdp_station_fsub.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing
-- Contains complete AIT input stage with 12 ADC streams and FSUB
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -78,13 +77,10 @@ entity lofar2_unb2c_sdp_station_fsub is
end lofar2_unb2c_sdp_station_fsub;
architecture str of lofar2_unb2c_sdp_station_fsub is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA <= BCK_RX;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
index cea5b8ce343dcc09a27bf0a67efd09a837bfc044..7d739b0f82e19e68cee96ffde59911ff0b4aa33e 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -94,7 +94,6 @@ entity tb_lofar2_unb2c_sdp_station_fsub is
end tb_lofar2_unb2c_sdp_station_fsub;
architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -261,9 +260,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -630,5 +627,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
index 9803806bb7a19218e6c1dcbde4aae46ebc93049b..15dc0b787d0e20a7d0dff92dbeaadb648a837fe0 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_lofar2_unb2c_sdp_station_fsub_sst_offload.vhd
@@ -57,7 +57,6 @@ entity tb_lofar2_unb2c_sdp_station_fsub_sst_offload is
end tb_lofar2_unb2c_sdp_station_fsub_sst_offload;
architecture tb of tb_lofar2_unb2c_sdp_station_fsub_sst_offload is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 2;
constant c_node_nr : natural := 1;
@@ -133,9 +132,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_fsub_sst_offload is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -281,5 +278,4 @@ begin
);
rx_sdp_stat_header <= func_sdp_map_stat_header(rx_hdr_fields_raw);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
index 5882edc6402407995c7e6c2f4360e7f0ab363fea..5ee8de349555ef55110c507da66066e4cebbe049 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_fsub/tb_tb_lofar2_unb2c_sdp_station_fsub.vhd
@@ -30,17 +30,12 @@ library IEEE, lofar2_sdp_lib;
use IEEE.std_logic_1164.all;
use lofar2_sdp_lib.sdp_pkg.all;
-
entity tb_tb_lofar2_unb2c_sdp_station_fsub is
end tb_tb_lofar2_unb2c_sdp_station_fsub;
-
architecture tb of tb_tb_lofar2_unb2c_sdp_station_fsub is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- Commented to save sim time in regression test
-- u_fsub_only_co : ENTITY work.tb_lofar2_unb2c_sdp_station_fsub
-- GENERIC MAP (
@@ -71,5 +66,4 @@ begin
g_sp_cross_subband_weight_phase => -10.0, -- subband weight phase rotation in degrees, for cross polarization of g_sp
g_read_all_SST => true -- when FALSE only read SST for g_subband, to save sim time
);
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
index 4e029c5caf0534b628e5af62912d7193c9bc6a2d..f637461c321b7f1416fadff1251f8bba7facf813 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full/lofar2_unb2c_sdp_station_full.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB, BF and RING
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -94,13 +93,10 @@ entity lofar2_unb2c_sdp_station_full is
end lofar2_unb2c_sdp_station_full;
architecture str of lofar2_unb2c_sdp_station_full is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA <= BCK_RX;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
index 4997f42d39c47848164d73828639b9826bd6c1cf..9e7d7250d9cc32cdaaad1ae0a4d120d643c38ca4 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_full_wg/lofar2_unb2c_sdp_station_full_wg.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing of SDP using the WG.
-- Contains AIT input stage with WG, FSUB, XSUB, BF and RING, so without ADC JESD.
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,9 +85,7 @@ entity lofar2_unb2c_sdp_station_full_wg is
end lofar2_unb2c_sdp_station_full_wg;
architecture str of lofar2_unb2c_sdp_station_full_wg is
-
begin
-
u_revision : entity lofar2_unb2c_sdp_station_lib.lofar2_unb2c_sdp_station
generic map (
g_design_name => g_design_name,
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
index 1941049c496cf60e677949c03a3971e38608d301..d210c368ad6efc98f279a3d97fe2809eb83f8294 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB and XSUB for XST from one node.
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -78,13 +77,10 @@ entity lofar2_unb2c_sdp_station_xsub_one is
end lofar2_unb2c_sdp_station_xsub_one;
architecture str of lofar2_unb2c_sdp_station_xsub_one is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA <= BCK_RX;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
index 6cf991c91b63bc9b1a2d4ef0a74c8ae572e92ce1..ae39ff5891c1972fcf7a040bd245d465d9095cbc 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one.vhd
@@ -65,7 +65,6 @@ entity tb_lofar2_unb2c_sdp_station_xsub_one is
end tb_lofar2_unb2c_sdp_station_xsub_one;
architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -123,7 +122,6 @@ architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one is
-- WPFB
signal xsub_stats_arr : t_slv_64_arr(0 to c_nof_complex * c_sdp_X_sq - 1);
-
-- DUT
signal ext_clk : std_logic := '0';
signal pps : std_logic := '0';
@@ -145,9 +143,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -358,5 +354,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
index 56f2437d8da9c8588ddeb59582c6b6c489066d33..657a3cebece3eccf10a661c3f3d048487d7d783a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_one/tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload.vhd
@@ -75,7 +75,6 @@ entity tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload is
end tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload;
architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := sel_a_b(g_try_xst_restart, 0, 2);
constant c_node_nr : natural := sel_a_b(g_try_xst_restart, 0, 1); -- use node > 0 to check nof_cycles_dly in sdp_statistics_offload.vhd
@@ -184,9 +183,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station_xsub_one_xst_offload is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -467,5 +464,4 @@ begin
-- rx_sdp_stat_index counts the S_pn * S_pn = X_sq = 12 * 12 = 144 complex statistics
rx_a_sp <= rx_sdp_stat_index / c_sdp_S_pn; -- signal input A
rx_b_sp <= rx_sdp_stat_index mod c_sdp_S_pn; -- signal input B
-
end tb;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
index 57fc97484c0b8179ea33eb92c1aef0320f24e0d7..40b0196d31b2f7a8aed0ebb53653aa608a97bd41 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/revisions/lofar2_unb2c_sdp_station_xsub_ring/lofar2_unb2c_sdp_station_xsub_ring.vhd
@@ -25,7 +25,6 @@
-- Unb2c version for lab testing
-- Contains complete AIT input stage with 12 ADC streams, FSUB, XSUB with ring.
-
library IEEE, common_lib, unb2c_board_lib, diag_lib, dp_lib, tech_jesd204b_lib, lofar2_unb2c_sdp_station_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -94,13 +93,10 @@ entity lofar2_unb2c_sdp_station_xsub_ring is
end lofar2_unb2c_sdp_station_xsub_ring;
architecture str of lofar2_unb2c_sdp_station_xsub_ring is
-
signal JESD204B_SERIAL_DATA : std_logic_vector((c_unb2c_board_tr_jesd204b.bus_w * c_unb2c_board_tr_jesd204b.nof_bus) - 1 downto 0);
signal jesd204b_sync_n_arr : std_logic_vector(c_unb2c_board_nof_sync_jesd204b - 1 downto 0);
signal JESD204B_REFCLK : std_logic;
-
begin
-
-- Mapping between JESD signal names and UNB2B pin/schematic names
JESD204B_REFCLK <= BCK_REF_CLK;
JESD204B_SERIAL_DATA <= BCK_RX;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
index 19bc94fc79321454802832c0cc13d698b2780ed4..0d4176a1f28ac31a330e9db3848355a5be3569f8 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station.vhd
@@ -42,7 +42,6 @@ use lofar2_sdp_lib.sdp_pkg.all;
use work.lofar2_unb2c_sdp_station_pkg.all;
use eth_lib.eth_pkg.all;
-
entity lofar2_unb2c_sdp_station is
generic (
g_design_name : string := "lofar2_unb2c_sdp_station";
@@ -108,9 +107,7 @@ entity lofar2_unb2c_sdp_station is
);
end lofar2_unb2c_sdp_station;
-
architecture str of lofar2_unb2c_sdp_station is
-
-- Revision parameters
constant c_revision_select : t_lofar2_unb2c_sdp_station_config := func_sel_revision_rec(g_design_name);
@@ -468,9 +465,7 @@ architecture str of lofar2_unb2c_sdp_station is
signal unb2_board_qsfp_leds_tx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_sosi_rst);
signal unb2_board_qsfp_leds_tx_siso_arr : t_dp_siso_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_siso_rst);
signal unb2_board_qsfp_leds_rx_sosi_arr : t_dp_sosi_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_sosi_rst);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -1016,5 +1011,4 @@ begin
tx_sosi_arr => unb2_board_qsfp_leds_tx_sosi_arr,
rx_sosi_arr => unb2_board_qsfp_leds_rx_sosi_arr
);
-
end str;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
index f7b15514a33880823548bec150ce5ca7bd4dbd13..45da1f25a4bb4ab8346c1c0ae99dbf3f8a48b39a 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/lofar2_unb2c_sdp_station_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
package lofar2_unb2c_sdp_station_pkg is
-
-----------------------------------------------------------------------------
-- Revision control
-----------------------------------------------------------------------------
@@ -55,12 +54,9 @@ package lofar2_unb2c_sdp_station_pkg is
-- Function to select the revision configuration.
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_sdp_station_config;
-
end lofar2_unb2c_sdp_station_pkg;
-
package body lofar2_unb2c_sdp_station_pkg is
-
function func_sel_revision_rec(g_design_name : string) return t_lofar2_unb2c_sdp_station_config is
begin
if g_design_name = "lofar2_unb2c_sdp_station_adc" then return c_ait;
@@ -75,8 +71,7 @@ package body lofar2_unb2c_sdp_station_pkg is
elsif g_design_name = "disturb2_unb2c_sdp_station_full" then return c_full_os;
else return c_full;
end if;
- end;
+ end;
end lofar2_unb2c_sdp_station_pkg;
-
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
index ebfd3d5a2442dc21215f6d88fc16740c764b55a0..663256c83f518a47f01c77824404e95a6ad0b0a7 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/mmm_lofar2_unb2c_sdp_station.vhd
@@ -328,20 +328,15 @@ entity mmm_lofar2_unb2c_sdp_station is
end mmm_lofar2_unb2c_sdp_station;
architecture str of mmm_lofar2_unb2c_sdp_station is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_copi, reg_unb_system_info_cipo );
@@ -549,7 +544,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
index 74c071dcbf0cb87b99138e0ad8419dbeb7565806..3fa9fa61c5117114f1c2adc01c8057ee2b2dd77c 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/src/vhdl/qsys_lofar2_unb2c_sdp_station_pkg.vhd
@@ -22,7 +22,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_lofar2_unb2c_sdp_station_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus platform designer:
-----------------------------------------------------------------------------
@@ -563,5 +562,5 @@ package qsys_lofar2_unb2c_sdp_station_pkg is
ram_equalizer_gains_cross_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X') -- export
);
end component qsys_lofar2_unb2c_sdp_station;
-end qsys_lofar2_unb2c_sdp_station_pkg;
+end qsys_lofar2_unb2c_sdp_station_pkg;
diff --git a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
index 2d86198b40b3e737332b6e4a56fe3cc530ecb2ea..8bdf7bca758f73305d94c939022399788dfe337d 100644
--- a/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
+++ b/applications/lofar2/designs/lofar2_unb2c_sdp_station/tb/vhdl/tb_lofar2_unb2c_sdp_station.vhd
@@ -50,7 +50,6 @@ entity tb_lofar2_unb2c_sdp_station is
end tb_lofar2_unb2c_sdp_station;
architecture tb of tb_lofar2_unb2c_sdp_station is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -115,9 +114,7 @@ architecture tb of tb_lofar2_unb2c_sdp_station is
-- jesd204b syncronization signals
signal jesd204b_sysref : std_logic;
signal jesd204b_sync_n : std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
begin
-
-- System setup
ext_clk <= (not ext_clk) or tb_end after c_ext_clk_period / 2; -- External clock (200 MHz)
@@ -243,5 +240,4 @@ begin
eth_serial_in => eth_txp_slv(0),
tb_end => eth_done
);
-
end tb;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
index 6e8b86e22bc453777ab02c743d6330d54a93f4e5..c784b9032b3cddb878ec4eb192b2d5252c0787ed 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/Prototype_ddrctrl_controller.vhd
@@ -35,7 +35,6 @@ use common_lib.common_mem_pkg.all;
use common_lib.common_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity ddrctrl_controller is
generic (
g_tech_ddr : t_c_tech_ddr;
@@ -83,7 +82,6 @@ entity ddrctrl_controller is
end ddrctrl_controller;
architecture rtl of ddrctrl_controller is
-
constant c_bitshift_w : natural := ceil_log2(g_burstsize); -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
constant c_adr_w : natural := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
constant c_pof_ma : natural := (((g_max_adr * (100 - g_stop_percentage)) / 100) / g_adr_per_b) * g_adr_per_b; -- percentage of max address.
@@ -92,7 +90,6 @@ architecture rtl of ddrctrl_controller is
-- constant for reading
-
constant c_rd_data_w : natural := g_nof_streams * g_out_data_w; -- 168
constant c_rest : natural := c_rd_data_w - (g_wr_data_w mod c_rd_data_w); -- 96
constant c_io_ddr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
@@ -131,27 +128,20 @@ architecture rtl of ddrctrl_controller is
constant c_t_reg_init : t_reg := (RESET, '0', '0', '0', TO_UVEC(g_max_adr, c_adr_w), (others => '0'), 0, '1', '1', '0', 0, (others => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init);
-
-- signals for readability
signal d_reg : t_reg := c_t_reg_init;
signal q_reg : t_reg := c_t_reg_init;
-
-
begin
-
q_reg <= d_reg when rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
p_state : process(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, wr_fifo_usedw, stop_in)
variable v : t_reg := c_t_reg_init;
-
begin
-
v := q_reg;
v.wr_sosi := inp_sosi;
-
case q_reg.state is
when RESET =>
v := c_t_reg_init;
@@ -164,7 +154,6 @@ begin
v.state := STOP_READING;
end if;
-
when STOP_READING =>
-- this is the last read burst, this make sure every data containing word in the memory has been read.
if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
@@ -186,7 +175,6 @@ begin
v.rd_burst_en := '1';
end if;
-
when WAIT_FOR_SOP =>
v.dvr_mosi.burstbegin := '0';
v.rst_ddrctrl_input := '0';
@@ -198,7 +186,6 @@ begin
v.wr_sosi.valid := '0';
end if;
-
when WRITING =>
-- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
v.wr_bursts_ready := TO_UINT(wr_fifo_usedw(g_wr_fifo_uw_w - 1 downto c_bitshift_w));
@@ -239,7 +226,6 @@ begin
v.state := STOP_WRITING;
end if;
-
when SET_STOP =>
-- this state sets a stop address dependend on the g_stop_percentage.
if inp_adr - c_pof_ma >= 0 then
@@ -284,7 +270,6 @@ begin
v.state := WRITING;
end if;
-
when STOP_WRITING =>
-- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
v.wr_sosi.valid := '0';
@@ -320,7 +305,6 @@ begin
v.state := LAST_WRITE_BURST;
end if;
-
when LAST_WRITE_BURST =>
-- this state stops the writing by generatign one last write burst which empties wr_fifo.
if dvr_miso.done = '1' then
@@ -335,7 +319,6 @@ begin
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
-
when START_READING =>
-- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
v.dvr_mosi.burstbegin := '0';
@@ -357,7 +340,6 @@ begin
v.state := READING;
end if;
-
when READING =>
-- rd_fifo needs a refil after rd_fifo_usedw <= 10 because of delays, if you wait until rd_fifo_usedw = 0 then you get an empty fifo which results in your outputs sosi.valid not being constatly valid.
if TO_UINT(rd_fifo_usedw) <= g_burstsize and dvr_miso.done = '1' and q_reg.rd_burst_en = '1' then
@@ -387,11 +369,8 @@ begin
if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
v.state := STOP_READING;
end if;
-
-
end case;
-
if rst = '1' then
v.state := RESET;
end if;
@@ -401,7 +380,6 @@ begin
end if;
d_reg <= v;
-
end process;
-- fill outputs
@@ -410,5 +388,4 @@ begin
stop_out <= q_reg.stopped;
outp_bsn <= q_reg.outp_bsn;
rst_ddrctrl_input <= q_reg.rst_ddrctrl_input or rst;
-
end rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
index f9e02cedd9422185e44dcec319bd6587ed3bda74..bc766c0ba825314d27c2048578e80d0c06edbc92 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
@@ -44,7 +44,6 @@ use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use io_ddr_lib.all;
-
entity ddrctrl is
generic (
g_tech_ddr : t_c_tech_ddr; -- type of memory
@@ -88,9 +87,7 @@ entity ddrctrl is
);
end ddrctrl;
-
architecture str of ddrctrl is
-
-- constant for readability
constant c_io_ddr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
constant c_wr_fifo_depth : natural := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
@@ -142,9 +139,7 @@ architecture str of ddrctrl is
signal state_vec : std_logic_vector(1 downto 0);
signal ddrctrl_ctrl_state_local : std_logic_vector(32 - 1 downto 0);
signal ctlr_wr_flush_en : std_logic;
-
begin
-
rd_siso.ready <= rd_ready;
rd_siso.xon <= '1';
ddrctrl_ctrl_state(5 downto 0) <= ddrctrl_ctrl_state_local(5 downto 0);
@@ -323,5 +318,4 @@ begin
stop_out => stop,
ddrctrl_ctrl_state => ddrctrl_ctrl_state_local
);
-
end str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
index 95495f5428cbfbda370325f91eb8bc5db29aa21a..69b4c10a71d9cde40702755a4709d38f7f538417 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
@@ -35,7 +35,6 @@ use common_lib.common_mem_pkg.all;
use common_lib.common_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity ddrctrl_controller is
generic (
g_tech_ddr : t_c_tech_ddr;
@@ -87,7 +86,6 @@ entity ddrctrl_controller is
end ddrctrl_controller;
architecture rtl of ddrctrl_controller is
-
constant c_bitshift_w : natural := ceil_log2(g_burstsize); -- bitshift to make sure there is only a burst start at a interval of c_burstsize.
constant c_adr_w : natural := func_tech_ddr_ctlr_address_w( g_tech_ddr ); -- the lengt of the address vector, for simulation this is smaller, otherwise the simulation would take to long, 27
constant c_pof_ma : natural := ((natural((real(g_max_adr) * (100.0 - real(g_stop_percentage))) / 100.0) / g_adr_per_b) * g_adr_per_b); -- percentage of max address.
@@ -97,7 +95,6 @@ architecture rtl of ddrctrl_controller is
-- constant for reading
-
constant c_rd_data_w : natural := g_nof_streams * g_out_data_w; -- 168
constant c_io_ddr_data_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 576
@@ -159,23 +156,17 @@ architecture rtl of ddrctrl_controller is
constant c_t_reg_init : t_reg := (RESET, '0', 4, '0', TO_UVEC(g_max_adr, c_adr_w), (others => '0'), 0, '1', '1', '0', 0, (others => '0'), 0, '1', c_mem_ctlr_mosi_rst, c_dp_sosi_init, (others => '0'));
-
-- signals for readability
signal d_reg : t_reg := c_t_reg_init;
signal q_reg : t_reg := c_t_reg_init;
-
-
begin
-
q_reg <= d_reg when rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
p_state : process(q_reg, rst, inp_of, inp_sosi, inp_adr, inp_bsn_adr, inp_data_stopped, dvr_miso, rd_fifo_usedw, wr_fifo_usedw, stop_in)
variable v : t_reg := c_t_reg_init;
-
begin
-
v := q_reg;
v.wr_sosi := inp_sosi;
--v.ddrctrl_ctrl_state(c_high_bsn_ndx DOWNTO c_low_bsn_ndx) := inp_sosi.bsn(c_start_bsn+c_bsn_ndx_w-1 DOWNTO c_start_bsn);
@@ -191,7 +182,6 @@ begin
v.timer := 0;
end if;
-
when STOP_FLUSH =>
v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(1, c_state_ndx_w);
v.wr_sosi.valid := '0';
@@ -213,7 +203,6 @@ begin
v.stopped := '0';
end if;
-
when STOP_READING =>
v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(2, c_state_ndx_w);
-- this is the last read burst, this make sure every data containing word in the memory has been read.
@@ -236,7 +225,6 @@ begin
v.rd_burst_en := '1';
end if;
-
when WAIT_FOR_SOP =>
v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(3, c_state_ndx_w);
v.dvr_mosi.burstbegin := '0';
@@ -252,7 +240,6 @@ begin
v.wr_sosi.valid := '0';
end if;
-
when WRITING =>
v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(4, c_state_ndx_w);
-- this state generates the rest of the write bursts, it also checks if there is a stop signal or if it needs to stop writing.
@@ -290,7 +277,6 @@ begin
v.state := STOP_WRITING;
end if;
-
when SET_STOP =>
v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(5, c_state_ndx_w);
-- this state sets a stop address dependend on the g_stop_percentage.
@@ -340,7 +326,6 @@ begin
v.state := WRITING;
end if;
-
when STOP_WRITING =>
v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(6, c_state_ndx_w);
-- this state stops the writing by generating one last whole write burst which almost empties wr_fifo.
@@ -377,7 +362,6 @@ begin
v.state := LAST_WRITE_BURST;
end if;
-
when LAST_WRITE_BURST =>
v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(7, c_state_ndx_w);
-- this state stops the writing by generatign one last write burst which empties wr_fifo.
@@ -399,7 +383,6 @@ begin
v.dvr_mosi.wr := '1';
v.dvr_mosi.rd := '0';
-
when START_READING =>
v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(8, c_state_ndx_w);
-- this state generates the first read burst, the size of this burst is dependend on the size of the last write burst.
@@ -429,7 +412,6 @@ begin
v.state := READING;
end if;
-
when READING =>
v.ddrctrl_ctrl_state(c_high_state_ndx downto c_low_state_ndx) := TO_UVEC(9, c_state_ndx_w);
v.wr_sosi.valid := '0';
@@ -461,11 +443,8 @@ begin
if q_reg.last_adr_to_write_to(c_adr_w - 1 downto 0) = TO_UVEC(q_reg.read_adr, c_adr_w) then
v.state := STOP_READING;
end if;
-
-
end case;
-
if rst = '1' then
v.state := RESET;
end if;
@@ -483,7 +462,6 @@ begin
v.ddrctrl_ctrl_state(c_high_bre_ndx downto c_low_bre_ndx) := TO_UVEC(q_reg.wr_bursts_ready, 32)(c_bre_ndx_w - 1 downto 0);
d_reg <= v;
-
end process;
-- fill outputs
@@ -493,6 +471,4 @@ begin
outp_bsn <= q_reg.outp_bsn;
rst_ddrctrl_input_ac <= q_reg.rst_ddrctrl_input_ac or rst;
ddrctrl_ctrl_state <= q_reg.ddrctrl_ctrl_state;
-
-
end rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
index 7947c5d3f4cdf581bfae54a01bdc0aad7736b576..a0f0eea2bd54923eddc34d38aa1508fc0997f093 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input.vhd
@@ -41,7 +41,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
-
entity ddrctrl_input is
generic (
g_tech_ddr : t_c_tech_ddr; -- type of memory
@@ -65,22 +64,17 @@ entity ddrctrl_input is
);
end ddrctrl_input;
-
architecture str of ddrctrl_input is
-
-- constant for readability
constant c_out_data_w : natural := g_nof_streams * g_data_w; -- the input data with for ddrctrl_repack
-
-- signals for connecting the components
signal sosi_p_rp : t_dp_sosi := c_dp_sosi_init;
signal sosi_rp_ac : t_dp_sosi := c_dp_sosi_init;
signal adr : natural := 0;
signal valid : std_logic := '0';
signal data_stopped_rp_ac : std_logic := '0';
-
begin
-
out_adr <= adr;
-- makes one data vector out of all the data from the t_dp_sosi_arr
@@ -128,5 +122,4 @@ begin
out_bsn_adr => out_bsn_adr,
out_data_stopped => out_data_stopped
);
-
end str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
index bd1d65946f1841cacaaf304e11a7c0a2c88efbcc..d5e7bd5d7ff86b33d07230934432be13e0621f10 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_address_counter.vhd
@@ -38,7 +38,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
-
entity ddrctrl_input_address_counter is
generic (
g_tech_ddr : t_c_tech_ddr; -- type of memory
@@ -56,9 +55,7 @@ entity ddrctrl_input_address_counter is
);
end ddrctrl_input_address_counter;
-
architecture rtl of ddrctrl_input_address_counter is
-
-- constants for readability
constant c_data_w : natural := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the with of the input data and output data, 576
@@ -79,20 +76,16 @@ architecture rtl of ddrctrl_input_address_counter is
constant c_t_reg_init : t_reg := (RESET, '0', c_dp_sosi_init, 0, '0', c_dp_sosi_init, '0', 0);
-
-- signals for readability
signal d_reg : t_reg := c_t_reg_init;
signal q_reg : t_reg := c_t_reg_init;
-
begin
-
q_reg <= d_reg when rising_edge(clk);
-- Increments the address each time in_sosi.valid = '1', if address = g_max_adr the address is reset to 0.
p_adr : process(rst, in_sosi, in_data_stopped, q_reg)
variable v : t_reg;
-
begin
v := q_reg;
@@ -102,7 +95,6 @@ begin
v.s_in_sosi := in_sosi;
v.s_in_data_stopped := in_data_stopped;
-
case q_reg.state is
when RESET =>
v := c_t_reg_init;
@@ -111,7 +103,6 @@ begin
v.out_bsn_adr := v.s_adr;
end if;
-
when COUNTING =>
v.s_adr := q_reg.s_adr + 1;
@@ -119,7 +110,6 @@ begin
v.out_bsn_adr := v.s_adr;
end if;
-
when MAX =>
v.s_adr := 0;
@@ -127,14 +117,11 @@ begin
v.out_bsn_adr := v.s_adr;
end if;
-
when IDLE =>
-- after a reset wait for a sop so the memory will be filled with whole blocks.
if in_sosi.sop = '1' then
v.bsn_passed := '1';
end if;
-
-
end case;
if rst = '1' then
@@ -156,5 +143,4 @@ begin
out_bsn_adr <= q_reg.out_bsn_adr;
out_sosi.bsn <= q_reg.out_sosi.bsn;
out_data_stopped <= q_reg.out_data_stopped;
-
end rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
index 5990dbd818a5f5fe5887fd9175847a9e80ac5968..4895077bd3f1da1a0570e9b981f67a2e1f635842 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_pack.vhd
@@ -44,7 +44,6 @@ end ddrctrl_input_pack;
architecture rtl of ddrctrl_input_pack is
begin
-
-- Putting all the data from the different streams into one data vector.
gen_extract_and_pack_data : for I in 0 to g_nof_streams - 1 generate
p_generate : process(in_sosi_arr) is
@@ -53,12 +52,10 @@ begin
end process;
end generate;
-
-- check if the input data is valid bij doing a and operation on all of them
out_sosi.valid <= func_dp_stream_arr_and(in_sosi_arr, "VALID");
out_sosi.sop <= func_dp_stream_arr_and(in_sosi_arr, "SOP");
out_sosi.eop <= func_dp_stream_arr_and(in_sosi_arr, "EOP");
out_sosi.sync <= func_dp_stream_arr_and(in_sosi_arr, "SYNC");
out_sosi.bsn <= in_sosi_arr(0).bsn;
-
end rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
index 046f8889ff566bbc515aea7ab299da4dcb588388..2c232e370e4a19cdca0067674e2991ebbd649fbd 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_input_repack.vhd
@@ -53,9 +53,7 @@ entity ddrctrl_input_repack is
);
end ddrctrl_input_repack;
-
architecture rtl of ddrctrl_input_repack is
-
-- constant for readability
constant c_out_data_w : natural := func_tech_ddr_ctlr_data_w( g_tech_ddr ); -- the output data with, 576
constant k_c_v_w : natural := c_out_data_w * 2; -- the c_v data with, 2*576=1152
@@ -79,22 +77,17 @@ architecture rtl of ddrctrl_input_repack is
constant c_t_reg_init : t_reg := (RESET, (others => '0'), 0, (others => '0'), '0', 0, 0, '0', c_dp_sosi_init, '0');
-
-- signals for readability
signal d_reg : t_reg := c_t_reg_init;
signal q_reg : t_reg := c_t_reg_init;
-
begin
-
q_reg <= d_reg when rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
p_state : process(q_reg, rst, in_sosi, in_stop)
variable v : t_reg;
-
begin
-
v := q_reg;
case q_reg.state is
@@ -107,7 +100,6 @@ begin
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
-
when FIRST_OUTPUT => -- if the input data exceeds output data vector width but not the c_v width
v.c_v(g_in_data_w * (q_reg.c_v_count + 1) + q_reg.out_of - 1 downto g_in_data_w * q_reg.c_v_count + q_reg.out_of) := in_sosi.data(g_in_data_w - 1 downto 0); -- fill c_v
v.c_v_count := q_reg.c_v_count + 1; -- increase the counter of c_v with 1
@@ -120,7 +112,6 @@ begin
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
-
when OVERFLOW_OUTPUT => -- if the input data exceeds the output data vector width and the c_v width
v.out_of := q_reg.out_of + (g_in_data_w * (q_reg.c_v_count + 1)) - (c_out_data_w * 2); -- check how much overflow there is and safe it in out_of
v.c_v(k_c_v_w - 1 downto k_c_v_w - (g_in_data_w - v.out_of)) := in_sosi.data(g_in_data_w - v.out_of - 1 downto 0); -- fill the rest of c_v untill the end
@@ -135,7 +126,6 @@ begin
v.out_sosi.eop := '0';
v.out_data_stopped := '0';
-
when BSN =>
v.c_v(k_c_v_w - 1 downto ((g_in_data_w * q_reg.c_v_count) + q_reg.out_of)) := (others => '0');
@@ -156,21 +146,16 @@ begin
v.out_data_count := '0';
v.out_sosi.eop := '1';
-
when RESET =>
v := c_t_reg_init;
v.q_bsn(c_dp_stream_bsn_w - 1 downto 0) := in_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0);
-
when STOP =>
v.out_sosi.valid := '0';
v.q_sop := '0';
v.out_data_stopped := '1';
-
-
end case;
-
if rst = '1' then
v.state := RESET;
elsif in_stop = '1' or in_sosi.valid = '0' then
@@ -186,12 +171,10 @@ begin
v.state := FILL_VECTOR;
end if;
-
d_reg <= v;
end process;
-- fill outputs
out_sosi <= q_reg.out_sosi;
out_data_stopped <= q_reg.out_data_stopped;
-
end rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
index 1a1b8efa1d4adc2910d1d684148c743125445fae..69fee61b011b63c1a46bd14c0fb2995ff764d283 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output.vhd
@@ -38,7 +38,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
-
entity ddrctrl_output is
generic (
g_technology : natural;
@@ -61,16 +60,13 @@ entity ddrctrl_output is
);
end ddrctrl_output;
-
architecture str of ddrctrl_output is
-
-- constant for readability
constant c_out_data_w : natural := g_nof_streams * g_data_w; -- the input data width for ddrctrl_repack 168
-- fifo
constant c_fifo_size : natural := 2;
-
-- signals for connecting the components
signal sosi : t_dp_sosi := c_dp_sosi_init;
signal out_sosi : t_dp_sosi := c_dp_sosi_init;
@@ -82,9 +78,7 @@ architecture str of ddrctrl_output is
-- SIGNAL siso : t_dp_siso := c_dp_siso_rst;
-- SIGNAL fifo_src_out_sosi : t_dp_sosi := c_dp_sosi_init;
-- SIGNAL fifo_usedw : STD_LOGIC_VECTOR(ceil_log2(c_fifo_size)-1 DOWNTO 0) := (OTHERS => '0');
-
begin
-
-- makes one data vector out of all the data from the t_dp_sosi_arr
u_ddrctrl_output_unpack : entity work.ddrctrl_output_unpack
generic map(
@@ -116,7 +110,6 @@ begin
out_sosi_arr => out_sosi_arr
);
-
-- u_fifo : ENTITY dp_lib.dp_fifo_dc_mixed_widths
-- GENERIC MAP (
-- g_technology => g_technology,
@@ -145,13 +138,10 @@ begin
-- src_out => fifo_src_out_sosi
-- );
-
p_out_siso_ready : process(out_siso, clk, out_sosi, q_out_siso)
variable sosi_valid : std_logic := '0';
-
begin
-
if out_siso.ready = '0' and not (q_out_siso.ready = out_siso.ready) then
sosi <= out_sosi;
sosi_valid := '0';
@@ -172,5 +162,4 @@ begin
sosi.sop <= sosi_valid and out_sosi.sop;
sosi.eop <= sosi_valid and out_sosi.eop;
end process;
-
end str;
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
index 0996454c917bb7b6f2753f87ac70c3605e4241dd..02b993e2c33a9cd801ae8ba2302f805422317263 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_repack.vhd
@@ -45,9 +45,7 @@ entity ddrctrl_output_repack is
end ddrctrl_output_repack;
architecture rtl of ddrctrl_output_repack is
-
begin
-
-- putting the data from the stream into different streams.
gen_repack_data : for I in 0 to g_nof_streams - 1 generate
out_sosi_arr(I).data(g_data_w - 1 downto 0) <= in_sosi.data(g_data_w * (I + 1) - 1 downto g_data_w * I);
diff --git a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
index 328e80cc75a16a222befe1fc565e6f06cad0f152..b9e56f78f12bcbf809079c757a77e8e3f6f7da34 100644
--- a/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+++ b/applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
@@ -57,9 +57,7 @@ entity ddrctrl_output_unpack is
);
end ddrctrl_output_unpack;
-
architecture rtl of ddrctrl_output_unpack is
-
constant c_v_w : natural := g_in_data_w * 2;
-- type for statemachine
@@ -85,18 +83,14 @@ architecture rtl of ddrctrl_output_unpack is
-- signals for readability
signal d_reg : t_reg := c_t_reg_init;
signal q_reg : t_reg := c_t_reg_init;
-
begin
-
q_reg <= d_reg when rising_edge(clk);
-- put the input data into c_v and fill the output vector from c_v
p_state : process(q_reg, rst, in_bsn, in_sosi, out_siso)
variable v : t_reg;
-
begin
-
v := q_reg;
if out_siso.ready = '1' or q_reg.state = OFF or q_reg.state = IDLE or q_reg.state = RESET or rst = '1' then
@@ -117,7 +111,6 @@ begin
v.out_sosi.sop := '0';
end if;
-
when OVER_HALF =>
-- generating output data from c_v but past the halfway point of c_v so there needs to be new data added
if q_reg.valid_data = '1' then
@@ -138,7 +131,6 @@ begin
v.out_sosi.sop := '0';
end if;
-
when FIRST_READ =>
-- put the second half of c_v into the first half of c_v
v.c_v(g_in_data_w - 1 downto 0) := q_reg.c_v(c_v_w - 1 downto g_in_data_w);
@@ -154,7 +146,6 @@ begin
v.bsn_cnt := 0;
v.op_data_cnt := 1;
-
when BSN =>
-- generating output data from c_v but past the halfway point of c_v so there needs to be new data added also increases the bsn output
v.out_sosi.valid := '0';
@@ -178,32 +169,25 @@ begin
v.a_of := 0;
v.bsn_cnt := q_reg.bsn_cnt + 1;
-
when RESET =>
v := c_t_reg_init;
-
when IDLE =>
-- the statemachine goes to Idle when its finished or when its waiting on other components.
v.out_sosi.valid := '0';
-
when OFF =>
-- the stamachine has a state off so it knows when to go to first read, it can't go to first read from IDLE
v.out_sosi := c_dp_sosi_init;
v.bsn_cnt := 0;
v.state_off := '1';
-
-
end case;
-
else
-- IDLE
v.out_sosi.valid := '0';
end if;
-
-- compensating for fifo delay
if q_reg.dd_fresh = '1' and q_reg.valid_data = '0' then
-- put the delay data into the second half of c_v beceause these are now zeros
@@ -216,7 +200,6 @@ begin
v.dd_fresh := '1';
end if;
-
if rst = '1' then
v.state := RESET;
elsif q_reg.state = RESET or (q_reg.valid_data = '0' and q_reg.state = OFF) or ((INCR_UVEC(INCR_UVEC(in_bsn, g_bim), -1)(c_dp_stream_bsn_w - 1 downto 0) = q_reg.out_sosi.bsn(c_dp_stream_bsn_w - 1 downto 0)) and v.out_sosi.eop = '1') then
@@ -248,6 +231,4 @@ begin
out_sosi <= q_reg.out_sosi;
out_ready <= q_reg.out_ready;
state_off <= q_reg.state_off;
-
-
end rtl;
diff --git a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
index 45282ae543b42d8d35a827095ef74faeeba2bea0..999afc3545127e74126d91f3c72c52bc67538ed6 100644
--- a/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
+++ b/applications/lofar2/libraries/ddrctrl/tb/vhdl/tb_ddrctrl.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright 2022
@@ -34,7 +33,6 @@ use common_lib.common_mem_pkg.all;
use common_lib.common_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_ddrctrl is
generic (
@@ -50,7 +48,6 @@ entity tb_ddrctrl is
end tb_ddrctrl;
architecture tb of tb_ddrctrl is
-
constant c_sim_model : boolean := true; -- determens if this is a simulation
-- Select DDR3 or DDR4 dependent on the technology and sim model
@@ -122,7 +119,6 @@ architecture tb of tb_ddrctrl is
constant c_check_bottom : natural := 5;
constant c_ones : std_logic_vector(c_check - c_check_bottom - 1 downto 0) := (others => '1');
-
-- input signals for ddrctrl.vhd
signal clk : std_logic := '1';
signal rst : std_logic := '0';
@@ -141,7 +137,6 @@ architecture tb of tb_ddrctrl is
signal test_running : std_logic := '0'; -- signal to tell wheter the testing has started
signal bsn_cnt : natural := g_block_size-1;
-
-- signals for checking the output data
signal output_data_cnt : natural := 0;
@@ -150,10 +145,7 @@ architecture tb of tb_ddrctrl is
signal phy3_ou : t_tech_ddr3_phy_ou;
signal phy4_io : t_tech_ddr4_phy_io;
signal phy4_ou : t_tech_ddr4_phy_ou;
-
-
begin
-
-- generating clock
clk <= not clk or tb_end after c_clk_period / 2;
mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2;
@@ -163,9 +155,7 @@ begin
p_test : process
variable out_siso_ready : natural := 0;
-
begin
-
-- start the test
out_siso.ready <= '1';
tb_end <= '0';
@@ -233,11 +223,9 @@ begin
end loop;
end loop;
-
in_sosi_arr(0).valid <= '0';
test_running <= '0';
-
-- stopping the testbench
wait for c_clk_period * g_block_size;
tb_end <= '1';
@@ -260,8 +248,6 @@ begin
wait for c_clk_period * 1;
end process;
-
-
-- DUT
u_ddrctrl : entity work.ddrctrl
generic map (
@@ -291,5 +277,4 @@ begin
phy4_io => phy4_io,
phy4_ou => phy4_ou
);
-
end tb;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
index ece0816c57f7cc3d5c8b76962dacd15a9d24db9d..107e1a05883b173a0ea9f423426ca1eb60511687 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd
@@ -109,9 +109,7 @@ entity node_sdp_adc_input_and_timing is
);
end node_sdp_adc_input_and_timing;
-
architecture str of node_sdp_adc_input_and_timing is
-
-- Waveform Generator
constant c_wg_buf_directory : string := "data/";
constant c_wg_buf_dat_w : natural := 18; -- default value of WG that fits 14 bits of ADC data
@@ -151,9 +149,7 @@ architecture str of node_sdp_adc_input_and_timing is
signal mm_jesd_ctrl_reg_rd : std_logic_vector(c_word_w - 1 downto 0);
signal jesd204b_disable_arr : std_logic_vector(c_sdp_S_pn - 1 downto 0);
signal jesd204b_reset_request : std_logic := '0';
-
begin
-
gen_no_jesd : if g_no_jesd = true generate
rx_clk <= dp_clk;
rx_rst <= dp_rst;
@@ -315,7 +311,6 @@ begin
trigger_out => trigger_wg
);
-
-----------------------------------------------------------------------------
-- WG (Test Signal Generator)
-----------------------------------------------------------------------------
@@ -355,7 +350,6 @@ begin
out_sosi_arr => wg_sosi_arr
);
-
-----------------------------------------------------------------------------
-- ADC/WG Mux (Input Select)
-----------------------------------------------------------------------------
@@ -386,7 +380,6 @@ begin
end process;
end generate;
-
---------------------------------------------------------------------------------------
-- Diagnostics on the bsn-framed data
-- . BSN Monitor (ToDo: can be removed as not part of the spec)
@@ -394,7 +387,6 @@ begin
-- . Data Buffer (variable depth from 1k-128k)
---------------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------------
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
@@ -418,7 +410,6 @@ begin
in_sosi_arr => st_sosi_arr(0 downto 0)
);
-
-----------------------------------------------------------------------------
-- Monitor ADU/WG output
-----------------------------------------------------------------------------
@@ -447,7 +438,6 @@ begin
in_sosi_arr => st_sosi_arr
);
-
-----------------------------------------------------------------------------
-- Diagnostic Data Buffer
-----------------------------------------------------------------------------
@@ -497,7 +487,6 @@ begin
snk_in_arr => st_sosi_arr
);
-
-----------------------------------------------------------------------------
-- Output Stage
-- . Thin dual clock fifo to cross from jesd frame clock (rx_clk) to dp_clk domain
@@ -573,5 +562,4 @@ begin
out_reg => mm_jesd_ctrl_reg_wr,
in_reg => mm_jesd_ctrl_reg_rd
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
index ccca16990ba2b4bd5037073fe8f4e238c4c4c171..a2ea28949b81de46b3caec0db64d887885664610 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_beamformer.vhd
@@ -111,7 +111,6 @@ entity node_sdp_beamformer is
end node_sdp_beamformer;
architecture str of node_sdp_beamformer is
-
-- Note that the sdp library contains src/python/sdp_hex.py to generate hex files.
constant c_bf_select_file_prefix : string := "data/bf_unit_ss_wide";
constant c_bf_weights_file_name : string := sel_a_b(g_sim, "data/bf_unit_weights", "UNUSED");
@@ -139,9 +138,7 @@ architecture str of node_sdp_beamformer is
signal rn_index : natural range 0 to c_sdp_N_pn_max - 1 := 0;
signal ref_sync : std_logic;
-
begin
-
-- Use register to ease timing closure.
rn_index <= TO_UINT(SUB_UVEC(gn_id, ring_info.O_rn)) when rising_edge(dp_clk);
ref_sync <= in_sosi_arr(0).sync when rising_edge(dp_clk);
@@ -449,5 +446,4 @@ begin
sp_sosi_arr(0) => bf_out_sosi,
scope_sosi_arr => scope_bf_out_sosi_arr
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
index 0a1c4695c85378ebb95f1c66ac7ef7dd9fa26907..fb263f5b4ccdd775cd50e95c9b7d44f38751bab2 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_correlator.vhd
@@ -93,7 +93,6 @@ entity node_sdp_correlator is
end node_sdp_correlator;
architecture str of node_sdp_correlator is
-
constant c_nof_controllers : positive := 2;
constant c_block_size : natural := c_sdp_N_crosslets_max * c_sdp_S_pn;
constant c_block_size_longwords : natural := ceil_div(c_block_size, 2); -- 32b -> 64b
@@ -141,9 +140,7 @@ architecture str of node_sdp_correlator is
signal prev_crosslets_info_rec : t_sdp_crosslets_info;
signal nof_crosslets_reg : std_logic_vector(c_sdp_nof_crosslets_reg_w - 1 downto 0);
signal nof_crosslets : std_logic_vector(c_sdp_nof_crosslets_reg_w - 1 downto 0);
-
begin
-
---------------------------------------------------------------
-- Requantize 18b to 16b
---------------------------------------------------------------
@@ -324,7 +321,6 @@ begin
dispatch_sosi_arr <= func_dp_stream_arr_reverse_range(dispatch_invert_sosi_arr);
-
---------------------------------------------------------------
-- dp_bsn_aligner_v2
---------------------------------------------------------------
@@ -495,5 +491,4 @@ begin
nof_crosslets => nof_crosslets, -- from MM
prev_crosslets_info_rec => prev_crosslets_info_rec
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
index ca4473fed798a61543db43b2971c34f0b8d56432..691a5a916f2e60945d2288c84c4eaaf418767720 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_filterbank.vhd
@@ -116,7 +116,6 @@ entity node_sdp_filterbank is
end node_sdp_filterbank;
architecture str of node_sdp_filterbank is
-
-- FIR coeffs file is copied to build data/ dir by design revision hdllib.cfg
-- from: $HDL_WORK/libraries/dsp/filter/src/hex
constant c_coefs_file_prefix : string := "data/Coeffs16384Kaiser-quant_1wb";
@@ -174,9 +173,7 @@ architecture str of node_sdp_filterbank is
signal dbg_g_wpfb : t_wpfb := g_wpfb;
signal dbg_c_subband_raw_dat_w : natural := c_subband_raw_dat_w;
signal dbg_c_subband_raw_fraction_w : natural := c_subband_raw_fraction_w;
-
begin
-
---------------------------------------------------------------
-- SPECTRAL INVERSION
---------------------------------------------------------------
@@ -443,5 +440,4 @@ begin
sdp_info => sdp_info,
weighted_subbands_flag => weighted_subbands_flag
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
index 93d3d21baf03d36bd370e28b9f16c8a2668da416..3e9de6c4baba26d5f0883cd46a1de604b0f50b4f 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/node_sdp_oversampled_filterbank.vhd
@@ -102,7 +102,6 @@ entity node_sdp_oversampled_filterbank is
end node_sdp_oversampled_filterbank;
architecture str of node_sdp_oversampled_filterbank is
-
-- See node_sdp_filterbank for location and genetion of hex files
constant c_coefs_file_prefix : string := "data/Coeffs16384Kaiser-quant_1wb";
constant c_gains_file_name : string := "data/gains_1024_complex_" &
@@ -213,9 +212,7 @@ architecture str of node_sdp_oversampled_filterbank is
signal dp_bsn_source_restart_delayed : std_logic;
signal dp_bsn_source_restart_wg : std_logic;
signal dp_bsn_source_restart_pipe_complex : std_logic;
-
begin
-
---------------------------------------------------------------
-- SPECTRAL INVERSION
---------------------------------------------------------------
@@ -291,7 +288,6 @@ begin
dp_bsn_source_restart => dp_bsn_source_restart_pipe
);
-
---------------------------------------------------------------
-- POLY-PHASE COMPLEX FILTERBANK
---------------------------------------------------------------
@@ -780,5 +776,4 @@ begin
sdp_info => sdp_info,
weighted_subbands_flag => weighted_subbands_flag
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
index aabbc80077c00b91c58e7c4fc9fd23451e213bf9..8281d80b1bd11b173bc637046d00f1ebb78177cc 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_local.vhd
@@ -60,7 +60,6 @@ entity sdp_beamformer_local is
end sdp_beamformer_local;
architecture str of sdp_beamformer_local is
-
constant c_complex_adder_latency : natural := ceil_log2(c_sdp_S_pn);
constant c_bf_weights_latency : natural := 5; -- 3 for complex multiplier + 2 RAM latency
constant c_total_latency : natural := 3 + c_bf_weights_latency + c_complex_adder_latency;
@@ -89,7 +88,6 @@ architecture str of sdp_beamformer_local is
signal complex_add_out_sosi : t_dp_sosi := c_dp_sosi_rst;
signal pipelined_in_sosi : t_dp_sosi := c_dp_sosi_rst;
signal dp_requantize_in_sosi : t_dp_sosi := c_dp_sosi_rst;
-
begin
---------------------------------------------------------------
-- COPY INPUT STREAMS FOR X AND Y POLARIZATION PATHS
@@ -251,5 +249,4 @@ begin
-- ST source
src_out => out_sosi
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
index 2ba6c2fb7accfbb26a6c290d0e8a277db0ca400c..210c308c6596fb1d5d456602cce0a2b7807e870a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_output.vhd
@@ -76,7 +76,6 @@ entity sdp_beamformer_output is
end sdp_beamformer_output;
architecture str of sdp_beamformer_output is
-
constant c_data_w : natural := c_nof_complex * c_sdp_W_beamlet; -- 16b
constant c_beamlet_index : natural := g_beamset_id * c_sdp_S_sub_bf; -- call beamset 'id' and beamlet 'index'
@@ -110,9 +109,7 @@ architecture str of sdp_beamformer_output is
-- Default set all data path driven header fields to 0
signal dp_offload_tx_hdr_fields : std_logic_vector(1023 downto 0) := (others => '0');
signal dp_offload_tx_header : t_sdp_cep_header; -- to view dp_offload_tx_hdr_fields in Wave window
-
begin
-
-------------------------------------------------------------------------------
-- Input rewiring: concatenate input complex fields to data field
-- . dp_repack_data works with data fields only
@@ -427,5 +424,4 @@ begin
src_in_arr(0) => out_siso,
src_out_arr(0) => out_sosi
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
index 4d917a2a779230fdb8092147f32533862f78b022..11f74388b5f5cb189b8d17adfe68ea0044199480 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_beamformer_remote.vhd
@@ -63,7 +63,6 @@ entity sdp_beamformer_remote is
end sdp_beamformer_remote;
architecture str of sdp_beamformer_remote is
-
constant c_data_w : natural := c_nof_complex * c_sdp_W_beamlet_sum;
constant c_block_size : natural := c_sdp_S_sub_bf * c_sdp_N_pol_bf;
constant c_fifo_size : natural := 2**ceil_log2((c_block_size * 9) / 16); -- 9/16 = 36/64, 1 block of 64 bit words rounded to the next power of 2 = 1024.
@@ -75,9 +74,7 @@ architecture str of sdp_beamformer_remote is
signal beamlets_sosi_arr : t_dp_sosi_arr(c_dual - 1 downto 0) := (others => c_dp_sosi_rst);
signal i_bf_sum_sosi : t_dp_sosi := c_dp_sosi_rst;
signal bf_sum_data_sosi : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
-- repacking beamlets re/im to data field.
p_wire_local_bf_sosi : process(local_bf_sosi)
begin
@@ -180,7 +177,6 @@ begin
beamlets_sosi_arr(1).im <= RESIZE_DP_DSP_DATA(beamlets_data_sosi_arr(1).data( c_data_w - 1 downto c_sdp_W_beamlet_sum));
end process;
-
---------------------------------------------------------------
-- ADD local + remote
---------------------------------------------------------------
@@ -197,7 +193,6 @@ begin
src_out => i_bf_sum_sosi
);
-
---------------------------------------------------------------
-- Local output
---------------------------------------------------------------
@@ -230,5 +225,4 @@ begin
snk_in => bf_sum_data_sosi,
src_out => to_ri_sosi
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
index 471c8c4f09ad8100c525814e688d1dfb7e0c6d8d..567bc51fb6c9d9c075bebdd60f9523ac9d0f2bdd 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_bf_weights.vhd
@@ -63,7 +63,6 @@ entity sdp_bf_weights is
end sdp_bf_weights;
architecture str of sdp_bf_weights is
-
constant c_gain_addr_w : natural := ceil_log2(c_sdp_Q_fft * c_sdp_S_sub_bf);
-- Product width, do -1 to skip double sign bit in product
@@ -72,9 +71,7 @@ architecture str of sdp_bf_weights is
signal in_sosi : t_dp_sosi;
signal cnt : natural range 0 to c_sdp_Q_fft * c_sdp_S_sub_bf - 1;
signal gains_rd_address : std_logic_vector(c_gain_addr_w - 1 downto 0);
-
begin
-
in_sosi <= in_sosi_arr(0); -- use ctrl from input [0]
---------------------------------------------------------------
@@ -148,5 +145,4 @@ begin
in_sosi_arr => in_sosi_arr,
out_sosi_arr => out_sosi_arr
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
index 9482e28ea72f440d16a9d470eb842f25837af51c..9296c034921d37dd48dfd5199116263e881872a5 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_crosslets_subband_select.vhd
@@ -81,7 +81,6 @@ entity sdp_crosslets_subband_select is
end sdp_crosslets_subband_select;
architecture str of sdp_crosslets_subband_select is
-
constant c_crosslets_info_dly : natural := 1;
constant c_col_select_addr_w : natural := ceil_log2(c_sdp_Q_fft * c_sdp_N_sub);
constant c_row_select_slv_w : natural := ceil_log2(c_sdp_P_pfb);
@@ -126,9 +125,7 @@ architecture str of sdp_crosslets_subband_select is
signal crosslets_info_rec : t_sdp_crosslets_info;
signal crosslets_info_rec_inout : t_sdp_crosslets_info;
signal active_crosslets_info_rec : t_sdp_crosslets_info;
-
begin
-
---------------------------------------------------------------
-- BSN sync scheduler
---------------------------------------------------------------
@@ -330,6 +327,7 @@ begin
-- Out Crosslet info pipeline
---------------------------------------------------------------
active_crosslets_info(c_sdp_crosslets_info_reg_w - 1 downto c_sdp_crosslets_info_reg_w - c_sdp_crosslets_index_w) <= TO_UVEC(r.step, c_sdp_crosslets_index_w);
+
gen_crosslets_info : for I in 0 to g_N_crosslets - 1 generate
active_crosslets_info((I + 1) * c_sdp_crosslets_index_w - 1 downto I * c_sdp_crosslets_index_w) <= TO_UVEC(r.offsets(I), c_sdp_crosslets_index_w);
end generate;
@@ -386,5 +384,4 @@ begin
cur_crosslets_info_rec <= func_sdp_map_crosslets_info(cur_crosslets_info);
prev_crosslets_info_rec <= func_sdp_map_crosslets_info(prev_crosslets_info);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
index ef69b79c2b6ac0094fbe5d18289ce3095e355a24..ba93d5bf2405af2d0ccdd5f517f258e1b9a146e6 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info.vhd
@@ -60,14 +60,10 @@ entity sdp_info is
);
end sdp_info;
-
architecture str of sdp_info is
-
signal sdp_info_ro: t_sdp_info := c_sdp_info_rst; -- ro = read only
signal block_period: std_logic_vector(15 downto 0);
-
begin
-
u_mm_fields: entity work.sdp_info_reg
port map (
@@ -85,7 +81,6 @@ begin
sdp_info => sdp_info
);
-
-- f_adc : '0' => 160M, '1' => 200M
-- fsub_type: '0' => critical sampled PFB, '1' => oversampled PFB
p_block_period : process(f_adc, fsub_type)
@@ -108,5 +103,4 @@ begin
sdp_info_ro.f_adc <= f_adc;
sdp_info_ro.fsub_type <= fsub_type;
sdp_info_ro.block_period <= block_period;
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
index dfd62b3ff67451e84c66c8d3156ab645e5e3f7ce..3feac6001af561964fa7328c52b3505040ee1f55 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_info_reg.vhd
@@ -57,9 +57,7 @@ entity sdp_info_reg is
);
end sdp_info_reg;
-
architecture str of sdp_info_reg is
-
constant c_field_arr : t_common_field_arr(8 downto 0) :=
( (field_name_pad("antenna_field_index"), "RW", 6, field_default(0)), -- = station_info[15:10]
(field_name_pad("station_id"), "RW", 10, field_default(0)), -- = station_info[9:0]
@@ -76,9 +74,7 @@ architecture str of sdp_info_reg is
signal sdp_info_rd : t_sdp_info;
signal sdp_info_wr : t_sdp_info;
-
begin
-
sdp_info <= sdp_info_rd;
p_sdp_info_rd : process(sdp_info_wr, sdp_info_ro)
@@ -92,7 +88,6 @@ begin
sdp_info_rd.block_period <= sdp_info_ro.block_period;
end process;
-
u_mm_fields: entity mm_lib.mm_fields
generic map(
g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
@@ -126,5 +121,4 @@ begin
sdp_info_wr.observation_id <= mm_fields_out(field_hi(c_field_arr, "observation_id") downto field_lo(c_field_arr, "observation_id"));
sdp_info_wr.nyquist_zone_index <= mm_fields_out(field_hi(c_field_arr, "nyquist_zone_index") downto field_lo(c_field_arr, "nyquist_zone_index"));
sdp_info_wr.beam_repositioning_flag <= sl(mm_fields_out(field_hi(c_field_arr, "beam_repositioning_flag") downto field_lo(c_field_arr, "beam_repositioning_flag")));
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
index cae9604c185f141fa381d10744dfdf8484c04447..e9dc68716674a535bb5dd91fa0448a5ab3eb1180 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_pkg.vhd
@@ -615,7 +615,6 @@ package sdp_pkg is
constant c_sdp_reg_dp_block_validate_err_xst_addr_w : natural := 4;
constant c_sdp_reg_dp_block_validate_bsn_at_sync_xst_addr_w : natural := 2;
-
-- RING MM address widths
constant c_sdp_reg_bsn_monitor_v2_ring_rx_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
constant c_sdp_reg_bsn_monitor_v2_ring_tx_addr_w : natural := ceil_log2(c_sdp_N_ring_lanes_max) + ceil_log2(c_sdp_N_pn_max) + c_sdp_reg_bsn_monitor_v2_addr_w;
@@ -680,7 +679,6 @@ package sdp_pkg is
end package sdp_pkg;
package body sdp_pkg is
-
function func_sdp_gn_index_to_pn_index(gn_index : natural) return natural is
-- Determine PN index that starts at 0 per antenna band. For LOFAR2 SDP
-- each antenna_band has c_sdp_N_pn_max = 16 PN. The pn_index defines the
@@ -820,7 +818,6 @@ package body sdp_pkg is
return func_sdp_get_stat_nof_packets(g_statistics_type, c_sdp_S_pn, c_sdp_P_sq, c_sdp_N_crosslets_max);
end func_sdp_get_stat_nof_packets;
-
function func_sdp_map_stat_header(hdr_fields_raw : std_logic_vector) return t_sdp_stat_header is
variable v : t_sdp_stat_header;
begin
@@ -881,7 +878,6 @@ package body sdp_pkg is
return v;
end func_sdp_map_stat_header;
-
function func_sdp_map_cep_header(hdr_fields_raw : std_logic_vector) return t_sdp_cep_header is
variable v : t_sdp_cep_header;
begin
@@ -937,7 +933,6 @@ package body sdp_pkg is
return v;
end func_sdp_map_cep_header;
-
function func_sdp_map_stat_data_id(g_statistics_type : string; data_id_slv : std_logic_vector) return t_sdp_stat_data_id is
variable v_rec : t_sdp_stat_data_id;
begin
@@ -968,7 +963,6 @@ package body sdp_pkg is
return v_slv;
end func_sdp_map_stat_data_id;
-
function func_sdp_map_crosslets_info(info_slv : std_logic_vector) return t_sdp_crosslets_info is
variable v_info : t_sdp_crosslets_info;
begin
@@ -989,7 +983,6 @@ package body sdp_pkg is
return v_info;
end func_sdp_map_crosslets_info;
-
function func_sdp_step_crosslets_info(info_rec : t_sdp_crosslets_info) return t_sdp_crosslets_info is
variable v_info : t_sdp_crosslets_info := info_rec;
begin
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
index 1028933de6299242241e226bc04400adaa29a381..d6d46c4f058fdc98860dc875b0817a9e217fd04b 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_scope.vhd
@@ -57,20 +57,15 @@ entity sdp_scope is
);
end sdp_scope;
-
architecture str of sdp_scope is
-
type t_dp_sosi_2arr_n is array (integer range <>) of t_dp_sosi_arr(g_n_deinterleave-1 downto 0);
signal cnt : natural;
signal deinterleaved_sosi_2arr_n : t_dp_sosi_2arr_n(g_nof_input - 1 downto 0);
signal deinterleaved_sosi_arr : t_dp_sosi_arr(g_nof_input * g_n_deinterleave-1 downto 0);
signal selected_sosi_arr : t_dp_sosi_arr(g_nof_input * g_n_deinterleave-1 downto 0) := (others => c_dp_sosi_rst);
-
begin
-
sim_only : if g_sim = true generate
-
gen_deinterleave : for I in 0 to g_nof_input - 1 generate
u_dp_deinterleave : entity dp_lib.dp_deinterleave_one_to_n
generic map(
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
index cf4189c6ce78763c23e2deedb067585d774051a7..e4c467900159aeef3f5d866a652e9dd00cf63ddf 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_station.vhd
@@ -95,7 +95,6 @@ entity sdp_station is
JESD204B_SYSREF : in std_logic;
JESD204B_SYNC_N : out std_logic_vector(c_sdp_N_sync_jesd - 1 downto 0);
-
----------------------------------------------
-- UDP Offload
----------------------------------------------
@@ -383,9 +382,7 @@ entity sdp_station is
);
end sdp_station;
-
architecture str of sdp_station is
-
-- WPFB subband width
constant c_fft : t_fft := func_wpfb_map_wpfb_parameters_to_fft(g_wpfb);
constant c_fft_raw_dat_w : natural := func_fft_raw_dat_w(c_fft);
@@ -596,9 +593,7 @@ architecture str of sdp_station is
signal sst_udp_src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
signal bst_udp_src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
signal xst_udp_src_port : std_logic_vector(c_network_udp_port_w - 1 downto 0);
-
begin
-
gn_index <= TO_UINT(gn_id);
-----------------------------------------------------------------------------
@@ -842,7 +837,6 @@ begin
end generate;
end generate;
-
-----------------------------------------------------------------------------
-- node_sdp_correlator (XSUB)
-----------------------------------------------------------------------------
@@ -902,7 +896,6 @@ begin
stat_ip_src_addr => stat_ip_src_addr,
stat_udp_src_port => xst_udp_src_port
);
-
end generate;
-----------------------------------------------------------------------------
@@ -977,7 +970,6 @@ begin
stat_ip_src_addr => stat_ip_src_addr,
stat_udp_src_port => bst_udp_src_port
);
-
end generate;
-- MM multiplexing
@@ -1316,7 +1308,6 @@ begin
);
end generate;
-
u_mem_mux_reg_ring_lane_info_bf : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => c_sdp_N_beamsets,
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
index d362ef60064b489d1363f3d3f18166ee2b1f9d25..858a12ce9f8e979dbd3e1828ce5c5b972007d6fa 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
@@ -163,9 +163,7 @@ entity sdp_statistics_offload is
);
end sdp_statistics_offload;
-
architecture str of sdp_statistics_offload is
-
constant c_nof_streams : natural := 1;
-- header fields
@@ -278,9 +276,7 @@ architecture str of sdp_statistics_offload is
signal dbg_c_mm_data_size : natural := c_mm_data_size;
signal dbg_c_mm_step_size : natural := c_mm_step_size;
signal dbg_c_mm_nof_data : natural := c_mm_nof_data;
-
begin
-
-------------------------------------------------------------------------------
-- Assemble offload header info
-------------------------------------------------------------------------------
@@ -365,7 +361,6 @@ begin
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "sdp_block_period" ) downto field_lo(c_sdp_stat_hdr_field_arr, "sdp_block_period" )) <= sdp_info.block_period;
dp_header_info(field_hi(c_sdp_stat_hdr_field_arr, "dp_bsn" ) downto field_lo(c_sdp_stat_hdr_field_arr, "dp_bsn" )) <= hdr_input.bsn_at_sync;
-
p_reg : process(dp_rst, dp_clk)
begin
if dp_rst = '1' then
@@ -467,18 +462,22 @@ begin
gen_data_id_sst : if g_statistics_type = "SST" generate
data_id_rec.sst_signal_input_index <= r.packet_count + p.local_si_offset;
end generate;
+
gen_data_id_sst_os : if g_statistics_type = "SST_OS" generate
-- Signal input index is repeated, first 0:11 (r.packet_count 0:11) with fsub_type = 0.
-- Then for r.packet_count 12:23, signal input index is again 0:11 but with fsub_type = 1.
fsub_type <= '0' when r.packet_count < c_sdp_S_pn else '1'; -- Set fsub_type = 0 for unshifted bands, '1' for shifted bands
data_id_rec.sst_signal_input_index <= r.packet_count + p.local_si_offset when r.packet_count < c_sdp_S_pn else r.packet_count - c_sdp_S_pn + p.local_si_offset;
end generate;
+
gen_no_os : if g_statistics_type /= "SST_OS" generate -- Set fsub_type to sdp_info.fsub_type when g_statistics_type is not SST_OS.
fsub_type <= sdp_info.fsub_type;
end generate;
+
gen_data_id_bst : if g_statistics_type = "BST" generate
data_id_rec.bst_beamlet_index <= c_beamlet_id;
end generate;
+
gen_data_id_xst : if g_statistics_type = "XST" generate
data_id_rec.xst_subband_index <= func_sdp_modulo_N_sub(hdr_input.crosslets_info_rec.offset_arr(r.crosslet_count));
data_id_rec.xst_signal_input_A_index <= p.local_si_offset;
@@ -717,5 +716,4 @@ begin
in_sosi_arr(0) => udp_sosi
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
index edb7f9964f369d673d4f870c79d9a5be845dac5f..c42b95e49f6a87ace78f6d4f0a6d4566a5d9563d 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_equalizer.vhd
@@ -83,7 +83,6 @@ entity sdp_subband_equalizer is
end sdp_subband_equalizer;
architecture str of sdp_subband_equalizer is
-
constant c_gain_addr_w : natural := ceil_log2(c_sdp_Q_fft * c_sdp_N_sub);
-- Product width, do -1 to skip double sign bit in product
@@ -103,9 +102,7 @@ architecture str of sdp_subband_equalizer is
signal weighted_cross_raw_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal sum_raw_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Prepare co and cross input
-----------------------------------------------------------------------------
diff --git a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
index 8b2c4e4eb3e3cd31763d26254f4ec4a2e316a0de..75cbf8a89d652a8f80617f94658647e4aefb2f6a 100644
--- a/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
+++ b/applications/lofar2/libraries/sdp/src/vhdl/sdp_subband_weights.vhd
@@ -74,7 +74,6 @@ entity sdp_subband_weights is
end sdp_subband_weights;
architecture str of sdp_subband_weights is
-
constant c_gain_addr_w : natural := ceil_log2(c_sdp_Q_fft * c_sdp_N_sub);
-- Product width, do -1 to skip double sign bit in product
@@ -83,9 +82,7 @@ architecture str of sdp_subband_weights is
signal in_sosi : t_dp_sosi;
signal cnt : natural range 0 to c_sdp_Q_fft * c_sdp_N_sub - 1;
signal gains_rd_address : std_logic_vector(c_gain_addr_w - 1 downto 0);
-
begin
-
in_sosi <= in_raw_sosi_arr(0); -- use ctrl from input [0]
-----------------------------------------------------------------------------
@@ -188,5 +185,4 @@ begin
in_sosi_arr => in_cross_raw_sosi_arr,
out_sosi_arr => weighted_cross_raw_sosi_arr
);
-
end str;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
index d677643371f2b2a16b9eaf0baff968668e72a0c3..39f4fb1d949f32e0ef866fd5d3505dfc7a93635a 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_subband_select.vhd
@@ -44,12 +44,9 @@ use dp_lib.tb_dp_pkg.all;
use work.sdp_pkg.all;
entity tb_sdp_crosslets_subband_select is
-
end tb_sdp_crosslets_subband_select;
-
architecture tb of tb_sdp_crosslets_subband_select is
-
constant c_clk_period : time := 10 ns;
constant c_mm_clk_period : time := 20 ns;
constant c_rl : natural := 1;
@@ -97,9 +94,7 @@ architecture tb of tb_sdp_crosslets_subband_select is
signal cur_crosslets_info_rec : t_sdp_crosslets_info;
signal exp_prev_crosslets_info_rec : t_sdp_crosslets_info;
signal prev_crosslets_info_rec : t_sdp_crosslets_info;
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -307,5 +302,4 @@ begin
cur_crosslets_info_rec => cur_crosslets_info_rec,
prev_crosslets_info_rec => prev_crosslets_info_rec
);
-
end tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
index cc7d5ac3fb409577e26022ec524ec825860a987d..ef323ac858df135b1b286ed9e8a2a1728705fed4 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_info.vhd
@@ -41,7 +41,6 @@ use common_lib.tb_common_pkg.all;
use common_lib.tb_common_mem_pkg.all;
use work.sdp_pkg.all;
-
entity tb_sdp_info is
end tb_sdp_info;
@@ -197,7 +196,6 @@ begin
proc_common_wait_some_cycles(mm_clk, 100);
tb_mm_reg_end <= '1';
wait;
-
end process;
-- check if values in sdp_info match with expected values
@@ -220,7 +218,6 @@ begin
wait;
end process;
-
-- SDP info
u_dut: entity work.sdp_info
port map (
@@ -238,5 +235,4 @@ begin
sdp_info => sdp_info
);
-
end tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
index d84f73d36b3aa9e40ad46423df5a9c748285ea2d..47cc9348b285cc47fc7700505b731c141889f73c 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_pkg.vhd
@@ -32,7 +32,6 @@ use common_lib.common_network_layers_pkg.all;
use work.sdp_pkg.all;
package tb_sdp_pkg is
-
-----------------------------------------------------------------------------
-- Derive low part of MAC, IP from global node (GN) index
-----------------------------------------------------------------------------
@@ -93,7 +92,6 @@ package tb_sdp_pkg is
cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
return t_real_arr; -- 0:3 = ampl, phase, re, im
-
-----------------------------------------------------------------------------
-- Beamformer (BF)
-----------------------------------------------------------------------------
@@ -104,11 +102,9 @@ package tb_sdp_pkg is
rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
nof_rem : natural)
return t_real_arr; -- 0:3 = ampl, phase, re, im
-
end package tb_sdp_pkg;
package body tb_sdp_pkg is
-
function func_sdp_gn_index_to_mac_15_0(gn_index : natural) return std_logic_vector is
constant c_unb_nr : natural := gn_index / 4; -- 4 PN per Uniboard2
constant c_node_nr : natural := gn_index mod 4;
@@ -423,7 +419,6 @@ package body tb_sdp_pkg is
return true;
end func_sdp_verify_cep_header;
-
function func_sdp_subband_equalizer(sp_subband_ampl, sp_subband_phase, sp_esub_gain, sp_esub_phase,
cross_subband_ampl, cross_subband_phase, cross_esub_gain, cross_esub_phase : real)
return t_real_arr is -- 0:3 = ampl, phase, re, im
@@ -448,7 +443,6 @@ package body tb_sdp_pkg is
return v_tuple;
end;
-
function func_sdp_beamformer(sp_subband_ampl, sp_subband_phase, sp_bf_gain, sp_bf_phase,
rem_subband_ampl, rem_subband_phase, rem_bf_gain, rem_bf_phase : real;
nof_rem : natural)
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
index eafe4669a300ad759180f02827acf1ef6068261e..235b962b494b04abec47bb73ebe22f026af5bdfa 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
@@ -50,7 +50,6 @@ use ring_lib.ring_pkg.all;
use work.sdp_pkg.all;
use work.tb_sdp_pkg.all;
-
entity tb_sdp_statistics_offload is
generic (
-- All
@@ -73,7 +72,6 @@ entity tb_sdp_statistics_offload is
end tb_sdp_statistics_offload;
architecture tb of tb_sdp_statistics_offload is
-
constant c_dp_clk_period : time := 5 ns; -- 200 MHz
constant c_mm_clk_period : time := sel_a_b(g_fast_mm_clk, 1 , 10) * 1 ns;
constant c_mm_dp_clk_ratio : natural := sel_a_b(c_mm_clk_period > c_dp_clk_period, c_mm_clk_period / c_dp_clk_period, 1);
@@ -250,9 +248,7 @@ architecture tb of tb_sdp_statistics_offload is
signal dbg_c_nof_block_per_sync : natural := c_nof_block_per_sync;
signal dbg_c_nof_clk_per_block : natural := c_nof_clk_per_block;
signal dbg_c_nof_clk_per_sync : natural := c_nof_clk_per_sync;
-
begin
-
-- Check consistency of constant value dependencies
assert c_ram_size = c_mm_ram_size report "Wrong derivation of RAM size." severity FAILURE;
@@ -382,9 +378,11 @@ begin
exp_dp_bsn <= cur_dp_bsn when rising_edge(dp_clk) and rx_offload_sosi.sync = '1'; -- previous sync interval
-- SST, SST_OS
exp_sst_signal_input <= (rx_packet_cnt mod c_sdp_S_pn) + c_sdp_S_pn * gn_index; -- Using MOD c_sdp_S_pn for SST_OS.
+
gen_fsub_type : if g_statistics_type = "SST_OS" generate
exp_sdp_info.fsub_type <= '0' when rx_packet_cnt < c_sdp_S_pn else '1';
end generate;
+
-- BST
exp_bst_beamlet_index <= c_beamlet_index;
-- XST
@@ -579,7 +577,6 @@ begin
v_exp_data := v_exp_data + J * c_packet_size; -- c_packet_size = 576
v_exp_data := v_exp_data + K * c_mm_Xsq_span; -- c_mm_Xsq_span = 4096
assert v_exp_data = v_rx_data report "Wrong XST payload data Rx" severity ERROR;
-
end if;
-- for debug in wave window
rx_val <= '1';
@@ -699,5 +696,4 @@ begin
-- To view the 32 bit 1GbE offload data more easily in the Wave window
sdp_offload_data <= sdp_offload_sosi.data(c_word_w - 1 downto 0);
rx_offload_data <= rx_offload_sosi.data(c_word_w - 1 downto 0);
-
end tb;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
index 50b2e2ec7a9353a620bf0d0aee250ad67f4f836c..c325ba9be21b0f986b274e1060af40f0e48548b3 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_tb_sdp_statistics_offload.vhd
@@ -36,7 +36,6 @@ end tb_tb_sdp_statistics_offload;
architecture tb of tb_tb_sdp_statistics_offload is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- -- All
-- g_fast_mm_clk : BOOLEAN := TRUE; -- When TRUE use 1 GHz mm_clk to speed up simulation, else use 100 MHz mm_clk
-- -- for real speed of u_dp_block_from_mm_dc in sdp_statistics_offload
@@ -72,5 +71,4 @@ begin
u_xst_P9_N7_RN0_7 : entity work.tb_sdp_statistics_offload generic map( true, "XST", 50, true, 3, 3, 0, 0, 8, 9, 7, 1); -- P_sq = 9 > N_rn/2+1 = 5
u_xst_P9_N4_RN0_7_slow_mm : entity work.tb_sdp_statistics_offload generic map(false, "XST", 50, true, 3, 3, 0, 0, 8, 9, 4, 1); -- P_sq = 9 > N_rn/2+1 = 5
u_xst_P9_N7_RN0_7_slow_mm : entity work.tb_sdp_statistics_offload generic map(false, "XST", 50, true, 3, 3, 0, 0, 8, 9, 7, 1); -- P_sq = 9 > N_rn/2+1 = 5
-
end tb;
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd
index a8639774e04480b29b516a8726d238269f4738f4..8a099df82cf0ffbf05d05dfd82c90c87a9dc7ade 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_eth_tester_wrapper.vhd
@@ -150,7 +150,6 @@ entity rdma_demo_eth_tester_wrapper is
);
end rdma_demo_eth_tester_wrapper;
-
architecture str of rdma_demo_eth_tester_wrapper is
constant c_nof_byte : natural := c_rdma_demo_nof_octet_output_100gbe;
@@ -182,9 +181,7 @@ architecture str of rdma_demo_eth_tester_wrapper is
signal mm_rst : std_logic := '0';
signal st_rst : std_logic := '0';
-
begin
-
u_eth_tester : entity eth_lib.eth_tester
generic map (
g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
@@ -379,5 +376,4 @@ begin
reg_strobe_total_count_rx_avs_readdata <= RESIZE_UVEC_32(reg_strobe_total_count_rx_cipo.rddata);
reg_strobe_total_count_rx_avs_readdatavalid <= reg_strobe_total_count_rx_cipo.rdval;
reg_strobe_total_count_rx_avs_waitrequest <= reg_strobe_total_count_rx_cipo.waitrequest;
-
end str;
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
index 438bd8acd6f28a0d75cea9da7cfd6ebe2106b507..ebb8993efb0cc384c2288d53b4d707f9babaffba 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_pkg.vhd
@@ -30,11 +30,9 @@ use common_lib.common_field_pkg.all;
use common_lib.common_network_layers_pkg.all;
package rdma_demo_pkg is
-
constant c_rdma_demo_nof_octet_generate_100gbe : natural := 64;
constant c_rdma_demo_nof_octet_output_100gbe : natural := 64;
-
-- hdr_field_sel bit selects where the hdr_field value is set:
-- . 0 = data path controlled, value is set in data path, so field_default()
-- is not used.
@@ -67,7 +65,6 @@ package rdma_demo_pkg is
constant c_rdma_demo_dp_app_hdr_len : natural := 12; -- octets
-
-- RoCEv2 header for RDMA write operation (excluding ETH, IP, UDP)
-- Base Transport Header (BTH) + RDMA Extended Transport Header (RETH) + Immediate Data
constant c_rdma_demo_roce_nof_hdr_fields : natural := 12 + 4 + 13 + 3 + 1;
@@ -117,10 +114,7 @@ package rdma_demo_pkg is
constant c_rdma_demo_roce_hdr_len : natural := 32; -- octets
constant c_rdma_demo_roce_icrc_len : natural := 4; -- octets
-
end rdma_demo_pkg;
package body rdma_demo_pkg is
-
end rdma_demo_pkg;
-
diff --git a/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd b/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd
index 7eab44990b6ef4e6cbc5a271f6d7d7647c196969..928a80f195b7c50c42937871cad1ff9bedde7783 100644
--- a/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd
+++ b/applications/rdma_demo/src/vhdl/rdma_demo_roce_tester_wrapper.vhd
@@ -151,7 +151,6 @@ entity rdma_demo_roce_tester_wrapper is
);
end rdma_demo_roce_tester_wrapper;
-
architecture str of rdma_demo_roce_tester_wrapper is
constant c_nof_byte : natural := c_rdma_demo_nof_octet_output_100gbe;
@@ -183,9 +182,7 @@ architecture str of rdma_demo_roce_tester_wrapper is
signal mm_rst : std_logic := '0';
signal st_rst : std_logic := '0';
-
begin
-
u_eth_tester : entity eth_lib.eth_tester
generic map (
g_nof_octet_generate => c_rdma_demo_nof_octet_generate_100gbe,
@@ -383,5 +380,4 @@ begin
reg_strobe_total_count_rx_avs_readdata <= RESIZE_UVEC_32(reg_strobe_total_count_rx_cipo.rddata);
reg_strobe_total_count_rx_avs_readdatavalid <= reg_strobe_total_count_rx_cipo.rdval;
reg_strobe_total_count_rx_avs_waitrequest <= reg_strobe_total_count_rx_cipo.waitrequest;
-
end str;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
index b04f2c161c4d53b9f965c93ccd3ff598cd469b2b..6dd67461421825c623cf4ea6fe6d758361b640e0 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/ring_pkg.vhd
@@ -27,14 +27,11 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package ring_pkg is
-
function nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return integer;
function nof_hops_to_source_rn(hops, this_rn, N_rn : std_logic_vector; lane_dir : natural) return std_logic_vector; -- return vector length is same as hops vector length
-
end ring_pkg;
package body ring_pkg is
-
function nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return integer is
variable v_source_rn : integer;
begin
@@ -43,6 +40,7 @@ package body ring_pkg is
if v_source_rn < 0 then -- Cannot use MOD as N_rn is not a constant.
v_source_rn := v_source_rn + N_rn;
end if;
+
else
v_source_rn := this_rn + hops;
if v_source_rn > N_rn then
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
index 9597c5e56d49692071b40179d85eb823a5270f9c..34b1424f815182181ca35334120e421656f29c93 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/tb_lofar2_unb2b_ring_bsp.vhd
@@ -66,7 +66,6 @@ entity tb_lofar2_unb2b_ring_bsp is
end tb_lofar2_unb2b_ring_bsp;
architecture tb of tb_lofar2_unb2b_ring_bsp is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
constant c_node_nr : natural := 0;
@@ -85,7 +84,6 @@ architecture tb of tb_lofar2_unb2b_ring_bsp is
constant c_nof_block_per_sync : natural := 16;
-
-- MM
constant c_mm_file_reg_sdp_info : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_SDP_INFO";
constant c_mm_file_reg_dp_xonoff_bg : string := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_DP_XONOFF_BG";
@@ -100,7 +98,6 @@ architecture tb of tb_lofar2_unb2b_ring_bsp is
signal tb_clk : std_logic := '0';
signal rd_data : std_logic_vector(c_32 - 1 downto 0);
-
-- 10GbE
signal tr_10GbE_src_out : t_dp_sosi;
signal tr_ref_clk_312 : std_logic := '0';
@@ -130,9 +127,7 @@ architecture tb of tb_lofar2_unb2b_ring_bsp is
signal si_lpbk_0 : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
signal si_lpbk_1 : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
signal si_lpbk_2 : std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -246,7 +241,6 @@ begin
);
-
------------------------------------------------------------------------------
-- MM slave accesses via file IO
------------------------------------------------------------------------------
@@ -264,7 +258,6 @@ begin
proc_common_wait_until_hi_lo(ext_clk, ext_pps);
-
----------------------------------------------------------------------------
-- Enable UDP offload (dp_xonoff) of beamset 0
----------------------------------------------------------------------------
@@ -283,7 +276,6 @@ begin
-- 6: BSN_init[31:0]
-- 7: BSN_init[63:32]
-
mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 0 , tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 1, 750 , tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 2, c_nof_block_per_sync, tb_clk);
@@ -293,7 +285,6 @@ begin
mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 6, 0 , tb_clk);
mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 7, 0 , tb_clk);
-
mmf_mm_bus_wr(c_mm_file_reg_bg_ctrl, 0, 3 , tb_clk);
proc_common_wait_some_cycles(ext_clk, 2 * c_nof_block_per_sync * 1000);
@@ -304,7 +295,6 @@ begin
mmf_mm_bus_rd(c_mm_file_reg_bsn_monitor_tx, I, rd_data, tb_clk);
end loop;
-
---------------------------------------------------------------------------
-- End Simulation
---------------------------------------------------------------------------
@@ -313,5 +303,4 @@ begin
proc_common_stop_simulation(true, ext_clk, sim_done, tb_end);
wait;
end process;
-
end tb;
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
index f7b313a11e15ce7982988ce640ac51dd57f86183..d13377d1b35d1ea75891924f3ed24f8a476641eb 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top.vhd
@@ -106,7 +106,6 @@ entity top is
);
end top;
-
architecture str of top is
---------------
-- Constants
@@ -329,7 +328,6 @@ architecture str of top is
signal ta2_unb2b_10GbE_ring_ch_snk_out_arr : t_dp_siso_arr(c_nof_streams_ring - 1 downto 0) := (others => c_dp_siso_rst);
signal ta2_unb2b_10GbE_ring_ch_snk_in_arr : t_dp_sosi_arr(c_nof_streams_ring - 1 downto 0) := (others => c_dp_sosi_rst);
-
signal ta2_unb2b_10GbE_qsfp_src_out_arr : t_dp_sosi_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_sosi_rst);
signal ta2_unb2b_10GbE_qsfp_src_in_arr : t_dp_siso_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_siso_rst);
signal ta2_unb2b_10GbE_qsfp_snk_out_arr : t_dp_siso_arr(c_nof_streams_qsfp - 1 downto 0) := (others => c_dp_siso_rst);
@@ -386,9 +384,7 @@ architecture str of top is
signal gn_index : natural := 0;
signal this_rn_id : std_logic_vector(c_sdp_W_gn_id - 1 downto 0);
signal sdp_info : t_sdp_info := c_sdp_info_rst;
-
begin
-
assert g_nof_lanes <= c_nof_streams_ring report "g_nof_lanes is configured too high!" severity ERROR;
------------
@@ -453,10 +449,8 @@ begin
gen_wire_bus : for i in 0 to c_nof_ring_bus - 1 generate
gen_wire_signals : for j in 0 to c_ring_bus_w - 1 generate
-
i_RING_TX(i)(j) <= unb2b_board_ring_io_serial_tx_arr(i * c_ring_bus_w + j);
unb2b_board_ring_io_serial_rx_arr(i * c_ring_bus_w + j) <= i_RING_RX(i)(j);
-
end generate;
end generate;
@@ -592,7 +586,6 @@ begin
kernel_snk_in_arr => kernel_from_lane_sosi_arr(g_nof_lanes - 1 downto 0)
);
-
-----------------------------------------------------------------------------
-- kernel clock crossing for bs sosi
-----------------------------------------------------------------------------
@@ -1523,4 +1516,3 @@ begin
);
end generate;
end str;
-
diff --git a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
index 7300ceb6ee14476b9228b1273a6e36214946daf3..deca506ed84e4395f8ee499a9cfd70dd56c8925f 100644
--- a/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/lofar2_unb2b_ring_bsp/top_components_pkg.vhd
@@ -28,7 +28,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package top_components_pkg is
-
component board is
port (
avs_eth_0_clk_export : out std_logic; -- export
@@ -454,7 +453,6 @@ package top_components_pkg is
board_kernel_stream_snk_tx_monitor_7_valid : out std_logic;
board_kernel_stream_snk_tx_monitor_7_ready : in std_logic;
-
board_kernel_stream_src_bs_data : in std_logic_vector(103 downto 0);
board_kernel_stream_src_bs_valid : in std_logic;
board_kernel_stream_src_bs_ready : out std_logic;
@@ -469,5 +467,3 @@ package top_components_pkg is
end component freeze_wrapper;
end top_components_pkg;
-
-
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
index b80bc1c49f134f86272a0ebd2c5fd64b42e15d5e..3af8c3fc2f25ce9d61ac987021c64ef9694a7b2a 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top.vhd
@@ -127,7 +127,6 @@ entity top is
);
end top;
-
architecture str of top is
---------------
-- Constants
@@ -250,7 +249,6 @@ architecture str of top is
signal reg_ta2_unb2b_mm_io_mosi : t_mem_mosi;
signal reg_ta2_unb2b_mm_io_miso : t_mem_miso;
-
-- QSFP
signal i_QSFP_TX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
signal i_QSFP_RX : t_unb2b_board_qsfp_bus_2arr(c_nof_qsfp_bus - 1 downto 0);
@@ -344,9 +342,7 @@ architecture str of top is
signal ta2_unb2b_mm_io_src_out : t_dp_sosi;
signal ta2_unb2b_mm_io_src_in : t_dp_siso;
-
constant c_ones : std_logic_vector(511 downto 0) := (others => '1');
-
begin
------------
-- Front IO
@@ -407,8 +403,6 @@ begin
QSFP_LED(i * 2 + 1) <= qsfp_red_led_arr(i);
end generate;
-
-
------------
-- RING IO
------------
@@ -472,7 +466,6 @@ begin
unb2b_board_front_io_serial_tx_arr(0) <= ta2_unb2b_10GbE_tx_serial_r(0);
ta2_unb2b_10GbE_rx_serial_r(0) <= unb2b_board_front_io_serial_rx_arr(0);
-
u_ta2_unb2b_10GbE : entity ta2_unb2b_10GbE_lib.ta2_unb2b_10GbE
generic map (
g_nof_mac => c_nof_10GbE_IP
@@ -495,7 +488,6 @@ begin
snk_in_arr => ta2_unb2b_10GbE_snk_in_arr
);
-
-----------------------------
-- 1GbE Monitoring & Control
-----------------------------
@@ -518,7 +510,6 @@ begin
snk_in => ta2_unb2b_1GbE_snk_in
);
-
--------------------------------------
-- Monitoring & Control UNB protocol
--------------------------------------
@@ -543,7 +534,6 @@ begin
);
-
----------
-- ADC
----------
@@ -855,7 +845,6 @@ begin
ETH_SGOUT => ETH_SGOUT
);
-
-----------------------------------------------------------------------------
-- Board qsys
-----------------------------------------------------------------------------
@@ -1022,7 +1011,6 @@ begin
kernel_mem0_byteenable => board_kernel_mem0_byteenable,
kernel_mem0_debugaccess => board_kernel_mem0_debugaccess,
-
ddr4a_pll_ref_clk => MB_I_REF_CLK,
ddr4a_oct_oct_rzqin => MB_I_IN.oct_rzqin,
ddr4a_mem_ck => MB_I_OU.ck(g_tech_ddr.ck_w - 1 downto 0),
@@ -1042,9 +1030,5 @@ begin
ddr4a_mem_dq => MB_I_IO.dq(g_tech_ddr.dq_w - 1 downto 0),
ddr4a_mem_dbi_n => MB_I_IO.dbi_n(g_tech_ddr.dbi_w - 1 downto 0)
-
);
-
-
end str;
-
diff --git a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
index 4b96f52db14a4825041e9ac01f4644e5bf1f19cd..fa7090c8ba2cab2ffc8a579323e373cdef3c2eb5 100644
--- a/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
+++ b/applications/ta2/bsp/hardware/ta2_unb2b_bsp/top_components_pkg.vhd
@@ -28,7 +28,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package top_components_pkg is
-
component board is
port (
avs_eth_0_clk_export : out std_logic; -- export
@@ -305,5 +304,3 @@ package top_components_pkg is
end component freeze_wrapper;
end top_components_pkg;
-
-
diff --git a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
index ba356beb865c8aa9956a75bcf8734dbbf2f99f5f..931a44d84138702620f0ed221b2c0a8252067b5c 100644
--- a/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
+++ b/applications/ta2/ip/ta2_channel_cross/ta2_channel_cross.vhd
@@ -100,9 +100,7 @@ entity ta2_channel_cross is
);
end ta2_channel_cross;
-
architecture str of ta2_channel_cross is
-
constant c_data_w : natural := c_byte_w * g_nof_bytes;
constant c_empty_w : natural := ceil_log2(g_nof_bytes);
constant c_err_w : natural := sel_a_b(g_use_err, g_err_w, 0);
@@ -126,7 +124,6 @@ architecture str of ta2_channel_cross is
signal dp_latency_adapter_rx_snk_out_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
signal dp_latency_adapter_rx_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal dp_latency_adapter_rx_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
-
begin
assert g_nof_bytes <= 32 report "g_nof_bytes of ta2_channel_cross is configured higher than 32" severity ERROR;
@@ -191,6 +188,7 @@ begin
kernel_src_out_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 - I)) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_byte_w * (I + 1) - 1 downto c_byte_w * I);
end generate;
end generate;
+
gen_no_reverse_rx_bytes : if not g_reverse_bytes generate
kernel_src_out_arr(stream).data(c_data_w - 1 downto 0) <= dp_latency_adapter_tx_src_out_arr(stream).data(c_data_w - 1 downto 0);
end generate;
@@ -227,6 +225,7 @@ begin
dp_latency_adapter_rx_snk_in_arr(stream).data(c_byte_w * (g_nof_bytes - I) - 1 downto c_byte_w * (g_nof_bytes - 1 - I)) <= kernel_snk_in_arr(stream).data(c_byte_w * (I + 1) - 1 downto c_byte_w * I);
end generate;
end generate;
+
gen_no_reverse_tx_bytes : if not g_reverse_bytes generate
dp_latency_adapter_rx_snk_in_arr(stream).data(c_data_w - 1 downto 0) <= kernel_snk_in_arr(stream).data(c_data_w - 1 downto 0);
end generate;
@@ -300,8 +299,5 @@ begin
src_in => dp_src_in_arr(stream),
src_out => dp_src_out_arr(stream)
);
-
end generate;
-
end str;
-
diff --git a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
index 92e3b7e45f07d01aaae080be987077f3295cd635..be705c1148968cb8f78a3d0045ceaec9f8fe07a8 100644
--- a/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_10GbE/ta2_unb2b_10GbE.vhd
@@ -91,9 +91,7 @@ entity ta2_unb2b_10GbE is
);
end ta2_unb2b_10GbE;
-
architecture str of ta2_unb2b_10GbE is
-
constant c_sim : boolean := false;
constant c_tx_fifo_fill : natural := 1125; -- Largest frame is 9000 bytes = 1125
@@ -133,9 +131,7 @@ architecture str of ta2_unb2b_10GbE is
signal dp_xonoff_src_out_arr : t_dp_sosi_arr(g_nof_mac - 1 downto 0);
signal dp_xonoff_src_in_arr : t_dp_siso_arr(g_nof_mac - 1 downto 0);
-
begin
-
--------
-- PLL
--------
@@ -177,7 +173,6 @@ begin
tr_ref_clk_156 => tr_ref_clk_156,
tr_ref_rst_156 => tr_ref_rst_156,
-
-- Output clocks
-- . Reference
eth_ref_clk_644 => eth_ref_clk_644,
@@ -206,6 +201,7 @@ begin
gen_err_in: if g_use_err generate
dp_latency_adapter_tx_snk_in_arr(mac).err(g_err_w - 1 downto 0) <= snk_in_arr(mac).data(71 + g_err_w downto 72);
end generate;
+
dp_latency_adapter_tx_snk_in_arr(mac).sop <= snk_in_arr(mac).data(64);
dp_latency_adapter_tx_snk_in_arr(mac).eop <= snk_in_arr(mac).data(65);
dp_latency_adapter_tx_snk_in_arr(mac).empty(2 downto 0) <= snk_in_arr(mac).data(71 downto 69);
@@ -232,7 +228,6 @@ begin
src_in => dp_latency_adapter_tx_src_in_arr(mac)
);
-
-----------------------------------------------------------------------------
-- RX XON frame control
-----------------------------------------------------------------------------
@@ -329,6 +324,7 @@ begin
gen_err_out: if g_use_err generate
src_out_arr(mac).data(71 + g_err_w downto 72) <= dp_latency_adapter_rx_src_out_arr(mac).err(g_err_w - 1 downto 0);
end generate;
+
src_out_arr(mac).data(64) <= dp_latency_adapter_rx_src_out_arr(mac).sop;
src_out_arr(mac).data(65) <= dp_latency_adapter_rx_src_out_arr(mac).eop;
src_out_arr(mac).data(71 downto 69) <= dp_latency_adapter_rx_src_out_arr(mac).empty(2 downto 0);
@@ -372,7 +368,4 @@ begin
serial_tx_arr => tx_serial_r,
serial_rx_arr => rx_serial_r
);
-
-
end str;
-
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
index d1e8fe88dc60e36be1208cefc8aac44145fa1be9..cd1da9699604da0e661e12c8a19e9b5af176e786 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE.vhd
@@ -71,9 +71,7 @@ entity ta2_unb2b_1GbE is
);
end ta2_unb2b_1GbE;
-
architecture str of ta2_unb2b_1GbE is
-
constant c_sim : boolean := false;
constant c_empty_w : natural := 2;
constant c_tx_fifo_size : natural := 10; -- Can be small as flow control is enabled
@@ -93,9 +91,7 @@ architecture str of ta2_unb2b_1GbE is
signal dp_xonoff_src_out : t_dp_sosi;
signal dp_xonoff_src_in : t_dp_siso;
-
begin
-
-------------------------------------------------------
-- Mapping Data from OpenCL kernel to 1GbE Interface --
-------------------------------------------------------
@@ -135,7 +131,6 @@ begin
src_in => dp_latency_adapter_tx_src_in
);
-
-----------------------------------------------------------------------------
-- TX XON frame control
-----------------------------------------------------------------------------
@@ -224,7 +219,6 @@ begin
src_in => dp_latency_adapter_rx_src_in
);
-
----------------------------------------------------------------------------
-- Data mapping
----------------------------------------------------------------------------
@@ -238,11 +232,7 @@ begin
src_out.data(33) <= dp_latency_adapter_rx_src_out.eop;
src_out.data(39 downto 38) <= dp_latency_adapter_rx_src_out.empty(1 downto 0);
-
src_out.valid <= dp_latency_adapter_rx_src_out.valid;
dp_latency_adapter_rx_src_in.ready <= src_in.ready;
dp_latency_adapter_rx_src_in.xon <= '1';
-
-
end str;
-
diff --git a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
index 0f59d6bcbbb7ae5a79a8b20493bd45cd0fb1ad4e..1083a6bc1589f0b8464b7266b90955fc2250ec08 100644
--- a/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_1GbE/ta2_unb2b_1GbE_ip_wrapper.vhd
@@ -61,7 +61,6 @@ entity ta2_unb2b_1GbE_ip_wrapper is
);
end ta2_unb2b_1GbE_ip_wrapper;
-
architecture str of ta2_unb2b_1GbE_ip_wrapper is
----------------------------------------------------------------------------
-- ta2_unb2b_1GbE Component
@@ -100,9 +99,7 @@ architecture str of ta2_unb2b_1GbE_ip_wrapper is
kernel_snk_ready : out std_logic -- Flow control towards kernel
);
end component ta2_unb2b_1GbE;
-
begin
-
u_ta2_unb2b_1GbE : ta2_unb2b_1GbE
port map (
st_clk => st_clk,
@@ -133,5 +130,4 @@ begin
kernel_snk_valid => kernel_snk_valid,
kernel_snk_ready => kernel_snk_ready
);
-
end str;
diff --git a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
index 2fce7e9a33e05637aa8ee742ad159174761e059f..44b951b237f233c191c40d984a4b9a66e3091ff4 100644
--- a/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
+++ b/applications/ta2/ip/ta2_unb2b_40GbE/ta2_unb2b_40GbE.vhd
@@ -79,15 +79,12 @@ entity ta2_unb2b_40GbE is
);
end ta2_unb2b_40GbE;
-
architecture str of ta2_unb2b_40GbE is
-
constant c_max_packet_size : natural := 128; -- 128 * 256 bits words
constant c_tx_fifo_fill : natural := 282; -- Largest frame is 9000 bytes = 1125
constant c_tx_fifo_size : natural := 512;
constant c_rx_fifo_size : natural := 64; -- should be large enough
-
constant c_data_w : natural := 256;
----------------------------------------------------------------------------
-- Reset signals
@@ -268,11 +265,7 @@ architecture str of ta2_unb2b_40GbE is
tx_inc_sizeok_fcserr : out std_logic_vector(0 downto 0) -- tx_inc_sizeok_fcserr
);
end component arria10_40g_mac;
-
-
-
begin
-
gen_mac: for mac in 0 to g_nof_mac - 1 generate
----------------------------------------------------------------------------
-- Data mapping
@@ -487,7 +480,6 @@ begin
rx_serial => rx_serial_r(4 * (mac + 1) - 1 downto 4 * mac)
);
-
-- No latency adapter needed as the RX MAC does not have a ready input
----------------------------------------------------------------------------
-- RX FIFO
@@ -518,7 +510,6 @@ begin
src_in => dp_fifo_dc_src_in_arr(mac)
);
-
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (dp_fifo_dc) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
@@ -569,7 +560,6 @@ begin
out_rst => rst_txmac_arr(mac)
);
-
-------------------------------------------------------------------------------
-- PLL for clock generation, every mac needs its own, due to clock nework limitations
-------------------------------------------------------------------------------
@@ -587,7 +577,4 @@ begin
end generate;
end generate;
-
-
end str;
-
diff --git a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
index 5f484fa67536192238fd5fde23e08019a2c3c8ae..4e29874e8d21f7e36ed70ea57ab2fdc582c7b927 100644
--- a/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
+++ b/applications/ta2/ip/ta2_unb2b_ddr/ta2_unb2b_ddr.vhd
@@ -72,7 +72,6 @@ entity ta2_unb2b_ddr is
mem1_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable
mem1_debugaccess : in std_logic := 'X'; -- debugacce
-
mb_I_ref_clk : in std_logic := '0';
mb_I_ref_rst : in std_logic := '1';
@@ -91,9 +90,7 @@ entity ta2_unb2b_ddr is
);
end ta2_unb2b_ddr;
-
architecture str of ta2_unb2b_ddr is
-
constant c_gigabytes_MB_I : natural := func_tech_ddr_module_size(g_ddr_MB_I);
constant c_mb_I_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_ddr_MB_I);
constant c_mb_I_ctlr_data_w : natural := 576; -- func_tech_ddr_ctlr_data_w(g_ddr_MB_I);
@@ -104,7 +101,6 @@ architecture str of ta2_unb2b_ddr is
constant c_mb_II_ctlr_data_w : natural := 576; -- func_tech_ddr_ctlr_data_w(g_ddr_MB_II);
constant c_mb_II_ctlr_byteenable_w : natural := 72;
-
constant c_data_w : natural := 512;
constant c_symbol_w : natural := 8;
constant c_addr_w : natural := 33;
@@ -158,7 +154,6 @@ architecture str of ta2_unb2b_ddr is
signal mb_I_amm_byteenable_0 : std_logic_vector(c_mb_I_ctlr_byteenable_w - 1 downto 0) := (others => '0');
signal mb_I_amm_readdatavalid_0 : std_logic;
-
-- Memory Bank II signals
signal mb_II_ref_rst_n : std_logic;
signal mb_II_emif_usr_clk : std_logic;
@@ -273,12 +268,8 @@ architecture str of ta2_unb2b_ddr is
s0_reset : in std_logic := 'X' -- reset
);
end component ta2_unb2b_ddr_clock_cross;
-
-
begin
-
gen_MB_I : if g_use_MB_I generate
-
u_mb_I_clock_cross : ta2_unb2b_ddr_clock_cross
generic map (
DATA_WIDTH => c_data_w,
@@ -367,7 +358,6 @@ begin
mb_I_ref_rst_n <= not mb_I_ref_rst;
gen_I_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_I.name = "DDR4" and c_gigabytes_MB_I = 8 and g_ddr_MB_I.mts = 1600 generate
-
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
port map (
amm_ready_0 => mb_I_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -403,14 +393,11 @@ begin
local_cal_success => OPEN, -- status_conduit_end.local_cal_success
local_cal_fail => open -- .local_cal_fail
);
-
end generate;
end generate;
-
gen_MB_II : if g_use_MB_II generate
-
u_mb_II_clock_cross : ta2_unb2b_ddr_clock_cross
generic map (
DATA_WIDTH => c_data_w,
@@ -499,7 +486,6 @@ begin
mb_II_ref_rst_n <= not mb_II_ref_rst;
gen_II_ip_arria10_e1sg_ddr4_8g_1600 : if g_ddr_MB_II.name = "DDR4" and c_gigabytes_MB_II = 8 and g_ddr_MB_II.mts = 1600 generate
-
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
port map (
amm_ready_0 => mb_II_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -535,13 +521,7 @@ begin
local_cal_success => OPEN, -- status_conduit_end.local_cal_success
local_cal_fail => open -- .local_cal_fail
);
-
end generate;
end generate;
-
-
-
-
end str;
-
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
index 0948a6c745bac6618ad40d53df16bef6d8cfc217..c5d1073de0edb6f9d4e164f6c0f7834f51b5a02d 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b.vhd
@@ -77,9 +77,7 @@ entity ta2_unb2b_jesd204b is
);
end ta2_unb2b_jesd204b;
-
architecture str of ta2_unb2b_jesd204b is
-
constant c_sim : boolean := false;
constant c_nof_streams_jesd204b : natural := 12;
@@ -101,9 +99,7 @@ architecture str of ta2_unb2b_jesd204b is
signal i_jesd204b_sync_n_arr : std_logic_vector(c_nof_streams_jesd204b - 1 downto 0);
signal jesd204b_serial_rx_arr : std_logic_vector(c_nof_streams_jesd204b - 1 downto 0) := (others => '0');
signal jesd204b_disable_arr : std_logic_vector(c_nof_streams_jesd204b - 1 downto 0);
-
begin
-
jesd204b_sync_n_arr <= i_jesd204b_sync_n_arr(g_nof_streams - 1 downto 0);
jesd204b_serial_rx_arr(g_nof_streams - 1 downto 0) <= serial_rx_arr;
jesd204b_disable_arr <= (others => '0');
@@ -168,7 +164,6 @@ begin
src_out => dp_fifo_dc_rx_src_out_arr(stream)
);
-
----------------------------------------------------------------------------
-- Latency adapter: adapt RL=1 (Upstream) to RL=0 (OpenCL kernel).
----------------------------------------------------------------------------
@@ -188,7 +183,6 @@ begin
src_in => dp_latency_adapter_rx_src_in_arr(stream)
);
-
----------------------------------------------------------------------------
-- Data mapping
----------------------------------------------------------------------------
@@ -204,4 +198,3 @@ begin
end generate;
end str;
-
diff --git a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
index 13f12f68205cad06a7fd32f1b46794dfd9ddf778..102c3f0ec1dcab780df235063bfcf51bbc7a36f8 100644
--- a/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
+++ b/applications/ta2/ip/ta2_unb2b_jesd204b/ta2_unb2b_jesd204b_ip_wrapper.vhd
@@ -56,7 +56,6 @@ entity ta2_unb2b_jesd204b_ip_wrapper is
);
end ta2_unb2b_jesd204b_ip_wrapper;
-
architecture str of ta2_unb2b_jesd204b_ip_wrapper is
----------------------------------------------------------------------------
-- ta2_unb2b_ Component
@@ -90,11 +89,7 @@ architecture str of ta2_unb2b_jesd204b_ip_wrapper is
);
end component ta2_unb2b_jesd204b;
-
-
-
begin
-
u_ta2_unb2b_jesd204b : ta2_unb2b_jesd204b
port map (
config_clk => config_clk,
@@ -115,6 +110,4 @@ begin
kernel_src_valid => kernel_src_valid,
kernel_src_ready => kernel_src_ready
);
-
end str;
-
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
index cd59a76a8888256379d5bd073339802b6a2e07c2..f73837193b44a6a43ee128f28d0b03de0a8b2ff2 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/ta2_unb2b_mm_io.vhd
@@ -92,7 +92,6 @@ entity ta2_unb2b_mm_io is
);
end ta2_unb2b_mm_io;
-
architecture str of ta2_unb2b_mm_io is
constant c_fifo_size : natural := 8;
constant c_wr_data_w : natural := 72;
@@ -121,7 +120,6 @@ architecture str of ta2_unb2b_mm_io is
signal reg_b : std_logic_vector(31 downto 0) := (others => '0');
signal reg_c : std_logic_vector(31 downto 0) := (others => '0');
signal reg_d : std_logic_vector(31 downto 0) := (others => '0');
-
begin
-- Connect MM <-> DP
wr_sosi.data(31 downto 0) <= mm_mosi.wrdata(31 downto 0);
@@ -171,7 +169,6 @@ begin
src_out => out_sosi
);
-
u_dp_fifo_dc_rd : entity dp_lib.dp_fifo_dc
generic map (
g_technology => c_tech_arria10_e1sg,
@@ -259,6 +256,4 @@ gen_opencl : if g_use_opencl generate
in_sosi <= snk_in;
end generate;
-
end str;
-
diff --git a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
index 17aa38a00bb1f808dce00aa50bb975265ce97ff0..262dbfdd93d69f7675bdc385c283003192bdcf92 100644
--- a/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
+++ b/applications/ta2/ip/ta2_unb2b_mm_io/tb_ta2_unb2b_mm_io.vhd
@@ -40,7 +40,6 @@ use dp_lib.tb_dp_pkg.all;
entity tb_ta2_unb2b_mm_io is
end tb_ta2_unb2b_mm_io;
-
architecture tb of tb_ta2_unb2b_mm_io is
constant c_data_value : natural := 10;
@@ -62,9 +61,7 @@ architecture tb of tb_ta2_unb2b_mm_io is
signal mm_miso : t_mem_miso := c_mem_miso_rst;
signal busy : boolean := false;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -98,7 +95,6 @@ begin
src_out => out_sosi
);
-
p_stim_mm : process
begin
wait until rst = '0';
@@ -172,8 +168,4 @@ begin
end if;
end if;
end process;
-
-
-
end tb;
-
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
index c886d0d6564d552238f88848504a899181b7ca23..e669d24a75b5631580f001a171f9755e4784b363 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/node_unb1_bn_capture.vhd
@@ -143,7 +143,6 @@ entity node_unb1_bn_capture is
end node_unb1_bn_capture;
architecture str of node_unb1_bn_capture is
-
-- Streaming ctrl path
constant c_dp_factor : natural := g_ai.rx_factor * g_ai.dd_factor;
constant c_wideband_factor : natural := c_dp_factor; -- = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
@@ -166,9 +165,7 @@ architecture str of node_unb1_bn_capture is
signal dp_bsn_trigger_sp_on : std_logic;
signal dp_bsn_trigger_sp_off : std_logic;
signal sp_flush_en : std_logic;
-
begin
-
-----------------------------------------------------------------------------
-- Node function
--
@@ -252,7 +249,6 @@ begin
sp_siso_arr => sp_siso_arr
);
-
------------------------------------------------------------------------------
-- 2a) I2C control for ADU AB
------------------------------------------------------------------------------
@@ -396,5 +392,4 @@ begin
snk_in => i_sp_sosi_arr(0), -- only uses eop (= block sync), bsn[]
trigger_out => dp_bsn_trigger_sp_off
);
-
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
index 00201416984df5014d90d65a64f10117be66e388..39f0e51e1884df2cdb6217cc4ab4c3e7354038a8 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture.vhd
@@ -85,9 +85,7 @@ entity unb1_bn_capture is
);
end unb1_bn_capture;
-
architecture str of unb1_bn_capture is
-
constant c_fw_version : t_unb1_board_fw_version := (1, 12); -- firmware version x.y
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 0, 0, 1, 1);
constant c_dp_clk_use_pll : boolean := true;
@@ -188,10 +186,7 @@ architecture str of unb1_bn_capture is
signal reg_bsn_scheduler_sp_on_miso : t_mem_miso;
signal reg_bsn_scheduler_sp_off_mosi : t_mem_mosi;
signal reg_bsn_scheduler_sp_off_miso : t_mem_miso;
-
-
begin
-
-----------------------------------------------------------------------------
-- SOPC system
-----------------------------------------------------------------------------
@@ -650,7 +645,6 @@ begin
ETH_SGOUT => ETH_SGOUT
);
-
-----------------------------------------------------------------------------
-- Specific node function
-----------------------------------------------------------------------------
@@ -741,6 +735,4 @@ begin
ADC_CD_SCL => ADC_CD_SCL, -- I2C CD
ADC_CD_SDA => ADC_CD_SDA
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
index 922af3e858862e706f720002ff7d89a36c717649..79c2b1400580a02c5830e985980641183a1f83f2 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_input.vhd
@@ -21,7 +21,6 @@
-- Purpose: Capture input from two ADU or use WG data and attach timestamp.
-
library IEEE, common_lib, unb1_board_lib, dp_lib, diag_lib, ppsh_lib, aduh_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -103,9 +102,7 @@ entity unb1_bn_capture_input is
);
end unb1_bn_capture_input;
-
architecture str of unb1_bn_capture_input is
-
constant c_dp_factor : natural := g_ai.rx_factor * g_ai.dd_factor;
constant c_wideband_factor : natural := c_dp_factor; -- Wideband rate factor = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
@@ -136,9 +133,7 @@ architecture str of unb1_bn_capture_input is
signal dp_shiftram_src_out_timestamped_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
signal nxt_dp_shiftram_src_out_timestamped_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1);
-
begin
-
-----------------------------------------------------------------------------
-- Input samples from ADUH or WG
-----------------------------------------------------------------------------
@@ -428,5 +423,4 @@ begin
DCLK => dp_clk,
sp_sosi_arr => dp_shiftram_src_out_timestamped_arr
);
-
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
index b8dd6fbcd43570b9f4653be2f853800f8c096927..c6706e2421ec5038f0025dda055ce0ad451a2c4a 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_mux.vhd
@@ -51,14 +51,11 @@ entity bn_capture_mux is
);
end bn_capture_mux;
-
architecture str of bn_capture_mux is
-
signal wide_siso_arr : t_dp_siso_arr(0 to g_nof_input - 1);
signal wide_sosi_arr : t_dp_sosi_arr(0 to g_nof_input - 1); -- = [0:3] = Signal Paths [A,B,C,D]
-- and e.g. A[255:0] = [A(t0), A(t1), ..., A(t31)], so 4*8=32 800M samples in time per one 256b word
begin
-
gen_fifo : for I in 0 to g_nof_input - 1 generate
u_n2w : entity dp_lib.dp_fifo_dc_mixed_widths
generic map (
@@ -111,6 +108,4 @@ begin
src_in => mux_wide_siso,
src_out => mux_wide_sosi
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
index 1534c16a81201c77196d4e5eef7a448c48ede018..ced8c5739b7c1d50b097614e358faaf035293607 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use unb1_board_lib.unb1_board_pkg.all;
package unb1_bn_capture_pkg is
-
-- Signal path input
type t_c_bn_capture_sp is record
sample_freq : natural; -- = 800; -- The ADC sample rate is 800 Msps, so the LVDS rate is 800 Mbps per ADC BI data line,
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
index 6c014a6fe2e02822c8693e48d4997b3d6456724e..97a864cc1cca127daca023931905f7daa081c719 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage.vhd
@@ -72,9 +72,7 @@ entity bn_capture_storage is
);
end bn_capture_storage;
-
architecture str of bn_capture_storage is
-
constant c_wr_fifo_depth : natural := 128;
constant c_rd_fifo_depth : natural := 2048;
@@ -107,9 +105,7 @@ architecture str of bn_capture_storage is
signal state : t_state;
signal nxt_state : t_state;
-
begin
-
phy_clk <= i_phy_clk;
phy_rst <= i_phy_rst;
@@ -203,7 +199,6 @@ begin
end case;
end process;
-
u_dp_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
generic map(
g_fifo_size => c_rd_fifo_depth
@@ -252,6 +247,4 @@ begin
mm_rd_usedw => mm_rd_usedw
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
index 756ce1b7f7ae17c7bfe5d38cfe62c50a476fb539..ded28ec91ca04a869ec6d7e2dbe80d9210eced4b 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/src/vhdl/unb1_bn_capture_storage_reg.vhd
@@ -56,9 +56,7 @@ entity bn_capture_storage_reg is
);
end bn_capture_storage_reg;
-
architecture rtl of bn_capture_storage_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(8),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
@@ -77,9 +75,7 @@ architecture rtl of bn_capture_storage_reg is
signal mm_done : std_logic;
signal mm_init_done : std_logic;
signal mm_ctlr_rdy : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -255,7 +251,4 @@ begin
out_dat => st_start_address,
out_new => open
);
-
-
end rtl;
-
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
index 87e60073de766f0a55b6532b91918c3730df5f45..6c96281275b7a849cd9deb61c52e1a746606a05e 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_node_unb1_bn_capture.vhd
@@ -39,7 +39,6 @@
-- The tb_end depends on reg stimuli done and I2C stimuli done so that
-- proves that the tb has run.
-
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib, aduh_lib, i2c_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -76,7 +75,6 @@ entity tb_node_unb1_bn_capture is
end tb_node_unb1_bn_capture;
architecture tb of tb_node_unb1_bn_capture is
-
-- UniBoard
constant c_sim : boolean := true;
constant c_version : std_logic_vector(1 downto 0) := "00";
@@ -88,7 +86,6 @@ architecture tb of tb_node_unb1_bn_capture is
c_unb1_board_ext_clk_freq_200M,
c_bn_capture_sp_sim);
-
constant c_eth_clk_period : time := 40 ns; -- 25 MHz XO on UniBoard
constant c_mm_clk_period : time := 20 ns; -- 50 MHz MM clock, altpll in SOPC will make this from the ETH 25 MHz XO clock
@@ -208,9 +205,7 @@ architecture tb of tb_node_unb1_bn_capture is
signal reg_bsn_scheduler_sp_on_miso : t_mem_miso;
signal reg_bsn_scheduler_sp_off_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_bsn_scheduler_sp_off_miso : t_mem_miso;
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -237,7 +232,6 @@ begin
pin_pps_toggle <= pin_pps(31);
pin_pps_capture_cnt <= pin_pps(pin_pps_capture_cnt'length - 1 downto 0);
-
----------------------------------------------------------------------------
-- Stimuli for MM reg_input slave port
----------------------------------------------------------------------------
@@ -518,7 +512,6 @@ begin
ADC_CD_SDA => ADC_CD_SDA
);
-
-----------------------------------------------------------------------------
-- ADU0 model and ADU1 model for BN port A,B and C,D
-----------------------------------------------------------------------------
@@ -572,5 +565,4 @@ begin
------------------------------------------------------------------------------
eth_rxp <= transport eth_txp after c_cable_delay;
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
index 2c11bf9501b83d55bc1869b31162e30a9d3e8eae..1cf7b5d6fb00cd64f696b1d5682bb1bcfb73bf9b 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture.vhd
@@ -34,7 +34,6 @@
-- . NIOS SW : /apps/bn_capture_ddr3/main.c
-- . Set g_use_phy = (0, 0, 0, 0, 1, 0, 1, 0)
-
library IEEE, common_lib, dp_lib, i2c_lib, unb1_board_lib, diag_lib, aduh_lib, ddr3_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -51,7 +50,6 @@ use unb1_board_lib.unb1_board_pkg.all;
use ddr3_lib.ddr3_pkg.all;
use i2c_lib.i2c_dev_unb_pkg.all;
-
entity tb_bn_capture is
generic (
-- TYPE t_c_unb_use_phy IS RECORD
@@ -69,7 +67,6 @@ entity tb_bn_capture is
end tb_bn_capture;
architecture tb of tb_bn_capture is
-
-- UniBoard
constant c_sim : boolean := true;
constant c_version : std_logic_vector(1 downto 0) := "00";
@@ -156,9 +153,7 @@ architecture tb of tb_bn_capture is
signal VERSION : std_logic_vector(c_unb_aux.version_w - 1 downto 0);
signal ID : std_logic_vector(c_unb_aux.id_w - 1 downto 0);
signal TESTIO : std_logic_vector(c_unb_aux.testio_w - 1 downto 0);
-
begin
-
-- Run 1 ms
----------------------------------------------------------------------------
@@ -257,7 +252,6 @@ begin
ADC_CD_SDA => ADC_CD_SDA
);
-
-----------------------------------------------------------------------------
-- ADU0 model and ADU1 model for BN port A,B and C,D
-----------------------------------------------------------------------------
@@ -309,10 +303,8 @@ begin
test_pattern_en => test_pattern_en
);
-
------------------------------------------------------------------------------
-- 1GbE Loopback model
------------------------------------------------------------------------------
eth_rxp <= transport eth_txp after c_cable_delay;
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
index a2a8d46e4733551fe19ec002538665fecfebc7f6..3c4226b3cc4c4723d29f664c07f4f5ac68d708a4 100644
--- a/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
+++ b/boards/uniboard1/designs/unb1_bn_capture/tb/vhdl/tb_unb1_bn_capture_input.vhd
@@ -67,7 +67,6 @@ entity tb_unb1_bn_capture_input is
end tb_unb1_bn_capture_input;
architecture tb of tb_unb1_bn_capture_input is
-
constant c_sim : boolean := true;
constant c_bn_capture_sp_sim : t_c_bn_capture_sp := (800, 1024, 48 * 1024, 4 * 1024, true); -- 800 MSps, block size 1024 samples, 48 blocks per sync interval, monitor buffer 4096 samples using sync
@@ -190,9 +189,7 @@ architecture tb of tb_unb1_bn_capture_input is
-- Signal paths
signal sp_sosi_arr : t_dp_sosi_arr(0 to c_ai.nof_sp - 1); -- = [0:3] = Signal Paths [A,B,C,D]
signal sp_siso_arr : t_dp_siso_arr(0 to c_ai.nof_sp - 1);
-
begin
-
gen_rdy : for I in 0 to c_ai.nof_sp - 1 generate
sp_siso_arr(I) <= c_dp_siso_rdy;
end generate;
@@ -368,7 +365,6 @@ begin
proc_mem_mm_bus_wr(0, v_bsn, mm_clk, reg_bsn_scheduler_wg_mosi);
proc_mem_mm_bus_wr(1, 0, mm_clk, reg_bsn_scheduler_wg_mosi); -- assume v_bsn < 2**31-1
-
-- Continue forever with WG data and keep reading the current BSN
while true loop
-- Read current BSN
@@ -404,8 +400,6 @@ begin
wait;
end process;
-
-
----------------------------------------------------------------------------
-- Stimuli for MM RAM WG slave port
----------------------------------------------------------------------------
@@ -503,7 +497,6 @@ begin
end if;
end process;
-
-----------------------------------------------------------------------------
-- ADU0 and ADU1 for BN port A,B and C,D
-----------------------------------------------------------------------------
@@ -610,5 +603,4 @@ begin
------------------------------------------------------------------------------
-- View sp_sosi_arr in Wave Window with aduh_quad_scope in unb1_bn_capture_input
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
index 6835c5e073e187a9ce80f2aae7d08e7c113931c6..f1ac60af9ffc42bc825a84959c8143f0e40f447b 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/node_unb1_bn_terminal_bg.vhd
@@ -104,7 +104,6 @@ entity node_unb1_bn_terminal_bg is
end node_unb1_bn_terminal_bg;
architecture str of node_unb1_bn_terminal_bg is
-
-- Terminals
constant c_mesh_usr_nof_input : natural := g_usr_nof_streams / c_unb1_board_nof_fn; -- 16 / 4 = 4
@@ -128,9 +127,7 @@ architecture str of node_unb1_bn_terminal_bg is
signal back_rx_usr_siso_2arr : t_unb1_board_back_siso_2arr;
signal back_rx_usr_sosi_2arr : t_unb1_board_back_sosi_2arr;
-
begin
-
-----------------------------------------------------------------------------
-- Block generator
-----------------------------------------------------------------------------
@@ -249,14 +246,12 @@ begin
-----------------------------------------------------------------------------
mesh_tx_usr_sosi_2arr <= func_unb1_board_transpose_2arr(back_rx_usr_sosi_2arr);
back_rx_usr_siso_2arr <= func_unb1_board_transpose_2arr(mesh_tx_usr_siso_2arr);
-
end generate;
-----------------------------------------------------------------------------
-- Mesh terminals
-----------------------------------------------------------------------------
gen_mesh: if g_use_mesh = true generate
-
u_terminals_mesh : entity unb1_board_lib.unb1_board_terminals_mesh
generic map (
g_sim => g_sim,
@@ -315,7 +310,6 @@ begin
ram_diag_data_buf_mosi => ram_mesh_diag_data_buf_mosi,
ram_diag_data_buf_miso => ram_mesh_diag_data_buf_miso
);
-
end generate;
end str;
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
index 295d507e437b5120f807a003b81ebdd6cb652bf6..a5254c63ff944c2e7aa6b0f5e8f60ce9605a1a86 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/src/vhdl/unb1_bn_terminal_bg.vhd
@@ -84,9 +84,7 @@ entity unb1_bn_terminal_bg is
);
end unb1_bn_terminal_bg;
-
architecture str of unb1_bn_terminal_bg is
-
constant c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
-- Use PHY Interface
-- TYPE t_c_unb_use_phy IS RECORD
@@ -201,9 +199,7 @@ architecture str of unb1_bn_terminal_bg is
-- STREAM
signal in_sosi_arr : t_dp_sosi_arr(c_usr_nof_streams - 1 downto 0);
signal in_siso_arr : t_dp_siso_arr(c_usr_nof_streams - 1 downto 0) := (others => c_dp_siso_rst);
-
begin
-
-----------------------------------------------------------------------------
-- SOPC system
-----------------------------------------------------------------------------
@@ -436,8 +432,6 @@ begin
ETH_SGOUT => ETH_SGOUT
);
-
-
-----------------------------------------------------------------------------
-- Design function
-----------------------------------------------------------------------------
@@ -510,7 +504,6 @@ begin
back_rx_serial_2arr => back_rx_serial_2arr
);
-
-----------------------------------------------------------------------------
-- Wires
-----------------------------------------------------------------------------
@@ -559,17 +552,4 @@ begin
);
end generate;
-
end;
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
index 7dc0e2687252b159a55d80a3fcaed4544de4ddef..65c1746710ca576d7336ad7f67c21868b6746d2e 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_node_unb1_bn_terminal_bg.vhd
@@ -88,7 +88,6 @@ entity tb_node_unb1_bn_terminal_bg is
end tb_node_unb1_bn_terminal_bg;
architecture tb of tb_node_unb1_bn_terminal_bg is
-
constant c_sim : boolean := true;
constant c_bg_data_file_dat : string := g_bg_data_file_name & ".dat";
@@ -114,7 +113,6 @@ architecture tb of tb_node_unb1_bn_terminal_bg is
constant c_bsn_init_lo : natural := 32; -- 16#76543210#;
constant c_bg_buf_adr_w : natural := ceil_log2(c_nof_samples_in_packet);
-
-- TRNB diagnostics
constant c_nof_gx : natural := g_mesh_nof_serial * c_unb1_board_nof_node; -- = 12 = 3 * 4
constant c_nof_gx_mask : natural := 2**c_nof_gx - 1;
@@ -150,9 +148,7 @@ architecture tb of tb_node_unb1_bn_terminal_bg is
signal in_siso_arr : t_dp_siso_arr(g_bf.nof_input_streams - 1 downto 0);
signal init_waveforms_done : std_logic;
-
begin
-
tb_clk <= dp_clk;
tb_end <= i_tb_end;
@@ -172,7 +168,6 @@ begin
init_waveforms_done <= '1';
-
----------------------------------------------------------------------------
-- Stimuli for BF input streams
----------------------------------------------------------------------------
@@ -351,7 +346,4 @@ begin
back_tx_serial_2arr => back_tx_serial_2arr,
back_rx_serial_2arr => back_rx_serial_2arr
);
-
end tb;
-
-
diff --git a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
index 5c5218d8424c3cfbf3a1f2161e3b406e822517ec..b521c00a23e2e0e0dbfa5383d9f9316d6aa5322c 100644
--- a/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
+++ b/boards/uniboard1/designs/unb1_bn_terminal_bg/tb/vhdl/tb_tb_node_unb1_bn_terminal_bg.vhd
@@ -31,7 +31,6 @@
-- > run -all
-- Observe in Wave window that rx_usr_sosi_2arr is delayed tx_usr_sosi_2arr
-
library IEEE, common_lib, dp_lib, bf_lib, unb_common_lib;
use IEEE.std_logic_1164.all;
use dp_lib.dp_stream_pkg.all;
@@ -48,7 +47,6 @@ entity tb_tb_node_bn_terminal_bg is
end tb_tb_node_bn_terminal_bg;
architecture tb of tb_tb_node_bn_terminal_bg is
-
constant c_dp_pps_period : natural := 1024; -- sufficiently long for all nodes to have initialized their TR PHY
constant c_mesh_nof_serial : natural := 3; -- need at least 3 to support the 4 input streams from the BG, use 4 to have transparant dp_distibute
@@ -63,9 +61,7 @@ architecture tb of tb_tb_node_bn_terminal_bg is
signal mesh_tx_serial_2arr : t_unb_mesh_sl_2arr;
signal mesh_rx_serial_2arr : t_unb_mesh_sl_2arr;
-
begin
-
u_tb_node_bn_terminal_bg : entity work.tb_node_bn_terminal_bg
generic map (
-- Tb
@@ -104,20 +100,15 @@ begin
proc_common_gen_pulse(1, c_dp_pps_period, '1', tb_clk, dp_pps);
-
------------------------------------------------------------------------------
-- Transceivers loopback
------------------------------------------------------------------------------
mesh_rx_serial_2arr <= mesh_tx_serial_2arr;
-
------------------------------------------------------------------------------
-- Test bench end
------------------------------------------------------------------------------
assert not(NOW > 0 ps and tb_end = '1') report "Note: TB END" severity FAILURE; -- need to use FAILURE to stop the simulation, apparently resetting the tr_nonbonded is not enough
-
end tb;
-
-
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
index db070b1f801c281646cdc119b1eeede24bbf7ec5..45beb6d4fd0ed4fb8bb98b369acc4cd213d51c4c 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/mmm_unb1_ddr3.vhd
@@ -112,9 +112,7 @@ entity mmm_unb1_ddr3 is
);
end mmm_unb1_ddr3;
-
architecture str of mmm_unb1_ddr3 is
-
-- Actual MM address widths, the MM data width is fixed at the default c_word_w=32
constant c_mm_reg_io_ddr_addr_w : natural := 4;
constant c_mm_reg_diag_data_buf_addr_w : natural := 5;
@@ -152,9 +150,7 @@ architecture str of mmm_unb1_ddr3 is
signal eth1g_reg_proc_miso : t_mem_miso;
signal mm_bus_switch : std_logic;
-
begin
-
mm_clk <= i_mm_clk;
eth1g_tse_clk <= i_tse_clk;
cal_clk <= i_cal_clk;
@@ -163,7 +159,6 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
@@ -208,7 +203,6 @@ begin
u_mm_file_reg_diag_rx_seq : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_DIAG_RX_SEQ")
port map(mm_rst, i_mm_clk, reg_diag_rx_seq_mosi, reg_diag_rx_seq_miso );
-
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
@@ -242,7 +236,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
----------------------------------------------------------------------------
@@ -399,5 +392,3 @@ begin
);
end generate;
end str;
-
-
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
index aa082048a3a5a4c1d31a515b86cbc437e25725d4..4467803f06ffb303fe56e6f532d212f62415c01b 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/node_unb1_ddr3.vhd
@@ -87,9 +87,7 @@ entity node_unb1_ddr3 is
);
end node_unb1_ddr3;
-
architecture str of node_unb1_ddr3 is
-
constant c_wr_data_w : natural := g_st_dat_w;
constant c_rd_data_w : natural := g_st_dat_w;
constant c_data_w : natural := g_st_dat_w;
@@ -111,9 +109,7 @@ architecture str of node_unb1_ddr3 is
signal out_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0); -- Output SOSI that contains the waveform data
signal in_siso_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy); -- Default xon='1'
signal in_sosi_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
-
begin
-
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
generic map(
-- System
@@ -189,4 +185,3 @@ begin
reg_rx_seq_miso => reg_diag_rx_seq_miso
);
end str;
-
diff --git a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
index 0078bdb463b55b6d92d3e716567f76651a24cd0b..80af69d3f773ad7d65ac0ba8e4e2be97b3efcab4 100644
--- a/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/src/vhdl/unb1_ddr3.vhd
@@ -72,7 +72,6 @@ entity unb1_ddr3 is
end unb1_ddr3;
architecture str of unb1_ddr3 is
-
-- Constant definitions for ctrl_unb_common
constant c_design_name : string := "unb1_ddr3";
constant c_design_note : string := "DDR3 reference design";
@@ -170,10 +169,7 @@ architecture str of unb1_ddr3 is
signal reg_diag_rx_seq_mosi : t_mem_mosi;
signal reg_diag_rx_seq_miso : t_mem_miso;
-
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -417,5 +413,4 @@ begin
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU
);
-
end str;
diff --git a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
index 9bcdac9295a1dd8731d4200ac2ae5c5efe569351..55751e463fe336cd8e7c907f3eb39d0f8ab65e8f 100644
--- a/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3/tb/vhdl/tb_unb1_ddr3.vhd
@@ -46,7 +46,6 @@ use technology_lib.technology_select_pkg.all;
use dp_lib.dp_stream_pkg.all;
use diag_lib.diag_pkg.all;
-
entity tb_unb1_ddr3 is
generic (
g_design_name : string := "unb1_ddr3"
@@ -54,7 +53,6 @@ entity tb_unb1_ddr3 is
end tb_unb1_ddr3;
architecture tb of tb_unb1_ddr3 is
-
-- UniBoard
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -97,9 +95,7 @@ architecture tb of tb_unb1_ddr3 is
signal sens_scl : std_logic;
signal sens_sda : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -174,6 +170,4 @@ begin
mem3_io => MB_I_io,
mem3_ou => MB_I_in
);
-
end tb;
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
index 8027e6e0dd9c2b189205a4ccd32b78a01daccff6..f2880d95fff355bf58535b3d9a1d9652632edff7 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/tb_unb1_ddr3_reorder_dual_rank.vhd
@@ -37,7 +37,6 @@ entity tb_unb1_ddr3_reorder_dual_rank is
end tb_unb1_ddr3_reorder_dual_rank;
architecture tb of tb_unb1_ddr3_reorder_dual_rank is
-
begin
u_tb_revision : entity work.tb_unb1_ddr3_reorder
generic map(
@@ -47,5 +46,4 @@ begin
g_sim_node_nr => g_sim_node_nr,
g_tech_ddr => g_tech_ddr
);
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
index 0974f466bf4f43c8b8b24ba69efc819d249e9685..5622c88c07a81536c2dbca7c7e0000626c3627c6 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_dual_rank/unb1_ddr3_reorder_dual_rank.vhd
@@ -70,9 +70,7 @@ entity unb1_ddr3_reorder_dual_rank is
);
end unb1_ddr3_reorder_dual_rank;
-
architecture str of unb1_ddr3_reorder_dual_rank is
-
begin
u_revision : entity work.unb1_ddr3_reorder
generic map(
@@ -106,9 +104,4 @@ begin
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU
);
-
end str;
-
-
-
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
index e9092a7f9c79fedfe7fa5105d69ec7d60dd95cc2..01306cde2b28d4f27ece81f4888cd13afadf67e7 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/tb_unb1_ddr3_reorder_single_rank.vhd
@@ -37,7 +37,6 @@ entity tb_unb1_ddr3_reorder_single_rank is
end tb_unb1_ddr3_reorder_single_rank;
architecture tb of tb_unb1_ddr3_reorder_single_rank is
-
begin
u_tb_revision : entity work.tb_unb1_ddr3_reorder
generic map(
@@ -47,5 +46,4 @@ begin
g_sim_node_nr => g_sim_node_nr,
g_tech_ddr => g_tech_ddr
);
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
index 008e30d0176baf034a9d71c90caf88d5d24bbbef..5bd73002e062806ac18d0eb832e82573ea720246 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/revisions/unb1_ddr3_reorder_single_rank/unb1_ddr3_reorder_single_rank.vhd
@@ -70,9 +70,7 @@ entity unb1_ddr3_reorder_single_rank is
);
end unb1_ddr3_reorder_single_rank;
-
architecture str of unb1_ddr3_reorder_single_rank is
-
begin
u_revision : entity work.unb1_ddr3_reorder
generic map(
@@ -106,9 +104,4 @@ begin
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU
);
-
end str;
-
-
-
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
index e68a8ec5d07e9c2f9936bf7483cd425079736d2c..34532416bb3622692dba4d69c0881e639d640e6c 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/mmm_unb1_ddr3_reorder.vhd
@@ -122,9 +122,7 @@ entity mmm_unb1_ddr3_reorder is
);
end mmm_unb1_ddr3_reorder;
-
architecture str of mmm_unb1_ddr3_reorder is
-
constant c_ram_ss_ss_transp_adr_w : natural := 16;
constant c_reg_diag_bg_adr_w : natural := 3;
@@ -159,9 +157,7 @@ architecture str of mmm_unb1_ddr3_reorder is
signal eth1g_reg_proc_miso : t_mem_miso;
signal mm_bus_switch : std_logic;
-
begin
-
mm_clk <= i_mm_clk;
eth1g_tse_clk <= i_tse_clk;
cal_clk <= i_cal_clk;
@@ -170,7 +166,6 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
@@ -254,7 +249,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
----------------------------------------------------------------------------
@@ -426,8 +420,6 @@ begin
coe_write_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wr,
coe_writedata_export_from_the_reg_bsn_monitor => reg_bsn_monitor_mosi.wrdata(c_word_w - 1 downto 0)
);
-
end generate;
end str;
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
index 2e3956bcd09f95b01c7212ff1295feea7cd5190c..2af884041ac29abf351f5c7214a288db05772a54 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/node_unb1_ddr3_reorder.vhd
@@ -101,9 +101,7 @@ port (
);
end node_unb1_ddr3_reorder;
-
architecture str of node_unb1_ddr3_reorder is
-
constant g_tech_select_default : natural := c_tech_select_default;
constant c_cross_domain_dvr_ctlr : boolean := true;
@@ -139,9 +137,7 @@ architecture str of node_unb1_ddr3_reorder is
signal db_siso_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
signal bsn_sosi_arr : t_dp_sosi_arr(3 downto 0) := (others => c_dp_sosi_rst);
-
begin
-
u_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
g_nof_streams => c_nof_bsn_streams, -- Check one input and one output stream
@@ -353,6 +349,4 @@ begin
-- ST interface
in_sosi_arr => db_sosi_arr
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
index 07190743fb2fb32ad211ca3531709e6ce8455465..a0f4448402a1c0f8d47f6c28dde9d61eeb5aca0d 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/src/vhdl/unb1_ddr3_reorder.vhd
@@ -77,9 +77,7 @@ entity unb1_ddr3_reorder is
);
end unb1_ddr3_reorder;
-
architecture str of unb1_ddr3_reorder is
-
-- Constant definitions for ctrl_unb_common
constant c_fw_version : t_unb1_board_fw_version := (0, 14);
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 1, 0, 0, 1);
@@ -189,9 +187,7 @@ architecture str of unb1_ddr3_reorder is
-- RX Sequencer
signal reg_diag_rx_seq_mosi : t_mem_mosi;
signal reg_diag_rx_seq_miso : t_mem_miso;
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -454,7 +450,4 @@ begin
MB_I_io => MB_I_IO,
MB_I_ou => MB_I_OU
);
-
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
index 89a57d08b452e0a6f906c92d4c8d33f862a896de..013700e86659870ff590f0e9f647e4980b63fb64 100644
--- a/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_reorder/tb/vhdl/tb_unb1_ddr3_reorder.vhd
@@ -53,7 +53,6 @@ entity tb_unb1_ddr3_reorder is
end tb_unb1_ddr3_reorder;
architecture tb of tb_unb1_ddr3_reorder is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -106,9 +105,7 @@ architecture tb of tb_unb1_ddr3_reorder is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -220,5 +217,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
index 7d0c3aabe121c5832e0b239a6d587388e59dd045..6687a715a0fd68ff9c0a2484c21174f5fc74d032 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/mmm_unb1_ddr3_transpose.vhd
@@ -31,7 +31,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use ddr3_lib.ddr3_pkg.all;
-
entity mmm_unb_ddr3_transpose is
generic (
g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
@@ -111,7 +110,6 @@ entity mmm_unb_ddr3_transpose is
end mmm_unb_ddr3_transpose;
architecture str of mmm_unb_ddr3_transpose is
-
constant c_stimuli_length : positive := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize * g_ddr3_seq.rd_chunksize;
constant c_reg_diag_bg_adr_w : natural := 3;
constant c_ram_diag_bg_adr_w : positive := ceil_log2(g_nof_streams * c_stimuli_length);
@@ -127,16 +125,13 @@ architecture str of mmm_unb_ddr3_transpose is
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
signal i_mm_clk : std_logic := '1';
-
begin
-
mm_clk <= i_mm_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
@@ -191,7 +186,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
index 9c38d3a1e38613e9e1746dd298ad87f3690dbb8c..1f1463d40ddf153677f593cf22140353f94e8eb3 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/src/vhdl/unb1_ddr3_transpose.vhd
@@ -74,9 +74,7 @@ entity unb1_ddr3_transpose is
);
end unb1_ddr3_transpose;
-
architecture str of unb1_ddr3_transpose is
-
-- Firmware version x.y
constant c_fw_version : t_unb1_board_fw_version := (0, 9);
-- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
@@ -139,7 +137,6 @@ architecture str of unb1_ddr3_transpose is
signal dp_clk : std_logic;
signal dp_pps : std_logic;
-
-- PIOs
signal pout_wdi : std_logic;
@@ -213,9 +210,7 @@ architecture str of unb1_ddr3_transpose is
signal out_siso_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
signal ddr_ref_rst : std_logic;
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -435,7 +430,6 @@ begin
bsn_sosi_arr(0) <= bg_sosi_arr(0);
bsn_sosi_arr(1) <= out_sosi_arr(0);
-
u_areset_ddr_ref_rst : entity common_lib.common_areset
generic map(
g_rst_level => '1',
@@ -447,7 +441,6 @@ begin
out_rst => ddr_ref_rst
);
-
u_ddr3_T: entity ddr3_lib.ddr3_transpose
generic map(
g_sim => g_sim,
@@ -551,6 +544,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
index d0e39f72acc713d7d6e13773fd73c874776907a3..3d8ecf213a834d8c9206e1a9f6204949b944cf1e 100644
--- a/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
+++ b/boards/uniboard1/designs/unb1_ddr3_transpose/tb/vhdl/tb_unb1_ddr3_transpose.vhd
@@ -24,7 +24,6 @@
-- The DUT can be targeted at unb 0, bn3 with the same Python scripts
-- that are used on hardware.
-
library IEEE, tech_ddr_lib, common_lib, unb1_board_lib, i2c_lib, ddr3_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -38,7 +37,6 @@ entity tb_unb1_ddr3_transpose is
end tb_unb1_ddr3_transpose;
architecture tb of tb_unb1_ddr3_transpose is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -91,9 +89,7 @@ architecture tb of tb_unb1_ddr3_transpose is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -200,5 +196,4 @@ begin
mem3_in => phy_ou,
mem3_io => phy_io
);
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
index ef7d86f3902eb7342605cfac87adfefbb1e12d31..02d12daee571723b79912c82f1427aafe8dfcaa0 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/mmm_unb1_fn_terminal_db.vhd
@@ -104,10 +104,7 @@ entity mmm_unb1_fn_terminal_db is
);
end mmm_unb1_fn_terminal_db;
-
architecture str of mmm_unb1_fn_terminal_db is
-
-
-- Simulation
constant c_mm_clk_period : time := 100 ps;
constant c_tse_clk_period : time := 8 ns;
@@ -121,7 +118,6 @@ architecture str of mmm_unb1_fn_terminal_db is
constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"002286080001";
signal eth_psc_access : std_logic;
-
signal reg_ppsh_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_ppsh_miso : t_mem_miso := c_mem_miso_rst;
@@ -138,10 +134,7 @@ architecture str of mmm_unb1_fn_terminal_db is
signal sim_eth_psc_access : std_logic;
signal sim_eth1g_reg_mosi : t_mem_mosi;
-
-
begin
-
mm_clk <= i_mm_clk;
eth1g_tse_clk <= i_tse_clk;
@@ -149,7 +142,6 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
@@ -223,7 +215,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
-----------------------------------------------------------------------------
@@ -369,15 +360,3 @@ begin
);
end generate;
end;
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
index 08fd646a246ab3a27dfd2de2e9d6469ca2ef2155..f7ddc510062859aa916d7f5743157ee601e5a717 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -122,7 +122,6 @@
-- removed to let all settings directly depend on g_bsn_latency. The
-- advantage is that it
-
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -132,7 +131,6 @@ use dp_lib.dp_stream_pkg.all;
use unb1_board_lib.unb1_board_pkg.all;
use unb1_board_lib.unb1_board_peripherals_pkg.all;
-
entity node_unb1_fn_terminal_db is
generic(
g_sim : boolean := false;
@@ -199,7 +197,6 @@ entity node_unb1_fn_terminal_db is
end node_unb1_fn_terminal_db;
architecture str of node_unb1_fn_terminal_db is
-
-----------------------------------------------------------------------------
-- BSN align
-----------------------------------------------------------------------------
@@ -245,9 +242,7 @@ architecture str of node_unb1_fn_terminal_db is
-- Data buffer
-----------------------------------------------------------------------------
signal db_in_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
-
begin
-
gen_mesh: if g_use_mesh = true generate
-----------------------------------------------------------------------------
-- Terminals
@@ -434,7 +429,5 @@ begin
-- Entity DP out
-----------------------------------------------------------------------------
dp_out_sosi_arr <= db_in_sosi_arr;
-
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
index fc3699036499ef5e3e9e2448bb79f084587a5fd7..c3b0cd899761a0826b370b36ba22671b8825cdff 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/src/vhdl/unb1_fn_terminal_db.vhd
@@ -84,9 +84,7 @@ entity unb1_fn_terminal_db is
);
end unb1_fn_terminal_db;
-
architecture str of unb1_fn_terminal_db is
-
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 0, 0, 0, 0, 1);
constant c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
@@ -169,9 +167,7 @@ architecture str of unb1_fn_terminal_db is
-- MM bsn_monitor
signal reg_bsn_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_bsn_monitor_miso : t_mem_miso;
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -404,15 +400,3 @@ begin
end generate;
end;
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
index 759135578c642c67b1fbec3d89e5ae082a57d582..25bd96f7d89711519fc854a42162f667075a8031 100644
--- a/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/designs/unb1_fn_terminal_db/tb/vhdl/tb_unb1_fn_terminal_db.vhd
@@ -93,7 +93,6 @@ entity tb_mmf_node_fn_terminal_db is
end tb_mmf_node_fn_terminal_db;
architecture tb of tb_mmf_node_fn_terminal_db is
-
constant c_sim : boolean := true;
constant c_use_back : boolean := sel_a_b(g_unb_sys.nof_unb = 4, true, false); -- To interconnect multiple boards via the backplane when g_unb_sys.nof_unb=4 else when g_unb_sys.nof_unb=1
@@ -193,9 +192,7 @@ architecture tb of tb_mmf_node_fn_terminal_db is
signal fn_in_mesh_serial_4arr : t_unb_mesh_sl_4arr;
signal fn_out_mesh_serial_4arr : t_unb_mesh_sl_4arr;
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -307,7 +304,6 @@ begin
back_tx_serial_2arr => bn_out_back_serial_4arr(UNB)(BN),
back_rx_serial_2arr => bn_in_back_serial_4arr(UNB)(BN)
);
-
end generate;
gen_fn: for FN in 0 to g_unb_sys.nof_fn - 1 generate
@@ -385,7 +381,6 @@ begin
tx_serial_2arr => fn_out_mesh_serial_4arr(UNB)(FN), -- Tx support for diagnostics
rx_serial_2arr => fn_in_mesh_serial_4arr(UNB)(FN) -- Rx
);
-
end generate;
------------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
index 5299c6650470d0ddf298e7479b8ba95312f8e79e..78bdc17f233b68281ae52a27903f3657d6d7e08d 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/mmm_unb1_heater.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_unb1_heater_pkg.all;
-
entity mmm_unb1_heater is
generic (
g_sim : boolean := false;
@@ -105,7 +104,6 @@ entity mmm_unb1_heater is
end mmm_unb1_heater;
architecture str of mmm_unb1_heater is
-
constant c_mm_clk_period : time := 8 ns; -- 125 MHz
constant c_epcs_clk_period : time := 50 ns; -- 20 MHz
@@ -114,18 +112,14 @@ architecture str of mmm_unb1_heater is
signal i_mm_clk : std_logic := '1';
signal i_epcs_clk : std_logic := '1';
-
begin
-
mm_clk <= i_mm_clk;
epcs_clk <= i_epcs_clk;
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
i_epcs_clk <= not i_epcs_clk after c_epcs_clk_period / 2;
@@ -163,7 +157,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
----------------------------------------------------------------------------
@@ -279,7 +272,6 @@ begin
coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-- the_reg_epcs
coe_clk_export_from_the_reg_epcs => OPEN,
coe_reset_export_from_the_reg_epcs => OPEN,
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
index 1e491f25b3e8691223f279e9a6aafe4f88339696..6ab5775f35323f6cb09dd41e5a6b51e08d93a79a 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/qsys_unb1_heater_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb1_heater_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-----------------------------------------------------------------------------
@@ -147,4 +146,3 @@ package qsys_unb1_heater_pkg is
end component qsys_unb1_heater;
end qsys_unb1_heater_pkg;
-
diff --git a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
index 0012749a73f97032717a9df00327480776bcbcb4..8187b73626611866ff1ac6d01ecd72c65c2b4ffa 100644
--- a/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/src/vhdl/unb1_heater.vhd
@@ -65,9 +65,7 @@ entity unb1_heater is
);
end unb1_heater;
-
architecture str of unb1_heater is
-
-- IP base address used by unb_os : 10.99.xx.yy
constant c_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63";
-- Firmware version x.y
@@ -145,9 +143,7 @@ architecture str of unb1_heater is
-- Heater
signal reg_heater_mosi : t_mem_mosi;
signal reg_heater_miso : t_mem_miso;
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -350,4 +346,3 @@ begin
sla_out => reg_heater_miso
);
end str;
-
diff --git a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
index 35c916b8e14f525610021bfca29b8e805ab5ac53..42cf774fa0baec99a5258e50fc374fe297a965b7 100644
--- a/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
+++ b/boards/uniboard1/designs/unb1_heater/tb/vhdl/tb_unb1_heater.vhd
@@ -58,7 +58,6 @@ entity tb_unb1_heater is
end tb_unb1_heater;
architecture tb of tb_unb1_heater is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -104,9 +103,7 @@ architecture tb of tb_unb1_heater is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -198,5 +195,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
index 6d6d6ce813f69f8beeb241235e70cbb68595eb15..158c2a2617ea08a4d6399a911ab2548a4f1643b3 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/tb_unb1_minimal_mm_arbiter.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_minimal_mm_arbiter.
-- Description: see tb_unb1_minimal
-
library IEEE, unb1_minimal_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_minimal_mm_arbiter is
end tb_unb1_minimal_mm_arbiter;
-
architecture tb of tb_unb1_minimal_mm_arbiter is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
index 59b341b2ad00e9223308ef834166fd25c0e743f9..94b8a71585d0c48b2e788098e0449a91a2a51c3c 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_mm_arbiter/unb1_minimal_mm_arbiter.vhd
@@ -59,11 +59,8 @@ entity unb1_minimal_mm_arbiter is
);
end unb1_minimal_mm_arbiter;
-
architecture str of unb1_minimal_mm_arbiter is
-
begin
-
u_revision : entity unb1_minimal_lib.unb1_minimal
generic map (
g_design_name => g_design_name,
@@ -97,6 +94,4 @@ begin
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
index cdf60e088a051c2708483695f41e17964b357a58..86785da2a3dbbdaa2ff1b05e30d779402650090d 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_minimal_qsys.
-- Description: see tb_unb1_minimal
-
library IEEE, unb1_minimal_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_minimal_qsys is
end tb_unb1_minimal_qsys;
-
architecture tb of tb_unb1_minimal_qsys is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
index e406b3e8a3edcd7776c653f7d319952b64298e21..984cbc8b4cea62a341335896d2d437aa93d8cfde 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/tb_unb1_minimal_qsys_stimuli.vhd
@@ -56,7 +56,6 @@ entity tb_unb1_minimal_qsys_stimuli is
end tb_unb1_minimal_qsys_stimuli;
architecture tb of tb_unb1_minimal_qsys_stimuli is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -129,7 +128,6 @@ architecture tb of tb_unb1_minimal_qsys_stimuli is
constant c_extpected_cnt : natural := (1000 ms) / c_ext_clk_period;
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -289,5 +287,4 @@ begin
tb_end <= '1';
wait;
end process;
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
index 031c28162db5569612766cb89fcba5da72fd5d59..0f6289c4b140bd78a6f0543e7a32a0b2e5d2a06e 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys/unb1_minimal_qsys.vhd
@@ -59,11 +59,8 @@ entity unb1_minimal_qsys is
);
end unb1_minimal_qsys;
-
architecture str of unb1_minimal_qsys is
-
begin
-
u_revision : entity unb1_minimal_lib.unb1_minimal
generic map (
g_design_name => g_design_name,
@@ -97,6 +94,4 @@ begin
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
index 980363e3dd9ba566f21e33c35377503f20d6116b..225991915478557e0526f302a2ea6e41550bec83 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/mmm_unb1_minimal_qsys_wo_pll.vhd
@@ -39,7 +39,6 @@ use tech_tse_lib.tech_tse_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
use work.qsys_wo_pll_unb1_minimal_pkg.all;
-
entity mmm_unb1_minimal_qsys_wo_pll is
generic (
g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
@@ -104,7 +103,6 @@ entity mmm_unb1_minimal_qsys_wo_pll is
end mmm_unb1_minimal_qsys_wo_pll;
architecture str of mmm_unb1_minimal_qsys_wo_pll is
-
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr < 4, "FN", "BN");
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
@@ -118,14 +116,11 @@ architecture str of mmm_unb1_minimal_qsys_wo_pll is
signal sim_eth1g_reg_mosi : t_mem_mosi;
constant c_mm_clk_period : time := 1000 ms / g_mm_clk_freq;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -149,12 +144,11 @@ begin
u_mm_file_eth1g_tse : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_TSE")
port map(mm_rst, mm_clk, eth1g_tse_mosi, eth1g_tse_miso );
-
-
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
eth1g_mm_rst <= '1', '0' after 40ns;
+
p_eth_setup : process
begin
sim_eth_mm_bus_switch <= '1';
@@ -183,7 +177,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
----------------------------------------------------------------------------
@@ -295,7 +288,6 @@ begin
coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-- the_reg_epcs
coe_clk_export_from_the_reg_epcs => OPEN,
coe_reset_export_from_the_reg_epcs => OPEN,
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
index f0f3a2a7c7c87518824958a77671b3c7ac140e6c..142125fe43a2877ae7f01bfc3caab67d082ade0a 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/qsys_wo_pll_unb1_minimal_pkg.vhd
@@ -23,14 +23,12 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_wo_pll_unb1_minimal_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-----------------------------------------------------------------------------
component qsys_wo_pll_unb1_minimal is
-
port (
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
@@ -132,7 +130,6 @@ package qsys_wo_pll_unb1_minimal_pkg is
coe_ram_writedata_export_from_the_avs_eth_0 : out std_logic_vector(31 downto 0); -- export
coe_read_export_from_the_reg_remu : out std_logic -- export
);
-
end component qsys_wo_pll_unb1_minimal;
end qsys_wo_pll_unb1_minimal_pkg;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
index 0f750b95376d8c95d8ca0836ae03936f8b7d1be6..0359b319110d7ccfaa3794a5b6938ae577521101 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/tb_unb1_minimal_qsys_wo_pll.vhd
@@ -58,7 +58,6 @@ entity tb_unb1_minimal_qsys_wo_pll is
end tb_unb1_minimal_qsys_wo_pll;
architecture tb of tb_unb1_minimal_qsys_wo_pll is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -104,9 +103,7 @@ architecture tb of tb_unb1_minimal_qsys_wo_pll is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -198,5 +195,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
index d11fdcc51e75202f977391db3405834febefe12d..408c4bc506017ca1d924566a62823f2e48154beb 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_qsys_wo_pll/unb1_minimal_qsys_wo_pll.vhd
@@ -62,10 +62,7 @@ entity unb1_minimal_qsys_wo_pll is
);
end unb1_minimal_qsys_wo_pll;
-
-
architecture str of unb1_minimal_qsys_wo_pll is
-
-- Firmware version x.y
constant c_fw_version : t_unb1_board_fw_version := (1, 1);
-- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim.
@@ -139,9 +136,7 @@ architecture str of unb1_minimal_qsys_wo_pll is
-- Remote Update
signal reg_remu_mosi : t_mem_mosi;
signal reg_remu_miso : t_mem_miso;
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -331,5 +326,4 @@ begin
-- Node function
-----------------------------------------------------------------------------
-- Insert node_[design_name] here
-
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
index b7c25399bfeefcfd429932da00417620e6d56a31..73b74d631423c98f5bfca6e7ad9ff68548eadaf6 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/tb_unb1_minimal_sopc.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_minimal_sopc.
-- Description: see tb_unb1_minimal
-
library IEEE, unb1_minimal_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_minimal_sopc is
end tb_unb1_minimal_sopc;
-
architecture tb of tb_unb1_minimal_sopc is
begin
u_tb_unb1_minimal : entity unb1_minimal_lib.tb_unb1_minimal
diff --git a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
index 5b2ca7c3f7f26d58970e0236f44a99691019e97f..31d891bafd689e7910b4bd57833a04e0d9393a30 100644
--- a/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/revisions/unb1_minimal_sopc/unb1_minimal_sopc.vhd
@@ -59,11 +59,8 @@ entity unb1_minimal_sopc is
);
end unb1_minimal_sopc;
-
architecture str of unb1_minimal_sopc is
-
begin
-
u_revision : entity unb1_minimal_lib.unb1_minimal
generic map (
g_design_name => g_design_name,
@@ -96,6 +93,4 @@ begin
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
index ba4b697c72624eb42ff5a3994d608b00d9ae011f..d0dbf2fd6e39c1f69358d620fdbd979b401fc58f 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/mmm_unb1_minimal.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_unb1_minimal_pkg.all;
-
entity mmm_unb1_minimal is
generic (
g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
@@ -103,7 +102,6 @@ entity mmm_unb1_minimal is
end mmm_unb1_minimal;
architecture str of mmm_unb1_minimal is
-
constant c_mm_clk_period : time := 8 ns; -- 125 MHz
constant c_epcs_clk_period : time := 50 ns; -- 20 MHz
@@ -143,18 +141,14 @@ architecture str of mmm_unb1_minimal is
signal slave_mosi_arr : t_mem_mosi_arr(c_nof_slaves - 1 downto 0);
signal slave_miso_arr : t_mem_miso_arr(c_nof_slaves - 1 downto 0);
-
begin
-
mm_clk <= i_mm_clk;
epcs_clk <= i_epcs_clk;
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
i_epcs_clk <= not i_epcs_clk after c_epcs_clk_period / 2;
@@ -189,7 +183,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
----------------------------------------------------------------------------
@@ -444,7 +437,6 @@ begin
coe_write_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wr,
coe_writedata_export_from_the_reg_mmdp_ctrl => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
-- the_reg_epcs
coe_clk_export_from_the_reg_epcs => OPEN,
coe_reset_export_from_the_reg_epcs => OPEN,
@@ -592,6 +584,4 @@ begin
reg_mmdp_data_mosi <= slave_mosi_arr(10);
slave_miso_arr(10) <= reg_mmdp_data_miso;
end generate;
-
-
end str;
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
index 0a216a48d02ae6569b438256644deceab252b2ac..63e5d9c4da7458d9ab0c6208a30252181f8406be 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/qsys_unb1_minimal_pkg.vhd
@@ -23,14 +23,12 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb1_minimal_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-----------------------------------------------------------------------------
component qsys_unb1_minimal is
-
port (
coe_ram_write_export_from_the_avs_eth_0 : out std_logic; -- export
coe_reg_read_export_from_the_avs_eth_0 : out std_logic; -- export
@@ -139,7 +137,6 @@ package qsys_unb1_minimal_pkg is
c3_from_the_altpll_0 : out std_logic; -- export
coe_read_export_from_the_reg_remu : out std_logic -- export
);
-
end component qsys_unb1_minimal;
component qsys_unb1_minimal_mm_arbiter is
@@ -191,4 +188,3 @@ package qsys_unb1_minimal_pkg is
end component qsys_unb1_minimal_mm_arbiter;
end qsys_unb1_minimal_pkg;
-
diff --git a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
index 7be378fdcb5a7c74543ecfc7d189044a03f30629..fbb7e941a498c245f4b613ce475fb52afcdcbf16 100644
--- a/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/src/vhdl/unb1_minimal.vhd
@@ -62,9 +62,7 @@ entity unb1_minimal is
);
end unb1_minimal;
-
architecture str of unb1_minimal is
-
-- IP base address used by unb_os : 10.99.xx.yy
constant c_base_ip : std_logic_vector(16 - 1 downto 0) := X"0A63";
-- Firmware version x.y
@@ -141,9 +139,7 @@ architecture str of unb1_minimal is
-- Remote Update
signal reg_remu_mosi : t_mem_mosi;
signal reg_remu_miso : t_mem_miso;
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -333,6 +329,4 @@ begin
-- Node function
-----------------------------------------------------------------------------
-- Insert node_[design_name] here
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
index b63da7ebd37fb6fd0a53fa2da45e4f05259a1359..4ffbccca21578df961a7fefa384f08dd05e2bbd5 100644
--- a/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
+++ b/boards/uniboard1/designs/unb1_minimal/tb/vhdl/tb_unb1_minimal.vhd
@@ -58,7 +58,6 @@ entity tb_unb1_minimal is
end tb_unb1_minimal;
architecture tb of tb_unb1_minimal is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -104,9 +103,7 @@ architecture tb of tb_unb1_minimal is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -198,5 +195,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
index 6f2d2143cc9eb0d0e1812a17f75842a5cf164387..438450102620f3443679561df9df3d0682264f75 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/mmm_unb1_terminal_bg_mesh_db.vhd
@@ -132,7 +132,6 @@ entity mmm_unb1_terminal_bg_mesh_db is
end entity mmm_unb1_terminal_bg_mesh_db;
architecture str of mmm_unb1_terminal_bg_mesh_db is
-
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr < 4, "FN", "BN");
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
@@ -263,10 +262,7 @@ architecture str of mmm_unb1_terminal_bg_mesh_db is
reg_diagnostics_clk_export : out std_logic
);
end component qsys_unb1_terminal_bg_mesh_db;
-
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
@@ -328,18 +324,18 @@ begin
eth1g_reg_mosi <= i_eth1g_reg_mosi;
end if;
end process;
+
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
+
----------------------------------------------------------------------------
-- SOPC or QSYS for synthesis
----------------------------------------------------------------------------
gen_qsys_unb1_terminal_bg_mesh_db : if g_sim = false generate
-
mm_rst_n <= not(mm_rst);
u_qsys_unb1_terminal_bg_mesh_db : qsys_unb1_terminal_bg_mesh_db
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
index 6c2d1dbc7be55e26f9707c044edfa6664f5f5936..f70200f9e086dfadf9bf9f00fef0540ef1e0761b 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/node_unb1_terminal_bg_mesh_db.vhd
@@ -139,7 +139,6 @@ entity node_unb1_terminal_bg_mesh_db is
end node_unb1_terminal_bg_mesh_db;
architecture str of node_unb1_terminal_bg_mesh_db is
-
-----------------------------------------------------------------------------
-- Block Generator
-----------------------------------------------------------------------------
@@ -193,9 +192,7 @@ architecture str of node_unb1_terminal_bg_mesh_db is
--. BSN Monitor
signal bsn_mon_snk_out_arr : t_dp_siso_arr(c_bsn_mon_nof_streams - 1 downto 0);
signal bsn_mon_snk_in_arr : t_dp_sosi_arr(c_bsn_mon_nof_streams - 1 downto 0);
-
begin
-
---------------------------------------------------------------------------------------
-- From 2d to 1d array. Input port to input BG.
---------------------------------------------------------------------------------------
@@ -425,5 +422,4 @@ begin
rx_usr_sosi_2arr(I)(J) <= bsn_align_src_out_arr(I * g_usr_nof_streams + J);
end generate;
end generate;
-
end str;
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
index 9202aa0cf7a380b48497b613c2cd2040077ad119..ec6f3afdfdca813569388e2c23ac27861bc3f7d1 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/src/vhdl/unb1_terminal_bg_mesh_db.vhd
@@ -83,9 +83,7 @@ entity unb1_terminal_bg_mesh_db is
);
end unb1_terminal_bg_mesh_db;
-
architecture str of unb1_terminal_bg_mesh_db is
-
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 1, 0, 0, 0, 0, 1);
constant c_fw_version : t_unb1_board_fw_version := (1, 0); -- firmware version x.y
@@ -209,9 +207,7 @@ architecture str of unb1_terminal_bg_mesh_db is
-- MM bsn_monitor
signal reg_bsn_monitor_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_bsn_monitor_miso : t_mem_miso;
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -478,15 +474,3 @@ begin
end generate;
end;
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
index 2fe9f2030eb6784dc3ed0771cd11736c2589800d..4069b5616d5cc8fc41c9b8f6975c3b1cf71290bd 100644
--- a/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
+++ b/boards/uniboard1/designs/unb1_terminal_bg_mesh_db/tb/vhdl/tb_unb1_terminal_bg_mesh_db.vhd
@@ -39,7 +39,6 @@ entity tb_unb1_terminal_bg_mesh_db is
end tb_unb1_terminal_bg_mesh_db;
architecture tb of tb_unb1_terminal_bg_mesh_db is
-
constant c_sim : boolean := true;
constant c_version : std_logic_vector(1 downto 0) := "00";
constant c_sim_level : natural := 1;
@@ -95,9 +94,7 @@ architecture tb of tb_unb1_terminal_bg_mesh_db is
signal bn_in_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
signal fn_in_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
signal fn_out_mesh_serial_3arr : t_unb1_board_mesh_sl_3arr;
-
begin
-
-- Run 1 ms
ext_clk <= not ext_clk after c_ext_clk_period / 2; -- External clock (200 MHz)
eth_clk <= not eth_clk after c_eth_clk_period / 2; -- 1GbE XO clock (25 MHz)
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
index ca717a19788b09252c46b2dfa658e606f91d1c62..e81056c6c6ca96cf753ae4d3907cf9546c9b5151 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_10GbE.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_10GbE is
end tb_unb1_test_10GbE;
-
architecture tb of tb_unb1_test_10GbE is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index 4dc4b63f76b5fd3665e5942d1668a5aee77e27ae..b0979cb122226b362df92eefb5f996545d98235f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -89,11 +89,8 @@ entity unb1_test_10GbE is
);
end unb1_test_10GbE;
-
architecture str of unb1_test_10GbE is
-
begin
-
u_revision : entity unb1_test_lib.unb1_test
generic map (
g_design_name => g_design_name,
@@ -155,6 +152,4 @@ begin
BN_BI_3_TX => BN_BI_3_TX,
BN_BI_3_RX => BN_BI_3_RX
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
index 1e2189fd170c587ec636b0538f202bd82bd1103c..d5bd19a9c3283e8b1302638e11c1c0abae86ce6b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/tb_unb1_test_10GbE_tx_only.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_10GbE_tx_only.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_10GbE_tx_only is
end tb_unb1_test_10GbE_tx_only;
-
architecture tb of tb_unb1_test_10GbE_tx_only is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
index bf41fa0ee477bfb07de7bd8f903c4431ac48e26e..3043972db629a52b6dfa4e96c2b9864da10aad4b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE_tx_only/unb1_test_10GbE_tx_only.vhd
@@ -81,11 +81,8 @@ entity unb1_test_10GbE_tx_only is
);
end unb1_test_10GbE_tx_only;
-
architecture str of unb1_test_10GbE_tx_only is
-
begin
-
u_revision : entity unb1_test_lib.unb1_test
generic map (
g_design_name => g_design_name,
@@ -138,6 +135,4 @@ begin
SI_FN_3_CNTRL => SI_FN_3_CNTRL,
SI_FN_RSTN => SI_FN_RSTN
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
index 1a4919e2d98356b54b75498355d6a3d132999524..c56b4f415af6b3b865a88031151e7d205b25a345 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/tb_unb1_test_1GbE.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_1GbE.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_1GbE is
end tb_unb1_test_1GbE;
-
architecture tb of tb_unb1_test_1GbE is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
index c343b9bba3b9b9f1fdb44a5da0288ee254c48a93..4ce67372f9f115a50cea341e785b020925f39eac 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_1GbE/unb1_test_1GbE.vhd
@@ -61,11 +61,8 @@ entity unb1_test_1GbE is
);
end unb1_test_1GbE;
-
architecture str of unb1_test_1GbE is
-
begin
-
u_revision : entity unb1_test_lib.unb1_test
generic map (
g_design_name => g_design_name,
@@ -99,6 +96,4 @@ begin
ETH_SGIN => ETH_SGIN,
ETH_SGOUT => ETH_SGOUT
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
index 95e5625c6384f3bb6285fe202fb8b20f45174454..c5dc616e081843f7d741d75432356777dfec2b9b 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/tb_unb1_test_all.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_all.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_all is
end tb_unb1_test_all;
-
architecture tb of tb_unb1_test_all is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
index 3fe8e0c0b7a93f726c50b00c88ccb87ccb0d10a6..d17bc71fa1fbc013fdfabeb004a906d400dbeb87 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_all/unb1_test_all.vhd
@@ -100,11 +100,8 @@ entity unb1_test_all is
);
end unb1_test_all;
-
architecture str of unb1_test_all is
-
begin
-
u_revision : entity unb1_test_lib.unb1_test
generic map (
g_design_name => g_design_name,
@@ -174,6 +171,4 @@ begin
MB_II_IO => MB_II_IO,
MB_II_OU => MB_II_OU
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
index 45dee37a1e0e4ae85d29192cc517a3c38df370d5..969c0768bd86ee7176b7cc6d416635f8877f0eeb 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/tb_unb1_test_ddr.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_ddr.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_ddr is
end tb_unb1_test_ddr;
-
architecture tb of tb_unb1_test_ddr is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
index c7999ff52f7bee585fbaa44db8a062a3844317ac..df41e0d91aa2d46276cfdedd4fe24ed6c6f178dd 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr/unb1_test_ddr.vhd
@@ -67,11 +67,8 @@ entity unb1_test_ddr is
);
end unb1_test_ddr;
-
architecture str of unb1_test_ddr is
-
begin
-
u_revision : entity unb1_test_lib.unb1_test
generic map (
g_design_name => g_design_name,
@@ -113,6 +110,4 @@ begin
-- MB_II_IO => MB_II_IO,
-- MB_II_OU => MB_II_OU
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
index 987b652ec9b3ac920638f4087339969cbfcbe98b..3dac8535f14e5439141cc3f0b2c24c215e38af24 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/tb_unb1_test_ddr_16g_MB_I.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_ddr_16g_MB_I.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_ddr_16g_MB_I is
end tb_unb1_test_ddr_16g_MB_I;
-
architecture tb of tb_unb1_test_ddr_16g_MB_I is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
index 60ce44f69def93013d0c25f149f1df87aacb5153..6f4ce8542b20eef5ee2826a2341f7f82603ee915 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I/unb1_test_ddr_16g_MB_I.vhd
@@ -67,11 +67,8 @@ entity unb1_test_ddr_16g_MB_I is
);
end unb1_test_ddr_16g_MB_I;
-
architecture str of unb1_test_ddr_16g_MB_I is
-
begin
-
u_revision : entity unb1_test_lib.unb1_test
generic map (
g_design_name => g_design_name,
@@ -110,6 +107,4 @@ begin
MB_I_IO => MB_I_IO,
MB_I_OU => MB_I_OU
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
index 8563b7b429f4fc97b1825cc62f7a60530f9a50e4..51e1bc635bf8462d08ea93c8bbf96c7da5a43486 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/tb_unb1_test_ddr_16g_MB_II.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_ddr_16g_MB_II.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_ddr_16g_MB_II is
end tb_unb1_test_ddr_16g_MB_II;
-
architecture tb of tb_unb1_test_ddr_16g_MB_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
index ddcbca83a07865fc5bed5054a1e9ad73f61aa852..af5925eda507c7a76e0257690a9d885df47dcd9a 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_II/unb1_test_ddr_16g_MB_II.vhd
@@ -67,11 +67,8 @@ entity unb1_test_ddr_16g_MB_II is
);
end unb1_test_ddr_16g_MB_II;
-
architecture str of unb1_test_ddr_16g_MB_II is
-
begin
-
u_revision : entity unb1_test_lib.unb1_test
generic map (
g_design_name => g_design_name,
@@ -110,6 +107,4 @@ begin
MB_II_IO => MB_II_IO,
MB_II_OU => MB_II_OU
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
index d46c182efc8743163ea81071bd2e90fdd1bf6b4f..29cb419b28d29b88ebc26bac8a44f34c3f0c40d6 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/tb_unb1_test_ddr_16g_MB_I_II.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_ddr_16g_MB_I_II.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_ddr_16g_MB_I_II is
end tb_unb1_test_ddr_16g_MB_I_II;
-
architecture tb of tb_unb1_test_ddr_16g_MB_I_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
index 7acc74681f182726087a85a26220a345b0ea99f1..8b8d0ee03e1c1620edc7073b57d164521b6a46de 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_16g_MB_I_II/unb1_test_ddr_16g_MB_I_II.vhd
@@ -72,11 +72,8 @@ entity unb1_test_ddr_16g_MB_I_II is
);
end unb1_test_ddr_16g_MB_I_II;
-
architecture str of unb1_test_ddr_16g_MB_I_II is
-
begin
-
u_revision : entity unb1_test_lib.unb1_test
generic map (
g_design_name => g_design_name,
@@ -120,6 +117,4 @@ begin
MB_II_IO => MB_II_IO,
MB_II_OU => MB_II_OU
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
index f6e193f507f6bd716a9958b9a4215ccd61dca96c..12ef1917691d1dd94bf1796d79807d0c7e2395c7 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I/tb_unb1_test_ddr_MB_I.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_ddr_MB_I.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_ddr_MB_I is
end tb_unb1_test_ddr_MB_I;
-
architecture tb of tb_unb1_test_ddr_MB_I is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
index b98a4e527b862de5fd3a811c21674b039c98bbcf..dda6de35318a4df53541a3050cad7b0e003989ec 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_II/tb_unb1_test_ddr_MB_II.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_ddr_MB_II.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_ddr_MB_II is
end tb_unb1_test_ddr_MB_II;
-
architecture tb of tb_unb1_test_ddr_MB_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
index 267bb2e42d73db5a776f8763536a21dd502e20af..c1f597d928df224812b1fc30abae65f8fe69fae1 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/tb_unb1_test_ddr_MB_I_II.vhd
@@ -23,15 +23,12 @@
-- Purpose: Test bench for unb1_test_ddr_MB_I_II.
-- Description: see tb_unb1_test
-
library IEEE, unb1_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb1_test_ddr_MB_I_II is
end tb_unb1_test_ddr_MB_I_II;
-
architecture tb of tb_unb1_test_ddr_MB_I_II is
begin
u_tb_unb1_test : entity unb1_test_lib.tb_unb1_test
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
index 8fd5ea7484f5aa21ade189233dbd19503d608f3b..f5524185b2b14002e0a574f0c58d1e38e60e3e3c 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_ddr_MB_I_II/unb1_test_ddr_MB_I_II.vhd
@@ -72,11 +72,8 @@ entity unb1_test_ddr_MB_I_II is
);
end unb1_test_ddr_MB_I_II;
-
architecture str of unb1_test_ddr_MB_I_II is
-
begin
-
u_revision : entity unb1_test_lib.unb1_test
generic map (
g_design_name => g_design_name,
@@ -120,6 +117,4 @@ begin
MB_II_IO => MB_II_IO,
MB_II_OU => MB_II_OU
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
index 29dd996bfa956e1f541eda03af01644df08f50c8..7e468fa82dd68c100cdca0d5f9bdb6d5d6a42c56 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd
@@ -40,7 +40,6 @@ use tech_tse_lib.tb_tech_tse_pkg.all;
use work.qsys_unb1_test_pkg.all;
use work.unb1_test_pkg.all;
-
entity mmm_unb1_test is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -197,7 +196,6 @@ entity mmm_unb1_test is
end mmm_unb1_test;
architecture str of mmm_unb1_test is
-
-- Block generator
constant c_ram_diag_bg_1GbE_addr_w : natural := ceil_log2(g_nof_streams_1GbE * pow2(ceil_log2(g_bg_block_size)));
constant c_ram_diag_bg_10GbE_addr_w : natural := ceil_log2(g_nof_streams_10GbE * pow2(ceil_log2(g_bg_block_size)));
@@ -253,14 +251,11 @@ architecture str of mmm_unb1_test is
signal sim_eth1g_reg_mosi : t_mem_mosi;
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
eth1g_mm_rst <= mm_rst;
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
@@ -361,7 +356,6 @@ begin
u_mm_file_reg_tr_xaui : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_TR_XAUI") -- , c_mm_clk_period, FALSE, 0)
port map(mm_rst, mm_clk, reg_tr_xaui_mosi, reg_tr_xaui_miso);
-
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
@@ -391,23 +385,19 @@ begin
end if;
end process;
-
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
-
----------------------------------------------------------------------------
-- QSYS
----------------------------------------------------------------------------
i_reset_n <= not mm_rst;
gen_qsys : if g_sim = false generate
-
u_qsys : qsys_unb1_test
port map (
clk_0 => mm_clk,
@@ -641,7 +631,6 @@ begin
reg_dp_offload_rx_10GbE_hdr_dat_write_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.wr,
reg_dp_offload_rx_10GbE_hdr_dat_writedata_export => reg_dp_offload_rx_10GbE_hdr_dat_mosi.wrdata(c_word_w - 1 downto 0),
-
-- the_reg_bsn_monitor_1GbE
reg_bsn_monitor_1GbE_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
reg_bsn_monitor_1GbE_clk_export => OPEN,
@@ -711,7 +700,6 @@ begin
reg_diag_rx_seq_10GbE_write_export => reg_diag_rx_seq_10GbE_mosi.wr,
reg_diag_rx_seq_10GbE_writedata_export => reg_diag_rx_seq_10GbE_mosi.wrdata(c_word_w - 1 downto 0),
-
-- reg_diag_tx_seq_1GbE
reg_diag_tx_seq_1GbE_address_export => reg_diag_tx_seq_1GbE_mosi.address(2 - 1 downto 0),
reg_diag_tx_seq_1GbE_clk_export => OPEN,
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
index 1589f5a61f0489adf82f16a66b91549032f7eae4..3c257fae3c3952152f5c7f2c4966ff5fd449cf8c 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/qsys_unb1_test_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb1_test_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v11.1 QSYS builder
-----------------------------------------------------------------------------
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
index e165615bf216bc5933cb363ecb7ce42c490093fb..2d696a1218f996dd3a87688ac3367ed18405558d 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/udp_stream.vhd
@@ -98,10 +98,7 @@ entity udp_stream is
);
end udp_stream;
-
-
architecture str of udp_stream is
-
-- Block generator
constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
'0', -- enable_sync
@@ -112,7 +109,6 @@ architecture str of udp_stream is
TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "1001" & "111011111100" & "0001" & "101111111";
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
@@ -132,9 +128,7 @@ architecture str of udp_stream is
signal diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
-
begin
-
gen_hdr_in_fields : for i in 0 to g_nof_streams - 1 generate
-- dst = src
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) downto field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000" & ID(7 downto 3) & RESIZE_UVEC(ID(2 downto 0), c_byte_w);
@@ -151,7 +145,6 @@ begin
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )) <= fifo_block_gen_src_out_arr(i).bsn(59 downto 0);
end generate;
-
-----------------------------------------------------------------------------
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
@@ -204,7 +197,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
@@ -244,7 +236,6 @@ begin
hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
);
-
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
@@ -277,13 +268,11 @@ begin
hdr_fields_out_arr => hdr_fields_out_arr
);
-
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
end generate;
-
-----------------------------------------------------------------------------
-- RX: Data buffers and BSN monitors
-----------------------------------------------------------------------------
@@ -297,8 +286,6 @@ begin
diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
end generate;
-
-
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
g_nof_streams => g_nof_streams,
@@ -320,7 +307,6 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
);
-
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
@@ -347,6 +333,4 @@ begin
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 9e7bc8c9f5baa179cdd0e3950fc3becdab56a05f..428faa733ef9d0cd312c91c357cf64025323e96e 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -111,10 +111,7 @@ entity unb1_test is
);
end unb1_test;
-
-
architecture str of unb1_test is
-
-- Firmware version x.y
constant c_fw_version : t_unb1_board_fw_version := (1, 2);
@@ -345,11 +342,7 @@ architecture str of unb1_test is
signal MB_I_ctlr_rst : std_logic;
signal MB_II_ctlr_clk : std_logic;
signal MB_II_ctlr_rst : std_logic;
-
-
-
begin
-
u_areset_ddr_ref_rst : entity common_lib.common_areset
generic map(
g_rst_level => '1',
@@ -643,7 +636,6 @@ begin
ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
-
gen_udp_stream_1GbE : if c_revision_select.use_streaming_1GbE = true generate
u_udp_stream_1GbE : entity work.udp_stream
generic map (
@@ -702,7 +694,6 @@ begin
);
end generate;
-
gen_udp_stream_10GbE : if c_revision_select.use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
generic map (
@@ -761,7 +752,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- tr_10GbE
-----------------------------------------------------------------------------
@@ -985,6 +975,4 @@ gen_mms_io_ddr_diag_MB_II : if c_revision_select.use_ddr_MB_II = 1 generate
);
end generate;
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
index 61d6ce08c81907b448d1a2af2b0ade6c487cff81..a1c4f5a3856ce1a8df548e1190e7af7fcedeb604 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test_pkg.vhd
@@ -27,7 +27,6 @@ use common_lib.common_field_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
package unb1_test_pkg is
-
type t_unb1_test_config is record
use_front : natural;
use_back : natural;
@@ -79,7 +78,6 @@ package unb1_test_pkg is
end unb1_test_pkg;
package body unb1_test_pkg is
-
constant c_all : t_unb1_test_config := ( 1, 0, true, 1, true, 3, 1, 1, 2, c_tech_ddr3_4g_single_rank_800m_master);
constant c_1GbE : t_unb1_test_config := ( 0, 0, true, 1, false, 0, 0, 0, 0, c_tech_ddr3_4g_single_rank_800m_master);
constant c_10GbE : t_unb1_test_config := ( 1, 0, false, 1, true, 3, 0, 0, 0, c_tech_ddr3_4g_single_rank_800m_master);
@@ -103,7 +101,7 @@ package body unb1_test_pkg is
elsif g_design_name = "unb1_test_ddr_16g_MB_I_II" then return c_ddr_16g_MB_I_II;
else return c_all;
end if;
+
end;
end unb1_test_pkg;
-
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index b4c91dc6407e986c1af5204953b7c59b0e21594c..fd3eea1c8906c14b0f5954900da4ffd3b0059732 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -54,7 +54,6 @@ use tech_ddr_lib.tech_ddr_pkg.all;
use tech_ddr_lib.tech_ddr_mem_model_component_pkg.all;
use work.unb1_test_pkg.all;
-
entity tb_unb1_test is
generic (
g_design_name : string := "unb1_test";
@@ -64,7 +63,6 @@ entity tb_unb1_test is
end tb_unb1_test;
architecture tb of tb_unb1_test is
-
constant c_sim : boolean := true;
constant c_id : std_logic_vector(7 downto 0) := TO_UVEC(g_sim_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(g_sim_node_nr, c_unb1_board_nof_chip_w);
@@ -129,9 +127,7 @@ architecture tb of tb_unb1_test is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -284,5 +280,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
index f458fc30705860b3678a7c9778e637943eed98b9..2a79752d439f79bbff34789cd312d69bab8def26 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/mmm_unb1_tr_10GbE.vhd
@@ -88,7 +88,6 @@ entity mmm_unb1_tr_10GbE is
end entity mmm_unb1_tr_10GbE;
architecture str of mmm_unb1_tr_10GbE is
-
signal mm_rst_n : std_logic;
component qsys_unb1_tr_10GbE is
@@ -226,10 +225,7 @@ architecture str of mmm_unb1_tr_10GbE is
reg_mdio_0_read_export : out std_logic
);
end component qsys_unb1_tr_10GbE;
-
-
begin
-
gen_sim : if g_sim = true generate
reg_wdi_mosi <= c_mem_mosi_rst;
reg_unb_system_info_mosi <= c_mem_mosi_rst;
@@ -248,11 +244,11 @@ begin
reg_tr_xaui_mosi <= c_mem_mosi_rst;
reg_bsn_monitor_mosi <= c_mem_mosi_rst;
end generate;
+
----------------------------------------------------------------------------
-- SOPC or QSYS for synthesis
----------------------------------------------------------------------------
gen_qsys_unb1_tr_10GbE : if g_sim = false generate
-
mm_rst_n <= not(mm_rst);
u_qsys_unb1_tr_10GbE : qsys_unb1_tr_10GbE
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
index 80c8a90812eb74a922cdf26f76bd8e117ae0491c..289839f6e9daa2b3af18e6de67b6f92ae6593bd0 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/src/vhdl/unb1_tr_10GbE.vhd
@@ -36,7 +36,6 @@ use eth_lib.eth_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
-
-- Purpose:
entity unb1_tr_10GbE is
@@ -91,9 +90,7 @@ entity unb1_tr_10GbE is
);
end unb1_tr_10GbE;
-
architecture str of unb1_tr_10GbE is
-
constant c_use_phy : t_c_unb1_board_use_phy := (1, 1, 0, 0, 0, 0, 0, 1);
constant c_nof_10GbE_streams : natural := 3; -- The number of 10G input streams
@@ -192,9 +189,7 @@ architecture str of unb1_tr_10GbE is
-- BSN monitors
signal dp_bsn_monitor_in_siso_arr : t_dp_siso_arr(c_nof_10GbE_streams + 1 + 1 - 1 downto 0);
signal dp_bsn_monitor_in_sosi_arr : t_dp_sosi_arr(c_nof_10GbE_streams + 1 + 1 - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- TX: 3 Block generators
-----------------------------------------------------------------------------
@@ -219,7 +214,6 @@ begin
out_sosi_arr => mms_diag_block_gen_src_out_arr
);
-
-----------------------------------------------------------------------------
-- 10GbE TX/RX
-----------------------------------------------------------------------------
@@ -273,7 +267,6 @@ begin
g_nof_macs => c_nof_10GbE_streams,
g_use_mdio => true
)
-
port map (
-- Transceiver PLL reference clock
tr_ref_clk_156 => SA_CLK,
@@ -354,8 +347,6 @@ begin
-- dp_offload_rx_restored_src_out_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
-- END GENERATE;
-
-
-----------------------------------------------------------------------------
-- RX: BSN monitors at several stages in the stream
-----------------------------------------------------------------------------
@@ -522,7 +513,6 @@ begin
reg_bsn_monitor_miso => reg_bsn_monitor_miso
);
-
reg_mdio_mosi_arr(0) <= reg_mdio_0_mosi;
reg_mdio_mosi_arr(1) <= reg_mdio_1_mosi;
reg_mdio_mosi_arr(2) <= reg_mdio_2_mosi;
@@ -530,6 +520,4 @@ begin
reg_mdio_0_miso <= reg_mdio_miso_arr(0);
reg_mdio_1_miso <= reg_mdio_miso_arr(1);
reg_mdio_2_miso <= reg_mdio_miso_arr(2);
-
end str;
-
diff --git a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
index f03ca1a313ce7ac50e6ba615533195df537b99dc..3c298d5e150f24bc44068be7a26b712e08eaa951 100644
--- a/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_tr_10GbE/tb/vhdl/tb_unb1_tr_10GbE.vhd
@@ -35,7 +35,6 @@ entity tb_unb1_tr_10GbE is
end tb_unb1_tr_10GbE;
architecture tb of tb_unb1_tr_10GbE is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -51,7 +50,6 @@ architecture tb of tb_unb1_tr_10GbE is
constant c_clk_period : time := 5 ns;
constant c_pps_period : natural := 1000;
-
-- DUT
signal clk : std_logic := '0';
signal pps : std_logic := '0';
@@ -78,9 +76,7 @@ architecture tb of tb_unb1_tr_10GbE is
signal fn_bn_1_tx : std_logic_vector(c_unb1_board_tr_mesh.bus_w - 1 downto 0);
signal fn_bn_2_tx : std_logic_vector(c_unb1_board_tr_mesh.bus_w - 1 downto 0);
signal fn_bn_3_tx : std_logic_vector(c_unb1_board_tr_mesh.bus_w - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -136,5 +132,4 @@ begin
SI_FN_2_RX => si_fn_0_tx,
SI_FN_3_RX => si_fn_0_tx
);
-
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
index 446603b1debca515cf5ea0fc1abda3115412b308..a26175ea386e55baf9e1192f275b4efe3d48cabb 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd
@@ -159,7 +159,6 @@ entity ctrl_unb1_board is
epcs_clk : in std_logic := '0'; -- from QSYS
epcs_clk_out : out std_logic;
-
dp_rst : out std_logic;
dp_clk : out std_logic; -- 200 MHz from CLK system clock
dp_phs_clk_vec : out std_logic_vector(g_dp_phs_clk_vec_w - 1 downto 0); -- divided and phase shifted from 200 MHz CLK system clock when a PLL is used
@@ -266,9 +265,7 @@ entity ctrl_unb1_board is
);
end ctrl_unb1_board;
-
architecture str of ctrl_unb1_board is
-
constant c_use_flash : boolean := g_sim = false or g_sim_flash_model = true; -- enable on HW, disable to save simulation time when not used in tb
constant c_rom_version : natural := 1; -- Only increment when something changes to the register map of rom_system_info.
@@ -335,9 +332,7 @@ architecture str of ctrl_unb1_board is
signal eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
signal eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
signal eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_siso_rdy);
-
begin
-
xo_clk <= i_xo_clk;
xo_rst <= i_xo_rst;
xo_rst_n <= i_xo_rst_n;
@@ -347,7 +342,6 @@ begin
cal_rec_clk <= clk40M;
eth1g_tse_clk_out <= clk125M;
-
-----------------------------------------------------------------------------
-- Node set up
-----------------------------------------------------------------------------
@@ -404,7 +398,6 @@ begin
node_ctrl_dp_clk_in <= dp_clk_in;
end generate;
-
-- for UNB1 designs with SOPC g_xo_clk_use_pll=FALSE and the the SOPC generates and outputs the mm_clk
-- for UNB1 designs with QSYS g_xo_clk_use_pll=TRUE and this ctrl_unb1_board generates and outputs the mm_clk
gen_clk25_pll: if g_xo_clk_use_pll = true generate
@@ -440,7 +433,6 @@ begin
);
end generate;
-
u_unb1_board_node_ctrl : entity work.unb1_board_node_ctrl
generic map (
g_pulse_us => g_mm_clk_freq / (10**6) -- nof system clock cycles to get us period, equal to system clock frequency / 10**6
@@ -495,7 +487,6 @@ begin
bck_id => this_bck_id
);
-
-----------------------------------------------------------------------------
-- Red LED control
-----------------------------------------------------------------------------
@@ -509,7 +500,6 @@ begin
TESTIO(c_unb1_board_testio_led_red) <= led_toggle_red;
end generate;
-
-----------------------------------------------------------------------------
-- Green LED control
-----------------------------------------------------------------------------
@@ -523,7 +513,6 @@ begin
TESTIO(c_unb1_board_testio_led_green) <= led_toggle_green;
end generate;
-
------------------------------------------------------------------------------
-- Toggle red LED when unb1_minimal is running, green LED for other designs.
------------------------------------------------------------------------------
@@ -538,7 +527,6 @@ begin
out_dat => led_toggle
);
-
------------------------------------------------------------------------------
-- WDI override
------------------------------------------------------------------------------
@@ -558,7 +546,6 @@ begin
wdi_override => wdi_override
);
-
------------------------------------------------------------------------------
-- Remote upgrade
------------------------------------------------------------------------------
@@ -582,7 +569,6 @@ begin
reg_remu_miso <= c_mem_miso_rst;
end generate;
-
-----------------------------------------------------------------------------
-- EPCS
-----------------------------------------------------------------------------
@@ -622,7 +608,6 @@ begin
reg_mmdp_data_miso <= c_mem_miso_rst;
end generate;
-
------------------------------------------------------------------------------
-- PPS input
------------------------------------------------------------------------------
@@ -702,7 +687,6 @@ begin
temp_alarm => temp_alarm
);
-
------------------------------------------------------------------------------
-- Ethernet 1GbE
------------------------------------------------------------------------------
@@ -725,11 +709,9 @@ begin
--On hardware always generate 1GbE for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
gen_eth1g : if g_sim = false or g_udp_offload = true generate
-
eth1g_st_clk <= dp_clk_in when g_udp_offload = true else mm_clk;
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
-
u_mac : entity eth_lib.eth
generic map (
g_technology => g_technology,
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
index dc25926e50f9ef58d722420409ad63ac1ccfb474..b6754497a9df7b060f29f3a9e7857ec10a2b674a 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_sens.vhd
@@ -28,7 +28,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
-
entity mms_unb1_board_sens is
generic (
g_sim : boolean := false;
@@ -54,9 +53,7 @@ entity mms_unb1_board_sens is
);
end mms_unb1_board_sens;
-
architecture str of mms_unb1_board_sens is
-
constant c_sens_nof_result : natural := 4; -- Should match nof read bytes via I2C in the unb1_board_sens_ctrl SEQUENCE list
constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
@@ -64,9 +61,7 @@ architecture str of mms_unb1_board_sens is
signal sens_data : t_slv_8_arr(0 to c_sens_nof_result - 1);
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
-
begin
-
u_unb1_board_sens_reg : entity work.unb1_board_sens_reg
generic map (
g_sens_nof_result => c_sens_nof_result,
@@ -113,6 +108,4 @@ begin
-- would produce -1 degrees so does not trigger a temperature alarm.
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '1' when (signed(sens_data(0)) > signed('0' & temp_high)) else '0';
-
end str;
-
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
index c5a41f645f8588a20eabc182f6c8c356a7f676b5..35016608694c658dc4ba2234c6ee3f4855414ee9 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/mms_unb1_board_system_info.vhd
@@ -62,9 +62,7 @@ entity mms_unb1_board_system_info is
);
end mms_unb1_board_system_info;
-
architecture str of mms_unb1_board_system_info is
-
-- Provide different prefixes (absolute and relative) for the same path. ModelSim understands $UNB, Quartus does not.
-- Required because the work paths of ModelSim and Quartus are different.
constant c_quartus_path_prefix : string := "";
@@ -84,9 +82,7 @@ architecture str of mms_unb1_board_system_info is
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
info <= i_info;
u_unb1_board_system_info: entity work.unb1_board_system_info
@@ -137,6 +133,4 @@ begin
rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
rd_val => rom_miso.rdval
);
-
end str;
-
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
index 08fd646a246ab3a27dfd2de2e9d6469ca2ef2155..f7ddc510062859aa916d7f5743157ee601e5a717 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/node_unb1_fn_terminal_db.vhd
@@ -122,7 +122,6 @@
-- removed to let all settings directly depend on g_bsn_latency. The
-- advantage is that it
-
library IEEE, common_lib, dp_lib, unb1_board_lib, diag_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -132,7 +131,6 @@ use dp_lib.dp_stream_pkg.all;
use unb1_board_lib.unb1_board_pkg.all;
use unb1_board_lib.unb1_board_peripherals_pkg.all;
-
entity node_unb1_fn_terminal_db is
generic(
g_sim : boolean := false;
@@ -199,7 +197,6 @@ entity node_unb1_fn_terminal_db is
end node_unb1_fn_terminal_db;
architecture str of node_unb1_fn_terminal_db is
-
-----------------------------------------------------------------------------
-- BSN align
-----------------------------------------------------------------------------
@@ -245,9 +242,7 @@ architecture str of node_unb1_fn_terminal_db is
-- Data buffer
-----------------------------------------------------------------------------
signal db_in_sosi_arr : t_dp_sosi_arr(g_usr_nof_streams - 1 downto 0);
-
begin
-
gen_mesh: if g_use_mesh = true generate
-----------------------------------------------------------------------------
-- Terminals
@@ -434,7 +429,5 @@ begin
-- Entity DP out
-----------------------------------------------------------------------------
dp_out_sosi_arr <= db_in_sosi_arr;
-
end generate;
-
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
index e7e030fc9e425c518a9636b2324bb216f9b5cc10..b3e77264270a51387859a01866e22ff72c27713a 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_io.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.unb1_board_pkg.all;
-
entity unb1_board_back_io is
generic (
g_bus_w : natural := 4
@@ -46,10 +45,8 @@ entity unb1_board_back_io is
);
end unb1_board_back_io;
-
architecture str of unb1_board_back_io is
begin
-
-- Map the serial streams to the back
wires : for I in 0 to g_bus_w - 1 generate
BN_BI_0_TX(I) <= tx_serial_2arr(0)(I);
@@ -64,15 +61,3 @@ begin
end generate;
end;
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
index f5d68d2f2c20b8de43002baca59ff4c0ee3f6e7e..8f32540b83c6c94ebffbfd2b5b331a084ff6851e 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_reorder.vhd
@@ -59,7 +59,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.unb1_board_pkg.all;
-
entity unb1_board_back_reorder is
port (
bck_id : in std_logic_vector(c_unb1_board_nof_uniboard_w - 1 downto 0);
@@ -81,11 +80,8 @@ entity unb1_board_back_reorder is
);
end unb1_board_back_reorder;
-
architecture rtl of unb1_board_back_reorder is
-
begin
-
p_comb : process(bck_id, tx_usr_sosi_2arr, rx_phy_sosi_2arr, rx_usr_siso_2arr, tx_phy_siso_2arr)
begin
-- Default set all IO to not used:
@@ -166,5 +162,4 @@ begin
when others => null;
end case;
end process;
-
end rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
index 54e4572ae61e500e09195b064191f84a5f1d3146..6aaadd11ea1fcea8cb001f040fb40ce135024ca9 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_select.vhd
@@ -63,11 +63,8 @@ entity unb1_board_back_select is
);
end unb1_board_back_select;
-
architecture rtl of unb1_board_back_select is
-
begin
-
p_sel: process(tx_usr_sosi_2arr, rx_usr_siso_2arr, tx_phy_siso_2arr, rx_phy_sosi_2arr, bck_id)
begin
-- Default pass on all busses between usr and phy...
@@ -86,5 +83,4 @@ begin
tx_phy_sosi_2arr(TO_UINT(bck_id)) <= (others => c_dp_sosi_x);
rx_phy_siso_2arr(TO_UINT(bck_id)) <= (others => c_dp_siso_x);
end process;
-
end rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
index 8d04d02cc64676feebd6ce1bb95705cee70b963e..1ee7f136478cfb001d46ccc8237c79f1ebe933a4 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_back_uth_terminals_bidir.vhd
@@ -77,14 +77,10 @@ entity unb1_board_back_uth_terminals_bidir is
);
end unb1_board_back_uth_terminals_bidir;
-
architecture str of unb1_board_back_uth_terminals_bidir is
-
constant c_tx_mux_mode : natural := 1; -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
constant c_rx_mux_mode : natural := 0; -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
-
begin
-
gen_bus : for I in 0 to c_unb1_board_tr_back.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
generic map (
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
index 87130a8e65f2c0ba61bf78ca9fb3afef762f0673..54d62c3a5def1be5cf5d2b3b32e667346ce45695 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk200_pll.vhd
@@ -135,9 +135,7 @@ entity unb1_board_clk200_pll is
);
end unb1_board_clk200_pll;
-
architecture stratix4 of unb1_board_clk200_pll is
-
constant c_reset_len : natural := c_meta_delay_len;
constant c_clk1_used : string := sel_a_b(g_clk_vec_w > 0, "PORT_USED", "PORT_UNUSED");
@@ -155,9 +153,7 @@ architecture stratix4 of unb1_board_clk200_pll is
signal st_locked : std_logic;
signal st_locked_n : std_logic;
-
begin
-
st_rst200 <= i_st_rst200;
st_clk200 <= i_st_clk200;
@@ -259,5 +255,4 @@ begin
clk => i_st_clk400,
out_rst => st_rst400
);
-
end stratix4;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
index f868d0815eaee3c8be73c80629f896a45999a2e2..f5684a4c5c866e8f11968beb953ac30f187a589c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk25_pll.vhd
@@ -50,10 +50,8 @@ entity unb1_board_clk25_pll is
);
end unb1_board_clk25_pll;
-
architecture stratixiv of unb1_board_clk25_pll is
begin
-
u_pll : entity tech_pll_lib.tech_pll_clk25
generic map (
g_technology => g_technology
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
index 8154e03d5b8eb9ef96d4e14feb7322bb7c6d0114..4498f945ae69c11320ddfe1a96de83c9ed05cb35 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_clk_rst.vhd
@@ -42,9 +42,7 @@ entity unb1_board_clk_rst is
);
end unb1_board_clk_rst;
-
architecture str of unb1_board_clk_rst is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
-- XO clock domain
@@ -52,9 +50,7 @@ architecture str of unb1_board_clk_rst is
-- SYS clock domain
signal sys_locked_n : std_logic;
-
begin
-
-- Reference clock and reset to SOPC system PLL
xo_rst_n <= not xo_rst;
@@ -82,5 +78,4 @@ begin
clk => sys_clk,
out_rst => sys_rst
);
-
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
index b5d260b21b6edce5654bdcede43a7270d19f8ca1..ce43144b74c4f5a0287591ac3fbecbad66a1bca6 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_front_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb1_board_pkg.all;
-
entity unb1_board_front_io is
generic (
g_nof_xaui : natural
@@ -56,13 +55,10 @@ entity unb1_board_front_io is
end unb1_board_front_io;
architecture str of unb1_board_front_io is
-
-- help signals so we can iterate through buses
signal si_fn_tx_arr : t_unb1_board_xaui_sl_2arr(c_unb1_board_tr_xaui.bus_w - 1 downto 0) := (others => (others => '0'));
signal si_fn_rx_arr : t_unb1_board_xaui_sl_2arr(c_unb1_board_tr_xaui.bus_w - 1 downto 0);
-
begin
-
-- XAUI buses
SI_FN_0_TX <= si_fn_tx_arr(0);
SI_FN_1_TX <= si_fn_tx_arr(1);
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
index f33599ea0ca50ef83fa823114c7af0501aea94ee..f16b3b3714b61fd33155b0e9e20b47225c1a6799 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_io.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.unb1_board_pkg.all;
-
entity unb1_board_mesh_io is
generic (
g_bus_w : natural := 3 -- use 4 to include the CMU transceives at port (3) else use 3 to only use the HW transceivers on port (2:0)
@@ -44,10 +43,8 @@ entity unb1_board_mesh_io is
);
end unb1_board_mesh_io;
-
architecture str of unb1_board_mesh_io is
begin
-
-- Map the serial streams to the mesh
wires : for I in 0 to g_bus_w - 1 generate
FN_BN_0_TX(I) <= tx_serial_2arr(0)(I);
@@ -62,15 +59,3 @@ begin
end generate;
end;
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
index 7a5783e637e7d97612297c539b524ba0adcc133e..28c28e6f37d7c579f208370edd249925e777aef4 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_bidir.vhd
@@ -139,7 +139,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.unb1_board_pkg.all;
-
entity unb1_board_mesh_reorder_bidir is
generic (
g_node_type : t_e_unb1_board_node := e_any; -- or e_fn, or e_bn
@@ -164,10 +163,8 @@ entity unb1_board_mesh_reorder_bidir is
);
end unb1_board_mesh_reorder_bidir;
-
architecture str of unb1_board_mesh_reorder_bidir is
begin
-
u_tx : entity work.unb1_board_mesh_reorder_tx
generic map (
g_node_type => g_node_type,
@@ -195,6 +192,4 @@ begin
rx_usr_sosi_2arr => rx_usr_sosi_2arr,
tx_usr_siso_2arr => tx_usr_siso_2arr
);
-
end str;
-
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
index 4957fde2406768f7395fb63b17c680665d548ac8..71b2ca81148443b5ee2188af3661006c96fc78a6 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_rx.vhd
@@ -37,7 +37,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.unb1_board_pkg.all;
-
entity unb1_board_mesh_reorder_rx is
generic (
g_node_type : t_e_unb1_board_node := e_any;
@@ -53,13 +52,9 @@ entity unb1_board_mesh_reorder_rx is
);
end unb1_board_mesh_reorder_rx;
-
architecture rtl of unb1_board_mesh_reorder_rx is
-
signal chip_id_i : std_logic_vector(chip_id'range);
-
begin
-
-- force chip_id(2) to '0' or '1' to reduce the case options in p_comb if the design will run only on a FN or only on a BN
chip_id_i <= func_unb1_board_chip_id(chip_id, g_node_type);
@@ -134,5 +129,4 @@ begin
end case;
end if;
end process;
-
end rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
index ef2d9e406c9f1d44ecce6900287334174b0bf7ed..7fe1309d411ffe2e996a2656772676fc7634a219 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_reorder_tx.vhd
@@ -37,7 +37,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.unb1_board_pkg.all;
-
entity unb1_board_mesh_reorder_tx is
generic (
g_node_type : t_e_unb1_board_node := e_any;
@@ -53,14 +52,10 @@ entity unb1_board_mesh_reorder_tx is
);
end unb1_board_mesh_reorder_tx;
-
architecture rtl of unb1_board_mesh_reorder_tx is
-
signal chip_id_reg : std_logic_vector(chip_id'range);
signal chip_id_i : std_logic_vector(chip_id'range);
-
begin
-
-- Register the chip_id from FPGA pins to ease timing closure.
-- . Alternatively these registers may better be removed and pin input chip_id[] set as false path for timing closure
u_chip_id : entity common_lib.common_pipeline
@@ -152,5 +147,4 @@ begin
end case;
end if;
end process;
-
end rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
index 23e79b3b51d8b682ff99dca63a6de96031680744..a4259a7adea7c7e99a672f4afb6a6cf2127f1b6b 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_mesh_uth_terminals_bidir.vhd
@@ -84,14 +84,10 @@ entity unb1_board_mesh_uth_terminals_bidir is
);
end unb1_board_mesh_uth_terminals_bidir;
-
architecture str of unb1_board_mesh_uth_terminals_bidir is
-
constant c_tx_mux_mode : natural := 0; -- can use 0 for non-blocking tx mux in dp_distribute or use 1 to preserve input order for tx
constant c_rx_mux_mode : natural := 0; -- must use 0 for non-blocking rx mux in dp_distribute (can not use 1 to preserve input order for rx, because some rx frames may go lost)
-
begin
-
gen_uth_terminal_bidir : for I in 0 to c_unb1_board_tr_mesh.nof_bus - 1 generate
u_uth_terminal_bidir : entity uth_lib.uth_terminal_bidir
generic map (
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
index 39383ca4e8cf79cf111c535ef6e46115d199607b..d5644e7de883ffe3e3e1cd1b9fe0caa76f9fd6ee 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_node_ctrl.vhd
@@ -55,16 +55,12 @@ entity unb1_board_node_ctrl is
);
end unb1_board_node_ctrl;
-
architecture str of unb1_board_node_ctrl is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
signal i_sys_rst : std_logic;
signal i_pulse_ms : std_logic;
-
begin
-
sys_rst <= i_sys_rst;
pulse_ms <= i_pulse_ms;
@@ -125,5 +121,4 @@ begin
wdi_in => wdi_in,
wdi_out => wdi_out
);
-
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
index 5cf82154fec9ab80235ab36a4388f1701b01898e..d524e5a62326d474ef631bf8ea9bd9333f760fe2 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_peripherals_pkg.vhd
@@ -42,8 +42,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package unb1_board_peripherals_pkg is
-
-
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb1_board_peripherals_mm_reg is record
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
index 086c5a29f0af06e777e9e5ae468d203b1d93ef39..180b535b22becf962ec54fbf906e62071c0757a8 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_pkg.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
package unb1_board_pkg is
-
-- UniBoard
constant c_unb1_board_nof_node : natural := 4; -- nof FN or nof BN on UniBoard
constant c_unb1_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb1_board_nof_node)
@@ -290,9 +289,7 @@ package unb1_board_pkg is
end unb1_board_pkg;
-
package body unb1_board_pkg is
-
function func_unb1_board_system_info(VERSION : in std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0);
ID : in std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0)) return t_c_unb1_board_system_info is
variable v_system_info : t_c_unb1_board_system_info;
@@ -320,7 +317,6 @@ package body unb1_board_pkg is
return v_chip_id;
end;
-
------------------------------------------------------------------------------
-- Connect mesh 2arr - back 2arr
------------------------------------------------------------------------------
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
index 572c988f6c007437b0e7c66007facb0159dceee6..ac56d4d4b26382c050acbec406dfede7432a5479 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use i2c_lib.i2c_pkg.all;
-
entity unb1_board_sens is
generic (
g_sim : boolean := false;
@@ -46,9 +45,7 @@ entity unb1_board_sens is
);
end entity;
-
architecture str of unb1_board_sens is
-
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
@@ -63,9 +60,7 @@ architecture str of unb1_board_sens is
signal smbus_out_err : std_logic;
signal smbus_out_ack : std_logic;
signal smbus_out_end : std_logic;
-
begin
-
u_unb1_board_sens_ctrl : entity work.unb1_board_sens_ctrl
generic map (
g_sim => g_sim,
@@ -106,5 +101,4 @@ begin
scl => scl,
sda => sda
);
-
end architecture;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
index 6e8d2bb9f749e3d1d180c8fa5cb44064f3ce7f18..a9747754f1745d8a09223b4dc012ea48eb23212c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_ctrl.vhd
@@ -26,7 +26,6 @@ use i2c_lib.i2c_dev_max1617_pkg.all;
use i2c_lib.i2c_dev_ltc4260_pkg.all;
use common_lib.common_pkg.all;
-
entity unb1_board_sens_ctrl is
generic (
g_sim : boolean := false;
@@ -50,9 +49,7 @@ entity unb1_board_sens_ctrl is
);
end entity;
-
architecture rtl of unb1_board_sens_ctrl is
-
-- I2C slave addresses of the devices on the I2C bus on UniBoard
constant FPGA_MAX1617_ADR : natural := MAX1617_ADR_LOW_LOW; -- FPGA temperature sensor, slave address is "0011000"
constant ETH_MAX1617_ADR : natural := MAX1617_ADR_MID_LOW; -- ETH temperature sensor, slave address is "0101001"
@@ -100,9 +97,7 @@ architecture rtl of unb1_board_sens_ctrl is
signal nxt_result_err : std_logic;
signal i_result_dat : t_slv_8_arr(result_dat'range);
signal nxt_result_dat : t_slv_8_arr(result_dat'range);
-
begin
-
result_dat <= i_result_dat;
regs: process(rst, clk)
@@ -171,5 +166,4 @@ begin
nxt_result_val <= rx_val;
nxt_result_err <= rx_err;
nxt_result_dat <= rx_dat when rx_val = '1' else i_result_dat;
-
end rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
index 0ef3eb536c6ea335c6de1ec8249205238f9944cd..43e27b565f8525aff904d8dad008a0f5714278f7 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_sens_reg.vhd
@@ -89,9 +89,7 @@ entity unb1_board_sens_reg is
);
end unb1_board_sens_reg;
-
architecture rtl of unb1_board_sens_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
-- +1 to fit sens_err in the last address
@@ -103,9 +101,7 @@ architecture rtl of unb1_board_sens_reg is
init_sl => '0');
signal i_temp_high : std_logic_vector(6 downto 0);
-
begin
-
temp_high <= i_temp_high;
------------------------------------------------------------------------------
@@ -158,5 +154,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
index 4a653cd7766caa01c875d3f5bb93146fa1506fe9..06b60254c051f75626dc4214d5d74b4cf1c8869f 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info.vhd
@@ -51,9 +51,7 @@ entity unb1_board_system_info is
);
end unb1_board_system_info;
-
architecture str of unb1_board_system_info is
-
signal cs_sim : std_logic;
signal hw_version_reg : std_logic_vector(hw_version'range);
@@ -65,9 +63,7 @@ architecture str of unb1_board_system_info is
signal nxt_node_id : std_logic_vector(node_id'range);
signal nxt_is_bn : std_logic;
signal nxt_is_bn3 : std_logic;
-
begin
-
p_reg : process(clk)
begin
if rising_edge(clk) then
@@ -102,5 +98,4 @@ begin
nxt_node_id <= id_reg(1 downto 0);
nxt_is_bn <= id_reg(2);
nxt_is_bn3 <= '1' when TO_UINT(id_reg(2 downto 0)) = 7 else '0';
-
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
index f8bc591fea0c1075f4919f956fca94d9ff2b384f..594354d35e7a30d3ea330b3020a46e422530eea1 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_system_info_reg.vhd
@@ -72,9 +72,7 @@ entity unb1_board_system_info_reg is
);
end unb1_board_system_info_reg;
-
architecture rtl of unb1_board_system_info_reg is
-
constant c_nof_fixed_regs : natural := 2; -- info, use_phy
constant c_nof_design_name_regs : natural := 13; -- design_name
constant c_nof_stamp_regs : natural := 3; -- date, time, svn rev
@@ -100,9 +98,7 @@ architecture rtl of unb1_board_system_info_reg is
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
begin
@@ -140,13 +136,8 @@ begin
elsif vA < c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs then
sla_out.rddata(c_word_w - 1 downto 0) <= c_design_note(vA - c_nof_fixed_regs - c_nof_design_name_regs - c_nof_stamp_regs);
-
end if;
-
end if;
end if;
end process;
-
-
end rtl;
-
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
index 5fc47736ae0f406b965eb1063d9164af3c0d6855..d0e464d77e299726b0f8d7fa82147d577b6578ba 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_back.vhd
@@ -43,7 +43,6 @@ use dp_lib.dp_stream_pkg.all;
use dp_lib.dp_packet_pkg.all;
use uth_lib.uth_pkg.all;
-
entity unb1_board_terminals_back is
generic (
g_sim : boolean := false;
@@ -99,9 +98,7 @@ entity unb1_board_terminals_back is
);
end unb1_board_terminals_back;
-
architecture str of unb1_board_terminals_back is
-
-- DP/UTH packet
constant c_packet_data_w : natural := g_usr_data_w; -- = 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w
@@ -137,9 +134,7 @@ architecture str of unb1_board_terminals_back is
signal tx_serial_arr : std_logic_vector(c_nof_gx - 1 downto 0);
signal rx_serial_arr : std_logic_vector(c_nof_gx - 1 downto 0);
-
begin
-
u_unb1_board_back_select: entity work.unb1_board_back_select
port map (
bck_id => bck_id,
@@ -273,5 +268,4 @@ begin
diagnostics_mm_mosi => reg_diagnostics_mosi,
diagnostics_mm_miso => reg_diagnostics_miso
);
-
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
index db68198b49d6622df568cd142f1360ae7734c7eb..b65dc635d740a2feb41f36c9ea01d9f6f5a088b7 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_terminals_mesh.vhd
@@ -48,7 +48,6 @@
-- must match the g_reorder setting for unb1_board_mesh_model_*.vhd. On
-- hardware use the default g_phy_ena_reorder = TRUE.
-
library IEEE, common_lib, dp_lib, uth_lib, tr_nonbonded_lib, diag_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -59,7 +58,6 @@ use dp_lib.dp_stream_pkg.all;
use dp_lib.dp_packet_pkg.all;
use uth_lib.uth_pkg.all;
-
entity unb1_board_terminals_mesh is
generic (
g_sim : boolean := false;
@@ -136,9 +134,7 @@ entity unb1_board_terminals_mesh is
);
end unb1_board_terminals_mesh;
-
architecture str of unb1_board_terminals_mesh is
-
-- DP/UTH packet
constant c_packet_data_w : natural := 32; -- fixed 32, packet data width for DP packet and for UTH packet, must be >= g_usr_data_w to avoid need for data packing
@@ -188,9 +184,7 @@ architecture str of unb1_board_terminals_mesh is
signal tx_serial_arr : std_logic_vector(c_phy_nof_gx - 1 downto 0);
signal rx_serial_arr : std_logic_vector(c_phy_nof_gx - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- g_mon_select
------------------------------------------------------------------------------
@@ -202,6 +196,7 @@ begin
end generate;
end generate;
end generate;
+
mon_rx_term_uth : if g_mon_select = 2 generate
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
@@ -209,6 +204,7 @@ begin
end generate;
end generate;
end generate;
+
mon_rx_term_pkt : if g_mon_select = 3 generate
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
@@ -216,6 +212,7 @@ begin
end generate;
end generate;
end generate;
+
mon_rx_term_dist : if g_mon_select = 4 generate
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
gen_j : for J in 0 to g_usr_nof_streams - 1 generate
@@ -223,6 +220,7 @@ begin
end generate;
end generate;
end generate;
+
mon_tx_mesh : if g_mon_select = 5 generate
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
@@ -230,6 +228,7 @@ begin
end generate;
end generate;
end generate;
+
mon_tx_term_uth : if g_mon_select = 6 generate
gen_i : for I in 0 to c_unb1_board_tr.nof_bus - 1 generate
gen_j : for J in 0 to g_phy_nof_serial - 1 generate
@@ -350,7 +349,6 @@ begin
tx_usr_siso_2arr => tx_term_siso_2arr -- g_use_tx
);
-
------------------------------------------------------------------------------
-- GX serial interface level (g_sim_level)
------------------------------------------------------------------------------
@@ -409,6 +407,4 @@ begin
diagnostics_mm_mosi => reg_diagnostics_mosi,
diagnostics_mm_miso => reg_diagnostics_miso
);
-
end str;
-
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
index 20437a399b8f4da203891c68ce42d49b83784218..5bc2d1698e2f30dff83d3194158162ed750a55a2 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_extend.vhd
@@ -43,9 +43,7 @@ entity unb1_board_wdi_extend is
);
end unb1_board_wdi_extend;
-
architecture str of unb1_board_wdi_extend is
-
signal wdi_evt : std_logic;
signal wdi_cnt : std_logic_vector(g_extend_w - 1 downto 0);
@@ -53,9 +51,7 @@ architecture str of unb1_board_wdi_extend is
signal i_wdi_out : std_logic;
signal nxt_wdi_out : std_logic;
-
begin
-
wdi_out <= i_wdi_out;
p_clk : process(rst, clk)
@@ -94,5 +90,4 @@ begin
cnt_en => wdi_cnt_en,
count => wdi_cnt
);
-
end str;
diff --git a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
index d03edab58d070f07460f2b65b56c626106051436..8645f86e8f80ca85685e98d3edef549b275d5a9c 100644
--- a/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/src/vhdl/unb1_board_wdi_reg.vhd
@@ -43,9 +43,7 @@ entity unb1_board_wdi_reg is
);
end unb1_board_wdi_reg;
-
architecture rtl of unb1_board_wdi_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
@@ -55,9 +53,7 @@ architecture rtl of unb1_board_wdi_reg is
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -82,9 +78,6 @@ begin
when others => null; -- unused MM addresses
end case;
end if;
-
end if;
end process;
-
end rtl;
-
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
index 0de4b7a3434aecd9579a31faa58a6fb83dd050f9..ca4d940d7bb06aeace52fde1a3d53c77a8550a22 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_mms_unb1_board_sens.vhd
@@ -38,9 +38,7 @@ use common_lib.common_mem_pkg.all;
use common_lib.tb_common_pkg.all;
use common_lib.tb_common_mem_pkg.all;
-
architecture tb of tb_mms_unb1_board_sens is
-
constant c_sim : boolean := true; -- FALSE;
constant c_repeat : natural := 2;
constant c_clk_freq : natural := 100 * 10**6;
@@ -77,9 +75,7 @@ architecture tb of tb_mms_unb1_board_sens is
signal scl_stretch : std_logic := 'Z';
signal scl : std_logic;
signal sda : std_logic;
-
begin
-
rst <= '0' after 4 * c_clk_period;
clk <= (not clk) or tb_end after c_clk_period / 2;
@@ -147,10 +143,8 @@ begin
assert TO_UINT(sens_dat) = c_sens_expected(3) report "Wrong hot swap V source value" severity ERROR;
proc_common_wait_some_cycles(clk, 1);
assert TO_UINT(sens_dat) = c_sens_expected(4) report "An I2C error occurred" severity ERROR;
-
end process;
-
-- I2C sensors master
u_mms_unb1_board_sens : entity work.mms_unb1_board_sens
generic map (
@@ -207,6 +201,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
-
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
index 59732556ad2edcd5774c9d8573708c0b13ed7810..f489d4b5d4fbd2961b7a502c764f3e3eecb93b8e 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_tb_tb_unb1_board_regression.vhd
@@ -34,8 +34,6 @@ end tb_tb_tb_unb1_board_regression;
architecture tb of tb_tb_tb_unb1_board_regression is
begin
-
u_tb_mms_unb1_board_sens : entity work.tb_mms_unb1_board_sens;
u_tb_unb1_board_mesh_reorder_bidir : entity work.tb_unb1_board_mesh_reorder_bidir;
-
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
index 820d767d9ae394a79698ad2fdfe8a363ef15e256..c30e88c962f588450e0ebe8fe699809b789ffd3f 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_clk200_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb1_board_clk200_pll is
end tb_unb1_board_clk200_pll;
-
architecture tb of tb_unb1_board_clk200_pll is
-
constant c_ext_clk_period : time := 5 ns; -- 200 MHz
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
@@ -65,9 +61,7 @@ architecture tb of tb_unb1_board_clk200_pll is
signal dp_rst200 : std_logic;
signal st_clk_vec : std_logic_vector(c_clk_vec_w - 1 downto 0); -- PLL c6-c1
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
@@ -138,5 +132,4 @@ begin
-- . g_sel=1
st_clk_vec => st_clk_vec
);
-
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
index 050793a9a417c5a361c5432625a64d6cee4115ea..1eaa6aa8070c062fe3b18135e3703eea919e7181 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_mesh_reorder_bidir.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose:
-- 1) Verify unb1_board_mesh_reorder_bidir for SOSI using the unb1_board_mesh_model_sosi
-- 2) Verify unb1_board_mesh_reorder_bidir for SISO using the unb1_board_mesh_model_siso
@@ -40,7 +39,6 @@
-- reordering on the PCB. Default use c_reorder=TRUE to also model the
-- transceiver bus reorderings on UniBoard PCB.
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -49,13 +47,10 @@ use dp_lib.dp_stream_pkg.all;
use work.unb1_board_pkg.all;
use work.tb_unb1_board_pkg.all;
-
entity tb_unb1_board_mesh_reorder_bidir is
end tb_unb1_board_mesh_reorder_bidir;
-
architecture tb of tb_unb1_board_mesh_reorder_bidir is
-
constant c_reorder : boolean := true;
constant c_chip_id_w : natural := c_unb1_board_aux.chip_id_w; -- = 3 to fit 8 fpgas in [2:0]
@@ -133,9 +128,7 @@ architecture tb of tb_unb1_board_mesh_reorder_bidir is
-- . User domain driving stimuli signals
signal fn_rx_usr_siso_3arr : t_unb1_board_mesh_siso_3arr := (others => (others => (others => c_dp_siso_rst)));
signal bn_rx_usr_siso_3arr : t_unb1_board_mesh_siso_3arr := (others => (others => (others => c_dp_siso_rst)));
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
------------------------------------------------------------------------------
@@ -176,7 +169,6 @@ begin
end loop;
end loop;
end loop;
-
end loop;
proc_common_wait_some_cycles(clk, 100);
@@ -184,7 +176,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- Monitor and verify
------------------------------------------------------------------------------
@@ -223,7 +214,6 @@ begin
end if;
end process;
-
------------------------------------------------------------------------------
-- UniBoard FN0,1,2,3
------------------------------------------------------------------------------
@@ -253,7 +243,6 @@ begin
);
end generate;
-
------------------------------------------------------------------------------
-- Mesh between FN0,1,2,3 and BN0,1,2,3 as it is wired on the UniBoard PCB
------------------------------------------------------------------------------
@@ -306,7 +295,6 @@ begin
end if;
end process;
-
-- >>> unb1_board_mesh_model_sosi
u_pcb_mesh_sosi : entity work.unb1_board_mesh_model_sosi
@@ -337,7 +325,6 @@ begin
fn3_rx_sosi_2arr => fn_rx_phy_sosi_3arr(3)
);
-
-- >>> unb1_board_mesh_model_siso
u_pcb_mesh_siso : entity work.unb1_board_mesh_model_siso
@@ -368,7 +355,6 @@ begin
fn3_tx_siso_2arr => fn_tx_phy_siso_3arr(3)
);
-
------------------------------------------------------------------------------
-- UniBoard BN0,1,2,3
------------------------------------------------------------------------------
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
index 5b8ebe20f3777cb148109b0612b6d695ef15812a..de88c784052fc566fbc1eb57b3421a3d233e5bdb 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_node_ctrl.vhd
@@ -24,13 +24,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb1_board_node_ctrl is
end tb_unb1_board_node_ctrl;
-
architecture tb of tb_unb1_board_node_ctrl is
-
constant c_scale : natural := 100; -- scale to speed up simulation
constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
@@ -65,9 +62,7 @@ architecture tb of tb_unb1_board_node_ctrl is
signal pulse_us : std_logic;
signal pulse_ms : std_logic;
signal pulse_s : std_logic;
-
begin
-
-- run 2000 ms
xo_clk <= not xo_clk after c_xo_clk_period / 2;
@@ -99,5 +94,4 @@ begin
pulse_ms => pulse_ms,
pulse_s => pulse_s
);
-
end tb;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
index 2b119ed295635045b653c6c1447b59f9afdd9d0e..f404f0a478c97d124b41261aa6adcb672de693b8 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/tb_unb1_board_pkg.vhd
@@ -28,7 +28,6 @@ use dp_lib.dp_stream_pkg.all;
use work.unb1_board_pkg.all;
package tb_unb1_board_pkg is
-
-- Aggregate types to contain all TR for all nodes on one side of the mesh or backplane interface
-- UniBoard TR mesh IO for 4 to 4 nodes : [node][bus][lane]
@@ -54,6 +53,5 @@ package tb_unb1_board_pkg is
type t_unb1_board_id_arr is array (natural range <>) of std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0);
end tb_unb1_board_pkg;
-
package body tb_unb1_board_pkg is
end tb_unb1_board_pkg;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
index 195d05a17d6ee7159788968c8c351bdffd7bcb12..59579fcd400bcbb69b4f32f9db8e55211e2480ef 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sl.vhd
@@ -48,13 +48,9 @@ entity unb1_board_back_model_sl is
);
end unb1_board_back_model_sl;
-
architecture beh of unb1_board_back_model_sl is
-
begin
-
gen_bn : for BN in 0 to c_unb1_board_nof_bn - 1 generate
-
----------------------------------------------------------------------------
-- Interconnect BN --> BN streaming with actual backplane routing
----------------------------------------------------------------------------
@@ -80,7 +76,6 @@ begin
-- | | Transmitting UniBoard
-- | Same scheme applies to all back nodes
-- Receiving UniBoard
-
end generate;
end beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
index bfd7635362d4a4178f12965355c850e38cfaf2f0..6262f52ab7711cb61a488128ea3ad22a12e0dfe7 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_back_model_sosi.vhd
@@ -24,7 +24,6 @@
-- Description:
-- Model the backplane at sosi level. See unb1_board_back_model_sl for more details.
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use dp_lib.dp_stream_pkg.all;
@@ -39,13 +38,9 @@ entity unb1_board_back_model_sosi is
);
end unb1_board_back_model_sosi;
-
architecture beh of unb1_board_back_model_sosi is
-
begin
-
gen_bn : for BN in 0 to c_unb1_board_nof_bn - 1 generate
-
----------------------------------------------------------------------------
-- Interconnect BN --> BN streaming with actual backplane routing
----------------------------------------------------------------------------
@@ -71,7 +66,6 @@ begin
-- | | Transmitting UniBoard
-- | Same scheme applies to all back nodes
-- Receiving UniBoard
-
end generate;
end beh;
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
index b7a65aa7a534cb8654b9ca8ecb539c92286a2bfc..c186f45bb476e7f843cdff7ffbc25496406a61b1 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_siso.vhd
@@ -30,7 +30,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.unb1_board_pkg.all;
-
entity unb1_board_mesh_model_siso is
generic (
g_reorder : boolean := true
@@ -60,10 +59,8 @@ entity unb1_board_mesh_model_siso is
);
end unb1_board_mesh_model_siso;
-
architecture beh of unb1_board_mesh_model_siso is
begin
-
-- Functional mesh connect for transpose
no_reorder : if g_reorder = false generate
-- BN(i)(j) <= FN(j)(i)
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
index 1eb7f377b536177886090c845b18853d2eed9269..11019e63c4c6db0e5fa6280786b6ca49c7c64b18 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sl.vhd
@@ -32,7 +32,6 @@ use dp_lib.dp_stream_pkg.all;
use work.unb1_board_pkg.all;
use work.tb_unb1_board_pkg.all;
-
entity unb1_board_mesh_model_sl is
generic (
g_reorder : boolean := true
@@ -48,10 +47,8 @@ entity unb1_board_mesh_model_sl is
);
end unb1_board_mesh_model_sl;
-
architecture beh of unb1_board_mesh_model_sl is
begin
-
-- Functional mesh connect for transpose
no_reorder : if g_reorder = false generate
-- BN(i)(j) <= FN(j)(i)
diff --git a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
index 16a1b0166ed973c56091f19b8203f12cf625cb03..17a37b3c881936f1a33457affc22e200b3e28df2 100644
--- a/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
+++ b/boards/uniboard1/libraries/unb1_board/tb/vhdl/unb1_board_mesh_model_sosi.vhd
@@ -30,7 +30,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.unb1_board_pkg.all;
-
entity unb1_board_mesh_model_sosi is
generic (
g_reorder : boolean := true
@@ -60,10 +59,8 @@ entity unb1_board_mesh_model_sosi is
);
end unb1_board_mesh_model_sosi;
-
architecture beh of unb1_board_mesh_model_sosi is
begin
-
-- Functional mesh connect for transpose
no_reorder : if g_reorder = false generate
-- BN(i)(j) <= FN(j)(i)
diff --git a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
index 8974e7b86e0b3516105cebbe017b29d93585abd8..ebe9c5d3e787e0ac953101ca9ea487f6c94d337b 100644
--- a/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/src/vhdl/unb2_led.vhd
@@ -48,9 +48,7 @@ entity unb2_led is
);
end unb2_led;
-
architecture str of unb2_led is
-
-- Firmware version x.y
constant c_fw_version : t_unb2_board_fw_version := (1, 1);
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
@@ -87,7 +85,6 @@ architecture str of unb2_led is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
xo_ethclk <= i_xo_ethclk;
xo_rst <= i_xo_rst;
@@ -162,7 +159,6 @@ begin
led_flash_red <= sel_a_b(g_factory_image = true, led_flash, '0');
led_flash_green <= sel_a_b(g_factory_image = false, led_flash, '0');
-
u_extend : common_lib.common_pulse_extend
generic map (
g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
@@ -174,17 +170,12 @@ begin
ep_out => led_flash
);
-
-
-
-- Red LED control
TESTIO(c_unb2_board_testio_led_red) <= led_flash_red;
-- Green LED control
TESTIO(c_unb2_board_testio_led_green) <= led_flash_green;
-
-
u_common_pulser_10Hz : entity common_lib.common_pulser
generic map (
g_pulse_period => 100,
@@ -227,6 +218,4 @@ begin
QSFP_LED(1) <= '1';
QSFP_LED(5) <= '1';
QSFP_LED(9) <= '1';
-
end str;
-
diff --git a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
index 63962939ea17bd9ea8cf53fc325b65126d2c2d39..71ff33a36be4bde8faadd07cc53b7d83f610e40f 100644
--- a/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
+++ b/boards/uniboard2/designs/unb2_led/tb/vhdl/tb_unb2_led.vhd
@@ -54,7 +54,6 @@ entity tb_unb2_led is
end tb_unb2_led;
architecture tb of tb_unb2_led is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -66,9 +65,7 @@ architecture tb of tb_unb2_led is
signal eth_clk : std_logic := '0';
signal TESTIO : std_logic_vector(c_unb2_board_aux.testio_w - 1 downto 0);
signal qsfp_led : std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -90,5 +87,4 @@ begin
TESTIO => TESTIO,
QSFP_LED => qsfp_led
);
-
end tb;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
index 3e498fbde532082d3b89cd345d034ea8aabbd443..2bd1ab97d597736b53b76506cb5b59a2d9c06e35 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/mmm_unb2_minimal.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_unb2_minimal_pkg.all;
-
entity mmm_unb2_minimal is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -102,19 +101,15 @@ entity mmm_unb2_minimal is
end mmm_unb2_minimal;
architecture str of mmm_unb2_minimal is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -148,7 +143,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
index 7f2a14415bbaa9805d689ff755947e184fb87bfc..305c225eae2455dcf6574d3992aa4340e2dfd4fe 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/qsys_unb2_minimal_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2_minimal_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v14 QSYS builder
-----------------------------------------------------------------------------
diff --git a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
index 3671e774db3d006dbec17a4d3c4dcb522336326b..c0ae33a4c217ae760f46c77bea8ca1b18d5a84e8 100644
--- a/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/src/vhdl/unb2_minimal.vhd
@@ -71,9 +71,7 @@ entity unb2_minimal is
);
end unb2_minimal;
-
architecture str of unb2_minimal is
-
-- Firmware version x.y
constant c_fw_version : t_unb2_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_50M;
@@ -153,9 +151,7 @@ architecture str of unb2_minimal is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -375,6 +371,4 @@ begin
-- red_led_arr => qsfp_red_led_arr,
-- QSFP_LED => QSFP_LED
-- );
-
end str;
-
diff --git a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
index f4bc5b2a068edeb73bba2a5de4241d6d3eabc5b6..5f1ebd006c75218dd65ffee60766d2b82c741210 100644
--- a/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
+++ b/boards/uniboard2/designs/unb2_minimal/tb/vhdl/tb_unb2_minimal.vhd
@@ -58,7 +58,6 @@ entity tb_unb2_minimal is
end tb_unb2_minimal;
architecture tb of tb_unb2_minimal is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -110,9 +109,7 @@ architecture tb of tb_unb2_minimal is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -216,5 +213,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index 0890ad356b63a63d02c07feaf838c0d8ee6b7fe9..24a8174ff6cb64308949e445ebd127229d2e1b41 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -26,7 +26,6 @@ use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-
entity unb2_pinning is
port (
@@ -139,12 +138,9 @@ entity unb2_pinning is
TESTIO : inout std_logic_vector(5 downto 0);
QSFP_LED : inout std_logic_vector(11 downto 0)
);
-
end unb2_pinning;
-
architecture str of unb2_pinning is
-
component ddr4 is
port (
global_reset_n : in std_logic := 'X'; -- reset_n
@@ -302,7 +298,6 @@ architecture str of unb2_pinning is
);
end component sys_clkctrl;
-
component system_pll is
port (
refclk : in std_logic := 'X'; -- clk
@@ -492,9 +487,7 @@ architecture str of unb2_pinning is
signal qsfp_led_out : std_logic_vector(11 downto 0);
signal bck_err_out : std_logic_vector(2 downto 0);
signal ver_id_pmbusalert : std_logic_vector(11 downto 0);
-
begin
-
WDI <= 'Z';
-- ****** DDR4 memory controllers ******
@@ -635,7 +628,6 @@ begin
amm_readdatavalid_0 => local_ii_read_data_valid
);
-
-- -- ****** Front side transceivers ******
--
RING_0_TX <= tx_serial_data_front(47 downto 36);
@@ -651,7 +643,6 @@ begin
& QSFP_0_RX & QSFP_1_RX & QSFP_2_RX & QSFP_3_RX & QSFP_4_RX & QSFP_5_RX
& RING_1_RX;
-
transceiver_phy_front : transceiver_phy
port map (
tx_analogreset => tx_analogreset_front,
@@ -789,7 +780,6 @@ begin
-- lower 24 transceivers use sb_clk
-
transceiver_phy_back_lower : transceiver_phy_24channel
port map (
tx_analogreset => tx_analogreset_back(23 downto 0),
@@ -881,7 +871,6 @@ begin
outclk => CLK_buffered -- altclkctrl_output.outclk
);
-
u_system_pll : system_pll
port map(
-- refclk => ETH_CLK,
@@ -905,7 +894,6 @@ begin
-- outclk2 => clk_125 -- 125MHz for 1ge
-- );
-
-- ****** i2c interfaces ******
u_qsys : unb2_pinning_qsys
@@ -997,5 +985,4 @@ begin
bck_err_out(0) <= bck_err_in(2);
ver_id_pmbusalert <= version & id & pmbus_alert & mb_event;
-
end str;
diff --git a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
index fb173d75bafd9d5ef8e02d000c0eb7bff1dfb4b9..8f346a6f27cd7e3c42e7cd900c8702cbe0dceea8 100644
--- a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
+++ b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
@@ -26,7 +26,6 @@ use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-
entity unb2_singlemac is
port (
@@ -121,14 +120,9 @@ entity unb2_singlemac is
TESTIO : inout std_logic_vector(5 downto 0);
QSFP_LED : inout std_logic_vector(11 downto 0)
);
-
end unb2_singlemac;
-
architecture str of unb2_singlemac is
-
-
-
component system_iopll is
port (
refclk : in std_logic := 'X'; -- clk
@@ -159,7 +153,6 @@ architecture str of unb2_singlemac is
);
end component;
-
component ip_arria10_mac_10g is
port (
csr_read : in std_logic := 'X'; -- read
@@ -218,7 +211,6 @@ architecture str of unb2_singlemac is
signal mm_clk : std_logic := '0';
signal clk_125 : std_logic := '0';
-
-- signals for the transceivers
signal tx_serial_data_front : std_logic_vector(0 downto 0);
signal rx_serial_data_front : std_logic_vector(0 downto 0);
@@ -243,7 +235,6 @@ architecture str of unb2_singlemac is
signal reg_mac_wrdata : std_logic_vector(31 downto 0);
signal reg_mac_address : std_logic_vector(12 downto 0);
-
-- signals for the bidirectional and misc ios
signal inta_in : std_logic;
signal intb_in : std_logic;
@@ -259,9 +250,7 @@ architecture str of unb2_singlemac is
signal toggle_count : std_logic_vector(31 downto 0);
signal toggle_count1 : std_logic_vector(31 downto 0);
signal led_state : std_logic;
-
begin
-
WDI <= 'Z';
-- -- ****** Front side transceivers and MAC ******
@@ -329,7 +318,6 @@ begin
avalon_st_rxstatus_error => open
);
-
-- ****** node control for resets and wdi
u_node_ctrl : entity unb_common_lib.unb_node_ctrl
@@ -363,7 +351,6 @@ begin
outclk_2 => clk_125 -- 125MHz for 1ge
);
-
-- bidirectional and misc
-- use PPS as output enable
@@ -392,7 +379,6 @@ begin
bck_err_out(1) <= bck_err_in(0);
bck_err_out(0) <= bck_err_in(2);
-
ver_id_pmbusalert <= version & id & pmbus_alert;
toggle_led_proc: process(mm_clk, reset_p)
@@ -424,5 +410,4 @@ begin
end if;
end if;
end process;
-
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
index f036f26b7d2f44d26fc4675caceff4211677b4b0..aa7c4a89fa5d2a486444c2e35025e7870e698116 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/tb_unb2_test_10GbE.vhd
@@ -23,11 +23,9 @@
library IEEE, unb2_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2_test_10GbE is
end tb_unb2_test_10GbE;
-
architecture tb of tb_unb2_test_10GbE is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
@@ -35,4 +33,3 @@ begin
g_design_name => "unb2_test_10GbE"
);
end tb;
-
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
index 0ece6a1e7b51b0c5bf7c48f87631425c4767e6f2..3fbb7d4604baf0a97b9f0e4dfa79204d605658c5 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_10GbE/unb2_test_10GbE.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2_test_10GbE is
generic (
g_design_name : string := "unb2_test_10GbE";
@@ -107,9 +106,7 @@ entity unb2_test_10GbE is
);
end unb2_test_10GbE;
-
architecture str of unb2_test_10GbE is
-
begin
u_revision : entity unb2_test_lib.unb2_test
generic map (
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
index 91c249b522cdc574150ec8ba5ff78141c7a8964f..3d56ebd96f5575db9fa150a6220db6377c5bf2db 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/tb_unb2_test_1GbE.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2_test_1GbE is
end tb_unb2_test_1GbE;
-
architecture tb of tb_unb2_test_1GbE is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
@@ -37,4 +33,3 @@ begin
g_design_name => "unb2_test_1GbE"
);
end tb;
-
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
index 8cd5538d0dc93ff673f1a5ae8a1055cfa70ed9ae..d80b47e0e24b0d05e1cb16aa34a0f3fccc1682e2 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_1GbE/unb2_test_1GbE.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2_test_1GbE is
generic (
g_design_name : string := "unb2_test_1GbE";
@@ -69,11 +68,8 @@ entity unb2_test_1GbE is
);
end unb2_test_1GbE;
-
architecture str of unb2_test_1GbE is
-
begin
-
u_revision : entity unb2_test_lib.unb2_test
generic map (
g_design_name => g_design_name,
@@ -113,5 +109,4 @@ begin
QSFP_LED => QSFP_LED
);
-
end str;
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
index 681063440dc169517514885f2a62a4dec7c66866..d1b4f650eeaad022550d1960905a35558c32fc5d 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/tb_unb2_test_all.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2_test_all is
end tb_unb2_test_all;
-
architecture tb of tb_unb2_test_all is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
@@ -38,4 +34,3 @@ begin
g_sim_model_ddr => false
);
end tb;
-
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
index 55b937b124c28bd497296f65a379e646cbbca1f1..2eaf164405e9fa77976a5c679e6d65f5e095b7a9 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_all/unb2_test_all.vhd
@@ -28,7 +28,6 @@ use unb2_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2_test_all is
generic (
g_design_name : string := "unb2_test_all";
@@ -118,9 +117,7 @@ entity unb2_test_all is
);
end unb2_test_all;
-
architecture str of unb2_test_all is
-
begin
u_revision : entity unb2_test_lib.unb2_test
generic map (
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
index c9175b51bcf7b31da238bd5555f84c5bfd6b220b..2c4a69008fa527571a7502f505ba163cef11cb5b 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/tb_unb2_test_ddr_MB_I.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2_test_ddr_MB_I is
end tb_unb2_test_ddr_MB_I;
-
architecture tb of tb_unb2_test_ddr_MB_I is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
@@ -38,4 +34,3 @@ begin
g_sim_model_ddr => false
);
end tb;
-
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
index 1fab91805385661cadeb489a567ad81d7aebfa9f..2443e9f95a5c7f3d10ad2d974128c933c46a957b 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I/unb2_test_ddr_MB_I.vhd
@@ -28,7 +28,6 @@ use unb2_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2_test_ddr_MB_I is
generic (
g_design_name : string := "unb2_test_ddr_MB_I";
@@ -78,9 +77,7 @@ entity unb2_test_ddr_MB_I is
);
end unb2_test_ddr_MB_I;
-
architecture str of unb2_test_ddr_MB_I is
-
begin
u_revision : entity unb2_test_lib.unb2_test
generic map (
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
index a9491c8a67bf7fe7efefb068d270db2a8b980fee..35969d021c7cbf1565629d5d2da994e3aecfbf0b 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/tb_unb2_test_ddr_MB_II.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2_test_ddr_MB_II is
end tb_unb2_test_ddr_MB_II;
-
architecture tb of tb_unb2_test_ddr_MB_II is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
@@ -38,4 +34,3 @@ begin
g_sim_model_ddr => false
);
end tb;
-
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
index f0c4966ae13228813d37ad76348243c9ebed3df7..13039a84e05ee9e1cb8e71edbf56cf5f09a672e2 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_II/unb2_test_ddr_MB_II.vhd
@@ -28,7 +28,6 @@ use unb2_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2_test_ddr_MB_II is
generic (
g_design_name : string := "unb2_test_ddr_MB_II";
@@ -78,9 +77,7 @@ entity unb2_test_ddr_MB_II is
);
end unb2_test_ddr_MB_II;
-
architecture str of unb2_test_ddr_MB_II is
-
begin
u_revision : entity unb2_test_lib.unb2_test
generic map (
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
index bc45cff61eacc5212248a59fe7e884a2c2501164..f7b56945a1495ebedbbaca7d0bb6cb04bbccaa11 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/tb_unb2_test_ddr_MB_I_II.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2_test_ddr_MB_I_II is
end tb_unb2_test_ddr_MB_I_II;
-
architecture tb of tb_unb2_test_ddr_MB_I_II is
begin
u_tb_unb2_test : entity unb2_test_lib.tb_unb2_test
@@ -38,4 +34,3 @@ begin
g_sim_model_ddr => false
);
end tb;
-
diff --git a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
index 7979e41adaf9bc677d91db5b7c0207ec8d466ab9..9680fc8e5d5f46fea841832f2bb4bcc4dfca3c60 100644
--- a/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2/designs/unb2_test/revisions/unb2_test_ddr_MB_I_II/unb2_test_ddr_MB_I_II.vhd
@@ -28,7 +28,6 @@ use unb2_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2_test_ddr_MB_I_II is
generic (
g_design_name : string := "unb2_test_ddr_MB_I_II";
@@ -84,9 +83,7 @@ entity unb2_test_ddr_MB_I_II is
);
end unb2_test_ddr_MB_I_II;
-
architecture str of unb2_test_ddr_MB_I_II is
-
begin
u_revision : entity unb2_test_lib.unb2_test
generic map (
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 2d556761d493630e1adf39baae4daabbef5f6133..0e6ff5436b8694a8ac2b36a829ca58f4d2925381 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -40,8 +40,6 @@ use work.qsys_unb2_test_pkg.all;
use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
use work.unb2_test_pkg.all;
-
-
entity mmm_unb2_test is
generic (
g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
@@ -220,9 +218,7 @@ entity mmm_unb2_test is
);
end mmm_unb2_test;
-
architecture str of mmm_unb2_test is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
@@ -280,14 +276,11 @@ architecture str of mmm_unb2_test is
signal sim_eth1g_eth0_reg_mosi : t_mem_mosi;
signal sim_eth1g_eth1_reg_mosi : t_mem_mosi;
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
@@ -425,13 +418,11 @@ begin
end if;
end process;
-
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
@@ -671,7 +662,6 @@ begin
-- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
-- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
index f9f6483e8ed7b7523c4573af0ef516a99cc6432e..3db6393627fe5aafe9588fa02a19d351423c55a7 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/qsys_unb2_test_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2_test_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-- $HDL_WORK/build/unb2/quartus/unb2_test_ddr/qsys_unb2_test/sim/qsys_unb2_test.vhd
@@ -380,4 +379,3 @@ package qsys_unb2_test_pkg is
end component qsys_unb2_test;
end qsys_unb2_test_pkg;
-
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
index 0f6da4d454bf096e1713ef9625863a42ddf12ae6..b025b45615e2eb7cf6660fc33fcf9c9cc9b64da5 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/udp_stream.vhd
@@ -100,10 +100,7 @@ entity udp_stream is
);
end udp_stream;
-
-
architecture str of udp_stream is
-
-- Block generator
constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
'0', -- enable_sync
@@ -114,7 +111,6 @@ architecture str of udp_stream is
TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
constant c_min_nof_words_per_block : natural := 1;
@@ -133,9 +129,7 @@ architecture str of udp_stream is
signal diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
-
begin
-
gen_hdr_in_fields : for i in 0 to g_nof_streams - 1 generate
-- dst = src
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) downto field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000" & ID(7 downto 3) & RESIZE_UVEC(ID(2 downto 0), c_byte_w);
@@ -152,7 +146,6 @@ begin
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )) <= fifo_block_gen_src_out_arr(i).bsn(46 downto 0);
end generate;
-
-----------------------------------------------------------------------------
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
@@ -207,7 +200,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
@@ -248,7 +240,6 @@ begin
hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
);
-
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
@@ -281,13 +272,11 @@ begin
hdr_fields_out_arr => hdr_fields_out_arr
);
-
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
end generate;
-
-----------------------------------------------------------------------------
-- RX: Data buffers and BSN monitors
-----------------------------------------------------------------------------
@@ -301,8 +290,6 @@ begin
diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
end generate;
-
-
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
g_nof_streams => g_nof_streams,
@@ -324,7 +311,6 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
);
-
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
@@ -352,6 +338,4 @@ begin
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
-
end str;
-
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
index ce367aa64071c81749c86ebe03d362089a2d2342..a4e2c262f85c563935ad879102395a2f2b226797 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test.vhd
@@ -137,9 +137,7 @@ entity unb2_test is
);
end unb2_test;
-
architecture str of unb2_test is
-
-- Firmware version x.y
constant c_fw_version : t_unb2_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_125M;
@@ -207,7 +205,6 @@ architecture str of unb2_test is
constant c_max_nof_blocks_per_packet_1GbE : natural := c_max_udp_payload_nof_words_1GbE / c_min_nof_words_per_block;
constant c_max_nof_blocks_per_packet_10GbE : natural := c_max_udp_payload_nof_words_10GbE / c_min_nof_words_per_block;
-
-- System
signal cs_sim : std_logic;
@@ -431,9 +428,7 @@ architecture str of unb2_test is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -757,7 +752,6 @@ begin
ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
-
gen_udp_stream_1GbE : if c_use_1GbE = true generate
u_udp_stream_1GbE : entity work.udp_stream
generic map (
@@ -822,16 +816,13 @@ begin
-----------------------------------------------------------------------------
gen_wires_1GbE : if c_use_1GbE = true generate
gen_1GbE_wires : for i in 0 to c_nof_streams_1GbE-1 generate
-
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
dp_offload_rx_1GbE_snk_in_arr(i) <= eth1g_udp_rx_sosi_arr(i);
eth1g_udp_rx_siso_arr(i) <= dp_offload_rx_1GbE_snk_out_arr(i);
-
end generate;
end generate;
-
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
generic map (
@@ -877,7 +868,6 @@ begin
reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
);
-
u_tr_10GbE_qsfp_and_ring: entity unb2_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
generic map (
g_sim => g_sim,
@@ -912,7 +902,6 @@ begin
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
-
i_QSFP_RX(0) <= QSFP_0_RX;
i_QSFP_RX(1) <= QSFP_1_RX;
i_QSFP_RX(2) <= QSFP_2_RX;
@@ -927,8 +916,6 @@ begin
QSFP_4_TX <= i_QSFP_TX(4);
QSFP_5_TX <= i_QSFP_TX(5);
-
-
u_front_io : entity unb2_board_lib.unb2_board_front_io
generic map (
g_nof_qsfp_bus => c_nof_qsfp_bus
@@ -971,7 +958,6 @@ begin
-- RING_TX => i_RING_TX
-- );
-
-- u_tr_10GbE_back: ENTITY unb2_board_10gbe_lib.unb2_board_10gbe -- BACK lines
-- GENERIC MAP (
-- g_sim => g_sim,
@@ -1034,7 +1020,6 @@ begin
-- BCK_ERR => BCK_ERR
-- );
-
u_front_led : entity unb2_board_lib.unb2_board_qsfp_leds
generic map (
g_sim => g_sim,
@@ -1091,7 +1076,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- Interface : DDR4 MB_I and MB_II
-----------------------------------------------------------------------------
@@ -1099,7 +1083,6 @@ begin
assert func_tech_ddr_ctlr_data_w(g_ddr_MB_I) = func_tech_ddr_ctlr_data_w(g_ddr_MB_II) report "unb2_test: DDR4 MB_I and MB_II must have the same ctlr data widths" severity FAILURE;
gen_stream_MB_I : if c_use_MB_I = true generate
-
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
generic map (
-- System
@@ -1254,4 +1237,3 @@ begin
end generate;
end str;
-
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
index 19dc929de3f2c854e5d41bf06fdef43c5357d7d0..da3fbc3dc0c7e427c802c985f802c95fa7b931eb 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/unb2_test_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use common_lib.common_field_pkg.all;
package unb2_test_pkg is
-
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
@@ -55,6 +54,4 @@ package unb2_test_pkg is
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
-
end unb2_test_pkg;
-
diff --git a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
index 2893054f64768a9b9b9c8a299846bf5aca9dbdf5..3fca57d0e88f3ca7b41acfec566ff13c9183f83c 100644
--- a/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/tb/vhdl/tb_unb2_test.vhd
@@ -60,7 +60,6 @@ entity tb_unb2_test is
end tb_unb2_test;
architecture tb of tb_unb2_test is
-
constant c_sim : boolean := true;
constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
@@ -136,7 +135,6 @@ architecture tb of tb_unb2_test is
signal si_lpbk_8 : std_logic_vector(c_unb2_board_tr_back.bus_w - 1 downto 0);
-
-- Model I2C sensor slaves as on the UniBoard
constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
constant c_fpga_temp : integer := 60;
@@ -148,9 +146,7 @@ architecture tb of tb_unb2_test is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -162,7 +158,6 @@ begin
mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2; -- MB I reference clock (25 MHz)
mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2; -- MB II reference clock (25 MHz)
-
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -325,5 +320,4 @@ begin
mem4_in => MB_II_OU,
mem4_io => MB_II_IO
);
-
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
index b90b45a0f509f04ee83baf6fd6981b17971aa07b..8a4c6bd89ad9db59424e1cbddfbcb0bf8b468f41 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/ctrl_unb2_board.vhd
@@ -246,9 +246,7 @@ entity ctrl_unb2_board is
);
end ctrl_unb2_board;
-
architecture str of ctrl_unb2_board is
-
constant c_rom_version : natural := 1; -- Only increment when something changes to the register map of rom_system_info.
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
@@ -295,9 +293,7 @@ architecture str of ctrl_unb2_board is
signal eth1g_udp_tx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
signal eth1g_udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
signal eth1g_udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0) := (others => c_dp_siso_rdy);
-
begin
-
ext_clk200 <= i_ext_clk200;
xo_ethclk <= i_xo_ethclk;
xo_rst <= i_xo_rst;
@@ -346,7 +342,6 @@ begin
out_rst => i_xo_rst
);
-
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
-- MB_II_REF_CLK --> mb_II_ref_rst
@@ -426,7 +421,6 @@ begin
end generate;
end generate;
-
-----------------------------------------------------------------------------
-- mm_clk
-- . use mm_sim_clk in sim
@@ -483,7 +477,6 @@ begin
mm_pulse_s => mm_pulse_s -- could be used to toggle a LED
);
-
-----------------------------------------------------------------------------
-- System info
-----------------------------------------------------------------------------
@@ -518,7 +511,6 @@ begin
bck_id => this_bck_id
);
-
-----------------------------------------------------------------------------
-- Red LED control
-----------------------------------------------------------------------------
@@ -532,7 +524,6 @@ begin
TESTIO(c_unb2_board_testio_led_red) <= led_toggle_red;
end generate;
-
-----------------------------------------------------------------------------
-- Green LED control
-----------------------------------------------------------------------------
@@ -546,7 +537,6 @@ begin
TESTIO(c_unb2_board_testio_led_green) <= led_toggle_green;
end generate;
-
------------------------------------------------------------------------------
-- Toggle red LED when unb2_minimal is running, green LED for other designs.
------------------------------------------------------------------------------
@@ -561,7 +551,6 @@ begin
out_dat => led_toggle
);
-
------------------------------------------------------------------------------
-- WDI override
------------------------------------------------------------------------------
@@ -581,7 +570,6 @@ begin
wdi_override => wdi_override
);
-
------------------------------------------------------------------------------
-- Remote upgrade
------------------------------------------------------------------------------
@@ -657,7 +645,6 @@ begin
pps_sys => dp_pps
);
-
------------------------------------------------------------------------------
-- I2C control for UniBoard sensors
------------------------------------------------------------------------------
@@ -729,7 +716,6 @@ begin
temp_alarm => temp_alarm
);
-
------------------------------------------------------------------------------
-- Ethernet 1GbE
------------------------------------------------------------------------------
@@ -751,7 +737,6 @@ begin
i_tse_clk <= i_xo_ethclk;
end generate;
-
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
udp_tx_siso_arr(i) <= eth1g_udp_tx_siso_arr(i);
@@ -770,7 +755,6 @@ begin
--On hardware always generate 1GbE for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
gen_eth: if g_sim = false or g_udp_offload = true generate
-
eth1g_st_clk <= dp_clk_in when g_udp_offload = true else i_mm_clk;
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
index 088f538a7a4797f4345b2f9473b0769e78e47cd4..f8a10253cf5088c77b01be22f6249b4f2881e0cb 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -28,7 +28,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
-
entity mms_unb2_board_sens is
generic (
g_sim : boolean := false;
@@ -55,9 +54,7 @@ entity mms_unb2_board_sens is
);
end mms_unb2_board_sens;
-
architecture str of mms_unb2_board_sens is
-
constant c_sens_nof_result : natural := 4; -- Should match nof read bytes via I2C in the unb2_board_sens_ctrl SEQUENCE list
constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
@@ -65,9 +62,7 @@ architecture str of mms_unb2_board_sens is
signal sens_data : t_slv_8_arr(0 to c_sens_nof_result - 1);
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
-
begin
-
u_unb2_board_sens_reg : entity work.unb2_board_sens_reg
generic map (
g_sens_nof_result => c_sens_nof_result,
@@ -115,6 +110,4 @@ begin
-- would produce -1 degrees so does not trigger a temperature alarm.
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '1' when (signed(sens_data(0)) > signed('0' & temp_high)) else '0';
-
end str;
-
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
index 75ff5e6a7c1259fb0bf4e1c5d491f9c40cf8018d..8116249508a7900047234ce33af9b17cac31ab6b 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -61,9 +61,7 @@ entity mms_unb2_board_system_info is
);
end mms_unb2_board_system_info;
-
architecture str of mms_unb2_board_system_info is
-
-- Provide different prefixes (absolute and relative) for the same path. ModelSim understands $UNB, Quartus does not.
-- Required because the work paths of ModelSim and Quartus are different.
constant c_quartus_path_prefix : string := "";
@@ -83,9 +81,7 @@ architecture str of mms_unb2_board_system_info is
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
info <= i_info;
u_unb2_board_system_info: entity work.unb2_board_system_info
@@ -136,6 +132,4 @@ begin
rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
rd_val => rom_miso.rdval
);
-
end str;
-
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
index e619ec2ef2c9d915839f7a714ccd5ac1fd82bc88..9697e2b7f1f752ba2a41427bec97e98a72ec56b9 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -29,7 +29,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use technology_lib.technology_pkg.all;
-
entity mms_unb2_fpga_sens is
generic (
g_sim : boolean := false;
@@ -53,9 +52,7 @@ entity mms_unb2_fpga_sens is
);
end mms_unb2_fpga_sens;
-
architecture str of mms_unb2_fpga_sens is
-
constant c_sens_nof_result : natural := 1; --
constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
@@ -63,9 +60,7 @@ architecture str of mms_unb2_fpga_sens is
signal sens_data : t_slv_8_arr(0 to c_sens_nof_result - 1);
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
-
begin
-
u_unb2_fpga_sens_reg : entity work.unb2_fpga_sens_reg
generic map (
g_sim => g_sim,
@@ -117,6 +112,4 @@ begin
-- would produce -1 degrees so does not trigger a temperature alarm.
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '0'; -- <= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
-
end str;
-
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
index a0060fe1cb2bd4a37e7d2d8c42b5f7049a119489..9210abec473ed84d946b293e806bb4b0984261fb 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_back_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2_board_pkg.all;
-
entity unb2_board_back_io is
generic (
g_nof_back_bus : natural := c_unb2_board_tr_back.nof_bus
@@ -43,26 +42,19 @@ entity unb2_board_back_io is
end unb2_board_back_io;
architecture str of unb2_board_back_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus - 1 downto 0);
signal si_rx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus - 1 downto 0);
-
begin
-
gen_buses : for i in 0 to g_nof_back_bus - 1 generate
BCK_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= BCK_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_back.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
index bf66c9ae6a4656b89d02363581b6f2bec874dfad..48fad46da5c7c879188216a074787a6333284c9b 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -51,13 +51,9 @@ entity unb2_board_clk125_pll is
);
end unb2_board_clk125_pll;
-
architecture arria10 of unb2_board_clk125_pll is
-
signal clk125buf : std_logic;
-
begin
-
no_clkbuf : if g_use_clkbuf = false generate
clk125buf <= clk125;
end generate;
@@ -74,7 +70,6 @@ begin
);
end generate;
-
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
generic map (
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
index 6bedd749d7db69cd5805e2b5ea138b9c52208028..9ca4ebe75e78f0da81b3f430987fdcaf05726dee 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -113,9 +113,7 @@ entity unb2_board_clk200_pll is
);
end unb2_board_clk200_pll;
-
architecture arria10 of unb2_board_clk200_pll is
-
constant c_reset_len : natural := c_meta_delay_len;
signal clk200buf : std_logic;
@@ -126,9 +124,7 @@ architecture arria10 of unb2_board_clk200_pll is
signal st_locked : std_logic;
signal st_locked_n : std_logic;
-
begin
-
st_rst200 <= i_st_rst200;
st_clk200 <= i_st_clk200;
st_clk200p <= i_st_clk200p;
@@ -218,5 +214,4 @@ begin
clk => i_st_clk400,
out_rst => st_rst400
);
-
end arria10;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
index eef69056556e7a347ff01b9692ed0716e83db3ab..70d83befad5f22b82c1e67a22ed53b6e41810b3f 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -49,10 +49,8 @@ entity unb2_board_clk25_pll is
);
end unb2_board_clk25_pll;
-
architecture arria10 of unb2_board_clk25_pll is
begin
-
u_pll : entity tech_pll_lib.tech_pll_clk25
generic map (
g_technology => g_technology
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
index 9d4d3c1bd320406e08799867ffc474a5868e740c..4bacebe5afdc117f5c7fa3e7c72c887bfcc81cf9 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -42,9 +42,7 @@ entity unb2_board_clk_rst is
);
end unb2_board_clk_rst;
-
architecture str of unb2_board_clk_rst is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
-- XO clock domain
@@ -52,9 +50,7 @@ architecture str of unb2_board_clk_rst is
-- SYS clock domain
signal sys_locked_n : std_logic;
-
begin
-
-- Reference clock and reset to SOPC system PLL
xo_rst_n <= not xo_rst;
@@ -82,5 +78,4 @@ begin
clk => sys_clk,
out_rst => sys_rst
);
-
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
index 2bbb9e4613b488d685580a4e4116110b8949e1d8..1e8e9a974ccf749390f10740b6ea31491bb2e456 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_front_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2_board_pkg.all;
-
entity unb2_board_front_io is
generic (
g_nof_qsfp_bus : natural := c_unb2_board_tr_qsfp.nof_bus
@@ -47,32 +46,24 @@ entity unb2_board_front_io is
end unb2_board_front_io;
architecture str of unb2_board_front_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus - 1 downto 0);
signal si_rx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus - 1 downto 0);
-
begin
-
gen_leds : for i in 0 to g_nof_qsfp_bus - 1 generate
QSFP_LED(i * 2) <= green_led_arr(i);
QSFP_LED(i * 2 + 1) <= red_led_arr(i);
end generate;
-
gen_buses : for i in 0 to g_nof_qsfp_bus - 1 generate
QSFP_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= QSFP_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
index 32c9cd53ff16aac7dce2793a3f61567e7f519e9c..b37cfbaf8f11db1f8998aab9844b0589d93c76f4 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -54,17 +54,13 @@ entity unb2_board_node_ctrl is
);
end unb2_board_node_ctrl;
-
architecture str of unb2_board_node_ctrl is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
signal mm_locked_n : std_logic;
signal i_mm_rst : std_logic;
signal i_mm_pulse_ms : std_logic;
-
begin
-
-- Create mm_rst reset in mm_clk domain based on mm_locked
mm_rst <= i_mm_rst;
@@ -110,5 +106,4 @@ begin
wdi_in => mm_wdi_in,
wdi_out => mm_wdi_out
);
-
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index 24ed076f795d179bb8dcaa4a15b03c1235644e26..aa42e0627dc1bfdf127e7b0e0fec5afdf9881fc2 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -42,8 +42,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package unb2_board_peripherals_pkg is
-
-
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb2_board_peripherals_mm_reg is record
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
index 00bdd220d79a9d20e0f31b2ff4d8420ae5827358..20f69332252ac3a14fc387c19ee4aae9ffb0b673 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pkg.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
-
-- UniBoard
constant c_unb2_board_nof_node : natural := 4; -- number of nodes on UniBoard
constant c_unb2_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb2_board_nof_node)
@@ -83,12 +82,10 @@ package unb2_board_pkg is
constant c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
constant c_unb2_board_tr_qsfp_nof_leds : natural := c_unb2_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
-
type t_unb2_board_qsfp_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_qsfp.bus_w - 1 downto 0);
type t_unb2_board_ring_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_ring.bus_w - 1 downto 0);
type t_unb2_board_back_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_back.bus_w - 1 downto 0);
-
-- Auxiliary
-- Test IO Interface
@@ -126,7 +123,6 @@ package unb2_board_pkg is
-- SIGNAL RECORD DECLARATIONS -----------------------------------------------
-
-- I2C, MDIO
-- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
-- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
@@ -151,9 +147,7 @@ package unb2_board_pkg is
end unb2_board_pkg;
-
package body unb2_board_pkg is
-
function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
variable v_system_info : t_c_unb2_board_system_info;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index 4baacf00df7f20eec805e3250c255b6e2b5c9d8c..45987424f355bbc7e5349362e411a7b0c149e1f6 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -26,7 +26,6 @@ use i2c_lib.i2c_dev_max1617_pkg.all;
use i2c_lib.i2c_dev_ltc4260_pkg.all;
use common_lib.common_pkg.all;
-
entity unb2_board_pmbus_ctrl is
generic (
g_sim : boolean := false;
@@ -50,9 +49,7 @@ entity unb2_board_pmbus_ctrl is
);
end entity;
-
architecture rtl of unb2_board_pmbus_ctrl is
-
-- I2C slave addresses for the PMBUS, power module readouts
constant LOC_POWER_CORE : natural := 16#01#;
constant LOC_POWER_ERAM : natural := 16#0D#;
@@ -67,7 +64,6 @@ architecture rtl of unb2_board_pmbus_ctrl is
constant LP_IOUT : natural := 16#8C#;
constant LP_TEMP : natural := 16#8D#;
-
type t_SEQUENCE is array (natural range <>) of natural;
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
@@ -139,9 +135,7 @@ architecture rtl of unb2_board_pmbus_ctrl is
signal nxt_result_err : std_logic;
signal i_result_dat : t_slv_8_arr(result_dat'range);
signal nxt_result_dat : t_slv_8_arr(result_dat'range);
-
begin
-
result_dat <= i_result_dat;
regs: process(rst, clk)
@@ -210,5 +204,4 @@ begin
nxt_result_val <= rx_val;
nxt_result_err <= rx_err;
nxt_result_dat <= rx_dat when rx_val = '1' else i_result_dat;
-
end rtl;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
index 80e8ae543fd3cd5fa9f949d11cc24054e678b5b3..db1d2a02523b0507df351a6a312d529c7a741251 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -88,9 +88,7 @@ entity unb2_board_qsfp_leds is
);
end unb2_board_qsfp_leds;
-
architecture str of unb2_board_qsfp_leds is
-
constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
constant c_nof_lanes : natural := g_nof_qsfp * c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
@@ -103,9 +101,7 @@ architecture str of unb2_board_qsfp_leds is
signal qsfp_on_arr : std_logic_vector(g_nof_qsfp - 1 downto 0);
signal qsfp_evt_arr : std_logic_vector(g_nof_qsfp - 1 downto 0);
-
begin
-
pulse_ms <= i_pulse_ms;
pulse_s <= i_pulse_s;
@@ -152,7 +148,6 @@ begin
end generate;
gen_user_image : if g_factory_image = false generate
-
red_led_arr <= (others => '0');
gen_green_ctrl_arr : for I in c_nof_lanes - 1 downto 0 generate
@@ -161,7 +156,6 @@ begin
end generate;
gen_green_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
-
qsfp_on_arr(I) <= orv(green_on_arr( (I + 1) * c_quad - 1 downto + I * c_quad));
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
@@ -182,5 +176,4 @@ begin
);
end generate;
end generate;
-
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
index fba74d7787a2aca45124388de49ce1165394de3f..b83c06965924d692e1324f51a4141d7acd068f1a 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_ring_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2_board_pkg.all;
-
entity unb2_board_ring_io is
generic (
g_nof_ring_bus : natural := c_unb2_board_tr_ring.nof_bus
@@ -38,26 +37,19 @@ entity unb2_board_ring_io is
end unb2_board_ring_io;
architecture str of unb2_board_ring_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0);
signal si_rx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0);
-
begin
-
gen_buses : for i in 0 to g_nof_ring_bus - 1 generate
RING_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= RING_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_ring.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
index 22bb96c97f6155fe68e9a5ac47f512f7716e3349..18a16b5aaba0e355cf70850c8564d86ccc50cdaa 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use i2c_lib.i2c_pkg.all;
-
entity unb2_board_sens is
generic (
g_sim : boolean := false;
@@ -47,9 +46,7 @@ entity unb2_board_sens is
);
end entity;
-
architecture str of unb2_board_sens is
-
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
constant c_sens_comma_w : natural := 0; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
@@ -64,9 +61,7 @@ architecture str of unb2_board_sens is
signal smbus_out_err : std_logic;
signal smbus_out_ack : std_logic;
signal smbus_out_end : std_logic;
-
begin
-
gen_unb2_board_sens_ctrl : if g_pmbus = false generate
u_unb2_board_sens_ctrl : entity work.unb2_board_sens_ctrl
generic map (
@@ -115,7 +110,6 @@ begin
);
end generate;
-
u_i2c_smbus : entity i2c_lib.i2c_smbus
generic map (
g_i2c_phy => c_sens_phy
@@ -134,5 +128,4 @@ begin
scl => scl,
sda => sda
);
-
end architecture;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
index 409b1bde3077676a5e480e0dbb30ec78ed1e20cb..da90d846f87364a7d68931a44fd5d93028a51c8d 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -26,7 +26,6 @@ use i2c_lib.i2c_dev_max1617_pkg.all;
use i2c_lib.i2c_dev_ltc4260_pkg.all;
use common_lib.common_pkg.all;
-
entity unb2_board_sens_ctrl is
generic (
g_sim : boolean := false;
@@ -50,9 +49,7 @@ entity unb2_board_sens_ctrl is
);
end entity;
-
architecture rtl of unb2_board_sens_ctrl is
-
-- I2C slave addresses of the devices on the I2C bus on UniBoard
constant ETH_MAX1617_ADR : natural := 16#29#; -- ETH temperature sensor
constant FPGA_TMP451_ADR : natural := 16#4C#; -- FPGA temperature sensor
@@ -100,9 +97,7 @@ architecture rtl of unb2_board_sens_ctrl is
signal nxt_result_err : std_logic;
signal i_result_dat : t_slv_8_arr(result_dat'range);
signal nxt_result_dat : t_slv_8_arr(result_dat'range);
-
begin
-
result_dat <= i_result_dat;
regs: process(rst, clk)
@@ -171,5 +166,4 @@ begin
nxt_result_val <= rx_val;
nxt_result_err <= rx_err;
nxt_result_dat <= rx_dat when rx_val = '1' else i_result_dat;
-
end rtl;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
index 1ff3381d0d874a40b95c1b3c288805da1c429f51..9790dc3ea0f4d588f779a2cbbc1b52487596c100 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -89,9 +89,7 @@ entity unb2_board_sens_reg is
);
end unb2_board_sens_reg;
-
architecture rtl of unb2_board_sens_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
-- +1 to fit sens_err in the last address
@@ -103,9 +101,7 @@ architecture rtl of unb2_board_sens_reg is
init_sl => '0');
signal i_temp_high : std_logic_vector(6 downto 0);
-
begin
-
temp_high <= i_temp_high;
------------------------------------------------------------------------------
@@ -158,5 +154,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
index 3ef429a1f90f2172a9910ac8fbfd3c88a7dff9e1..c3958aa4075c5c30ba82ba3ebb60a095c07d8833 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info.vhd
@@ -50,9 +50,7 @@ entity unb2_board_system_info is
);
end unb2_board_system_info;
-
architecture str of unb2_board_system_info is
-
signal cs_sim : std_logic;
signal hw_version_reg : std_logic_vector(hw_version'range);
@@ -63,9 +61,7 @@ architecture str of unb2_board_system_info is
signal nxt_chip_id : std_logic_vector(chip_id'range);
signal nxt_node_id : std_logic_vector(node_id'range);
signal nxt_is_node2 : std_logic;
-
begin
-
p_reg : process(clk)
begin
if rising_edge(clk) then
@@ -98,5 +94,4 @@ begin
nxt_chip_id <= id_reg(1 downto 0);
nxt_node_id <= id_reg(1 downto 0);
nxt_is_node2 <= '1' when TO_UINT(id_reg(1 downto 0)) = 2 else '0';
-
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
index 138a1de924c094b4e0a801b028efc85c8dd0c0ec..2b7a13332c5803c8e7a09da72b6fbb027358d1e5 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -71,9 +71,7 @@ entity unb2_board_system_info_reg is
);
end unb2_board_system_info_reg;
-
architecture rtl of unb2_board_system_info_reg is
-
constant c_nof_fixed_regs : natural := 2; -- info, use_phy
constant c_nof_design_name_regs : natural := 13; -- design_name
constant c_nof_stamp_regs : natural := 3; -- date, time, svn rev
@@ -92,9 +90,7 @@ architecture rtl of unb2_board_system_info_reg is
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
begin
@@ -132,13 +128,8 @@ begin
elsif vA < c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs then
sla_out.rddata(c_word_w - 1 downto 0) <= c_design_note(vA - c_nof_fixed_regs - c_nof_design_name_regs - c_nof_stamp_regs);
-
end if;
-
end if;
end if;
end process;
-
-
end rtl;
-
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
index d474968663c28b049db63a3c073f134b1bab2cf5..e09adb5ff956c56a6a0ad91728c26da6f7fd03e3 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -43,9 +43,7 @@ entity unb2_board_wdi_extend is
);
end unb2_board_wdi_extend;
-
architecture str of unb2_board_wdi_extend is
-
signal wdi_evt : std_logic;
signal wdi_cnt : std_logic_vector(g_extend_w - 1 downto 0);
@@ -53,9 +51,7 @@ architecture str of unb2_board_wdi_extend is
signal i_wdi_out : std_logic;
signal nxt_wdi_out : std_logic;
-
begin
-
wdi_out <= i_wdi_out;
p_clk : process(rst, clk)
@@ -94,5 +90,4 @@ begin
cnt_en => wdi_cnt_en,
count => wdi_cnt
);
-
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
index 365e280976be5335fc7d3e67cb924844680f1f01..fa05af1d4f06f94cf92b05921391eaadd7b20ab7 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -43,9 +43,7 @@ entity unb2_board_wdi_reg is
);
end unb2_board_wdi_reg;
-
architecture rtl of unb2_board_wdi_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
@@ -55,9 +53,7 @@ architecture rtl of unb2_board_wdi_reg is
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -82,9 +78,6 @@ begin
when others => null; -- unused MM addresses
end case;
end if;
-
end if;
end process;
-
end rtl;
-
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
index c8474454b250d148ec7dd110a5f7d2736c3f6088..049c7da72e89a2425d552442030f2e3bf2964138 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -29,7 +29,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2_fpga_sens_reg is
generic (
g_sim : boolean;
@@ -59,13 +58,9 @@ entity unb2_fpga_sens_reg is
);
end unb2_fpga_sens_reg;
-
architecture str of unb2_fpga_sens_reg is
-
--SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
-
begin
-
temp_high <= (others => '0'); -- i_temp_high;
u_fpga_sense: entity fpga_sense_lib.fpga_sense
@@ -85,5 +80,4 @@ begin
reg_voltage_store_mosi => sla_voltage_in,
reg_voltage_store_miso => sla_voltage_out
);
-
end str;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index a8f66880989aff67eb2ab5a5df50a842e5798213..3449629f924542e11912156b5b8a71b0cbca0838 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -38,9 +38,7 @@ use common_lib.common_mem_pkg.all;
use common_lib.tb_common_pkg.all;
use common_lib.tb_common_mem_pkg.all;
-
architecture tb of tb_mms_unb2_board_sens is
-
constant c_sim : boolean := true; -- FALSE;
constant c_repeat : natural := 2;
constant c_clk_freq : natural := 100 * 10**6;
@@ -77,9 +75,7 @@ architecture tb of tb_mms_unb2_board_sens is
signal scl_stretch : std_logic := 'Z';
signal scl : std_logic;
signal sda : std_logic;
-
begin
-
rst <= '0' after 4 * c_clk_period;
clk <= (not clk) or tb_end after c_clk_period / 2;
@@ -147,10 +143,8 @@ begin
assert TO_UINT(sens_dat) = c_sens_expected(3) report "Wrong hot swap V source value" severity ERROR;
proc_common_wait_some_cycles(clk, 1);
assert TO_UINT(sens_dat) = c_sens_expected(4) report "An I2C error occurred" severity ERROR;
-
end process;
-
-- I2C sensors master
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
generic map (
@@ -207,6 +201,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
-
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index 3e7d5fa1b90e7d33b47070cafe35d3e4beeba0ae..bd1504ec133b48c2ee0a1855949db6f37474baa8 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2_board_clk125_pll is
end tb_unb2_board_clk125_pll;
-
architecture tb of tb_unb2_board_clk125_pll is
-
constant c_ext_clk_period : time := 8 ns; -- 125 MHz
signal tb_end : std_logic := '0';
@@ -48,9 +44,7 @@ architecture tb of tb_unb2_board_clk125_pll is
signal c2_clk100 : std_logic;
signal c3_clk125 : std_logic;
signal pll_locked : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index 01c62f46e18afd135ac10ee8541ec24dc3469872..ae4e087f1ebbb885fdc524cf39c36ecfaae6575c 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2_board_clk200_pll is
end tb_unb2_board_clk200_pll;
-
architecture tb of tb_unb2_board_clk200_pll is
-
constant c_ext_clk_period : time := 5 ns; -- 200 MHz
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
@@ -63,9 +59,7 @@ architecture tb of tb_unb2_board_clk200_pll is
signal dp_clk200 : std_logic;
signal dp_rst200 : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
@@ -112,5 +106,4 @@ begin
st_clk200 => dp_clk200,
st_rst200 => dp_rst200
);
-
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b460c275ce5418d63af3d6f509f9d2a1c240bbe0..b8ea88958d0d5715d52945bb2c636f11ca860615 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2_board_clk25_pll is
end tb_unb2_board_clk25_pll;
-
architecture tb of tb_unb2_board_clk25_pll is
-
constant c_ext_clk_period : time := 40 ns; -- 25 MHz
signal tb_end : std_logic := '0';
@@ -48,9 +44,7 @@ architecture tb of tb_unb2_board_clk25_pll is
signal c2_clk100 : std_logic;
signal c3_clk125 : std_logic;
signal pll_locked : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 35e015a38b70609756ed4853710a53c6957244b2..1d6125db58dc61776f1aa9f906a18959ecabfcde 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -24,13 +24,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2_board_node_ctrl is
end tb_unb2_board_node_ctrl;
-
architecture tb of tb_unb2_board_node_ctrl is
-
constant c_scale : natural := 100; -- scale to speed up simulation
constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
@@ -62,9 +59,7 @@ architecture tb of tb_unb2_board_node_ctrl is
signal pulse_us : std_logic;
signal pulse_ms : std_logic;
signal pulse_s : std_logic;
-
begin
-
-- run 2000 ms
mm_clk <= not mm_clk after c_mm_clk_period / 2;
@@ -95,5 +90,4 @@ begin
mm_pulse_ms => pulse_ms,
mm_pulse_s => pulse_s
);
-
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 86668b2331a93494aabdafcb603c1503a73acbe1..2a4f41e54767bb5b341bc1677d6083e49cee22ff 100644
--- a/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2/libraries/unb2_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -46,7 +46,6 @@ entity tb_unb2_board_qsfp_leds is
end tb_unb2_board_qsfp_leds;
architecture tb of tb_unb2_board_qsfp_leds is
-
constant c_clk_freq_hz : natural := 200 * 10**6;
constant c_clk_period_ns : natural := 10**9 / c_clk_freq_hz;
constant c_nof_clk_per_us : natural := 1000 / c_clk_period_ns;
@@ -84,9 +83,7 @@ architecture tb of tb_unb2_board_qsfp_leds is
signal dbg_sop : std_logic;
signal dbg_sop_slv : std_logic_vector(c_nof_lanes - 1 downto 0);
signal dbg_sosi : t_dp_sosi;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -186,5 +183,4 @@ begin
green_led_arr => user_green_led_arr,
red_led_arr => user_red_led_arr
);
-
end tb;
diff --git a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 0fe7b9e242dc1e68fa544ef94cfb79ba88ab3b66..24d2ecc45e73c420bdd45d639c7d0ce09edbc2ad 100644
--- a/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2/libraries/unb2_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -28,7 +28,6 @@ use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_pkg.all;
use work.unb2_board_pkg.all;
-
entity unb2_board_10gbe is
generic (
g_sim : boolean := false;
@@ -69,13 +68,10 @@ entity unb2_board_10gbe is
);
end unb2_board_10gbe;
-
architecture str of unb2_board_10gbe is
-
signal tr_ref_clk_312 : std_logic;
signal tr_ref_clk_156 : std_logic;
signal tr_ref_rst_156 : std_logic;
-
begin
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
generic map (
@@ -90,7 +86,6 @@ begin
rst_312 => open
);
-
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_technology => g_technology,
@@ -131,5 +126,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
index ff6593f3fec841d3bac7cc724bedbfb5efa3ce94..f2b16a715495109a68ad8c1939b70094532de969 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
@@ -88,4 +88,3 @@
local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
);
-
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
index 6f46a0519ffd6e40f4f84a48533ee73be70935d5..c028fced708026eff114f3297a08f0c515850074 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
@@ -88,4 +88,3 @@
local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
);
-
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
index 0d95ca2ee81df5d887c141a5c655aa30ea2eed37..f1ce0394dc61a6390274e086ee406a1851c0acb0 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/mmm_unb2a_heater.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_unb2a_heater_pkg.all;
-
entity mmm_unb2a_heater is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -106,19 +105,15 @@ entity mmm_unb2a_heater is
end mmm_unb2a_heater;
architecture str of mmm_unb2a_heater is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -155,7 +150,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
index 7229f0b80cf7a447603e7698ad53c23162a6cd26..b60792517e855717caef9e115180635f2a54d2bf 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/qsys_unb2a_heater_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2a_heater_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v15.1 QSYS builder
-----------------------------------------------------------------------------
diff --git a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
index 1d6e8e0086f565ae6969ae2c712aa5a7948b85e1..5c298a90dc10e64e4061ee6f27663ba742bab6f9 100644
--- a/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/src/vhdl/unb2a_heater.vhd
@@ -72,9 +72,7 @@ entity unb2a_heater is
);
end unb2a_heater;
-
architecture str of unb2a_heater is
-
-- Firmware version x.y
constant c_fw_version : t_unb2_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_50M;
@@ -158,9 +156,7 @@ architecture str of unb2a_heater is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -384,7 +380,6 @@ begin
QSFP_LED => QSFP_LED
);
-
u_heater : entity util_lib.util_heater
generic map (
g_technology => g_technology,
@@ -403,4 +398,3 @@ begin
sla_out => reg_heater_miso
);
end str;
-
diff --git a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
index 5618e365de6cac953e79487a770ba036be37ec1d..16c91fe7540da69df83e96af141730e13484a3c9 100644
--- a/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
+++ b/boards/uniboard2a/designs/unb2a_heater/tb/vhdl/tb_unb2a_heater.vhd
@@ -58,7 +58,6 @@ entity tb_unb2a_heater is
end tb_unb2a_heater;
architecture tb of tb_unb2a_heater is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -110,9 +109,7 @@ architecture tb of tb_unb2a_heater is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -216,5 +213,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
index a175b4e2e2b2fbf9fdbc27a061622f9dbc2753d3..4290c6d733f4a7085f678a1d48faca2ef9196844 100644
--- a/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/src/vhdl/unb2a_led.vhd
@@ -48,9 +48,7 @@ entity unb2a_led is
);
end unb2a_led;
-
architecture str of unb2a_led is
-
-- Firmware version x.y
constant c_fw_version : t_unb2_board_fw_version := (1, 1);
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
@@ -87,7 +85,6 @@ architecture str of unb2a_led is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
xo_ethclk <= i_xo_ethclk;
xo_rst <= i_xo_rst;
@@ -162,7 +159,6 @@ begin
led_flash_red <= sel_a_b(g_factory_image = true, led_flash, '0');
led_flash_green <= sel_a_b(g_factory_image = false, led_flash, '0');
-
u_extend : entity common_lib.common_pulse_extend
generic map (
g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
@@ -174,17 +170,12 @@ begin
ep_out => led_flash
);
-
-
-
-- Red LED control
TESTIO(c_unb2_board_testio_led_red) <= led_flash_red;
-- Green LED control
TESTIO(c_unb2_board_testio_led_green) <= led_flash_green;
-
-
u_common_pulser_10Hz : entity common_lib.common_pulser
generic map (
g_pulse_period => 100,
@@ -227,6 +218,4 @@ begin
QSFP_LED(1) <= '1';
QSFP_LED(5) <= '1';
QSFP_LED(9) <= '1';
-
end str;
-
diff --git a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
index ae2986db69e157f5d2995bfdd8428ad148bacefb..4e604241be67822b45600364a912743390aec8aa 100644
--- a/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
+++ b/boards/uniboard2a/designs/unb2a_led/tb/vhdl/tb_unb2a_led.vhd
@@ -54,7 +54,6 @@ entity tb_unb2a_led is
end tb_unb2a_led;
architecture tb of tb_unb2a_led is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -66,9 +65,7 @@ architecture tb of tb_unb2a_led is
signal eth_clk : std_logic := '0';
signal TESTIO : std_logic_vector(c_unb2_board_aux.testio_w - 1 downto 0);
signal qsfp_led : std_logic_vector(c_unb2_board_tr_qsfp_nof_leds - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -90,5 +87,4 @@ begin
TESTIO => TESTIO,
QSFP_LED => qsfp_led
);
-
end tb;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
index 9508f28879e9b4660c2f155b5f76f4beae9d4fd1..2a634cb5632302f7c4fca1240baf02519ad780cc 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/mmm_unb2a_minimal.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_unb2a_minimal_pkg.all;
-
entity mmm_unb2a_minimal is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -102,19 +101,15 @@ entity mmm_unb2a_minimal is
end mmm_unb2a_minimal;
architecture str of mmm_unb2a_minimal is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -148,7 +143,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
index 5d8ec0f7e9aceeb0ab4b57f6815266c749df3cde..6897ea10bfdf03e5d40e7f2c1d7a4d618ada9160 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/qsys_unb2a_minimal_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2a_minimal_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v14 QSYS builder
-----------------------------------------------------------------------------
diff --git a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
index f9fd13d39a76c9f1083df5b245b8c58e2c98d7d8..ea1f2090f826ec063406aeb77ede160913651c0f 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/src/vhdl/unb2a_minimal.vhd
@@ -71,9 +71,7 @@ entity unb2a_minimal is
);
end unb2a_minimal;
-
architecture str of unb2a_minimal is
-
-- Firmware version x.y
constant c_fw_version : t_unb2_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_50M;
@@ -153,9 +151,7 @@ architecture str of unb2a_minimal is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -373,6 +369,4 @@ begin
red_led_arr => qsfp_red_led_arr,
QSFP_LED => QSFP_LED
);
-
end str;
-
diff --git a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
index 229e507f6ae2f3ecd3b45ae254b8999af9866fcb..6f8ae35cfe579d513b79e2dcab5f944ebc4d484d 100644
--- a/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
+++ b/boards/uniboard2a/designs/unb2a_minimal/tb/vhdl/tb_unb2a_minimal.vhd
@@ -60,7 +60,6 @@ entity tb_unb2a_minimal is
end tb_unb2a_minimal;
architecture tb of tb_unb2a_minimal is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -114,9 +113,7 @@ architecture tb of tb_unb2a_minimal is
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
constant c_pmbus_tcvr0_address : std_logic_vector(6 downto 0) := TO_UVEC(I2C_UNB2_PMB_TCVR0_BMR461_ADR, 7);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
index d810f5c1e5363d2c4999375c3c0a7a634b0cefc2..61f50f2ce0bc398f6c4533ed9ab3dee477749f57 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/tb_unb2a_test_10GbE.vhd
@@ -23,11 +23,9 @@
library IEEE, unb2a_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2a_test_10GbE is
end tb_unb2a_test_10GbE;
-
architecture tb of tb_unb2a_test_10GbE is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
@@ -35,4 +33,3 @@ begin
g_design_name => "unb2a_test_10GbE"
);
end tb;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
index e287fb3c66f2f5fea7775f30d6521c08b2941449..bbcc7c1c0f2542aabfe38115e8c1fcea9feaa6ff 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_10GbE/unb2a_test_10GbE.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2a_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2a_test_10GbE is
generic (
g_design_name : string := "unb2a_test_10GbE";
@@ -107,9 +106,7 @@ entity unb2a_test_10GbE is
);
end unb2a_test_10GbE;
-
architecture str of unb2a_test_10GbE is
-
begin
u_revision : entity unb2a_test_lib.unb2a_test
generic map (
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
index 4235e78702540062916f21f2390f9acf41a8a4b8..bbf7b8271ea4ddd6c7f042781bfc78f503bbd945 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/tb_unb2a_test_1GbE.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2a_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2a_test_1GbE is
end tb_unb2a_test_1GbE;
-
architecture tb of tb_unb2a_test_1GbE is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
@@ -37,4 +33,3 @@ begin
g_design_name => "unb2a_test_1GbE"
);
end tb;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
index d397d48345f9dbd2bcebfcb68e1599754aa435cc..d326502fefb6a118e511aa62ae030c5a6ff00fae 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_1GbE/unb2a_test_1GbE.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2a_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2a_test_1GbE is
generic (
g_design_name : string := "unb2a_test_1GbE";
@@ -69,11 +68,8 @@ entity unb2a_test_1GbE is
);
end unb2a_test_1GbE;
-
architecture str of unb2a_test_1GbE is
-
begin
-
u_revision : entity unb2a_test_lib.unb2a_test
generic map (
g_design_name => g_design_name,
@@ -113,5 +109,4 @@ begin
QSFP_LED => QSFP_LED
);
-
end str;
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
index fe6292e768f9aad1dacee9352dd0078b19a311eb..f0a08f448d7e3658153742a5b8473e590dd296bb 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/tb_unb2a_test_all.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2a_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2a_test_all is
end tb_unb2a_test_all;
-
architecture tb of tb_unb2a_test_all is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
@@ -38,4 +34,3 @@ begin
g_sim_model_ddr => false
);
end tb;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
index 2243b164a77d82f0131933ba1b96dfefe20fe55b..3f78a1a9417af8293d22b4d3d1ee4a644a46b2bb 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_all/unb2a_test_all.vhd
@@ -28,7 +28,6 @@ use unb2a_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2a_test_all is
generic (
g_design_name : string := "unb2a_test_all";
@@ -118,9 +117,7 @@ entity unb2a_test_all is
);
end unb2a_test_all;
-
architecture str of unb2a_test_all is
-
begin
u_revision : entity unb2a_test_lib.unb2a_test
generic map (
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
index c4f4c2fc7409b7df8ec244c095a44d70d3098d77..e09dc3465bee813c7f871f01784d257b03639bde 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/tb_unb2a_test_ddr_MB_I.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2a_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2a_test_ddr_MB_I is
end tb_unb2a_test_ddr_MB_I;
-
architecture tb of tb_unb2a_test_ddr_MB_I is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
@@ -38,4 +34,3 @@ begin
g_sim_model_ddr => false
);
end tb;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
index a510857612effa6c76def774b93ede3368677c73..7f6bcc8d641644078cdd129bbb6d2c638a0c94ed 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I/unb2a_test_ddr_MB_I.vhd
@@ -28,7 +28,6 @@ use unb2a_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2a_test_ddr_MB_I is
generic (
g_design_name : string := "unb2a_test_ddr_MB_I";
@@ -78,9 +77,7 @@ entity unb2a_test_ddr_MB_I is
);
end unb2a_test_ddr_MB_I;
-
architecture str of unb2a_test_ddr_MB_I is
-
begin
u_revision : entity unb2a_test_lib.unb2a_test
generic map (
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
index 94c31dfa5967dae24ac606c78e4b18b8834091cc..0c5b8a474e1248f370d3feab3d2c8b69c14c40a1 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/tb_unb2a_test_ddr_MB_II.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2a_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2a_test_ddr_MB_II is
end tb_unb2a_test_ddr_MB_II;
-
architecture tb of tb_unb2a_test_ddr_MB_II is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
@@ -38,4 +34,3 @@ begin
g_sim_model_ddr => false
);
end tb;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
index 96168f2b76c5271bad0b2b18c2ed9ef6f0a06399..45225efbb730d73c0748f64cf82136088e54adb1 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_II/unb2a_test_ddr_MB_II.vhd
@@ -28,7 +28,6 @@ use unb2a_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2a_test_ddr_MB_II is
generic (
g_design_name : string := "unb2a_test_ddr_MB_II";
@@ -78,9 +77,7 @@ entity unb2a_test_ddr_MB_II is
);
end unb2a_test_ddr_MB_II;
-
architecture str of unb2a_test_ddr_MB_II is
-
begin
u_revision : entity unb2a_test_lib.unb2a_test
generic map (
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
index 3502dfe0dd4ee5f507b3a41fa0d3e2effca04118..4e43f4e2f6a42a7dc5706a2cbaeedd040212ddf1 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/tb_unb2a_test_ddr_MB_I_II.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2a_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2a_test_ddr_MB_I_II is
end tb_unb2a_test_ddr_MB_I_II;
-
architecture tb of tb_unb2a_test_ddr_MB_I_II is
begin
u_tb_unb2a_test : entity unb2a_test_lib.tb_unb2a_test
@@ -38,4 +34,3 @@ begin
g_sim_model_ddr => false
);
end tb;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
index 4f5fd33af052fff7dd512c9baf6d520f75e031d8..a6f576bdf924b428376ed1e7f639da238f856878 100644
--- a/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/revisions/unb2a_test_ddr_MB_I_II/unb2a_test_ddr_MB_I_II.vhd
@@ -28,7 +28,6 @@ use unb2a_board_lib.unb2_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2a_test_ddr_MB_I_II is
generic (
g_design_name : string := "unb2a_test_ddr_MB_I_II";
@@ -84,9 +83,7 @@ entity unb2a_test_ddr_MB_I_II is
);
end unb2a_test_ddr_MB_I_II;
-
architecture str of unb2a_test_ddr_MB_I_II is
-
begin
u_revision : entity unb2a_test_lib.unb2a_test
generic map (
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 2008c4a831237817c846ff326f7ef5798cf581c2..262091355adb479dc226846baa15fb29cc297e0e 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -40,8 +40,6 @@ use work.qsys_unb2a_test_pkg.all;
use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
use work.unb2a_test_pkg.all;
-
-
entity mmm_unb2a_test is
generic (
g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
@@ -223,9 +221,7 @@ entity mmm_unb2a_test is
);
end mmm_unb2a_test;
-
architecture str of mmm_unb2a_test is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
@@ -283,14 +279,11 @@ architecture str of mmm_unb2a_test is
signal sim_eth1g_eth0_reg_mosi : t_mem_mosi;
signal sim_eth1g_eth1_reg_mosi : t_mem_mosi;
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
@@ -434,13 +427,11 @@ begin
end if;
end process;
-
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
@@ -619,7 +610,6 @@ begin
reg_10gbase_r_24_readdata_export => reg_10gbase_r_24_miso.rddata(c_word_w - 1 downto 0),
reg_10gbase_r_24_waitrequest_export => reg_10gbase_r_24_miso.waitrequest,
-
reg_tr_10gbe_qsfp_ring_reset_export => OPEN,
reg_tr_10gbe_qsfp_ring_clk_export => OPEN,
reg_tr_10gbe_qsfp_ring_address_export => reg_tr_10GbE_qsfp_ring_mosi.address(c_reg_tr_10GbE_qsfp_ring_multi_adr_w - 1 downto 0),
@@ -698,7 +688,6 @@ begin
-- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
-- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index 3722b4a589731ca2a7e53e0900eabd15b57225a9..1a5006c92d75968729f9fc849d656f8f42f90f68 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2a_test_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-- $HDL_WORK/build/unb2a/quartus/unb2a_test_ddr/qsys_unb2a_test/sim/qsys_unb2a_test.vhd
@@ -394,7 +393,4 @@ package qsys_unb2a_test_pkg is
);
end component qsys_unb2a_test;
-
-
end qsys_unb2a_test_pkg;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
index 6c98ef16b95fcb030a46ea25935a5a14365af4b8..1784bbb118a15525eff62cb4869aba6a45da3f93 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/udp_stream.vhd
@@ -100,10 +100,7 @@ entity udp_stream is
);
end udp_stream;
-
-
architecture str of udp_stream is
-
-- Block generator
constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
'0', -- enable_sync
@@ -114,7 +111,6 @@ architecture str of udp_stream is
TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
constant c_min_nof_words_per_block : natural := 1;
@@ -133,9 +129,7 @@ architecture str of udp_stream is
signal diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
-
begin
-
gen_hdr_in_fields : for i in 0 to g_nof_streams - 1 generate
-- dst = src
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) downto field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000" & ID(7 downto 3) & RESIZE_UVEC(ID(2 downto 0), c_byte_w);
@@ -152,7 +146,6 @@ begin
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )) <= fifo_block_gen_src_out_arr(i).bsn(46 downto 0);
end generate;
-
-----------------------------------------------------------------------------
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
@@ -207,7 +200,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
@@ -248,7 +240,6 @@ begin
hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
);
-
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
@@ -281,13 +272,11 @@ begin
hdr_fields_out_arr => hdr_fields_out_arr
);
-
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
end generate;
-
-----------------------------------------------------------------------------
-- RX: Data buffers and BSN monitors
-----------------------------------------------------------------------------
@@ -301,8 +290,6 @@ begin
diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
end generate;
-
-
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
g_nof_streams => g_nof_streams,
@@ -325,7 +312,6 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
);
-
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
@@ -353,6 +339,4 @@ begin
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
-
end str;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
index 956661fc96079e81756188b3af018246196aaceb..73f726f8a9557e0bf3dd2f5c30c5fe6ba386ea37 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test.vhd
@@ -137,15 +137,11 @@ entity unb2a_test is
);
end unb2a_test;
-
architecture str of unb2a_test is
-
-- Firmware version x.y
constant c_fw_version : t_unb2_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2_board_mm_clk_freq_125M;
-
-
-- Revision controlled constants
constant c_use_1GbE : boolean := false; -- g_design_name="unb2a_test_1GbE" OR g_design_name="unb2a_test_10GbE" OR g_design_name="unb2a_test_all";
constant c_use_10GbE : boolean := g_design_name = "unb2a_test_10GbE" or g_design_name = "unb2a_test_all";
@@ -209,7 +205,6 @@ architecture str of unb2a_test is
constant c_max_nof_blocks_per_packet_1GbE : natural := c_max_udp_payload_nof_words_1GbE / c_min_nof_words_per_block;
constant c_max_nof_blocks_per_packet_10GbE : natural := c_max_udp_payload_nof_words_10GbE / c_min_nof_words_per_block;
-
-- System
signal cs_sim : std_logic;
@@ -436,9 +431,7 @@ architecture str of unb2a_test is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
assert false report "g_design_name=" & g_design_name severity WARNING;
-----------------------------------------------------------------------------
-- General control function
@@ -764,7 +757,6 @@ begin
ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
-
gen_udp_stream_1GbE : if c_use_1GbE = true generate
u_udp_stream_1GbE : entity work.udp_stream
generic map (
@@ -829,16 +821,13 @@ begin
-----------------------------------------------------------------------------
gen_wires_1GbE : if c_use_1GbE = true generate
gen_1GbE_wires : for i in 0 to c_nof_streams_1GbE-1 generate
-
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
dp_offload_rx_1GbE_snk_in_arr(i) <= eth1g_udp_rx_sosi_arr(i);
eth1g_udp_rx_siso_arr(i) <= dp_offload_rx_1GbE_snk_out_arr(i);
-
end generate;
end generate;
-
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
generic map (
@@ -867,7 +856,6 @@ begin
reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
-- loopback:
--dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
--dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
@@ -880,7 +868,6 @@ begin
dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
@@ -892,7 +879,6 @@ begin
reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
);
-
u_tr_10GbE_qsfp_and_ring: entity unb2a_board_10gbe_lib.unb2_board_10gbe -- QSFP and Ring lines
generic map (
g_sim => g_sim,
@@ -930,7 +916,6 @@ begin
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
-
i_QSFP_RX(0) <= QSFP_0_RX;
i_QSFP_RX(1) <= QSFP_1_RX;
i_QSFP_RX(2) <= QSFP_2_RX;
@@ -945,8 +930,6 @@ begin
QSFP_4_TX <= i_QSFP_TX(4);
QSFP_5_TX <= i_QSFP_TX(5);
-
-
u_front_io : entity unb2a_board_lib.unb2_board_front_io
generic map (
g_nof_qsfp_bus => c_nof_qsfp_bus
@@ -989,7 +972,6 @@ begin
-- RING_TX => i_RING_TX
-- );
-
-- u_tr_10GbE_back: ENTITY unb2a_board_10gbe_lib.unb2_board_10gbe -- BACK lines
-- GENERIC MAP (
-- g_sim => g_sim,
@@ -1052,7 +1034,6 @@ begin
-- BCK_ERR => BCK_ERR
-- );
-
u_front_led : entity unb2a_board_lib.unb2_board_qsfp_leds
generic map (
g_sim => g_sim,
@@ -1107,7 +1088,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- Interface : DDR4 MB_I and MB_II
-----------------------------------------------------------------------------
@@ -1115,7 +1095,6 @@ begin
assert func_tech_ddr_ctlr_data_w(g_ddr_MB_I) = func_tech_ddr_ctlr_data_w(g_ddr_MB_II) report "unb2a_test: DDR4 MB_I and MB_II must have the same ctlr data widths" severity FAILURE;
gen_stream_MB_I : if c_use_MB_I = true generate
-
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
generic map (
-- System
@@ -1270,4 +1249,3 @@ begin
end generate;
end str;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
index 86fbfc91d63b98a607226e57aa4d9e6c6d1907b4..b3bb5004d9a3571a7699de756f01fa9f7c2188c3 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/unb2a_test_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use common_lib.common_field_pkg.all;
package unb2a_test_pkg is
-
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
@@ -55,6 +54,4 @@ package unb2a_test_pkg is
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
-
end unb2a_test_pkg;
-
diff --git a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
index 27189108a85ab118e75a06c9978f44441612e511..819942904d1b93c6625ca6826dd11e4e79bc2b42 100644
--- a/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/tb/vhdl/tb_unb2a_test.vhd
@@ -60,7 +60,6 @@ entity tb_unb2a_test is
end tb_unb2a_test;
architecture tb of tb_unb2a_test is
-
constant c_sim : boolean := true;
constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
@@ -136,7 +135,6 @@ architecture tb of tb_unb2a_test is
signal si_lpbk_8 : std_logic_vector(c_unb2_board_tr_back.bus_w - 1 downto 0);
-
-- Model I2C sensor slaves as on the UniBoard
constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
constant c_fpga_temp : integer := 60;
@@ -148,9 +146,7 @@ architecture tb of tb_unb2a_test is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -162,7 +158,6 @@ begin
mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2; -- MB I reference clock (25 MHz)
mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2; -- MB II reference clock (25 MHz)
-
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -325,5 +320,4 @@ begin
mem4_in => MB_II_OU,
mem4_io => MB_II_IO
);
-
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
index 685a1ec112f356fa348a5f013653f98952b53ce4..2f62140372553a4993ae19a4fad7e85e5493390d 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/ctrl_unb2_board.vhd
@@ -248,15 +248,12 @@ entity ctrl_unb2_board is
);
end ctrl_unb2_board;
-
architecture str of ctrl_unb2_board is
-
constant c_rom_version : natural := 1; -- Only increment when something changes to the register map of rom_system_info.
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
constant c_mm_clk_freq : natural := sel_a_b(g_sim = false,g_mm_clk_freq,c_unb2_board_mm_clk_freq_10M);
-
-- Clock and reset
signal i_ext_clk200 : std_logic;
signal ext_pps : std_logic;
@@ -308,9 +305,7 @@ architecture str of ctrl_unb2_board is
attribute maxfan : integer;
attribute maxfan of dp_rst : signal is 1024;
-
begin
-
ext_clk200 <= i_ext_clk200;
xo_ethclk <= i_xo_ethclk;
xo_rst <= i_xo_rst;
@@ -359,7 +354,6 @@ begin
out_rst => i_xo_rst
);
-
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
-- MB_II_REF_CLK --> mb_II_ref_rst
@@ -513,7 +507,6 @@ begin
bck_id => this_bck_id
);
-
-----------------------------------------------------------------------------
-- Red LED control
-----------------------------------------------------------------------------
@@ -527,7 +520,6 @@ begin
TESTIO(c_unb2_board_testio_led_red) <= led_toggle_red;
end generate;
-
-----------------------------------------------------------------------------
-- Green LED control
-----------------------------------------------------------------------------
@@ -541,7 +533,6 @@ begin
TESTIO(c_unb2_board_testio_led_green) <= led_toggle_green;
end generate;
-
------------------------------------------------------------------------------
-- Toggle red LED when unb2_minimal is running, green LED for other designs.
------------------------------------------------------------------------------
@@ -556,7 +547,6 @@ begin
out_dat => led_toggle
);
-
------------------------------------------------------------------------------
-- WDI override
------------------------------------------------------------------------------
@@ -576,7 +566,6 @@ begin
wdi_override => wdi_override
);
-
------------------------------------------------------------------------------
-- Remote upgrade
------------------------------------------------------------------------------
@@ -654,7 +643,6 @@ begin
pps_sys => dp_pps
);
-
------------------------------------------------------------------------------
-- I2C control for UniBoard sensors
------------------------------------------------------------------------------
@@ -731,7 +719,6 @@ begin
temp_alarm => temp_alarm
);
-
------------------------------------------------------------------------------
-- Ethernet 1GbE
------------------------------------------------------------------------------
@@ -753,7 +740,6 @@ begin
i_tse_clk <= i_xo_ethclk;
end generate;
-
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
udp_tx_siso_arr(i) <= eth1g_udp_tx_siso_arr(i);
@@ -772,7 +758,6 @@ begin
--On hardware always generate 1GbE for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
gen_eth: if g_sim = false or g_udp_offload = true generate
-
eth1g_st_clk <= dp_clk_in when g_udp_offload = true else i_mm_clk;
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
index 1f6e0b05adcb8055a924b55700136b8fbb17b16a..f3276e71962da4539f3196a98d0488c0e136745b 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_sens.vhd
@@ -28,7 +28,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
-
entity mms_unb2_board_sens is
generic (
g_sim : boolean := false;
@@ -57,18 +56,14 @@ entity mms_unb2_board_sens is
);
end mms_unb2_board_sens;
-
architecture str of mms_unb2_board_sens is
-
constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
signal sens_err : std_logic;
signal sens_data : t_slv_8_arr(0 to g_sens_nof_result - 1);
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
-
begin
-
u_unb2_board_sens_reg : entity work.unb2_board_sens_reg
generic map (
g_sens_nof_result => g_sens_nof_result,
@@ -117,6 +112,4 @@ begin
-- would produce -1 degrees so does not trigger a temperature alarm.
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '1' when (signed(sens_data(0)) > signed('0' & temp_high)) else '0';
-
end str;
-
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
index 75ff5e6a7c1259fb0bf4e1c5d491f9c40cf8018d..8116249508a7900047234ce33af9b17cac31ab6b 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_board_system_info.vhd
@@ -61,9 +61,7 @@ entity mms_unb2_board_system_info is
);
end mms_unb2_board_system_info;
-
architecture str of mms_unb2_board_system_info is
-
-- Provide different prefixes (absolute and relative) for the same path. ModelSim understands $UNB, Quartus does not.
-- Required because the work paths of ModelSim and Quartus are different.
constant c_quartus_path_prefix : string := "";
@@ -83,9 +81,7 @@ architecture str of mms_unb2_board_system_info is
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
info <= i_info;
u_unb2_board_system_info: entity work.unb2_board_system_info
@@ -136,6 +132,4 @@ begin
rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
rd_val => rom_miso.rdval
);
-
end str;
-
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
index e619ec2ef2c9d915839f7a714ccd5ac1fd82bc88..9697e2b7f1f752ba2a41427bec97e98a72ec56b9 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/mms_unb2_fpga_sens.vhd
@@ -29,7 +29,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use technology_lib.technology_pkg.all;
-
entity mms_unb2_fpga_sens is
generic (
g_sim : boolean := false;
@@ -53,9 +52,7 @@ entity mms_unb2_fpga_sens is
);
end mms_unb2_fpga_sens;
-
architecture str of mms_unb2_fpga_sens is
-
constant c_sens_nof_result : natural := 1; --
constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
@@ -63,9 +60,7 @@ architecture str of mms_unb2_fpga_sens is
signal sens_data : t_slv_8_arr(0 to c_sens_nof_result - 1);
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
-
begin
-
u_unb2_fpga_sens_reg : entity work.unb2_fpga_sens_reg
generic map (
g_sim => g_sim,
@@ -117,6 +112,4 @@ begin
-- would produce -1 degrees so does not trigger a temperature alarm.
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '0'; -- <= '1' WHEN (SIGNED(sens_data(0)) > SIGNED('0' & temp_high)) ELSE '0';
-
end str;
-
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
index a0060fe1cb2bd4a37e7d2d8c42b5f7049a119489..9210abec473ed84d946b293e806bb4b0984261fb 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_back_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2_board_pkg.all;
-
entity unb2_board_back_io is
generic (
g_nof_back_bus : natural := c_unb2_board_tr_back.nof_bus
@@ -43,26 +42,19 @@ entity unb2_board_back_io is
end unb2_board_back_io;
architecture str of unb2_board_back_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus - 1 downto 0);
signal si_rx_2arr : t_unb2_board_back_bus_2arr(g_nof_back_bus - 1 downto 0);
-
begin
-
gen_buses : for i in 0 to g_nof_back_bus - 1 generate
BCK_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= BCK_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_back.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
index bf66c9ae6a4656b89d02363581b6f2bec874dfad..48fad46da5c7c879188216a074787a6333284c9b 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -51,13 +51,9 @@ entity unb2_board_clk125_pll is
);
end unb2_board_clk125_pll;
-
architecture arria10 of unb2_board_clk125_pll is
-
signal clk125buf : std_logic;
-
begin
-
no_clkbuf : if g_use_clkbuf = false generate
clk125buf <= clk125;
end generate;
@@ -74,7 +70,6 @@ begin
);
end generate;
-
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
generic map (
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
index 6bedd749d7db69cd5805e2b5ea138b9c52208028..9ca4ebe75e78f0da81b3f430987fdcaf05726dee 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk200_pll.vhd
@@ -113,9 +113,7 @@ entity unb2_board_clk200_pll is
);
end unb2_board_clk200_pll;
-
architecture arria10 of unb2_board_clk200_pll is
-
constant c_reset_len : natural := c_meta_delay_len;
signal clk200buf : std_logic;
@@ -126,9 +124,7 @@ architecture arria10 of unb2_board_clk200_pll is
signal st_locked : std_logic;
signal st_locked_n : std_logic;
-
begin
-
st_rst200 <= i_st_rst200;
st_clk200 <= i_st_clk200;
st_clk200p <= i_st_clk200p;
@@ -218,5 +214,4 @@ begin
clk => i_st_clk400,
out_rst => st_rst400
);
-
end arria10;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
index eef69056556e7a347ff01b9692ed0716e83db3ab..70d83befad5f22b82c1e67a22ed53b6e41810b3f 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk25_pll.vhd
@@ -49,10 +49,8 @@ entity unb2_board_clk25_pll is
);
end unb2_board_clk25_pll;
-
architecture arria10 of unb2_board_clk25_pll is
begin
-
u_pll : entity tech_pll_lib.tech_pll_clk25
generic map (
g_technology => g_technology
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
index 9d4d3c1bd320406e08799867ffc474a5868e740c..4bacebe5afdc117f5c7fa3e7c72c887bfcc81cf9 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_clk_rst.vhd
@@ -42,9 +42,7 @@ entity unb2_board_clk_rst is
);
end unb2_board_clk_rst;
-
architecture str of unb2_board_clk_rst is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
-- XO clock domain
@@ -52,9 +50,7 @@ architecture str of unb2_board_clk_rst is
-- SYS clock domain
signal sys_locked_n : std_logic;
-
begin
-
-- Reference clock and reset to SOPC system PLL
xo_rst_n <= not xo_rst;
@@ -82,5 +78,4 @@ begin
clk => sys_clk,
out_rst => sys_rst
);
-
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
index 2bbb9e4613b488d685580a4e4116110b8949e1d8..1e8e9a974ccf749390f10740b6ea31491bb2e456 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_front_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2_board_pkg.all;
-
entity unb2_board_front_io is
generic (
g_nof_qsfp_bus : natural := c_unb2_board_tr_qsfp.nof_bus
@@ -47,32 +46,24 @@ entity unb2_board_front_io is
end unb2_board_front_io;
architecture str of unb2_board_front_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus - 1 downto 0);
signal si_rx_2arr : t_unb2_board_qsfp_bus_2arr(g_nof_qsfp_bus - 1 downto 0);
-
begin
-
gen_leds : for i in 0 to g_nof_qsfp_bus - 1 generate
QSFP_LED(i * 2) <= green_led_arr(i);
QSFP_LED(i * 2 + 1) <= red_led_arr(i);
end generate;
-
gen_buses : for i in 0 to g_nof_qsfp_bus - 1 generate
QSFP_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= QSFP_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_qsfp.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_qsfp.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
index 284c10f68ec05d94e394561ad0641b1ba3bff7b0..226d6091e3a666822673eee57b30d41e244cb5cc 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_hmc_ctrl.vhd
@@ -25,7 +25,6 @@ use i2c_lib.i2c_smbus_pkg.all;
use i2c_lib.i2c_dev_unb2_pkg.all;
use common_lib.common_pkg.all;
-
entity unb2_board_hmc_ctrl is
generic (
g_sim : boolean := false;
@@ -49,9 +48,7 @@ entity unb2_board_hmc_ctrl is
);
end entity;
-
architecture rtl of unb2_board_hmc_ctrl is
-
type t_SEQUENCE is array (natural range <>) of natural;
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
@@ -117,9 +114,7 @@ architecture rtl of unb2_board_hmc_ctrl is
signal nxt_result_err : std_logic;
signal i_result_dat : t_slv_8_arr(result_dat'range);
signal nxt_result_dat : t_slv_8_arr(result_dat'range);
-
begin
-
result_dat <= i_result_dat;
regs: process(rst, clk)
@@ -188,5 +183,4 @@ begin
nxt_result_val <= rx_val;
nxt_result_err <= rx_err;
nxt_result_dat <= rx_dat when rx_val = '1' else i_result_dat;
-
end rtl;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
index 32c9cd53ff16aac7dce2793a3f61567e7f519e9c..b37cfbaf8f11db1f8998aab9844b0589d93c76f4 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_node_ctrl.vhd
@@ -54,17 +54,13 @@ entity unb2_board_node_ctrl is
);
end unb2_board_node_ctrl;
-
architecture str of unb2_board_node_ctrl is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
signal mm_locked_n : std_logic;
signal i_mm_rst : std_logic;
signal i_mm_pulse_ms : std_logic;
-
begin
-
-- Create mm_rst reset in mm_clk domain based on mm_locked
mm_rst <= i_mm_rst;
@@ -110,5 +106,4 @@ begin
wdi_in => mm_wdi_in,
wdi_out => mm_wdi_out
);
-
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
index 9417764144dda257c268e1bfbe37a4c667121147..a936b7c0e6942cd9da490062dece4fb4710ee815 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_peripherals_pkg.vhd
@@ -42,8 +42,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package unb2_board_peripherals_pkg is
-
-
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb2_board_peripherals_mm_reg is record
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
index 5a80929f83244b2ef553cba37df8501e57f14ed4..081135d117cace5d448362750f4499d99563a5d8 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pkg.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
package unb2_board_pkg is
-
-- UniBoard
constant c_unb2_board_nof_node : natural := 4; -- number of nodes on UniBoard
constant c_unb2_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb2_board_nof_node)
@@ -88,12 +87,10 @@ package unb2_board_pkg is
constant c_unb2_board_tr_qsfp : t_c_unb2_board_tr := (6, 4, 6); -- per node: 6 buses with 4 channels
constant c_unb2_board_tr_qsfp_nof_leds : natural := c_unb2_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
-
type t_unb2_board_qsfp_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_qsfp.bus_w - 1 downto 0);
type t_unb2_board_ring_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_ring.bus_w - 1 downto 0);
type t_unb2_board_back_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2_board_tr_back.bus_w - 1 downto 0);
-
-- Auxiliary
-- Test IO Interface
@@ -131,7 +128,6 @@ package unb2_board_pkg is
-- SIGNAL RECORD DECLARATIONS -----------------------------------------------
-
-- I2C, MDIO
-- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
-- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
@@ -156,9 +152,7 @@ package unb2_board_pkg is
end unb2_board_pkg;
-
package body unb2_board_pkg is
-
function func_unb2_board_system_info(VERSION : in std_logic_vector(c_unb2_board_aux.version_w - 1 downto 0);
ID : in std_logic_vector(c_unb2_board_aux.id_w - 1 downto 0)) return t_c_unb2_board_system_info is
variable v_system_info : t_c_unb2_board_system_info;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
index 14226a8a743f12115a2d86f18823f493351f3893..efe7114174765639425ad726eff2c665d6c350ed 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_pmbus_ctrl.vhd
@@ -25,7 +25,6 @@ use i2c_lib.i2c_smbus_pkg.all;
use i2c_lib.i2c_dev_unb2_pkg.all;
use common_lib.common_pkg.all;
-
entity unb2_board_pmbus_ctrl is
generic (
g_sim : boolean := false;
@@ -49,9 +48,7 @@ entity unb2_board_pmbus_ctrl is
);
end entity;
-
architecture rtl of unb2_board_pmbus_ctrl is
-
type t_SEQUENCE is array (natural range <>) of natural;
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
@@ -117,9 +114,7 @@ architecture rtl of unb2_board_pmbus_ctrl is
signal nxt_result_err : std_logic;
signal i_result_dat : t_slv_8_arr(result_dat'range);
signal nxt_result_dat : t_slv_8_arr(result_dat'range);
-
begin
-
result_dat <= i_result_dat;
regs: process(rst, clk)
@@ -188,5 +183,4 @@ begin
nxt_result_val <= rx_val;
nxt_result_err <= rx_err;
nxt_result_dat <= rx_dat when rx_val = '1' else i_result_dat;
-
end rtl;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
index 80e8ae543fd3cd5fa9f949d11cc24054e678b5b3..db1d2a02523b0507df351a6a312d529c7a741251 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_qsfp_leds.vhd
@@ -88,9 +88,7 @@ entity unb2_board_qsfp_leds is
);
end unb2_board_qsfp_leds;
-
architecture str of unb2_board_qsfp_leds is
-
constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
constant c_nof_lanes : natural := g_nof_qsfp * c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
@@ -103,9 +101,7 @@ architecture str of unb2_board_qsfp_leds is
signal qsfp_on_arr : std_logic_vector(g_nof_qsfp - 1 downto 0);
signal qsfp_evt_arr : std_logic_vector(g_nof_qsfp - 1 downto 0);
-
begin
-
pulse_ms <= i_pulse_ms;
pulse_s <= i_pulse_s;
@@ -152,7 +148,6 @@ begin
end generate;
gen_user_image : if g_factory_image = false generate
-
red_led_arr <= (others => '0');
gen_green_ctrl_arr : for I in c_nof_lanes - 1 downto 0 generate
@@ -161,7 +156,6 @@ begin
end generate;
gen_green_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
-
qsfp_on_arr(I) <= orv(green_on_arr( (I + 1) * c_quad - 1 downto + I * c_quad));
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
@@ -182,5 +176,4 @@ begin
);
end generate;
end generate;
-
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
index fba74d7787a2aca45124388de49ce1165394de3f..b83c06965924d692e1324f51a4141d7acd068f1a 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_ring_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2_board_pkg.all;
-
entity unb2_board_ring_io is
generic (
g_nof_ring_bus : natural := c_unb2_board_tr_ring.nof_bus
@@ -38,26 +37,19 @@ entity unb2_board_ring_io is
end unb2_board_ring_io;
architecture str of unb2_board_ring_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0);
signal si_rx_2arr : t_unb2_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0);
-
begin
-
gen_buses : for i in 0 to g_nof_ring_bus - 1 generate
RING_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= RING_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2_board_tr_ring.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
index 097523040219564a5a78f81f7983e3725439f59a..877028aa9cafa4b330899aaf95b5b6d92c69e7f7 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens.vhd
@@ -48,9 +48,7 @@ entity unb2_board_sens is
);
end entity;
-
architecture str of unb2_board_sens is
-
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
@@ -67,7 +65,6 @@ architecture str of unb2_board_sens is
-- octave:8> log2(delay/t)
-- ans = 13
-
--CONSTANT c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, g_comma_w);
@@ -78,9 +75,7 @@ architecture str of unb2_board_sens is
signal smbus_out_err : std_logic;
signal smbus_out_ack : std_logic;
signal smbus_out_end : std_logic;
-
begin
-
gen_unb2_board_sens_ctrl : if g_i2c_peripheral = c_i2c_peripheral_sens generate
u_unb2_board_sens_ctrl : entity work.unb2_board_sens_ctrl
generic map (
@@ -172,5 +167,4 @@ begin
scl => scl,
sda => sda
);
-
end architecture;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
index 32d56026555ac7aedb128c204fdba55da7bda98f..9da0c246c199f3d96b40c90dda720db9f370a1f9 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_ctrl.vhd
@@ -27,7 +27,6 @@ use i2c_lib.i2c_dev_ltc4260_pkg.all;
use i2c_lib.i2c_dev_unb2_pkg.all;
use common_lib.common_pkg.all;
-
entity unb2_board_sens_ctrl is
generic (
g_sim : boolean := false;
@@ -51,9 +50,7 @@ entity unb2_board_sens_ctrl is
);
end entity;
-
architecture rtl of unb2_board_sens_ctrl is
-
-- I2C slave commands of the devices on the I2C bus on UniBoard
constant TMP451_LOC_HI : natural := 16#00#;
constant TMP451_LOC_LO : natural := 16#15#;
@@ -133,9 +130,7 @@ architecture rtl of unb2_board_sens_ctrl is
signal nxt_result_err : std_logic;
signal i_result_dat : t_slv_8_arr(result_dat'range);
signal nxt_result_dat : t_slv_8_arr(result_dat'range);
-
begin
-
result_dat <= i_result_dat;
regs: process(rst, clk)
@@ -204,5 +199,4 @@ begin
nxt_result_val <= rx_val;
nxt_result_err <= rx_err;
nxt_result_dat <= rx_dat when rx_val = '1' else i_result_dat;
-
end rtl;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
index 1ff3381d0d874a40b95c1b3c288805da1c429f51..9790dc3ea0f4d588f779a2cbbc1b52487596c100 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_sens_reg.vhd
@@ -89,9 +89,7 @@ entity unb2_board_sens_reg is
);
end unb2_board_sens_reg;
-
architecture rtl of unb2_board_sens_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
-- +1 to fit sens_err in the last address
@@ -103,9 +101,7 @@ architecture rtl of unb2_board_sens_reg is
init_sl => '0');
signal i_temp_high : std_logic_vector(6 downto 0);
-
begin
-
temp_high <= i_temp_high;
------------------------------------------------------------------------------
@@ -158,5 +154,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
index 3ef429a1f90f2172a9910ac8fbfd3c88a7dff9e1..c3958aa4075c5c30ba82ba3ebb60a095c07d8833 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info.vhd
@@ -50,9 +50,7 @@ entity unb2_board_system_info is
);
end unb2_board_system_info;
-
architecture str of unb2_board_system_info is
-
signal cs_sim : std_logic;
signal hw_version_reg : std_logic_vector(hw_version'range);
@@ -63,9 +61,7 @@ architecture str of unb2_board_system_info is
signal nxt_chip_id : std_logic_vector(chip_id'range);
signal nxt_node_id : std_logic_vector(node_id'range);
signal nxt_is_node2 : std_logic;
-
begin
-
p_reg : process(clk)
begin
if rising_edge(clk) then
@@ -98,5 +94,4 @@ begin
nxt_chip_id <= id_reg(1 downto 0);
nxt_node_id <= id_reg(1 downto 0);
nxt_is_node2 <= '1' when TO_UINT(id_reg(1 downto 0)) = 2 else '0';
-
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
index 138a1de924c094b4e0a801b028efc85c8dd0c0ec..2b7a13332c5803c8e7a09da72b6fbb027358d1e5 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_system_info_reg.vhd
@@ -71,9 +71,7 @@ entity unb2_board_system_info_reg is
);
end unb2_board_system_info_reg;
-
architecture rtl of unb2_board_system_info_reg is
-
constant c_nof_fixed_regs : natural := 2; -- info, use_phy
constant c_nof_design_name_regs : natural := 13; -- design_name
constant c_nof_stamp_regs : natural := 3; -- date, time, svn rev
@@ -92,9 +90,7 @@ architecture rtl of unb2_board_system_info_reg is
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
begin
@@ -132,13 +128,8 @@ begin
elsif vA < c_nof_fixed_regs + c_nof_design_name_regs + c_nof_stamp_regs + c_nof_design_note_regs then
sla_out.rddata(c_word_w - 1 downto 0) <= c_design_note(vA - c_nof_fixed_regs - c_nof_design_name_regs - c_nof_stamp_regs);
-
end if;
-
end if;
end if;
end process;
-
-
end rtl;
-
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
index d474968663c28b049db63a3c073f134b1bab2cf5..e09adb5ff956c56a6a0ad91728c26da6f7fd03e3 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_extend.vhd
@@ -43,9 +43,7 @@ entity unb2_board_wdi_extend is
);
end unb2_board_wdi_extend;
-
architecture str of unb2_board_wdi_extend is
-
signal wdi_evt : std_logic;
signal wdi_cnt : std_logic_vector(g_extend_w - 1 downto 0);
@@ -53,9 +51,7 @@ architecture str of unb2_board_wdi_extend is
signal i_wdi_out : std_logic;
signal nxt_wdi_out : std_logic;
-
begin
-
wdi_out <= i_wdi_out;
p_clk : process(rst, clk)
@@ -94,5 +90,4 @@ begin
cnt_en => wdi_cnt_en,
count => wdi_cnt
);
-
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
index 365e280976be5335fc7d3e67cb924844680f1f01..fa05af1d4f06f94cf92b05921391eaadd7b20ab7 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_board_wdi_reg.vhd
@@ -43,9 +43,7 @@ entity unb2_board_wdi_reg is
);
end unb2_board_wdi_reg;
-
architecture rtl of unb2_board_wdi_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
@@ -55,9 +53,7 @@ architecture rtl of unb2_board_wdi_reg is
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -82,9 +78,6 @@ begin
when others => null; -- unused MM addresses
end case;
end if;
-
end if;
end process;
-
end rtl;
-
diff --git a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
index c8474454b250d148ec7dd110a5f7d2736c3f6088..049c7da72e89a2425d552442030f2e3bf2964138 100644
--- a/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/src/vhdl/unb2_fpga_sens_reg.vhd
@@ -29,7 +29,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2_fpga_sens_reg is
generic (
g_sim : boolean;
@@ -59,13 +58,9 @@ entity unb2_fpga_sens_reg is
);
end unb2_fpga_sens_reg;
-
architecture str of unb2_fpga_sens_reg is
-
--SIGNAL i_temp_high : STD_LOGIC_VECTOR(6 DOWNTO 0);
-
begin
-
temp_high <= (others => '0'); -- i_temp_high;
u_fpga_sense: entity fpga_sense_lib.fpga_sense
@@ -85,5 +80,4 @@ begin
reg_voltage_store_mosi => sla_voltage_in,
reg_voltage_store_miso => sla_voltage_out
);
-
end str;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
index 3128953b34d30f0046f43514a5b1daec64864d77..a91ab0e90c9610711bd7a345d391b1dd8092e692 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_mms_unb2_board_sens.vhd
@@ -40,7 +40,6 @@ use common_lib.tb_common_mem_pkg.all;
use work.unb2_board_pkg.all;
architecture tb of tb_mms_unb2_board_sens is
-
constant c_sim : boolean := true; -- FALSE;
constant c_repeat : natural := 2;
constant c_clk_freq : natural := 100 * 10**6;
@@ -77,9 +76,7 @@ architecture tb of tb_mms_unb2_board_sens is
signal scl_stretch : std_logic := 'Z';
signal scl : std_logic;
signal sda : std_logic;
-
begin
-
rst <= '0' after 4 * c_clk_period;
clk <= (not clk) or tb_end after c_clk_period / 2;
@@ -147,10 +144,8 @@ begin
assert TO_UINT(sens_dat) = c_sens_expected(3) report "Wrong hot swap V source value" severity ERROR;
proc_common_wait_some_cycles(clk, 1);
assert TO_UINT(sens_dat) = c_sens_expected(4) report "An I2C error occurred" severity ERROR;
-
end process;
-
-- I2C sensors master
u_mms_unb2_board_sens : entity work.mms_unb2_board_sens
generic map (
@@ -210,6 +205,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
-
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
index 3e7d5fa1b90e7d33b47070cafe35d3e4beeba0ae..bd1504ec133b48c2ee0a1855949db6f37474baa8 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk125_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2_board_clk125_pll is
end tb_unb2_board_clk125_pll;
-
architecture tb of tb_unb2_board_clk125_pll is
-
constant c_ext_clk_period : time := 8 ns; -- 125 MHz
signal tb_end : std_logic := '0';
@@ -48,9 +44,7 @@ architecture tb of tb_unb2_board_clk125_pll is
signal c2_clk100 : std_logic;
signal c3_clk125 : std_logic;
signal pll_locked : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
index 01c62f46e18afd135ac10ee8541ec24dc3469872..ae4e087f1ebbb885fdc524cf39c36ecfaae6575c 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk200_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2_board_clk200_pll is
end tb_unb2_board_clk200_pll;
-
architecture tb of tb_unb2_board_clk200_pll is
-
constant c_ext_clk_period : time := 5 ns; -- 200 MHz
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
@@ -63,9 +59,7 @@ architecture tb of tb_unb2_board_clk200_pll is
signal dp_clk200 : std_logic;
signal dp_rst200 : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
@@ -112,5 +106,4 @@ begin
st_clk200 => dp_clk200,
st_rst200 => dp_rst200
);
-
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
index b460c275ce5418d63af3d6f509f9d2a1c240bbe0..b8ea88958d0d5715d52945bb2c636f11ca860615 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_clk25_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2_board_clk25_pll is
end tb_unb2_board_clk25_pll;
-
architecture tb of tb_unb2_board_clk25_pll is
-
constant c_ext_clk_period : time := 40 ns; -- 25 MHz
signal tb_end : std_logic := '0';
@@ -48,9 +44,7 @@ architecture tb of tb_unb2_board_clk25_pll is
signal c2_clk100 : std_logic;
signal c3_clk125 : std_logic;
signal pll_locked : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
index 35e015a38b70609756ed4853710a53c6957244b2..1d6125db58dc61776f1aa9f906a18959ecabfcde 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_node_ctrl.vhd
@@ -24,13 +24,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2_board_node_ctrl is
end tb_unb2_board_node_ctrl;
-
architecture tb of tb_unb2_board_node_ctrl is
-
constant c_scale : natural := 100; -- scale to speed up simulation
constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
@@ -62,9 +59,7 @@ architecture tb of tb_unb2_board_node_ctrl is
signal pulse_us : std_logic;
signal pulse_ms : std_logic;
signal pulse_s : std_logic;
-
begin
-
-- run 2000 ms
mm_clk <= not mm_clk after c_mm_clk_period / 2;
@@ -95,5 +90,4 @@ begin
mm_pulse_ms => pulse_ms,
mm_pulse_s => pulse_s
);
-
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
index 86668b2331a93494aabdafcb603c1503a73acbe1..2a4f41e54767bb5b341bc1677d6083e49cee22ff 100644
--- a/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board/tb/vhdl/tb_unb2_board_qsfp_leds.vhd
@@ -46,7 +46,6 @@ entity tb_unb2_board_qsfp_leds is
end tb_unb2_board_qsfp_leds;
architecture tb of tb_unb2_board_qsfp_leds is
-
constant c_clk_freq_hz : natural := 200 * 10**6;
constant c_clk_period_ns : natural := 10**9 / c_clk_freq_hz;
constant c_nof_clk_per_us : natural := 1000 / c_clk_period_ns;
@@ -84,9 +83,7 @@ architecture tb of tb_unb2_board_qsfp_leds is
signal dbg_sop : std_logic;
signal dbg_sop_slv : std_logic_vector(c_nof_lanes - 1 downto 0);
signal dbg_sosi : t_dp_sosi;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -186,5 +183,4 @@ begin
green_led_arr => user_green_led_arr,
red_led_arr => user_red_led_arr
);
-
end tb;
diff --git a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
index 62b69dadc36b6e77433c1c35b5f20ff2699be195..1abc9ae0a3a1e55644b88e23af49158714ea4835 100644
--- a/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
+++ b/boards/uniboard2a/libraries/unb2a_board_10gbe/src/vhdl/unb2_board_10gbe.vhd
@@ -27,7 +27,6 @@ use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2_board_10gbe is
generic (
g_sim : boolean := false;
@@ -71,13 +70,10 @@ entity unb2_board_10gbe is
);
end unb2_board_10gbe;
-
architecture str of unb2_board_10gbe is
-
signal tr_ref_clk_312 : std_logic;
signal tr_ref_clk_156 : std_logic;
signal tr_ref_rst_156 : std_logic;
-
begin
u_unb2_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
generic map (
@@ -92,7 +88,6 @@ begin
rst_312 => open
);
-
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_technology => g_technology,
@@ -136,5 +131,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
index 0b79a074c69efa82d9bf04551262e1f632f69eb7..4b7405306f3ac123a1f109107a81d09bce051d17 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/src/vhdl/unb2b_arp_ping.vhd
@@ -81,9 +81,7 @@ entity unb2b_arp_ping is
);
end unb2b_arp_ping;
-
architecture str of unb2b_arp_ping is
-
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_50M;
-- System
@@ -178,7 +176,6 @@ architecture str of unb2b_arp_ping is
signal src_ip : std_logic_vector(c_network_ip_addr_slv'range);
signal src_mac : std_logic_vector(c_network_eth_mac_slv'range);
begin
-
system_info <= func_unb2b_board_system_info(VERSION, ID);
back_id <= to_uvec(system_info.bck_id, c_8); -- xx = bck_id
node_id_ip <= to_uvec(system_info.node_id + 1, c_8); -- yy = node_id +1 to avoid reserved 00
@@ -328,7 +325,6 @@ begin
end if;
end process;
-
eth1g_mm_rst <= mm_rst;
-- led control
@@ -340,7 +336,6 @@ begin
end if;
end process;
-
--u_eth1g_master : ENTITY eth1g_lib.eth1g_master(beh)
u_eth1g_master : entity eth1g_lib.eth1g_master(rtl)
generic map (
@@ -362,7 +357,6 @@ begin
src_ip => src_ip
);
-
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
generic map (
g_sim => g_sim,
@@ -386,6 +380,4 @@ begin
red_led_arr => qsfp_red_led_arr,
QSFP_LED => QSFP_LED
);
-
end str;
-
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
index 4ca8b24be467127c4e18369dd8281268b9fe9845..e5066695940d5c016c797f682f075981cb035c43 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_eth1g.vhd
@@ -39,7 +39,6 @@
-- > as 10
-- > run -all
-
library IEEE, common_lib, dp_lib, technology_lib, eth_lib, tech_tse_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -55,7 +54,6 @@ use tech_tse_lib.tech_tse_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
use eth_lib.eth_pkg.all;
-
entity tb_eth1g is
-- Test bench control parameters
generic (
@@ -76,9 +74,7 @@ entity tb_eth1g is
);
end tb_eth1g;
-
architecture tb of tb_eth1g is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
constant cable_delay : time := 12 ns;
@@ -247,7 +243,6 @@ architecture tb of tb_eth1g is
signal udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
signal udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
-
-- LCU TSE interface
signal lcu_init : std_logic := '1';
signal lcu_tse_miso : t_mem_miso;
@@ -273,9 +268,7 @@ architecture tb of tb_eth1g is
signal rx_pkt_cnt : natural := 0;
signal rx_pkt_discarded_cnt: natural := 0;
signal rx_pkt_flushed_cnt : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
-- run 50 us
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
@@ -335,7 +328,6 @@ begin
wait;
end process;
-
p_eth_control : process
variable v_eth_control_word : std_logic_vector(c_word_w - 1 downto 0);
begin
@@ -502,7 +494,6 @@ begin
wait;
end process;
-
p_lcu_receiver : process
begin
-- . Avalon ST
@@ -653,5 +644,4 @@ begin
end if;
wait;
end process;
-
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
index cbae4775137ff0fde278d9b0377adde1058c2fa3..ce140222f1027601e53316b1a3479af8727686f2 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_tb_eth1g.vhd
@@ -33,24 +33,19 @@ use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
-
entity tb_tb_eth1g is
generic (
g_technology_dut : natural := c_tech_select_default
);
end tb_tb_eth1g;
-
architecture tb of tb_tb_eth1g is
-
constant c_technology_lcu : natural := c_tech_select_default;
constant c_tb_end_vec : std_logic_vector(15 downto 0) := (others => '1');
signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
-
begin
-
-- g_technology_dut : NATURAL := c_tech_select_default;
-- g_technology_lcu : NATURAL := c_tech_select_default;
-- g_frm_discard_en : BOOLEAN := TRUE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
diff --git a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
index 9ef33d30ab51783b30bd3fa13d8e207605b05832..7acf42ed8e04c75dc18ba3b005bbfcc6e48bbc9a 100644
--- a/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
+++ b/boards/uniboard2b/designs/unb2b_arp_ping/tb/vhdl/tb_unb2b_arp_ping.vhd
@@ -56,7 +56,6 @@ use tech_tse_lib.tech_tse_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_unb2b_arp_ping is
generic (
g_frm_discard_en : boolean := false; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
@@ -75,7 +74,6 @@ entity tb_unb2b_arp_ping is
end tb_unb2b_arp_ping;
architecture tb of tb_unb2b_arp_ping is
-
constant c_sim : boolean := false; -- TRUE;
constant c_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model;
@@ -292,9 +290,7 @@ architecture tb of tb_unb2b_arp_ping is
signal tx_total_header : t_network_total_header; -- transmitted packet header
signal discard_total_header: t_network_total_header; -- transmitted packet header for to be discarded packet
signal exp_total_header : t_network_total_header; -- expected received packet header
-
begin
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -444,7 +440,6 @@ begin
exp_total_header.icmp <= c_exp_icmp_header;
exp_total_header.udp <= c_exp_udp_header;
-
p_lcu_transmitter : process
begin
-- . Avalon ST
@@ -505,7 +500,6 @@ begin
wait;
end process;
-
p_lcu_receiver : process
begin
-- . Avalon ST
@@ -578,5 +572,4 @@ begin
end if;
wait;
end process;
-
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
index 8c7247cb87a00c56859336548244665f7a501267..ccfa91c51360b894621e7c726d976f3ca44be5c8 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/mmm_unb2b_heater.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_unb2b_heater_pkg.all;
-
entity mmm_unb2b_heater is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -106,19 +105,15 @@ entity mmm_unb2b_heater is
end mmm_unb2b_heater;
architecture str of mmm_unb2b_heater is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -155,7 +150,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
index 831de95afb0760286cb83dc572b3e1001adba83f..b36fb7ceda0540405cad0b725787029d599db6c2 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/qsys_unb2b_heater_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2b_heater_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v17 QSYS builder
-----------------------------------------------------------------------------
@@ -159,5 +158,4 @@ package qsys_unb2b_heater_pkg is
);
end component qsys_unb2b_heater;
-
end qsys_unb2b_heater_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
index 9c548cd558828340c757355a4f4819280a09aa53..be12b6758a30a849d1b19047b11e49d489991e88 100644
--- a/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/src/vhdl/unb2b_heater.vhd
@@ -72,9 +72,7 @@ entity unb2b_heater is
);
end unb2b_heater;
-
architecture str of unb2b_heater is
-
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_50M;
@@ -158,9 +156,7 @@ architecture str of unb2b_heater is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -385,7 +381,6 @@ begin
QSFP_LED => QSFP_LED
);
-
u_heater : entity util_lib.util_heater
generic map (
g_technology => g_technology,
@@ -407,4 +402,3 @@ begin
sla_out => reg_heater_miso
);
end str;
-
diff --git a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
index 0d2dfea153be6fd6b2a1e357f557b3b80a453152..aec05451addeae374aa66e1819b2f275f8230316 100644
--- a/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
+++ b/boards/uniboard2b/designs/unb2b_heater/tb/vhdl/tb_unb2b_heater.vhd
@@ -58,7 +58,6 @@ entity tb_unb2b_heater is
end tb_unb2b_heater;
architecture tb of tb_unb2b_heater is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -110,9 +109,7 @@ architecture tb of tb_unb2b_heater is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -216,5 +213,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 7d7bea513e97a96a44ba6a4da73962bd7ade270c..1188b1f4a3a8c3bda14f3b6fb3aaf6912e8d9d4f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -16,4 +16,3 @@
refclk => CONNECTED_TO_refclk, -- refclk.clk
rst => CONNECTED_TO_rst -- reset.reset
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 1bc0ee7c56cf0561ddbb42d55933480e42c046b8..4d125d7d6b09eb801f54521d54896e4cd0d3f452 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -12,4 +12,3 @@
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index e6c8fc658b5b43427db74a6adb53ee16cf62b553..2fdfadb51af42decdc595af06f6653c82f64f67b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -12,4 +12,3 @@
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index 46793b217ef01564f7707dd7e5d33d21bb5b0f64..f5e2ba1f77a9a3ef8e6ec47a9929ad820950c0a3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -160,4 +160,3 @@
reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index 4aa29f21f8c2cd0ba644f59c2b91cac8ea4c33a0..e49f93a337e01a20a39b99a717881d143e0d0970 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -22,4 +22,3 @@
rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index bfd91a8bfa3fda8a6e8e4b5b40fa8e1f089e3a1c..af64e251092b8abe7083a94e7070e5407b77a322 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -14,4 +14,3 @@
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 342b6062c183b2ab4d90c5d7b8a360017f7b7631..26992b63a4edbecaa5e2a236b47a7c62d9e417d4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -14,4 +14,3 @@
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 9868df2cdd27ad40136cdb1b2611f283587904e7..745dc1937c6fff32fda95a03e5bd47b88e8206b7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -98,4 +98,3 @@
somf => CONNECTED_TO_somf, -- somf.export
sysref => CONNECTED_TO_sysref -- sysref.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index 7da9be04fe1b103526227ce32d2cb6ca6fd36a07..acbc33a2d1959920765b1866572b908d153acbc2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -14,4 +14,3 @@
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index c97253ac7931f744e6bead40b44ceea923313f43..42aae3ddf073f5dfbfee338c2139ed38675a6a2a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index b57aa7daff98dbab340fda442699b89b58d52aab..4ddaf7fa7d6f6d85a966525b9dd908dbdae955a3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index 3c94c1901f613072062b922ea5210533129da04d..d648f26fb1cb1a3e9c804714afad5c500ffa4798 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -31,7 +31,6 @@ use common_lib.common_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
use work.eth_pkg.all;
-
entity avs2_eth_coe is
port (
----------------------------------------------------------------------------
@@ -100,10 +99,8 @@ entity avs2_eth_coe is
);
end avs2_eth_coe;
-
architecture wrap of avs2_eth_coe is
begin
-
------------------------------------------------------------------------------
-- Wires
@@ -135,5 +132,4 @@ begin
-- Interrupt Sender interface
ins_interrupt_irq <= coe_irq_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index 3fc6ebb7a2de575f47b388de4ca11860366bf4fe..e879f1b9edecdcf0c9866d6359c01c0b6a645338 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -28,7 +28,6 @@ use IEEE.numeric_std.all;
use work.common_pkg.all;
package common_network_layers_pkg is
-
-- All *_len constants are in nof octets = nof bytes = c_8 bits
------------------------------------------------------------------------------
@@ -353,6 +352,5 @@ package common_network_layers_pkg is
end common_network_layers_pkg;
-
package body common_network_layers_pkg is
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 9469fd2656c232a4d88c0eaa1403bedeaf1e0a2e..4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -35,7 +35,6 @@ use IEEE.numeric_std.all;
use IEEE.math_real.all;
package common_pkg is
-
-- CONSTANT DECLARATIONS ----------------------------------------------------
-- some integers
@@ -160,7 +159,6 @@ package common_pkg is
clken : std_logic; -- := '1';
end record;
-
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
@@ -461,7 +459,6 @@ package common_pkg is
end common_pkg;
package body common_pkg is
-
function pow2(n : natural) return natural is
begin
return 2**n;
@@ -1393,7 +1390,6 @@ package body common_pkg is
return v_mat;
end;
-
-- Support concatenation of up to 7 slv into 1 slv
function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
constant c_max_w : natural := a'length + b'length + c'length + d'length + e'length + f'length + g'length;
@@ -1545,7 +1541,6 @@ package body common_pkg is
return func_slv_extract(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
-
function TO_UINT(vec : std_logic_vector) return natural is
begin
return to_integer(unsigned(vec));
@@ -1675,7 +1670,6 @@ package body common_pkg is
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
-
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
@@ -1837,7 +1831,6 @@ package body common_pkg is
return v_res;
end;
-
-- Functions s_round, s_round_up and u_round:
--
-- . The returned output width is input width - n.
@@ -2137,7 +2130,6 @@ package body common_pkg is
return str((i + 1) * width - 1 downto i * width);
end;
-
function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
@@ -2147,7 +2139,6 @@ package body common_pkg is
return v_concat_slv;
end;
-
------------------------------------------------------------------------------
-- common_fifo_*
------------------------------------------------------------------------------
@@ -2177,7 +2168,6 @@ package body common_pkg is
--synthesis translate_on
end procedure proc_common_fifo_asserts;
-
------------------------------------------------------------------------------
-- common_fanout_tree
------------------------------------------------------------------------------
@@ -2198,7 +2188,6 @@ package body common_pkg is
return v_stage_pipeline_arr;
end function func_common_fanout_tree_pipelining;
-
------------------------------------------------------------------------------
-- common_reorder_symbol
------------------------------------------------------------------------------
@@ -2360,4 +2349,3 @@ package body common_pkg is
end proc_common_dclk_generate_sclk;
end common_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 40128fea21ea799361fb11525746787d64202e63..7b6d1a2da0ec2558d87aa708358be0b79c70944d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package dp_stream_pkg is
-
------------------------------------------------------------------------------
-- General DP stream record defintion
------------------------------------------------------------------------------
@@ -395,9 +394,7 @@ package dp_stream_pkg is
end dp_stream_pkg;
-
package body dp_stream_pkg is
-
-- Check sosi.valid against siso.ready
procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
signal clk : in std_logic;
@@ -412,6 +409,7 @@ package body dp_stream_pkg is
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
report "RL ERROR" severity FAILURE;
end if;
+
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
end if;
end proc_dp_siso_alert;
@@ -623,7 +621,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_first;
-
-- Shift and combine part of previous data and this data,
function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
@@ -656,7 +653,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift;
-
-- Shift part of tail data and account for input empty
function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
@@ -685,7 +681,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_last;
-
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
@@ -713,7 +708,6 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_split;
-
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -727,7 +721,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_sosi_arr_mux;
-
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
@@ -845,7 +838,6 @@ package body dp_stream_pkg is
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
-
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
@@ -913,7 +905,6 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
-
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
@@ -1164,7 +1155,6 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_copy_valid_bsn;
-
-- Functions to combinatorially handle channels
function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
@@ -1195,7 +1185,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_remove;
-
function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1203,7 +1192,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_error_set;
-
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1211,7 +1199,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_bsn_set;
-
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
@@ -1224,7 +1211,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_combine_info_and_data;
-
function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
@@ -1487,4 +1473,3 @@ package body dp_stream_pkg is
end;
end dp_stream_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index d1ec55fe6f2419a5805d9ba52139b75498a111d5..103667575791b885ea6d707accd5dc6c04bcb535 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -28,9 +28,7 @@ use common_lib.common_network_layers_pkg.all;
use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
-
package eth_pkg is
-
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
@@ -57,7 +55,6 @@ package eth_pkg is
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- Definitions for eth header status
------------------------------------------------------------------------------
@@ -219,9 +216,7 @@ package eth_pkg is
end eth_pkg;
-
package body eth_pkg is
-
-- Register mapping functions
function func_eth_mm_reg_demux(mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
variable v_reg : t_eth_mm_reg_demux;
@@ -231,6 +226,7 @@ package body eth_pkg is
v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
end loop;
+
return v_reg;
end func_eth_mm_reg_demux;
@@ -350,4 +346,3 @@ package body eth_pkg is
end func_eth_mm_reg_status;
end eth_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 2eb92cbc7db8058c485f2204fe2a2969a018a1a6..177eb750c7386763043b7282d1bfb4b3a3fc6636 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package tech_tse_pkg is
-
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
constant c_tech_tse_byte_addr_w : natural := c_tech_tse_reg_addr_w + 2;
constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
@@ -84,6 +83,5 @@ package tech_tse_pkg is
end tech_tse_pkg;
-
package body tech_tse_pkg is
end tech_tse_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index 3c94c1901f613072062b922ea5210533129da04d..d648f26fb1cb1a3e9c804714afad5c500ffa4798 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -31,7 +31,6 @@ use common_lib.common_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
use work.eth_pkg.all;
-
entity avs2_eth_coe is
port (
----------------------------------------------------------------------------
@@ -100,10 +99,8 @@ entity avs2_eth_coe is
);
end avs2_eth_coe;
-
architecture wrap of avs2_eth_coe is
begin
-
------------------------------------------------------------------------------
-- Wires
@@ -135,5 +132,4 @@ begin
-- Interrupt Sender interface
ins_interrupt_irq <= coe_irq_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index 3fc6ebb7a2de575f47b388de4ca11860366bf4fe..e879f1b9edecdcf0c9866d6359c01c0b6a645338 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -28,7 +28,6 @@ use IEEE.numeric_std.all;
use work.common_pkg.all;
package common_network_layers_pkg is
-
-- All *_len constants are in nof octets = nof bytes = c_8 bits
------------------------------------------------------------------------------
@@ -353,6 +352,5 @@ package common_network_layers_pkg is
end common_network_layers_pkg;
-
package body common_network_layers_pkg is
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 9469fd2656c232a4d88c0eaa1403bedeaf1e0a2e..4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -35,7 +35,6 @@ use IEEE.numeric_std.all;
use IEEE.math_real.all;
package common_pkg is
-
-- CONSTANT DECLARATIONS ----------------------------------------------------
-- some integers
@@ -160,7 +159,6 @@ package common_pkg is
clken : std_logic; -- := '1';
end record;
-
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
@@ -461,7 +459,6 @@ package common_pkg is
end common_pkg;
package body common_pkg is
-
function pow2(n : natural) return natural is
begin
return 2**n;
@@ -1393,7 +1390,6 @@ package body common_pkg is
return v_mat;
end;
-
-- Support concatenation of up to 7 slv into 1 slv
function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
constant c_max_w : natural := a'length + b'length + c'length + d'length + e'length + f'length + g'length;
@@ -1545,7 +1541,6 @@ package body common_pkg is
return func_slv_extract(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
-
function TO_UINT(vec : std_logic_vector) return natural is
begin
return to_integer(unsigned(vec));
@@ -1675,7 +1670,6 @@ package body common_pkg is
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
-
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
@@ -1837,7 +1831,6 @@ package body common_pkg is
return v_res;
end;
-
-- Functions s_round, s_round_up and u_round:
--
-- . The returned output width is input width - n.
@@ -2137,7 +2130,6 @@ package body common_pkg is
return str((i + 1) * width - 1 downto i * width);
end;
-
function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
@@ -2147,7 +2139,6 @@ package body common_pkg is
return v_concat_slv;
end;
-
------------------------------------------------------------------------------
-- common_fifo_*
------------------------------------------------------------------------------
@@ -2177,7 +2168,6 @@ package body common_pkg is
--synthesis translate_on
end procedure proc_common_fifo_asserts;
-
------------------------------------------------------------------------------
-- common_fanout_tree
------------------------------------------------------------------------------
@@ -2198,7 +2188,6 @@ package body common_pkg is
return v_stage_pipeline_arr;
end function func_common_fanout_tree_pipelining;
-
------------------------------------------------------------------------------
-- common_reorder_symbol
------------------------------------------------------------------------------
@@ -2360,4 +2349,3 @@ package body common_pkg is
end proc_common_dclk_generate_sclk;
end common_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 40128fea21ea799361fb11525746787d64202e63..7b6d1a2da0ec2558d87aa708358be0b79c70944d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package dp_stream_pkg is
-
------------------------------------------------------------------------------
-- General DP stream record defintion
------------------------------------------------------------------------------
@@ -395,9 +394,7 @@ package dp_stream_pkg is
end dp_stream_pkg;
-
package body dp_stream_pkg is
-
-- Check sosi.valid against siso.ready
procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
signal clk : in std_logic;
@@ -412,6 +409,7 @@ package body dp_stream_pkg is
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
report "RL ERROR" severity FAILURE;
end if;
+
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
end if;
end proc_dp_siso_alert;
@@ -623,7 +621,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_first;
-
-- Shift and combine part of previous data and this data,
function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
@@ -656,7 +653,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift;
-
-- Shift part of tail data and account for input empty
function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
@@ -685,7 +681,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_last;
-
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
@@ -713,7 +708,6 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_split;
-
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -727,7 +721,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_sosi_arr_mux;
-
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
@@ -845,7 +838,6 @@ package body dp_stream_pkg is
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
-
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
@@ -913,7 +905,6 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
-
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
@@ -1164,7 +1155,6 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_copy_valid_bsn;
-
-- Functions to combinatorially handle channels
function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
@@ -1195,7 +1185,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_remove;
-
function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1203,7 +1192,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_error_set;
-
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1211,7 +1199,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_bsn_set;
-
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
@@ -1224,7 +1211,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_combine_info_and_data;
-
function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
@@ -1487,4 +1473,3 @@ package body dp_stream_pkg is
end;
end dp_stream_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index d1ec55fe6f2419a5805d9ba52139b75498a111d5..103667575791b885ea6d707accd5dc6c04bcb535 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -28,9 +28,7 @@ use common_lib.common_network_layers_pkg.all;
use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
-
package eth_pkg is
-
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
@@ -57,7 +55,6 @@ package eth_pkg is
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- Definitions for eth header status
------------------------------------------------------------------------------
@@ -219,9 +216,7 @@ package eth_pkg is
end eth_pkg;
-
package body eth_pkg is
-
-- Register mapping functions
function func_eth_mm_reg_demux(mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
variable v_reg : t_eth_mm_reg_demux;
@@ -231,6 +226,7 @@ package body eth_pkg is
v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
end loop;
+
return v_reg;
end func_eth_mm_reg_demux;
@@ -350,4 +346,3 @@ package body eth_pkg is
end func_eth_mm_reg_status;
end eth_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 2eb92cbc7db8058c485f2204fe2a2969a018a1a6..177eb750c7386763043b7282d1bfb4b3a3fc6636 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package tech_tse_pkg is
-
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
constant c_tech_tse_byte_addr_w : natural := c_tech_tse_reg_addr_w + 2;
constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
@@ -84,6 +83,5 @@ package tech_tse_pkg is
end tech_tse_pkg;
-
package body tech_tse_pkg is
end tech_tse_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 5508d1789da1ac4db16e535b9aa1295e1f43e3da..06df7d37f4b4ceeb07d517f45c42b0cfa1cac3f2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -82,4 +82,3 @@
coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index 69ff39c0a085b9815fbe0884313e42bb7617a3b1..fafd41bbfa80eae91afc0da3d18e2f4b799f6a95 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -14,4 +14,3 @@
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 6d24dae5a954061b71e7efa2fb33079b1f9a1cc0..38fce9676fd1136ba002d70216e0ae804269cd9f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -58,4 +58,3 @@
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
reset_req => CONNECTED_TO_reset_req -- .reset_req
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index 927069ecd1caf7e424fcd3c77ebd6a5ee5d34908..c76f427acbe4d282fd1db94d2af4ffdce37d9027 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -98,4 +98,3 @@
somf => CONNECTED_TO_somf, -- somf.export
sysref => CONNECTED_TO_sysref -- sysref.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index a169c6edebc1ee1265bca717f3b34fcb629efda7..f745d32d0b9a636140d0cb000f2acf129a6741ad 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -44,11 +43,8 @@ entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_sc
);
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
-
begin
-
--synthesis translate_off
process (clk)
variable write_line : line;
@@ -61,7 +57,6 @@ begin
deallocate (write_line);
end if;
end if;
-
end process;
wfifo_used <= A_REP(std_logic'('0'), 6);
@@ -69,11 +64,8 @@ begin
fifo_FF <= std_logic'('0');
wfifo_empty <= std_logic'('1');
--synthesis translate_on
-
end europa;
-
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -109,7 +101,6 @@ entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo
);
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
--synthesis translate_off
component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
@@ -158,9 +149,7 @@ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi
signal internal_r_dat : std_logic_vector(7 downto 0);
signal internal_wfifo_empty : std_logic;
signal internal_wfifo_used : std_logic_vector(5 downto 0);
-
begin
-
--vhdl renameroo for output signals
fifo_FF <= internal_fifo_FF;
--vhdl renameroo for output signals
@@ -182,7 +171,6 @@ begin
fifo_wr => fifo_wr
);
-
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- wfifo : scfifo
@@ -210,11 +198,8 @@ begin
-- );
--
--synthesis read_comments_as_HDL off
-
end europa;
-
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -245,7 +230,6 @@ entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_sc
);
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
signal bytes_left : std_logic_vector(31 downto 0);
signal fifo_rd_d : std_logic;
@@ -253,9 +237,7 @@ architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_18
signal new_rom : std_logic;
signal num_bytes : std_logic_vector(31 downto 0);
signal rfifo_entries : std_logic_vector(6 downto 0);
-
begin
-
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full1;
--synthesis translate_off
@@ -276,7 +258,6 @@ begin
bytes_left <= num_bytes;
end if;
end if;
-
end process;
fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
@@ -287,11 +268,8 @@ begin
num_bytes <= std_logic_vector'("00000000000000000000000000000000");
fifo_rdata <= std_logic_vector'("00000000");
--synthesis translate_on
-
end europa;
-
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -328,7 +306,6 @@ entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo
);
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
--synthesis translate_off
component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
@@ -377,9 +354,7 @@ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi
signal internal_fifo_rdata : std_logic_vector(7 downto 0);
signal internal_rfifo_full : std_logic;
signal internal_rfifo_used : std_logic_vector(5 downto 0);
-
begin
-
--vhdl renameroo for output signals
fifo_EF <= internal_fifo_EF;
--vhdl renameroo for output signals
@@ -401,7 +376,6 @@ begin
rst_n => rst_n
);
-
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- rfifo : scfifo
@@ -429,11 +403,8 @@ begin
-- );
--
--synthesis read_comments_as_HDL off
-
end europa;
-
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -474,7 +445,6 @@ attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
port (
@@ -569,9 +539,7 @@ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi
signal wfifo_used : std_logic_vector(5 downto 0);
signal woverflow : std_logic;
signal wr_rfifo : std_logic;
-
begin
-
--avalon_jtag_slave, which is an e_avalon_slave
rd_wfifo <= r_ena and not wfifo_empty;
wr_rfifo <= t_ena and not rfifo_full;
@@ -590,7 +558,6 @@ begin
rd_wfifo => rd_wfifo
);
-
--the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
port map(
@@ -606,7 +573,6 @@ begin
wr_rfifo => wr_rfifo
);
-
ipen_AE <= ien_AE and fifo_AE;
ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
av_irq <= ipen_AE or ipen_AF;
@@ -623,7 +589,6 @@ begin
pause_irq <= std_logic'('0');
end if;
end if;
-
end process;
process (clk, rst_n)
@@ -635,7 +600,6 @@ begin
r_val <= r_ena and not wfifo_empty;
t_dav <= not rfifo_full;
end if;
-
end process;
process (clk, rst_n)
@@ -683,7 +647,6 @@ begin
read_0 <= not av_address;
end if;
end if;
-
end process;
fifo_wdata <= av_writedata(7 downto 0);
@@ -696,7 +659,6 @@ begin
elsif clk'event and clk = '1' then
readyfordata <= not fifo_FF;
end if;
-
end process;
--vhdl renameroo for output signals
@@ -711,7 +673,6 @@ begin
sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
sim_r_ena <= std_logic'('0');
end if;
-
end process;
r_ena <= sim_r_ena;
@@ -721,7 +682,6 @@ begin
process (fifo_EF)
begin
dataavailable <= not fifo_EF;
-
end process;
--synthesis translate_on
@@ -756,6 +716,4 @@ begin
-- end process;
--
--synthesis read_comments_as_HDL off
-
end europa;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index e357a3b8ab8b753e39cd616f442cea5802961fe9..bc11c57e416cd6de852d448d82730d0e93d92791 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -26,4 +26,3 @@
av_irq => CONNECTED_TO_av_irq, -- irq.irq
rst_n => CONNECTED_TO_rst_n -- reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index c400576a1989800e74ead77a4db7a59cb69b132b..64222401d7c70495e31aafcbeecd90272b38bdb4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -48,7 +47,6 @@ entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46
);
end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
-
architecture europa of qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
component altsyncram is
generic (
@@ -79,9 +77,7 @@ generic (
signal clocken0 : std_logic;
signal internal_readdata : std_logic_vector(31 downto 0);
signal wren : std_logic;
-
begin
-
wren <= chipselect and write;
clocken0 <= clken and not reset_req;
the_altsyncram : altsyncram
@@ -114,6 +110,4 @@ begin
--s2, which is an e_avalon_slave
--vhdl renameroo for output signals
readdata <= internal_readdata;
-
end europa;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index 1013d9c8feaee689211abf025dc3e1a81551a57f..f453120efc4f037dc4efbc07b42a93186450fe1d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -26,4 +26,3 @@
writedata => CONNECTED_TO_writedata, -- .writedata
byteenable => CONNECTED_TO_byteenable -- .byteenable
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 6ac45a007be4bf9d435b0a91ff37409242ff7b8e..580187433d6ad3516adc8f3613297cd106f122a7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index 54214733fc49773d36f56b87b503a8a1220498be..b05a01d44469adf2ce2a5524f755a45e93ee3b55 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 275c472861d35f58a6c976cd42ce79be5287a2d2..0cc60e970e8bf720a6ebe320a18a2ffee267bccc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -42,14 +41,11 @@ entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
);
end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
-
architecture europa of qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
signal clk_en : std_logic;
signal data_out : std_logic;
signal read_mux_out : std_logic;
-
begin
-
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
read_mux_out <= to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))) and data_out;
@@ -62,11 +58,8 @@ begin
data_out <= writedata(0);
end if;
end if;
-
end process;
readdata <= std_logic_vector'("00000000000000000000000000000000") or (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_mux_out)));
out_port <= data_out;
-
end europa;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 7653111094bca57be5233a89107b0f690ad5b8a2..4639e141f52b87b436009b6f01944420186ed973 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -22,4 +22,3 @@
chipselect => CONNECTED_TO_chipselect, -- .chipselect
readdata => CONNECTED_TO_readdata -- .readdata
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index beaf80437e1cbb723c0b36a79cd5060e9bb9ccb1..ec324643910e8ec28eea3841bf69396535f66ce8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index d4d2ea56c7cb49acf1d12bcecb6ee1da296eafc8..902a48132b9b35e040acf2ea2bdc5803e567864e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index 35a921ca9eb4623cef62876c50e32e8ac9441d2c..b7e771b662f1b2279fb0a2605ad86648a3821987 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 0dd4b690ec0c8735094b49e19288ec05db9e00d3..170f85ed587a093a331bd7da8153feb63a78358e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 391087f9353773b9f778890575bed96b9a20dae8..495dae0b21c808c2f09bc98a269f98a22332116b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index 57e4a4c70ff09483261c400f1174b0ffbb6680ca..e099a81cd1f19acfb178d8108c3a40c275935b38 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index 6ef3680e583a70a0853d728d15f4c2a7d75f3b83..d25eb92a9c789a0a393083008b9dd982889f184e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 813521ee099177f2f8fb4d251d1f7beaaef58d43..837cb45819d6d993ab0e2ec2cd835b1f69bd1365 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index 911de6ef25dec9ec456ad7a0ef0ed236f5f03f71..b97ef222ecfeac9b9cdc0609f289add83696334d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index bda7f7ffb4281d2c28f4cead93cac6e077b948c4..1871be2f741a5f58a41c9f333411b3b210fec9e6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 2037678c5866e082ec6d723154ca3a5a85cdf1df..229a2d315e14744572cd30efdc1e44a03cb55744 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index 24125dfe0e6c18178b6eedb1e3bdde814f814938..ae35f2bd1988023e11957c39257a521354f840f8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index 8b3e6b4cf8042e835ebd0b85293b5d87998cf23b..a954c70405f58c881dbee5a2d7c5a50b9fdbe730 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -42,7 +41,6 @@ entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
);
end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
-
architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
signal clk_en : std_logic;
signal control_interrupt_enable : std_logic;
@@ -62,9 +60,7 @@ architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsb
signal status_wr_strobe : std_logic;
signal timeout_event : std_logic;
signal timeout_occurred : std_logic;
-
begin
-
clk_en <= std_logic'('1');
process (clk, reset_n)
begin
@@ -79,7 +75,6 @@ begin
end if;
end if;
end if;
-
end process;
counter_is_zero <= to_std_logic(((std_logic_vector'("000000000000000") & (internal_counter)) = std_logic_vector'("00000000000000000000000000000000")));
@@ -93,7 +88,6 @@ begin
force_reload <= period_h_wr_strobe or period_l_wr_strobe;
end if;
end if;
-
end process;
do_start_counter <= std_logic'('1');
@@ -111,7 +105,6 @@ begin
end if;
end if;
end if;
-
end process;
--delayed_unxcounter_is_zeroxx0, which is an e_register
@@ -124,7 +117,6 @@ begin
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end if;
end if;
-
end process;
timeout_event <= (counter_is_zero) and not (delayed_unxcounter_is_zeroxx0);
@@ -141,7 +133,6 @@ begin
end if;
end if;
end if;
-
end process;
irq <= timeout_occurred and control_interrupt_enable;
@@ -156,7 +147,6 @@ begin
readdata <= read_mux_out;
end if;
end if;
-
end process;
period_l_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000010"))));
@@ -171,11 +161,8 @@ begin
control_register <= writedata(0);
end if;
end if;
-
end process;
control_interrupt_enable <= control_register;
status_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000"))));
-
end europa;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index d3f78c4dc85a4cff63250d20f5f89177160f1511..ff04a90d2be254067a63715a1ab244263a405a8f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -22,4 +22,3 @@
chipselect => CONNECTED_TO_chipselect, -- .chipselect
write_n => CONNECTED_TO_write_n -- .write_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
index 99377fe8a1497703e6eaf832e5e5f67c8c239b75..5e0e90fde0e616c1acf47f212484ceb92e1baddf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/unb2b_jesd_node0.vhd
@@ -79,11 +79,8 @@ entity unb2b_jesd_node0 is
);
end unb2b_jesd_node0;
-
architecture str of unb2b_jesd_node0 is
-
begin
-
u_revision : entity unb2b_jesd_lib.unb2b_jesd
generic map (
g_design_name => g_design_name,
@@ -130,6 +127,4 @@ begin
jesd204_rx_sysref => jesd204_rx_sysref,
jesd204_device_clk => jesd204_device_clk
);
-
end str;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 7d7bea513e97a96a44ba6a4da73962bd7ade270c..1188b1f4a3a8c3bda14f3b6fb3aaf6912e8d9d4f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -16,4 +16,3 @@
refclk => CONNECTED_TO_refclk, -- refclk.clk
rst => CONNECTED_TO_rst -- reset.reset
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 1bc0ee7c56cf0561ddbb42d55933480e42c046b8..4d125d7d6b09eb801f54521d54896e4cd0d3f452 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -12,4 +12,3 @@
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index e6c8fc658b5b43427db74a6adb53ee16cf62b553..2fdfadb51af42decdc595af06f6653c82f64f67b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -12,4 +12,3 @@
in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index 46793b217ef01564f7707dd7e5d33d21bb5b0f64..f5e2ba1f77a9a3ef8e6ec47a9929ad820950c0a3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -160,4 +160,3 @@
reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index 4aa29f21f8c2cd0ba644f59c2b91cac8ea4c33a0..e49f93a337e01a20a39b99a717881d143e0d0970 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -22,4 +22,3 @@
rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index bfd91a8bfa3fda8a6e8e4b5b40fa8e1f089e3a1c..af64e251092b8abe7083a94e7070e5407b77a322 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -14,4 +14,3 @@
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 342b6062c183b2ab4d90c5d7b8a360017f7b7631..26992b63a4edbecaa5e2a236b47a7c62d9e417d4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -14,4 +14,3 @@
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 9868df2cdd27ad40136cdb1b2611f283587904e7..745dc1937c6fff32fda95a03e5bd47b88e8206b7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -98,4 +98,3 @@
somf => CONNECTED_TO_somf, -- somf.export
sysref => CONNECTED_TO_sysref -- sysref.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index 7da9be04fe1b103526227ce32d2cb6ca6fd36a07..acbc33a2d1959920765b1866572b908d153acbc2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -14,4 +14,3 @@
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index c97253ac7931f744e6bead40b44ceea923313f43..42aae3ddf073f5dfbfee338c2139ed38675a6a2a 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index b57aa7daff98dbab340fda442699b89b58d52aab..4ddaf7fa7d6f6d85a966525b9dd908dbdae955a3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
index 3c94c1901f613072062b922ea5210533129da04d..d648f26fb1cb1a3e9c804714afad5c500ffa4798 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/avs2_eth_coe.vhd
@@ -31,7 +31,6 @@ use common_lib.common_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
use work.eth_pkg.all;
-
entity avs2_eth_coe is
port (
----------------------------------------------------------------------------
@@ -100,10 +99,8 @@ entity avs2_eth_coe is
);
end avs2_eth_coe;
-
architecture wrap of avs2_eth_coe is
begin
-
------------------------------------------------------------------------------
-- Wires
@@ -135,5 +132,4 @@ begin
-- Interrupt Sender interface
ins_interrupt_irq <= coe_irq_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
index 3fc6ebb7a2de575f47b388de4ca11860366bf4fe..e879f1b9edecdcf0c9866d6359c01c0b6a645338 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_network_layers_pkg.vhd
@@ -28,7 +28,6 @@ use IEEE.numeric_std.all;
use work.common_pkg.all;
package common_network_layers_pkg is
-
-- All *_len constants are in nof octets = nof bytes = c_8 bits
------------------------------------------------------------------------------
@@ -353,6 +352,5 @@ package common_network_layers_pkg is
end common_network_layers_pkg;
-
package body common_network_layers_pkg is
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
index 9469fd2656c232a4d88c0eaa1403bedeaf1e0a2e..4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/common_pkg.vhd
@@ -35,7 +35,6 @@ use IEEE.numeric_std.all;
use IEEE.math_real.all;
package common_pkg is
-
-- CONSTANT DECLARATIONS ----------------------------------------------------
-- some integers
@@ -160,7 +159,6 @@ package common_pkg is
clken : std_logic; -- := '1';
end record;
-
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
@@ -461,7 +459,6 @@ package common_pkg is
end common_pkg;
package body common_pkg is
-
function pow2(n : natural) return natural is
begin
return 2**n;
@@ -1393,7 +1390,6 @@ package body common_pkg is
return v_mat;
end;
-
-- Support concatenation of up to 7 slv into 1 slv
function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
constant c_max_w : natural := a'length + b'length + c'length + d'length + e'length + f'length + g'length;
@@ -1545,7 +1541,6 @@ package body common_pkg is
return func_slv_extract(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
-
function TO_UINT(vec : std_logic_vector) return natural is
begin
return to_integer(unsigned(vec));
@@ -1675,7 +1670,6 @@ package body common_pkg is
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
-
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
@@ -1837,7 +1831,6 @@ package body common_pkg is
return v_res;
end;
-
-- Functions s_round, s_round_up and u_round:
--
-- . The returned output width is input width - n.
@@ -2137,7 +2130,6 @@ package body common_pkg is
return str((i + 1) * width - 1 downto i * width);
end;
-
function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
@@ -2147,7 +2139,6 @@ package body common_pkg is
return v_concat_slv;
end;
-
------------------------------------------------------------------------------
-- common_fifo_*
------------------------------------------------------------------------------
@@ -2177,7 +2168,6 @@ package body common_pkg is
--synthesis translate_on
end procedure proc_common_fifo_asserts;
-
------------------------------------------------------------------------------
-- common_fanout_tree
------------------------------------------------------------------------------
@@ -2198,7 +2188,6 @@ package body common_pkg is
return v_stage_pipeline_arr;
end function func_common_fanout_tree_pipelining;
-
------------------------------------------------------------------------------
-- common_reorder_symbol
------------------------------------------------------------------------------
@@ -2360,4 +2349,3 @@ package body common_pkg is
end proc_common_dclk_generate_sclk;
end common_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
index 40128fea21ea799361fb11525746787d64202e63..7b6d1a2da0ec2558d87aa708358be0b79c70944d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/dp_stream_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package dp_stream_pkg is
-
------------------------------------------------------------------------------
-- General DP stream record defintion
------------------------------------------------------------------------------
@@ -395,9 +394,7 @@ package dp_stream_pkg is
end dp_stream_pkg;
-
package body dp_stream_pkg is
-
-- Check sosi.valid against siso.ready
procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
signal clk : in std_logic;
@@ -412,6 +409,7 @@ package body dp_stream_pkg is
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
report "RL ERROR" severity FAILURE;
end if;
+
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
end if;
end proc_dp_siso_alert;
@@ -623,7 +621,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_first;
-
-- Shift and combine part of previous data and this data,
function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
@@ -656,7 +653,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift;
-
-- Shift part of tail data and account for input empty
function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
@@ -685,7 +681,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_last;
-
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
@@ -713,7 +708,6 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_split;
-
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -727,7 +721,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_sosi_arr_mux;
-
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
@@ -845,7 +838,6 @@ package body dp_stream_pkg is
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
-
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
@@ -913,7 +905,6 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
-
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
@@ -1164,7 +1155,6 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_copy_valid_bsn;
-
-- Functions to combinatorially handle channels
function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
@@ -1195,7 +1185,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_remove;
-
function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1203,7 +1192,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_error_set;
-
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1211,7 +1199,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_bsn_set;
-
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
@@ -1224,7 +1211,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_combine_info_and_data;
-
function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
@@ -1487,4 +1473,3 @@ package body dp_stream_pkg is
end;
end dp_stream_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
index d1ec55fe6f2419a5805d9ba52139b75498a111d5..103667575791b885ea6d707accd5dc6c04bcb535 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/eth_pkg.vhd
@@ -28,9 +28,7 @@ use common_lib.common_network_layers_pkg.all;
use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
-
package eth_pkg is
-
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
@@ -57,7 +55,6 @@ package eth_pkg is
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- Definitions for eth header status
------------------------------------------------------------------------------
@@ -219,9 +216,7 @@ package eth_pkg is
end eth_pkg;
-
package body eth_pkg is
-
-- Register mapping functions
function func_eth_mm_reg_demux(mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
variable v_reg : t_eth_mm_reg_demux;
@@ -231,6 +226,7 @@ package body eth_pkg is
v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
end loop;
+
return v_reg;
end func_eth_mm_reg_demux;
@@ -350,4 +346,3 @@ package body eth_pkg is
end func_eth_mm_reg_status;
end eth_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
index 2eb92cbc7db8058c485f2204fe2a2969a018a1a6..177eb750c7386763043b7282d1bfb4b3a3fc6636 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/sim/tech_tse_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package tech_tse_pkg is
-
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
constant c_tech_tse_byte_addr_w : natural := c_tech_tse_reg_addr_w + 2;
constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
@@ -84,6 +83,5 @@ package tech_tse_pkg is
end tech_tse_pkg;
-
package body tech_tse_pkg is
end tech_tse_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
index 3c94c1901f613072062b922ea5210533129da04d..d648f26fb1cb1a3e9c804714afad5c500ffa4798 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/avs2_eth_coe.vhd
@@ -31,7 +31,6 @@ use common_lib.common_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
use work.eth_pkg.all;
-
entity avs2_eth_coe is
port (
----------------------------------------------------------------------------
@@ -100,10 +99,8 @@ entity avs2_eth_coe is
);
end avs2_eth_coe;
-
architecture wrap of avs2_eth_coe is
begin
-
------------------------------------------------------------------------------
-- Wires
@@ -135,5 +132,4 @@ begin
-- Interrupt Sender interface
ins_interrupt_irq <= coe_irq_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
index 3fc6ebb7a2de575f47b388de4ca11860366bf4fe..e879f1b9edecdcf0c9866d6359c01c0b6a645338 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_network_layers_pkg.vhd
@@ -28,7 +28,6 @@ use IEEE.numeric_std.all;
use work.common_pkg.all;
package common_network_layers_pkg is
-
-- All *_len constants are in nof octets = nof bytes = c_8 bits
------------------------------------------------------------------------------
@@ -353,6 +352,5 @@ package common_network_layers_pkg is
end common_network_layers_pkg;
-
package body common_network_layers_pkg is
end common_network_layers_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
index 9469fd2656c232a4d88c0eaa1403bedeaf1e0a2e..4bd7e15cc8fdafe0a37772e3eaedca527d52c4bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/common_pkg.vhd
@@ -35,7 +35,6 @@ use IEEE.numeric_std.all;
use IEEE.math_real.all;
package common_pkg is
-
-- CONSTANT DECLARATIONS ----------------------------------------------------
-- some integers
@@ -160,7 +159,6 @@ package common_pkg is
clken : std_logic; -- := '1';
end record;
-
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
@@ -461,7 +459,6 @@ package common_pkg is
end common_pkg;
package body common_pkg is
-
function pow2(n : natural) return natural is
begin
return 2**n;
@@ -1393,7 +1390,6 @@ package body common_pkg is
return v_mat;
end;
-
-- Support concatenation of up to 7 slv into 1 slv
function func_slv_concat(use_a, use_b, use_c, use_d, use_e, use_f, use_g : boolean; a, b, c, d, e, f, g : std_logic_vector) return std_logic_vector is
constant c_max_w : natural := a'length + b'length + c'length + d'length + e'length + f'length + g'length;
@@ -1545,7 +1541,6 @@ package body common_pkg is
return func_slv_extract(use_a, use_b, false, false, false, false, false, a_w, b_w, 0, 0, 0, 0, 0, vec, sel);
end func_slv_extract;
-
function TO_UINT(vec : std_logic_vector) return natural is
begin
return to_integer(unsigned(vec));
@@ -1675,7 +1670,6 @@ package body common_pkg is
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
-
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
@@ -1837,7 +1831,6 @@ package body common_pkg is
return v_res;
end;
-
-- Functions s_round, s_round_up and u_round:
--
-- . The returned output width is input width - n.
@@ -2137,7 +2130,6 @@ package body common_pkg is
return str((i + 1) * width - 1 downto i * width);
end;
-
function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
@@ -2147,7 +2139,6 @@ package body common_pkg is
return v_concat_slv;
end;
-
------------------------------------------------------------------------------
-- common_fifo_*
------------------------------------------------------------------------------
@@ -2177,7 +2168,6 @@ package body common_pkg is
--synthesis translate_on
end procedure proc_common_fifo_asserts;
-
------------------------------------------------------------------------------
-- common_fanout_tree
------------------------------------------------------------------------------
@@ -2198,7 +2188,6 @@ package body common_pkg is
return v_stage_pipeline_arr;
end function func_common_fanout_tree_pipelining;
-
------------------------------------------------------------------------------
-- common_reorder_symbol
------------------------------------------------------------------------------
@@ -2360,4 +2349,3 @@ package body common_pkg is
end proc_common_dclk_generate_sclk;
end common_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
index 40128fea21ea799361fb11525746787d64202e63..7b6d1a2da0ec2558d87aa708358be0b79c70944d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/dp_stream_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package dp_stream_pkg is
-
------------------------------------------------------------------------------
-- General DP stream record defintion
------------------------------------------------------------------------------
@@ -395,9 +394,7 @@ package dp_stream_pkg is
end dp_stream_pkg;
-
package body dp_stream_pkg is
-
-- Check sosi.valid against siso.ready
procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
signal clk : in std_logic;
@@ -412,6 +409,7 @@ package body dp_stream_pkg is
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
report "RL ERROR" severity FAILURE;
end if;
+
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
end if;
end proc_dp_siso_alert;
@@ -623,7 +621,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_first;
-
-- Shift and combine part of previous data and this data,
function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
@@ -656,7 +653,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift;
-
-- Shift part of tail data and account for input empty
function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
@@ -685,7 +681,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_last;
-
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
@@ -713,7 +708,6 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_split;
-
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -727,7 +721,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_sosi_arr_mux;
-
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
@@ -845,7 +838,6 @@ package body dp_stream_pkg is
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
-
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
@@ -913,7 +905,6 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
-
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
@@ -1164,7 +1155,6 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_copy_valid_bsn;
-
-- Functions to combinatorially handle channels
function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
@@ -1195,7 +1185,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_remove;
-
function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1203,7 +1192,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_error_set;
-
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1211,7 +1199,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_bsn_set;
-
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
@@ -1224,7 +1211,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_combine_info_and_data;
-
function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
@@ -1487,4 +1473,3 @@ package body dp_stream_pkg is
end;
end dp_stream_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
index d1ec55fe6f2419a5805d9ba52139b75498a111d5..103667575791b885ea6d707accd5dc6c04bcb535 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/eth_pkg.vhd
@@ -28,9 +28,7 @@ use common_lib.common_network_layers_pkg.all;
use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
-
package eth_pkg is
-
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
@@ -57,7 +55,6 @@ package eth_pkg is
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- Definitions for eth header status
------------------------------------------------------------------------------
@@ -219,9 +216,7 @@ package eth_pkg is
end eth_pkg;
-
package body eth_pkg is
-
-- Register mapping functions
function func_eth_mm_reg_demux(mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
variable v_reg : t_eth_mm_reg_demux;
@@ -231,6 +226,7 @@ package body eth_pkg is
v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
end loop;
+
return v_reg;
end func_eth_mm_reg_demux;
@@ -350,4 +346,3 @@ package body eth_pkg is
end func_eth_mm_reg_status;
end eth_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
index 2eb92cbc7db8058c485f2204fe2a2969a018a1a6..177eb750c7386763043b7282d1bfb4b3a3fc6636 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/avs2_eth_coe_10/synth/tech_tse_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package tech_tse_pkg is
-
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
constant c_tech_tse_byte_addr_w : natural := c_tech_tse_reg_addr_w + 2;
constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
@@ -84,6 +83,5 @@ package tech_tse_pkg is
end tech_tse_pkg;
-
package body tech_tse_pkg is
end tech_tse_pkg;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 5508d1789da1ac4db16e535b9aa1295e1f43e3da..06df7d37f4b4ceeb07d517f45c42b0cfa1cac3f2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -82,4 +82,3 @@
coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index 69ff39c0a085b9815fbe0884313e42bb7617a3b1..fafd41bbfa80eae91afc0da3d18e2f4b799f6a95 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -14,4 +14,3 @@
reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 6d24dae5a954061b71e7efa2fb33079b1f9a1cc0..38fce9676fd1136ba002d70216e0ae804269cd9f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -58,4 +58,3 @@
reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
reset_req => CONNECTED_TO_reset_req -- .reset_req
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index 927069ecd1caf7e424fcd3c77ebd6a5ee5d34908..c76f427acbe4d282fd1db94d2af4ffdce37d9027 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -98,4 +98,3 @@
somf => CONNECTED_TO_somf, -- somf.export
sysref => CONNECTED_TO_sysref -- sysref.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
index a169c6edebc1ee1265bca717f3b34fcb629efda7..f745d32d0b9a636140d0cb000f2acf129a6741ad 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/altera_avalon_jtag_uart_180/sim/qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -44,11 +43,8 @@ entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_sc
);
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
-
begin
-
--synthesis translate_off
process (clk)
variable write_line : line;
@@ -61,7 +57,6 @@ begin
deallocate (write_line);
end if;
end if;
-
end process;
wfifo_used <= A_REP(std_logic'('0'), 6);
@@ -69,11 +64,8 @@ begin
fifo_FF <= std_logic'('0');
wfifo_empty <= std_logic'('1');
--synthesis translate_on
-
end europa;
-
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -109,7 +101,6 @@ entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo
);
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
--synthesis translate_off
component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_w is
@@ -158,9 +149,7 @@ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi
signal internal_r_dat : std_logic_vector(7 downto 0);
signal internal_wfifo_empty : std_logic;
signal internal_wfifo_used : std_logic_vector(5 downto 0);
-
begin
-
--vhdl renameroo for output signals
fifo_FF <= internal_fifo_FF;
--vhdl renameroo for output signals
@@ -182,7 +171,6 @@ begin
fifo_wr => fifo_wr
);
-
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- wfifo : scfifo
@@ -210,11 +198,8 @@ begin
-- );
--
--synthesis read_comments_as_HDL off
-
end europa;
-
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -245,7 +230,6 @@ entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_sc
);
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
signal bytes_left : std_logic_vector(31 downto 0);
signal fifo_rd_d : std_logic;
@@ -253,9 +237,7 @@ architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_18
signal new_rom : std_logic;
signal num_bytes : std_logic_vector(31 downto 0);
signal rfifo_entries : std_logic_vector(6 downto 0);
-
begin
-
--vhdl renameroo for output signals
rfifo_full <= internal_rfifo_full1;
--synthesis translate_off
@@ -276,7 +258,6 @@ begin
bytes_left <= num_bytes;
end if;
end if;
-
end process;
fifo_EF <= to_std_logic((bytes_left = std_logic_vector'("00000000000000000000000000000000")));
@@ -287,11 +268,8 @@ begin
num_bytes <= std_logic_vector'("00000000000000000000000000000000");
fifo_rdata <= std_logic_vector'("00000000");
--synthesis translate_on
-
end europa;
-
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -328,7 +306,6 @@ entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo
);
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r is
--synthesis translate_off
component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_sim_scfifo_r is
@@ -377,9 +354,7 @@ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi
signal internal_fifo_rdata : std_logic_vector(7 downto 0);
signal internal_rfifo_full : std_logic;
signal internal_rfifo_used : std_logic_vector(5 downto 0);
-
begin
-
--vhdl renameroo for output signals
fifo_EF <= internal_fifo_EF;
--vhdl renameroo for output signals
@@ -401,7 +376,6 @@ begin
rst_n => rst_n
);
-
--synthesis translate_on
--synthesis read_comments_as_HDL on
-- rfifo : scfifo
@@ -429,11 +403,8 @@ begin
-- );
--
--synthesis read_comments_as_HDL off
-
end europa;
-
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -474,7 +445,6 @@ attribute ALTERA_ATTRIBUTE : string;
attribute ALTERA_ATTRIBUTE of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi : entity is "SUPPRESS_DA_RULE_INTERNAL=" "R101,C106,D101,D103" "";
end entity qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi;
-
architecture europa of qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi is
component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_w is
port (
@@ -569,9 +539,7 @@ end component qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi
signal wfifo_used : std_logic_vector(5 downto 0);
signal woverflow : std_logic;
signal wr_rfifo : std_logic;
-
begin
-
--avalon_jtag_slave, which is an e_avalon_slave
rd_wfifo <= r_ena and not wfifo_empty;
wr_rfifo <= t_ena and not rfifo_full;
@@ -590,7 +558,6 @@ begin
rd_wfifo => rd_wfifo
);
-
--the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r, which is an e_instance
the_qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r : qsys_unb2b_minimal_jtag_uart_0_altera_avalon_jtag_uart_180_tj65noi_scfifo_r
port map(
@@ -606,7 +573,6 @@ begin
wr_rfifo => wr_rfifo
);
-
ipen_AE <= ien_AE and fifo_AE;
ipen_AF <= ien_AF and ((pause_irq or fifo_AF));
av_irq <= ipen_AE or ipen_AF;
@@ -623,7 +589,6 @@ begin
pause_irq <= std_logic'('0');
end if;
end if;
-
end process;
process (clk, rst_n)
@@ -635,7 +600,6 @@ begin
r_val <= r_ena and not wfifo_empty;
t_dav <= not rfifo_full;
end if;
-
end process;
process (clk, rst_n)
@@ -683,7 +647,6 @@ begin
read_0 <= not av_address;
end if;
end if;
-
end process;
fifo_wdata <= av_writedata(7 downto 0);
@@ -696,7 +659,6 @@ begin
elsif clk'event and clk = '1' then
readyfordata <= not fifo_FF;
end if;
-
end process;
--vhdl renameroo for output signals
@@ -711,7 +673,6 @@ begin
sim_t_dat <= Vector_To_Std_Logic(A_WE_StdLogicVector((std_logic'(t_dav) = '1'), r_dat, A_REP(r_val, 8)));
sim_r_ena <= std_logic'('0');
end if;
-
end process;
r_ena <= sim_r_ena;
@@ -721,7 +682,6 @@ begin
process (fifo_EF)
begin
dataavailable <= not fifo_EF;
-
end process;
--synthesis translate_on
@@ -756,6 +716,4 @@ begin
-- end process;
--
--synthesis read_comments_as_HDL off
-
end europa;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index e357a3b8ab8b753e39cd616f442cea5802961fe9..bc11c57e416cd6de852d448d82730d0e93d92791 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -26,4 +26,3 @@
av_irq => CONNECTED_TO_av_irq, -- irq.irq
rst_n => CONNECTED_TO_rst_n -- reset.reset_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
index c400576a1989800e74ead77a4db7a59cb69b132b..64222401d7c70495e31aafcbeecd90272b38bdb4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/altera_avalon_onchip_memory2_180/sim/qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -48,7 +47,6 @@ entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46
);
end entity qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y;
-
architecture europa of qsys_unb2b_minimal_onchip_memory2_0_altera_avalon_onchip_memory2_180_lo46q2y is
component altsyncram is
generic (
@@ -79,9 +77,7 @@ generic (
signal clocken0 : std_logic;
signal internal_readdata : std_logic_vector(31 downto 0);
signal wren : std_logic;
-
begin
-
wren <= chipselect and write;
clocken0 <= clken and not reset_req;
the_altsyncram : altsyncram
@@ -114,6 +110,4 @@ begin
--s2, which is an e_avalon_slave
--vhdl renameroo for output signals
readdata <= internal_readdata;
-
end europa;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index 1013d9c8feaee689211abf025dc3e1a81551a57f..f453120efc4f037dc4efbc07b42a93186450fe1d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -26,4 +26,3 @@
writedata => CONNECTED_TO_writedata, -- .writedata
byteenable => CONNECTED_TO_byteenable -- .byteenable
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 6ac45a007be4bf9d435b0a91ff37409242ff7b8e..580187433d6ad3516adc8f3613297cd106f122a7 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index 54214733fc49773d36f56b87b503a8a1220498be..b05a01d44469adf2ce2a5524f755a45e93ee3b55 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
index 275c472861d35f58a6c976cd42ce79be5287a2d2..0cc60e970e8bf720a6ebe320a18a2ffee267bccc 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/altera_avalon_pio_180/sim/qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -42,14 +41,11 @@ entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
);
end entity qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq;
-
architecture europa of qsys_unb2b_minimal_pio_wdi_altera_avalon_pio_180_2botkdq is
signal clk_en : std_logic;
signal data_out : std_logic;
signal read_mux_out : std_logic;
-
begin
-
clk_en <= std_logic'('1');
--s1, which is an e_avalon_slave
read_mux_out <= to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))) and data_out;
@@ -62,11 +58,8 @@ begin
data_out <= writedata(0);
end if;
end if;
-
end process;
readdata <= std_logic_vector'("00000000000000000000000000000000") or (std_logic_vector'("0000000000000000000000000000000") & (A_TOSTDLOGICVECTOR(read_mux_out)));
out_port <= data_out;
-
end europa;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 7653111094bca57be5233a89107b0f690ad5b8a2..4639e141f52b87b436009b6f01944420186ed973 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -22,4 +22,3 @@
chipselect => CONNECTED_TO_chipselect, -- .chipselect
readdata => CONNECTED_TO_readdata -- .readdata
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index beaf80437e1cbb723c0b36a79cd5060e9bb9ccb1..ec324643910e8ec28eea3841bf69396535f66ce8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index d4d2ea56c7cb49acf1d12bcecb6ee1da296eafc8..902a48132b9b35e040acf2ea2bdc5803e567864e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index 35a921ca9eb4623cef62876c50e32e8ac9441d2c..b7e771b662f1b2279fb0a2605ad86648a3821987 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 0dd4b690ec0c8735094b49e19288ec05db9e00d3..170f85ed587a093a331bd7da8153feb63a78358e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 391087f9353773b9f778890575bed96b9a20dae8..495dae0b21c808c2f09bc98a269f98a22332116b 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index 57e4a4c70ff09483261c400f1174b0ffbb6680ca..e099a81cd1f19acfb178d8108c3a40c275935b38 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index 6ef3680e583a70a0853d728d15f4c2a7d75f3b83..d25eb92a9c789a0a393083008b9dd982889f184e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 813521ee099177f2f8fb4d251d1f7beaaef58d43..837cb45819d6d993ab0e2ec2cd835b1f69bd1365 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index 911de6ef25dec9ec456ad7a0ef0ed236f5f03f71..b97ef222ecfeac9b9cdc0609f289add83696334d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index bda7f7ffb4281d2c28f4cead93cac6e077b948c4..1871be2f741a5f58a41c9f333411b3b210fec9e6 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 2037678c5866e082ec6d723154ca3a5a85cdf1df..229a2d315e14744572cd30efdc1e44a03cb55744 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/sim/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/avs_common_mm_10/synth/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index 24125dfe0e6c18178b6eedb1e3bdde814f814938..ae35f2bd1988023e11957c39257a521354f840f8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -42,4 +42,3 @@
coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
index 8b3e6b4cf8042e835ebd0b85293b5d87998cf23b..a954c70405f58c881dbee5a2d7c5a50b9fdbe730 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/altera_avalon_timer_180/sim/qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -42,7 +41,6 @@ entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
);
end entity qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby;
-
architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsby is
signal clk_en : std_logic;
signal control_interrupt_enable : std_logic;
@@ -62,9 +60,7 @@ architecture europa of qsys_unb2b_minimal_timer_0_altera_avalon_timer_180_5qqtsb
signal status_wr_strobe : std_logic;
signal timeout_event : std_logic;
signal timeout_occurred : std_logic;
-
begin
-
clk_en <= std_logic'('1');
process (clk, reset_n)
begin
@@ -79,7 +75,6 @@ begin
end if;
end if;
end if;
-
end process;
counter_is_zero <= to_std_logic(((std_logic_vector'("000000000000000") & (internal_counter)) = std_logic_vector'("00000000000000000000000000000000")));
@@ -93,7 +88,6 @@ begin
force_reload <= period_h_wr_strobe or period_l_wr_strobe;
end if;
end if;
-
end process;
do_start_counter <= std_logic'('1');
@@ -111,7 +105,6 @@ begin
end if;
end if;
end if;
-
end process;
--delayed_unxcounter_is_zeroxx0, which is an e_register
@@ -124,7 +117,6 @@ begin
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end if;
end if;
-
end process;
timeout_event <= (counter_is_zero) and not (delayed_unxcounter_is_zeroxx0);
@@ -141,7 +133,6 @@ begin
end if;
end if;
end if;
-
end process;
irq <= timeout_occurred and control_interrupt_enable;
@@ -156,7 +147,6 @@ begin
readdata <= read_mux_out;
end if;
end if;
-
end process;
period_l_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000010"))));
@@ -171,11 +161,8 @@ begin
control_register <= writedata(0);
end if;
end if;
-
end process;
control_interrupt_enable <= control_register;
status_wr_strobe <= (chipselect and not write_n) and to_std_logic((((std_logic_vector'("00000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000"))));
-
end europa;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index d3f78c4dc85a4cff63250d20f5f89177160f1511..ff04a90d2be254067a63715a1ab244263a405a8f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -22,4 +22,3 @@
chipselect => CONNECTED_TO_chipselect, -- .chipselect
write_n => CONNECTED_TO_write_n -- .write_n
);
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
index 0099aadc7debfa1da44d8490cdcb8e8b9d2ed493..514ae4a7481860c8aec306184d0d937322216be4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/unb2b_jesd_node3.vhd
@@ -79,11 +79,8 @@ entity unb2b_jesd_node3 is
);
end unb2b_jesd_node3;
-
architecture str of unb2b_jesd_node3 is
-
begin
-
u_revision : entity unb2b_jesd_lib.unb2b_jesd
generic map (
g_design_name => g_design_name,
@@ -130,6 +127,4 @@ begin
jesd204_rx_sysref => jesd204_rx_sysref,
jesd204_device_clk => jesd204_device_clk
);
-
end str;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
index 0cfce242e5beba068c00079da247406eaaee7ead..91849daf0fb485fa8e569cd2d38af59bb2829758 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/mmm_unb2b_jesd.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_unb2b_jesd_pkg.all;
-
entity mmm_unb2b_jesd is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -118,7 +117,6 @@ entity mmm_unb2b_jesd is
end mmm_unb2b_jesd;
architecture str of mmm_unb2b_jesd is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
@@ -132,12 +130,10 @@ architecture str of mmm_unb2b_jesd is
signal link_clk : std_logic;
signal frame_clk : std_logic;
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -171,7 +167,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
@@ -322,7 +317,6 @@ begin
reg_mmdp_ctrl_write_export => reg_mmdp_ctrl_mosi.wr,
reg_mmdp_ctrl_writedata_export => reg_mmdp_ctrl_mosi.wrdata(c_word_w - 1 downto 0),
-
ram_diag_data_buf_jesd_clk_export => OPEN,
ram_diag_data_buf_jesd_reset_export => OPEN,
ram_diag_data_buf_jesd_address_export => ram_diag_data_buf_jesd_mosi.address(17 - 1 downto 0),
@@ -339,7 +333,6 @@ begin
reg_diag_data_buf_jesd_read_export => reg_diag_data_buf_jesd_mosi.rd,
reg_diag_data_buf_jesd_readdata_export => reg_diag_data_buf_jesd_miso.rddata(c_word_w - 1 downto 0),
-
-- connections to the JESD IP:
--altjesd_reset_seq_irq_irq =>
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
index 7adf946bf84016e3346870c67a5501529e20b685..fd4dfd48d297596d0790d66898ca7b23f920e06f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/qsys_unb2b_jesd_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2b_jesd_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v14 QSYS builder
-----------------------------------------------------------------------------
diff --git a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
index ace483155e5d153a60148f3feb0d2e00c6a711b3..91de0e9f2772a37c0081c401f556e230fda90183 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/src/vhdl/unb2b_jesd.vhd
@@ -80,9 +80,7 @@ entity unb2b_jesd is
);
end unb2b_jesd;
-
architecture str of unb2b_jesd is
-
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_100M;
@@ -180,10 +178,7 @@ architecture str of unb2b_jesd is
signal reg_diag_data_buf_jesd_mosi : t_mem_mosi;
signal reg_diag_data_buf_jesd_miso : t_mem_miso;
signal diag_data_buf_snk_in_arr : t_dp_sosi_arr(1 - 1 downto 0);
-
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -407,7 +402,6 @@ begin
diag_data_buf_snk_in_arr(i).err <= (others => '0');
end generate;
-
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
generic map (
g_technology => g_technology,
@@ -431,6 +425,4 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr,
in_sync => st_pps
);
-
end str;
-
diff --git a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
index 2c0f4a07c3549829d1c9409997027339a123db41..ec0e76432a205b9af472413490552af89cc5ef35 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/tb/vhdl/tb_unb2b_jesd.vhd
@@ -60,7 +60,6 @@ entity tb_unb2b_minimal is
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -114,9 +113,7 @@ architecture tb of tb_unb2b_minimal is
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
constant c_pmbus_tcvr0_address : std_logic_vector(6 downto 0) := TO_UVEC(I2C_unb2b_PMB_TCVR0_BMR461_ADR, 7);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
diff --git a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
index 17b40afcd4fe100788288d234a3dbad3fc47e40f..a915740dc56c968cea7358d18a0c7d354f1f3e2a 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/revisions/unb2b_minimal_125m/unb2b_minimal_125m.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2b_board_lib.unb2b_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2b_minimal_125m is
generic (
g_design_name : string := "unb2b_minimal_125m";
@@ -72,9 +71,7 @@ entity unb2b_minimal_125m is
);
end unb2b_minimal_125m;
-
architecture str of unb2b_minimal_125m is
-
begin
u_revision : entity unb2b_minimal_lib.unb2b_minimal
generic map (
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
index b686089538f34706f394e4b62b024792197fef95..94c4b4e44734dbcd37a02a86632e8a6eeedde24e 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/mmm_unb2b_minimal.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_unb2b_minimal_pkg.all;
-
entity mmm_unb2b_minimal is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -106,19 +105,15 @@ entity mmm_unb2b_minimal is
end mmm_unb2b_minimal;
architecture str of mmm_unb2b_minimal is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -155,7 +150,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
index 78235c8ddc94da83e4f7b6b3ab818bb4753eb2ee..1470cca51163e20c03fea684792e0fc3269da00f 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/qsys_unb2b_minimal_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2b_minimal_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus v14 QSYS builder
-----------------------------------------------------------------------------
diff --git a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
index 3d548a9e6f7f35f3a72ac98603571afe58f8b869..af68ce0e0a9d34558339dd888f16ea75c5e61838 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/src/vhdl/unb2b_minimal.vhd
@@ -72,9 +72,7 @@ entity unb2b_minimal is
);
end unb2b_minimal;
-
architecture str of unb2b_minimal is
-
-- Firmware version x.y
-- If x >= 2, rom_info starts on 0x10000 and max size = 0x8192 words
constant c_fw_version : t_unb2b_board_fw_version := (2, 0);
@@ -160,9 +158,7 @@ architecture str of unb2b_minimal is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -389,6 +385,4 @@ begin
red_led_arr => qsfp_red_led_arr,
QSFP_LED => QSFP_LED
);
-
end str;
-
diff --git a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
index 99a1387392162ee160509ec8fab2cf49c16b7c59..08f2d036be105e43527af6fdc08992fc0229a514 100644
--- a/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
+++ b/boards/uniboard2b/designs/unb2b_minimal/tb/vhdl/tb_unb2b_minimal.vhd
@@ -60,7 +60,6 @@ entity tb_unb2b_minimal is
end tb_unb2b_minimal;
architecture tb of tb_unb2b_minimal is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -114,9 +113,7 @@ architecture tb of tb_unb2b_minimal is
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
constant c_pmbus_tcvr0_address : std_logic_vector(6 downto 0) := TO_UVEC(I2C_UNB2_PMB_TCVR0_BMR461_ADR, 7);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
index 9311380c77452d8eccef53b5fd2e271e062f252b..cf02b0fabcf9a9f8f98d2a9352b47b30dfa5dd3d 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/tb_unb2b_test_10GbE.vhd
@@ -23,11 +23,9 @@
library IEEE, unb2b_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2b_test_10GbE is
end tb_unb2b_test_10GbE;
-
architecture tb of tb_unb2b_test_10GbE is
begin
u_tb_unb2b_test : entity unb2b_test_lib.tb_unb2b_test
@@ -35,4 +33,3 @@ begin
g_design_name => "unb2b_test_10GbE"
);
end tb;
-
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
index 97f02d9fb2122e6284c85aec9011ad5882ae9033..b8d21e890e0a16f9cabfc918278fcac6875bfa86 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_10GbE/unb2b_test_10GbE.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2b_board_lib.unb2b_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2b_test_10GbE is
generic (
g_design_name : string := "unb2b_test_10GbE";
@@ -107,9 +106,7 @@ entity unb2b_test_10GbE is
);
end unb2b_test_10GbE;
-
architecture str of unb2b_test_10GbE is
-
begin
u_revision : entity unb2b_test_lib.unb2b_test
generic map (
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
index 73fbba080763b28d951e02d7aee098c866dfe9af..a5b99242985e239c70f5ac80f75cfea8c4e61616 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/tb_unb2b_test_ddr_MB_I_II.vhd
@@ -20,16 +20,12 @@
--
-------------------------------------------------------------------------------
-
-
library IEEE, unb2b_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2b_test_ddr_MB_I_II is
end tb_unb2b_test_ddr_MB_I_II;
-
architecture tb of tb_unb2b_test_ddr_MB_I_II is
begin
u_tb_unb2b_test : entity unb2b_test_lib.tb_unb2b_test
@@ -38,4 +34,3 @@ begin
g_sim_model_ddr => false
);
end tb;
-
diff --git a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
index 049740b6f0675890d5d96a70af3df4891255bbdd..150e0d63045d3adf645914ff4000210671f53740 100644
--- a/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/revisions/unb2b_test_ddr_MB_I_II/unb2b_test_ddr_MB_I_II.vhd
@@ -28,7 +28,6 @@ use unb2b_board_lib.unb2b_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2b_test_ddr_MB_I_II is
generic (
g_design_name : string := "unb2b_test_ddr_MB_I_II";
@@ -84,9 +83,7 @@ entity unb2b_test_ddr_MB_I_II is
);
end unb2b_test_ddr_MB_I_II;
-
architecture str of unb2b_test_ddr_MB_I_II is
-
begin
u_revision : entity unb2b_test_lib.unb2b_test
generic map (
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index 7af096606c6843b87aa957edd299be3fd43f727c..ab0300e724b7bb8f55b4b891a838ca736862dc05 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -40,8 +40,6 @@ use work.qsys_unb2b_test_pkg.all;
use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
use work.unb2b_test_pkg.all;
-
-
entity mmm_unb2b_test is
generic (
g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
@@ -221,9 +219,7 @@ entity mmm_unb2b_test is
);
end mmm_unb2b_test;
-
architecture str of mmm_unb2b_test is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
@@ -281,14 +277,11 @@ architecture str of mmm_unb2b_test is
signal sim_eth1g_eth0_reg_mosi : t_mem_mosi;
signal sim_eth1g_eth1_reg_mosi : t_mem_mosi;
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
eth1g_eth0_mm_rst <= mm_rst;
eth1g_eth1_mm_rst <= mm_rst;
@@ -429,13 +422,11 @@ begin
end if;
end process;
-
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
@@ -683,7 +674,6 @@ begin
-- reg_dp_offload_rx_1GbE_hdr_dat_write_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wr,
-- reg_dp_offload_rx_1GbE_hdr_dat_writedata_export => reg_dp_offload_rx_1GbE_hdr_dat_mosi.wrdata(c_word_w-1 DOWNTO 0),
-
reg_bsn_monitor_1gbe_reset_export => OPEN,
reg_bsn_monitor_1gbe_clk_export => OPEN,
reg_bsn_monitor_1gbe_address_export => reg_bsn_monitor_1GbE_mosi.address(c_reg_rsp_bsn_monitor_1GbE_adr_w - 1 downto 0),
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index eaffab4dbf822f5375ed53456112368654eb1166..02021567e290a50a5b46eff215147816e76578ef 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2b_test_pkg is
-
-----------------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder generated file:
-- $HDL_WORK/build/unb2b/quartus/unb2b_test_ddr/qsys_unb2b_test/sim/qsys_unb2b_test.vhd
@@ -386,7 +385,4 @@ package qsys_unb2b_test_pkg is
);
end component qsys_unb2b_test;
-
-
end qsys_unb2b_test_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
index efb781f7ca602baf3405aa38343802062da19851..db643432f2f69347a5544c11a16615c59ae5ed39 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/udp_stream.vhd
@@ -100,10 +100,7 @@ entity udp_stream is
);
end udp_stream;
-
-
architecture str of udp_stream is
-
-- Block generator
constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
'0', -- enable_sync
@@ -114,7 +111,6 @@ architecture str of udp_stream is
TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
constant c_min_nof_words_per_block : natural := 1;
@@ -133,9 +129,7 @@ architecture str of udp_stream is
signal diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
-
begin
-
gen_hdr_in_fields : for i in 0 to g_nof_streams - 1 generate
-- dst = src
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) downto field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000" & ID(7 downto 3) & RESIZE_UVEC(ID(2 downto 0), c_byte_w);
@@ -152,7 +146,6 @@ begin
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )) <= fifo_block_gen_src_out_arr(i).bsn(46 downto 0);
end generate;
-
-----------------------------------------------------------------------------
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
@@ -207,7 +200,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
@@ -248,7 +240,6 @@ begin
hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
);
-
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
@@ -281,13 +272,11 @@ begin
hdr_fields_out_arr => hdr_fields_out_arr
);
-
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
end generate;
-
-----------------------------------------------------------------------------
-- RX: Data buffers and BSN monitors
-----------------------------------------------------------------------------
@@ -301,8 +290,6 @@ begin
diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
end generate;
-
-
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
g_nof_streams => g_nof_streams,
@@ -325,7 +312,6 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
);
-
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
@@ -353,6 +339,4 @@ begin
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
-
end str;
-
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
index f9dcc6a928d1d6e59bf5d84ea37fd962d5945b66..5886a9aef1f2cdadbdeb47b185fea035593d6c63 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test.vhd
@@ -137,15 +137,11 @@ entity unb2b_test is
);
end unb2b_test;
-
architecture str of unb2b_test is
-
-- Firmware version x.y
constant c_fw_version : t_unb2b_board_fw_version := (1, 1);
constant c_mm_clk_freq : natural := c_unb2b_board_mm_clk_freq_125M;
-
-
-- Revision controlled constants
constant c_use_1GbE : boolean := false; -- g_design_name="unb2b_test_1GbE" OR g_design_name="unb2b_test_10GbE" OR g_design_name="unb2b_test_all";
constant c_use_10GbE : boolean := g_design_name = "unb2b_test_10GbE" or g_design_name = "unb2b_test_all";
@@ -209,7 +205,6 @@ architecture str of unb2b_test is
constant c_max_nof_blocks_per_packet_1GbE : natural := c_max_udp_payload_nof_words_1GbE / c_min_nof_words_per_block;
constant c_max_nof_blocks_per_packet_10GbE : natural := c_max_udp_payload_nof_words_10GbE / c_min_nof_words_per_block;
-
-- System
signal cs_sim : std_logic;
@@ -433,9 +428,7 @@ architecture str of unb2b_test is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2b_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
assert false report "g_design_name=" & g_design_name severity WARNING;
-----------------------------------------------------------------------------
-- General control function
@@ -758,7 +751,6 @@ begin
ram_diag_data_buf_ddr_MB_II_miso => ram_diag_data_buf_ddr_MB_II_miso
);
-
gen_udp_stream_1GbE : if c_use_1GbE = true generate
u_udp_stream_1GbE : entity work.udp_stream
generic map (
@@ -823,16 +815,13 @@ begin
-----------------------------------------------------------------------------
gen_wires_1GbE : if c_use_1GbE = true generate
gen_1GbE_wires : for i in 0 to c_nof_streams_1GbE-1 generate
-
eth1g_udp_tx_sosi_arr(i) <= dp_offload_tx_1GbE_src_out_arr(i);
dp_offload_tx_1GbE_src_in_arr(i) <= eth1g_udp_tx_siso_arr(i);
dp_offload_rx_1GbE_snk_in_arr(i) <= eth1g_udp_rx_sosi_arr(i);
eth1g_udp_rx_siso_arr(i) <= dp_offload_rx_1GbE_snk_out_arr(i);
-
end generate;
end generate;
-
gen_udp_stream_10GbE : if c_use_10GbE = true generate
u_udp_stream_10GbE : entity work.udp_stream
generic map (
@@ -861,7 +850,6 @@ begin
reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
-- loopback:
--dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
--dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
@@ -874,7 +862,6 @@ begin
dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
@@ -886,7 +873,6 @@ begin
reg_diag_rx_seq_miso => reg_diag_rx_seq_10GbE_miso
);
-
u_tr_10GbE_qsfp_and_ring: entity unb2b_board_10gbe_lib.unb2b_board_10gbe -- QSFP and Ring lines
generic map (
g_sim => g_sim,
@@ -922,7 +908,6 @@ begin
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
-
i_QSFP_RX(0) <= QSFP_0_RX;
i_QSFP_RX(1) <= QSFP_1_RX;
i_QSFP_RX(2) <= QSFP_2_RX;
@@ -937,8 +922,6 @@ begin
QSFP_4_TX <= i_QSFP_TX(4);
QSFP_5_TX <= i_QSFP_TX(5);
-
-
u_front_io : entity unb2b_board_lib.unb2b_board_front_io
generic map (
g_nof_qsfp_bus => c_nof_qsfp_bus
@@ -981,7 +964,6 @@ begin
-- RING_TX => i_RING_TX
-- );
-
-- u_tr_10GbE_back: ENTITY unb2b_board_10gbe_lib.unb2b_board_10gbe -- BACK lines
-- GENERIC MAP (
-- g_sim => g_sim,
@@ -1044,7 +1026,6 @@ begin
-- BCK_ERR => BCK_ERR
-- );
-
u_front_led : entity unb2b_board_lib.unb2b_board_qsfp_leds
generic map (
g_sim => g_sim,
@@ -1099,7 +1080,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- Interface : DDR4 MB_I and MB_II
-----------------------------------------------------------------------------
@@ -1107,7 +1087,6 @@ begin
assert func_tech_ddr_ctlr_data_w(g_ddr_MB_I) = func_tech_ddr_ctlr_data_w(g_ddr_MB_II) report "unb2b_test: DDR4 MB_I and MB_II must have the same ctlr data widths" severity FAILURE;
gen_stream_MB_I : if c_use_MB_I = true generate
-
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
generic map (
-- System
@@ -1262,4 +1241,3 @@ begin
end generate;
end str;
-
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
index f78eda85f93b4c9cc0aaf6b2d8f7a79de1b4e271..1fbcce3b6de1d7bae0adb60756efb0bb0f6b8cc3 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/unb2b_test_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use common_lib.common_field_pkg.all;
package unb2b_test_pkg is
-
-- dp_offload_tx
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
@@ -55,6 +54,4 @@ package unb2b_test_pkg is
--CONSTANT c_hdr_field_ovr_init : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1001"&"111111111100"&"0011"&"00";
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "001" & "111111111100" & "0011" & "00";
-
end unb2b_test_pkg;
-
diff --git a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
index 8a8e92d8e22cf01124d5401fbb844e8d93105898..fbf404947d04d7a4da2c9edc811afae477859de1 100644
--- a/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/tb/vhdl/tb_unb2b_test.vhd
@@ -60,7 +60,6 @@ entity tb_unb2b_test is
end tb_unb2b_test;
architecture tb of tb_unb2b_test is
-
constant c_sim : boolean := true;
constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
@@ -136,7 +135,6 @@ architecture tb of tb_unb2b_test is
signal si_lpbk_8 : std_logic_vector(c_unb2b_board_tr_back.bus_w - 1 downto 0);
-
-- Model I2C sensor slaves as on the UniBoard
constant c_fpga_temp_address : std_logic_vector(6 downto 0) := "0011000"; -- MAX1618 address LOW LOW
constant c_fpga_temp : integer := 60;
@@ -148,9 +146,7 @@ architecture tb of tb_unb2b_test is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -162,7 +158,6 @@ begin
mb_I_ref_clk <= not mb_I_ref_clk after c_mb_I_ref_clk_period / 2; -- MB I reference clock (25 MHz)
mb_II_ref_clk <= not mb_II_ref_clk after c_mb_II_ref_clk_period / 2; -- MB II reference clock (25 MHz)
-
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -325,5 +320,4 @@ begin
mem4_in => MB_II_OU,
mem4_io => MB_II_IO
);
-
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
index ca0506287312c5d6f9c8f57bd5d8719672a86c8d..a23d26634c2fbf51d0e5ce4ec96d2069c24970cc 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/ctrl_unb2b_board.vhd
@@ -219,7 +219,6 @@ entity ctrl_unb2b_board is
ram_scrap_mosi : in t_mem_mosi;
ram_scrap_miso : out t_mem_miso;
-
--
-- >>> Ctrl FPGA pins
--
@@ -255,9 +254,7 @@ entity ctrl_unb2b_board is
);
end ctrl_unb2b_board;
-
architecture str of ctrl_unb2b_board is
-
constant c_rom_version : natural := 3; -- Only increment when something changes to the register map of rom_system_info.
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
@@ -316,9 +313,7 @@ architecture str of ctrl_unb2b_board is
attribute maxfan : integer;
attribute maxfan of dp_rst : signal is 1024;
-
begin
-
ext_clk200 <= i_ext_clk200;
xo_ethclk <= i_xo_ethclk;
xo_rst <= i_xo_rst;
@@ -367,7 +362,6 @@ begin
out_rst => i_xo_rst
);
-
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
-- MB_II_REF_CLK --> mb_II_ref_rst
@@ -520,7 +514,6 @@ begin
bck_id => this_bck_id
);
-
-----------------------------------------------------------------------------
-- Red LED control
-----------------------------------------------------------------------------
@@ -534,7 +527,6 @@ begin
TESTIO(c_unb2b_board_testio_led_red) <= led_toggle_red;
end generate;
-
-----------------------------------------------------------------------------
-- Green LED control
-----------------------------------------------------------------------------
@@ -548,7 +540,6 @@ begin
TESTIO(c_unb2b_board_testio_led_green) <= led_toggle_green;
end generate;
-
------------------------------------------------------------------------------
-- Toggle red LED when unb2b_minimal is running, green LED for other designs.
------------------------------------------------------------------------------
@@ -563,7 +554,6 @@ begin
out_dat => led_toggle
);
-
------------------------------------------------------------------------------
-- WDI override
------------------------------------------------------------------------------
@@ -583,7 +573,6 @@ begin
wdi_override => wdi_override
);
-
------------------------------------------------------------------------------
-- Remote upgrade
------------------------------------------------------------------------------
@@ -661,7 +650,6 @@ begin
pps_sys => dp_pps
);
-
------------------------------------------------------------------------------
-- I2C control for UniBoard sensors
------------------------------------------------------------------------------
@@ -738,7 +726,6 @@ begin
temp_alarm => temp_alarm
);
-
------------------------------------------------------------------------------
-- Ethernet 1GbE
------------------------------------------------------------------------------
@@ -760,7 +747,6 @@ begin
i_tse_clk <= i_xo_ethclk;
end generate;
-
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
udp_tx_siso_arr(i) <= eth1g_udp_tx_siso_arr(i);
@@ -779,7 +765,6 @@ begin
--On hardware always generate 1GbE for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
gen_eth: if g_sim = false or g_udp_offload = true generate
-
eth1g_st_clk <= dp_clk_in when g_udp_offload = true else i_mm_clk;
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
@@ -840,5 +825,4 @@ begin
rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
rd_val => ram_scrap_miso.rdval
);
-
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
index ca49243913061ee0fc8f2633a216464097f94d77..80d5432cf6ed616ad16f6149380e518f04c943fb 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_sens.vhd
@@ -28,7 +28,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
-
entity mms_unb2b_board_sens is
generic (
g_sim : boolean := false;
@@ -57,18 +56,14 @@ entity mms_unb2b_board_sens is
);
end mms_unb2b_board_sens;
-
architecture str of mms_unb2b_board_sens is
-
constant c_temp_high_w : natural := 7; -- Allow user to use only 7 (no sign, only positive) of 8 bits to set set max temp
signal sens_err : std_logic;
signal sens_data : t_slv_8_arr(0 to g_sens_nof_result - 1);
signal temp_high : std_logic_vector(c_temp_high_w - 1 downto 0);
-
begin
-
u_unb2b_board_sens_reg : entity work.unb2b_board_sens_reg
generic map (
g_sens_nof_result => g_sens_nof_result,
@@ -117,6 +112,4 @@ begin
-- would produce -1 degrees so does not trigger a temperature alarm.
-- temp_high is 7 bits, preceded by a '0' to allow only positive temps to be set.
temp_alarm <= '1' when (signed(sens_data(0)) > signed('0' & temp_high)) else '0';
-
end str;
-
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
index 4bf6770a4bc28f8bad31e273b873cb1687ca42b5..690b1507ac402793d47bcb056b7b37114c1613f9 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_board_system_info.vhd
@@ -61,9 +61,7 @@ entity mms_unb2b_board_system_info is
);
end mms_unb2b_board_system_info;
-
architecture str of mms_unb2b_board_system_info is
-
-- Provide different prefixes (absolute and relative) for the same path. ModelSim understands $UNB, Quartus does not.
-- Required because the work paths of ModelSim and Quartus are different.
constant c_quartus_path_prefix : string := "";
@@ -83,9 +81,7 @@ architecture str of mms_unb2b_board_system_info is
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
info <= i_info;
u_unb2b_board_system_info: entity work.unb2b_board_system_info
@@ -136,6 +132,4 @@ begin
rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
rd_val => rom_miso.rdval
);
-
end str;
-
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
index 60877870534b27059eefb81b59db7cc2c50b15b1..8debc61a00f8796d34118b4aa36ceb74fbc6cd97 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/mms_unb2b_fpga_sens.vhd
@@ -29,7 +29,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use technology_lib.technology_pkg.all;
-
entity mms_unb2b_fpga_sens is
generic (
g_sim : boolean := false;
@@ -53,11 +52,8 @@ entity mms_unb2b_fpga_sens is
);
end mms_unb2b_fpga_sens;
-
architecture str of mms_unb2b_fpga_sens is
-
begin
-
u_fpga_sense: entity fpga_sense_lib.fpga_sense
generic map (
g_technology => g_technology,
@@ -77,6 +73,4 @@ begin
reg_voltage_store_mosi => reg_voltage_mosi,
reg_voltage_store_miso => reg_voltage_miso
);
-
end str;
-
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
index b4e3a66d5b5674d4c959b7af913dc74fd8ee394c..4054420d21a4f987e7375b8fb9b59906f14d0a14 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_back_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2b_board_pkg.all;
-
entity unb2b_board_back_io is
generic (
g_nof_back_bus : natural := c_unb2b_board_tr_back.nof_bus
@@ -43,26 +42,19 @@ entity unb2b_board_back_io is
end unb2b_board_back_io;
architecture str of unb2b_board_back_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2b_board_back_bus_2arr(g_nof_back_bus - 1 downto 0);
signal si_rx_2arr : t_unb2b_board_back_bus_2arr(g_nof_back_bus - 1 downto 0);
-
begin
-
gen_buses : for i in 0 to g_nof_back_bus - 1 generate
BCK_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= BCK_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2b_board_tr_back.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2b_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
index 4d5d8677239207a819c7978d586a26318e35fc06..f2886ef970e244fdfc973e7c87111c79e50f3c7c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk125_pll.vhd
@@ -51,13 +51,9 @@ entity unb2b_board_clk125_pll is
);
end unb2b_board_clk125_pll;
-
architecture arria10 of unb2b_board_clk125_pll is
-
signal clk125buf : std_logic;
-
begin
-
no_clkbuf : if g_use_clkbuf = false generate
clk125buf <= clk125;
end generate;
@@ -74,7 +70,6 @@ begin
);
end generate;
-
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
generic map (
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
index f2e6b39a75a81ca728bd581fa250f47bce857c03..ac2db2f0ca43b5d3458a016c25a86eae4d501a1c 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk200_pll.vhd
@@ -113,9 +113,7 @@ entity unb2b_board_clk200_pll is
);
end unb2b_board_clk200_pll;
-
architecture arria10 of unb2b_board_clk200_pll is
-
constant c_reset_len : natural := c_meta_delay_len;
signal clk200buf : std_logic;
@@ -126,9 +124,7 @@ architecture arria10 of unb2b_board_clk200_pll is
signal st_locked : std_logic;
signal st_locked_n : std_logic;
-
begin
-
st_rst200 <= i_st_rst200;
st_clk200 <= i_st_clk200;
st_clk200p <= i_st_clk200p;
@@ -218,5 +214,4 @@ begin
clk => i_st_clk400,
out_rst => st_rst400
);
-
end arria10;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
index cd0e38e1e6f960ecf7ed41910f9c0205eefc29ab..24625f7333a8fd823fd6eed0cf2e5198724b47e4 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk25_pll.vhd
@@ -49,10 +49,8 @@ entity unb2b_board_clk25_pll is
);
end unb2b_board_clk25_pll;
-
architecture arria10 of unb2b_board_clk25_pll is
begin
-
u_pll : entity tech_pll_lib.tech_pll_clk25
generic map (
g_technology => g_technology
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
index 32eb4b1ad5c180cbdc6f9b40172e6c7cfaab9a9c..a5877c96a459a50258e9d6de8005778240fbda51 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_clk_rst.vhd
@@ -42,9 +42,7 @@ entity unb2b_board_clk_rst is
);
end unb2b_board_clk_rst;
-
architecture str of unb2b_board_clk_rst is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
-- XO clock domain
@@ -52,9 +50,7 @@ architecture str of unb2b_board_clk_rst is
-- SYS clock domain
signal sys_locked_n : std_logic;
-
begin
-
-- Reference clock and reset to SOPC system PLL
xo_rst_n <= not xo_rst;
@@ -82,5 +78,4 @@ begin
clk => sys_clk,
out_rst => sys_rst
);
-
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
index ad046d5128e058bc7f16a41b554a4f33842ff4ad..8eaa8e52bc3779e074e5dadfa7cb482dfaf3e66f 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_front_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2b_board_pkg.all;
-
entity unb2b_board_front_io is
generic (
g_nof_qsfp_bus : natural := c_unb2b_board_tr_qsfp.nof_bus
@@ -47,32 +46,24 @@ entity unb2b_board_front_io is
end unb2b_board_front_io;
architecture str of unb2b_board_front_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2b_board_qsfp_bus_2arr(g_nof_qsfp_bus - 1 downto 0);
signal si_rx_2arr : t_unb2b_board_qsfp_bus_2arr(g_nof_qsfp_bus - 1 downto 0);
-
begin
-
gen_leds : for i in 0 to g_nof_qsfp_bus - 1 generate
QSFP_LED(i * 2) <= green_led_arr(i);
QSFP_LED(i * 2 + 1) <= red_led_arr(i);
end generate;
-
gen_buses : for i in 0 to g_nof_qsfp_bus - 1 generate
QSFP_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= QSFP_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2b_board_tr_qsfp.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j);
serial_rx_arr(i * c_unb2b_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
index c0081cd7dfdb4523b23f468123843d9a7c2b59fe..06b87a197e1dbb9cfea0f70f306cb3308e86a314 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_hmc_ctrl.vhd
@@ -25,7 +25,6 @@ use i2c_lib.i2c_smbus_pkg.all;
use i2c_lib.i2c_dev_unb2_pkg.all;
use common_lib.common_pkg.all;
-
entity unb2b_board_hmc_ctrl is
generic (
g_sim : boolean := false;
@@ -49,9 +48,7 @@ entity unb2b_board_hmc_ctrl is
);
end entity;
-
architecture rtl of unb2b_board_hmc_ctrl is
-
type t_SEQUENCE is array (natural range <>) of natural;
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
@@ -117,9 +114,7 @@ architecture rtl of unb2b_board_hmc_ctrl is
signal nxt_result_err : std_logic;
signal i_result_dat : t_slv_8_arr(result_dat'range);
signal nxt_result_dat : t_slv_8_arr(result_dat'range);
-
begin
-
result_dat <= i_result_dat;
regs: process(rst, clk)
@@ -188,5 +183,4 @@ begin
nxt_result_val <= rx_val;
nxt_result_err <= rx_err;
nxt_result_dat <= rx_dat when rx_val = '1' else i_result_dat;
-
end rtl;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
index bf6f0a76698683b958de71fb937a2a3806f5f304..affbc014cb1d346b7737e6de055d4398127139e8 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_node_ctrl.vhd
@@ -54,17 +54,13 @@ entity unb2b_board_node_ctrl is
);
end unb2b_board_node_ctrl;
-
architecture str of unb2b_board_node_ctrl is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
signal mm_locked_n : std_logic;
signal i_mm_rst : std_logic;
signal i_mm_pulse_ms : std_logic;
-
begin
-
-- Create mm_rst reset in mm_clk domain based on mm_locked
mm_rst <= i_mm_rst;
@@ -110,5 +106,4 @@ begin
wdi_in => mm_wdi_in,
wdi_out => mm_wdi_out
);
-
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
index 315c4812d9457e4a804d5c1c244442539e83df5f..50a6d2d7a593b54b932f9ed9bdfcec53db98972a 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_peripherals_pkg.vhd
@@ -42,8 +42,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package unb2b_board_peripherals_pkg is
-
-
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb2b_board_peripherals_mm_reg is record
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
index 3d07f2e6e0df67c531f85a3dd916a0a8400adf75..ecc6fbb01be98b27604e6e0aa49c84cb2d09a4fc 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pkg.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
package unb2b_board_pkg is
-
-- UniBoard
constant c_unb2b_board_nof_node : natural := 4; -- number of nodes on UniBoard
constant c_unb2b_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb2b_board_nof_node)
@@ -93,12 +92,10 @@ package unb2b_board_pkg is
constant c_unb2b_board_nof_sync_jesd204b : natural := 4; -- 4 channels used in unb2b lab tests, 1 for each RCU.
constant c_unb2b_board_tr_qsfp_nof_leds : natural := c_unb2b_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
-
type t_unb2b_board_qsfp_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2b_board_tr_qsfp.bus_w - 1 downto 0);
type t_unb2b_board_ring_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2b_board_tr_ring.bus_w - 1 downto 0);
type t_unb2b_board_back_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2b_board_tr_back.bus_w - 1 downto 0);
-
-- Auxiliary
-- Test IO Interface
@@ -136,7 +133,6 @@ package unb2b_board_pkg is
-- SIGNAL RECORD DECLARATIONS -----------------------------------------------
-
-- I2C, MDIO
-- . If no I2C bus arbitration or clock stretching is needed then the SCL only needs to be output.
-- . Can also be used for a PHY Management Data IO interface with serial clock MDC and serial data MDIO
@@ -161,9 +157,7 @@ package unb2b_board_pkg is
end unb2b_board_pkg;
-
package body unb2b_board_pkg is
-
function func_unb2b_board_system_info(VERSION : in std_logic_vector(c_unb2b_board_aux.version_w - 1 downto 0);
ID : in std_logic_vector(c_unb2b_board_aux.id_w - 1 downto 0)) return t_c_unb2b_board_system_info is
variable v_system_info : t_c_unb2b_board_system_info;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
index f88c8c517d275e75aa3431fc08ab3ccbb1afc16a..c900196512ceae7f91f3fea9cbf0e2aba2b702cd 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_pmbus_ctrl.vhd
@@ -25,7 +25,6 @@ use i2c_lib.i2c_smbus_pkg.all;
use i2c_lib.i2c_dev_unb2_pkg.all;
use common_lib.common_pkg.all;
-
entity unb2b_board_pmbus_ctrl is
generic (
g_sim : boolean := false;
@@ -49,9 +48,7 @@ entity unb2b_board_pmbus_ctrl is
);
end entity;
-
architecture rtl of unb2b_board_pmbus_ctrl is
-
type t_SEQUENCE is array (natural range <>) of natural;
-- The I2C bit rate is c_i2c_bit_rate = 50 [kbps], so 20 us period. Hence 20 us wait time for SDA is enough
@@ -117,9 +114,7 @@ architecture rtl of unb2b_board_pmbus_ctrl is
signal nxt_result_err : std_logic;
signal i_result_dat : t_slv_8_arr(result_dat'range);
signal nxt_result_dat : t_slv_8_arr(result_dat'range);
-
begin
-
result_dat <= i_result_dat;
regs: process(rst, clk)
@@ -188,5 +183,4 @@ begin
nxt_result_val <= rx_val;
nxt_result_err <= rx_err;
nxt_result_dat <= rx_dat when rx_val = '1' else i_result_dat;
-
end rtl;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
index 56768d408644a04faf215f7af6b4a24e54a0d809..08ffbbe35b61070253acda92abc2d44202345617 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_qsfp_leds.vhd
@@ -88,9 +88,7 @@ entity unb2b_board_qsfp_leds is
);
end unb2b_board_qsfp_leds;
-
architecture str of unb2b_board_qsfp_leds is
-
constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
constant c_nof_lanes : natural := g_nof_qsfp * c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
@@ -103,9 +101,7 @@ architecture str of unb2b_board_qsfp_leds is
signal qsfp_on_arr : std_logic_vector(g_nof_qsfp - 1 downto 0);
signal qsfp_evt_arr : std_logic_vector(g_nof_qsfp - 1 downto 0);
-
begin
-
pulse_ms <= i_pulse_ms;
pulse_s <= i_pulse_s;
@@ -152,7 +148,6 @@ begin
end generate;
gen_user_image : if g_factory_image = false generate
-
red_led_arr <= (others => '0');
gen_green_ctrl_arr : for I in c_nof_lanes - 1 downto 0 generate
@@ -161,7 +156,6 @@ begin
end generate;
gen_green_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
-
qsfp_on_arr(I) <= orv(green_on_arr( (I + 1) * c_quad - 1 downto + I * c_quad));
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
@@ -182,5 +176,4 @@ begin
);
end generate;
end generate;
-
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
index 6c2bc52569c209b363e2775a2ba7b1c752ce398f..4d89b79a08e3f6a00a0076e2f4b7523ec2f07012 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_ring_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2b_board_pkg.all;
-
entity unb2b_board_ring_io is
generic (
g_nof_ring_bus : natural := c_unb2b_board_tr_ring.nof_bus
@@ -38,26 +37,19 @@ entity unb2b_board_ring_io is
end unb2b_board_ring_io;
architecture str of unb2b_board_ring_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2b_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0);
signal si_rx_2arr : t_unb2b_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0);
-
begin
-
gen_buses : for i in 0 to g_nof_ring_bus - 1 generate
RING_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= RING_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2b_board_tr_ring.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2b_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2b_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
index 8af6487703fd509d0645edf2779756f723e4d202..bdcc956341f6e19ac53b011b4d505c2928505a45 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens.vhd
@@ -48,9 +48,7 @@ entity unb2b_board_sens is
);
end entity;
-
architecture str of unb2b_board_sens is
-
-- I2C clock rate settings
constant c_sens_clk_cnt : natural := sel_a_b(g_sim, 1, func_i2c_calculate_clk_cnt(g_clk_freq / 10**6)); -- define I2C clock rate
--CONSTANT c_sens_comma_w : NATURAL := 13; -- 2**c_i2c_comma_w * system clock period comma time after I2C start and after each octet
@@ -67,7 +65,6 @@ architecture str of unb2b_board_sens is
-- octave:8> log2(delay/t)
-- ans = 13
-
--CONSTANT c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, c_sens_comma_w);
constant c_sens_phy : t_c_i2c_phy := (c_sens_clk_cnt, g_comma_w);
@@ -78,9 +75,7 @@ architecture str of unb2b_board_sens is
signal smbus_out_err : std_logic;
signal smbus_out_ack : std_logic;
signal smbus_out_end : std_logic;
-
begin
-
gen_unb2b_board_sens_ctrl : if g_i2c_peripheral = c_i2c_peripheral_sens generate
u_unb2b_board_sens_ctrl : entity work.unb2b_board_sens_ctrl
generic map (
@@ -172,5 +167,4 @@ begin
scl => scl,
sda => sda
);
-
end architecture;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
index cdc5cd4fdd094a980ca8241c56b8b9a5dcdddae1..60b4028d32b6c4203b3485c3e4794d9ec058570d 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_ctrl.vhd
@@ -27,7 +27,6 @@ use i2c_lib.i2c_dev_ltc4260_pkg.all;
use i2c_lib.i2c_dev_unb2_pkg.all;
use common_lib.common_pkg.all;
-
entity unb2b_board_sens_ctrl is
generic (
g_sim : boolean := false;
@@ -51,9 +50,7 @@ entity unb2b_board_sens_ctrl is
);
end entity;
-
architecture rtl of unb2b_board_sens_ctrl is
-
-- I2C slave commands of the devices on the I2C bus on UniBoard
constant TMP451_LOC_HI : natural := 16#00#;
constant TMP451_LOC_LO : natural := 16#15#;
@@ -133,9 +130,7 @@ architecture rtl of unb2b_board_sens_ctrl is
signal nxt_result_err : std_logic;
signal i_result_dat : t_slv_8_arr(result_dat'range);
signal nxt_result_dat : t_slv_8_arr(result_dat'range);
-
begin
-
result_dat <= i_result_dat;
regs: process(rst, clk)
@@ -204,5 +199,4 @@ begin
nxt_result_val <= rx_val;
nxt_result_err <= rx_err;
nxt_result_dat <= rx_dat when rx_val = '1' else i_result_dat;
-
end rtl;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
index 6c5be4d3ec0144c159a079a7272128e5881bd231..b7b2e852c0b8c482d15b8331209b0a909f6a6721 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_sens_reg.vhd
@@ -89,9 +89,7 @@ entity unb2b_board_sens_reg is
);
end unb2b_board_sens_reg;
-
architecture rtl of unb2b_board_sens_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_nof_dat : natural := g_sens_nof_result + 1 + 1; -- +1 to fit user set temp_high one additional address
-- +1 to fit sens_err in the last address
@@ -103,9 +101,7 @@ architecture rtl of unb2b_board_sens_reg is
init_sl => '0');
signal i_temp_high : std_logic_vector(6 downto 0);
-
begin
-
temp_high <= i_temp_high;
------------------------------------------------------------------------------
@@ -158,5 +154,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
index e99056b991ea0760002de84a70e3373e549e2340..adf5baaffbd23aa5f2b97e2505c658967f120276 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info.vhd
@@ -50,9 +50,7 @@ entity unb2b_board_system_info is
);
end unb2b_board_system_info;
-
architecture str of unb2b_board_system_info is
-
signal cs_sim : std_logic;
signal hw_version_reg : std_logic_vector(hw_version'range);
@@ -63,9 +61,7 @@ architecture str of unb2b_board_system_info is
signal nxt_chip_id : std_logic_vector(chip_id'range);
signal nxt_node_id : std_logic_vector(node_id'range);
signal nxt_is_node2 : std_logic;
-
begin
-
p_reg : process(clk)
begin
if rising_edge(clk) then
@@ -98,5 +94,4 @@ begin
nxt_chip_id <= id_reg(1 downto 0);
nxt_node_id <= id_reg(1 downto 0);
nxt_is_node2 <= '1' when TO_UINT(id_reg(1 downto 0)) = 2 else '0';
-
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
index a913aba7b0b0ddc107861ac83afa15a0afc7a38d..c3f5a857aa5ddf0586bf89976b5b8d5928120fdf 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
@@ -71,9 +71,7 @@ entity unb2b_board_system_info_reg is
);
end unb2b_board_system_info_reg;
-
architecture rtl of unb2b_board_system_info_reg is
-
constant c_nof_fixed_regs : natural := 2; -- info, use_phy
constant c_nof_design_name_regs : natural := 13; -- design_name
constant c_nof_stamp_regs : natural := 2; -- date, time
@@ -100,9 +98,7 @@ architecture rtl of unb2b_board_system_info_reg is
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_revision_id : t_slv_32_arr(0 to c_nof_revision_id_regs - 1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
begin
@@ -142,14 +138,8 @@ begin
elsif vA < c_design_note_offset + c_nof_design_note_regs then
sla_out.rddata(c_word_w - 1 downto 0) <= c_design_note(vA - c_design_note_offset);
-
end if;
-
end if;
end if;
-
end process;
-
-
end rtl;
-
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
index 92df366e56eaff80ffdf9bc8cdb0162b6055e765..74ccf1459b4566fda04c42e9f0c7bcdac29ad01d 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_extend.vhd
@@ -43,9 +43,7 @@ entity unb2b_board_wdi_extend is
);
end unb2b_board_wdi_extend;
-
architecture str of unb2b_board_wdi_extend is
-
signal wdi_evt : std_logic;
signal wdi_cnt : std_logic_vector(g_extend_w - 1 downto 0);
@@ -53,9 +51,7 @@ architecture str of unb2b_board_wdi_extend is
signal i_wdi_out : std_logic;
signal nxt_wdi_out : std_logic;
-
begin
-
wdi_out <= i_wdi_out;
p_clk : process(rst, clk)
@@ -94,5 +90,4 @@ begin
cnt_en => wdi_cnt_en,
count => wdi_cnt
);
-
end str;
diff --git a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
index c8ca0c95958eace700092d62efc4c5ceb4e50602..f052cbb7b21c950df7ca60ccab1ad3afb4019eac 100644
--- a/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_wdi_reg.vhd
@@ -43,9 +43,7 @@ entity unb2b_board_wdi_reg is
);
end unb2b_board_wdi_reg;
-
architecture rtl of unb2b_board_wdi_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
@@ -55,9 +53,7 @@ architecture rtl of unb2b_board_wdi_reg is
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -82,9 +78,6 @@ begin
when others => null; -- unused MM addresses
end case;
end if;
-
end if;
end process;
-
end rtl;
-
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
index 390acfb09ab7f064755acbfef20c2c590e65b6d2..ef80a940f59a7650e4e52b4a9ea66389cf3ca932 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_mms_unb2b_board_sens.vhd
@@ -40,7 +40,6 @@ use common_lib.tb_common_mem_pkg.all;
use work.unb2b_board_pkg.all;
architecture tb of tb_mms_unb2b_board_sens is
-
constant c_sim : boolean := true; -- FALSE;
constant c_repeat : natural := 2;
constant c_clk_freq : natural := 100 * 10**6;
@@ -77,9 +76,7 @@ architecture tb of tb_mms_unb2b_board_sens is
signal scl_stretch : std_logic := 'Z';
signal scl : std_logic;
signal sda : std_logic;
-
begin
-
rst <= '0' after 4 * c_clk_period;
clk <= (not clk) or tb_end after c_clk_period / 2;
@@ -147,10 +144,8 @@ begin
assert TO_UINT(sens_dat) = c_sens_expected(3) report "Wrong hot swap V source value" severity ERROR;
proc_common_wait_some_cycles(clk, 1);
assert TO_UINT(sens_dat) = c_sens_expected(4) report "An I2C error occurred" severity ERROR;
-
end process;
-
-- I2C sensors master
u_mms_unb2b_board_sens : entity work.mms_unb2b_board_sens
generic map (
@@ -210,6 +205,4 @@ begin
ana_volt_source => c_uniboard_supply,
ana_volt_adin => c_uniboard_adin
);
-
end tb;
-
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
index ee3b10a99bbae7bd414fca3f73690293f97636f2..df9a474f610174d3792ccb898670b46681356db3 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk125_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2b_board_clk125_pll is
end tb_unb2b_board_clk125_pll;
-
architecture tb of tb_unb2b_board_clk125_pll is
-
constant c_ext_clk_period : time := 8 ns; -- 125 MHz
signal tb_end : std_logic := '0';
@@ -48,9 +44,7 @@ architecture tb of tb_unb2b_board_clk125_pll is
signal c2_clk100 : std_logic;
signal c3_clk125 : std_logic;
signal pll_locked : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
index 4f4044773d337a9a73598f2ffdf5414a83b680d3..e0559528e8cc578ca11794aa41f5b15b09b1eb37 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk200_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2b_board_clk200_pll is
end tb_unb2b_board_clk200_pll;
-
architecture tb of tb_unb2b_board_clk200_pll is
-
constant c_ext_clk_period : time := 5 ns; -- 200 MHz
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
@@ -63,9 +59,7 @@ architecture tb of tb_unb2b_board_clk200_pll is
signal dp_clk200 : std_logic;
signal dp_rst200 : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
@@ -112,5 +106,4 @@ begin
st_clk200 => dp_clk200,
st_rst200 => dp_rst200
);
-
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
index 69037930d6e8e4e7662e5ad29c178baaed29f46f..02d31bf344c1f93ca78584062c1c502ce14416ea 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_clk25_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2b_board_clk25_pll is
end tb_unb2b_board_clk25_pll;
-
architecture tb of tb_unb2b_board_clk25_pll is
-
constant c_ext_clk_period : time := 40 ns; -- 25 MHz
signal tb_end : std_logic := '0';
@@ -48,9 +44,7 @@ architecture tb of tb_unb2b_board_clk25_pll is
signal c2_clk100 : std_logic;
signal c3_clk125 : std_logic;
signal pll_locked : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
index 1d150935cfc9f82ec810634e3cc245e56a139ba6..9f41504493b612ccd9a7bcfad71468dfb29e42f4 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_node_ctrl.vhd
@@ -24,13 +24,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2b_board_node_ctrl is
end tb_unb2b_board_node_ctrl;
-
architecture tb of tb_unb2b_board_node_ctrl is
-
constant c_scale : natural := 100; -- scale to speed up simulation
constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
@@ -62,9 +59,7 @@ architecture tb of tb_unb2b_board_node_ctrl is
signal pulse_us : std_logic;
signal pulse_ms : std_logic;
signal pulse_s : std_logic;
-
begin
-
-- run 2000 ms
mm_clk <= not mm_clk after c_mm_clk_period / 2;
@@ -95,5 +90,4 @@ begin
mm_pulse_ms => pulse_ms,
mm_pulse_s => pulse_s
);
-
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
index 8e3a7c84de0de6c74b5d57a1a9eeb6134bf0b464..b7d1a8ba03c55658283f0d6f4d43cf20062e0114 100644
--- a/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board/tb/vhdl/tb_unb2b_board_qsfp_leds.vhd
@@ -46,7 +46,6 @@ entity tb_unb2b_board_qsfp_leds is
end tb_unb2b_board_qsfp_leds;
architecture tb of tb_unb2b_board_qsfp_leds is
-
constant c_clk_freq_hz : natural := 200 * 10**6;
constant c_clk_period_ns : natural := 10**9 / c_clk_freq_hz;
constant c_nof_clk_per_us : natural := 1000 / c_clk_period_ns;
@@ -84,9 +83,7 @@ architecture tb of tb_unb2b_board_qsfp_leds is
signal dbg_sop : std_logic;
signal dbg_sop_slv : std_logic_vector(c_nof_lanes - 1 downto 0);
signal dbg_sosi : t_dp_sosi;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -186,5 +183,4 @@ begin
green_led_arr => user_green_led_arr,
red_led_arr => user_red_led_arr
);
-
end tb;
diff --git a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
index fd76808239ad60d2bddfbaa945e2e6a78ba74c98..615aa3863ad6316b754355c47b5b07308c4ef2cf 100644
--- a/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
+++ b/boards/uniboard2b/libraries/unb2b_board_10gbe/src/vhdl/unb2b_board_10gbe.vhd
@@ -27,7 +27,6 @@ use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2b_board_10gbe is
generic (
g_sim : boolean := false;
@@ -72,13 +71,10 @@ entity unb2b_board_10gbe is
);
end unb2b_board_10gbe;
-
architecture str of unb2b_board_10gbe is
-
signal tr_ref_clk_312 : std_logic;
signal tr_ref_clk_156 : std_logic;
signal tr_ref_rst_156 : std_logic;
-
begin
u_unb2b_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
generic map (
@@ -93,7 +89,6 @@ begin
rst_312 => open
);
-
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_technology => g_technology,
@@ -138,5 +133,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
index 05ad57e1f91a445847c34ce7b68b35f2467df5bf..40e4278b6c8442b5a18c6278b4780c03ef227fbe 100644
--- a/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
+++ b/boards/uniboard2c/designs/unb2c_led/src/vhdl/unb2c_led.vhd
@@ -49,9 +49,7 @@ entity unb2c_led is
);
end unb2c_led;
-
architecture str of unb2c_led is
-
-- Firmware version x.y
constant c_fw_version : t_unb2c_board_fw_version := (2, 0);
constant c_reset_len : natural := 40000; -- 4; -- >= c_meta_delay_len from common_pkg
@@ -90,7 +88,6 @@ architecture str of unb2c_led is
signal r_TOGGLE_1HZ : std_logic := '0';
signal leddiv : std_logic := '0';
signal clk200 : std_logic;
-
begin
xo_rst_n <= not xo_rst;
@@ -114,7 +111,6 @@ begin
end if;
end process p_led;
-
-- by using the fpll, the CLKUSR is used for calibration. So in case fpll does not work, check CLKUSR
u_unb2c_board_clk200_pll : entity unb2c_board_lib.unb2c_board_clk200_pll
@@ -128,8 +124,6 @@ begin
st_clk200 => clk200
);
-
-
xo_ethclk <= ETH_CLK(0); -- use the ETH_CLK pin as xo_clk
u_common_areset_xo : entity common_lib.common_areset
@@ -143,8 +137,6 @@ begin
out_rst => xo_rst
);
-
-
u_unb2c_board_clk125_pll : entity unb2c_board_lib.unb2c_board_clk125_pll
generic map (
g_use_fpll => true, -- FALSE, -- switch fpll or fixedpll
@@ -180,7 +172,6 @@ begin
led_flash_red <= sel_a_b(g_factory_image = true, led_flash, '0');
led_flash_green <= sel_a_b(g_factory_image = false, led_flash, '0');
-
u_extend : entity common_lib.common_pulse_extend
generic map (
g_extend_w => 22 -- (2^22) / 50e6 = 0.083886 th of 1 sec
@@ -192,17 +183,12 @@ begin
ep_out => led_flash
);
-
-
-
-- Red LED control
TESTIO(c_unb2c_board_testio_led_red) <= led_flash_red;
-- Green LED control
TESTIO(c_unb2c_board_testio_led_green) <= led_flash_green;
-
-
u_common_pulser_10Hz : entity common_lib.common_pulser
generic map (
g_pulse_period => 100,
@@ -246,6 +232,4 @@ begin
QSFP_LED(1) <= clk200;
QSFP_LED(5) <= ETH_CLK(0);
QSFP_LED(9) <= ETH_CLK(1);
-
end str;
-
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
index a8d6353638e66e47f99d7d389820ba1e29b080b6..c93a01d6edde99eae874b1c13b9b5e3a6202a0e3 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/mmm_unb2c_minimal.vhd
@@ -30,7 +30,6 @@ use mm_lib.mm_file_pkg.all;
use mm_lib.mm_file_unb_pkg.all;
use work.qsys_unb2c_minimal_pkg.all;
-
entity mmm_unb2c_minimal is
generic (
g_sim : boolean := false; -- FALSE: use QSYS; TRUE: use mm_file I/O
@@ -99,19 +98,15 @@ entity mmm_unb2c_minimal is
end mmm_unb2c_minimal;
architecture str of mmm_unb2c_minimal is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
u_mm_file_reg_unb_system_info : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "PIO_SYSTEM_INFO")
port map(mm_rst, mm_clk, reg_unb_system_info_mosi, reg_unb_system_info_miso );
@@ -142,7 +137,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk, c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
index 7e84ec80545ce3e18e50f350ce22b5c6221feff5..0d31242e088c49a836b4f27adaa586763bfc9338 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/qsys_unb2c_minimal_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2c_minimal_pkg is
-
----------------------------------------------------------------------
-- this component declaration is copy-pasted from Quartus QSYS builder
----------------------------------------------------------------------
diff --git a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
index 811b44df0631662932ab3265c131e363f85e22fb..87ec5850530b265c069f02e647273a4534d0804e 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/src/vhdl/unb2c_minimal.vhd
@@ -64,9 +64,7 @@ entity unb2c_minimal is
);
end unb2c_minimal;
-
architecture str of unb2c_minimal is
-
-- Firmware version x.y
-- If x >= 2, rom_info starts on 0x10000 and max size = 0x8192 words
constant c_fw_version : t_unb2c_board_fw_version := (2, 0);
@@ -143,9 +141,7 @@ architecture str of unb2c_minimal is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -355,6 +351,4 @@ begin
red_led_arr => qsfp_red_led_arr,
QSFP_LED => QSFP_LED
);
-
end str;
-
diff --git a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
index 40b4f29907df813af52325ccdeb01aab1675099a..5fc724c707fc437f308a4c839036bf3d318bfbc6 100644
--- a/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_minimal/tb/vhdl/tb_unb2c_minimal.vhd
@@ -59,7 +59,6 @@ entity tb_unb2c_minimal is
end tb_unb2c_minimal;
architecture tb of tb_unb2c_minimal is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -92,9 +91,7 @@ architecture tb of tb_unb2c_minimal is
signal TESTIO : std_logic_vector(c_unb2c_board_aux.testio_w - 1 downto 0);
signal qsfp_led : std_logic_vector(c_unb2c_board_tr_qsfp_nof_leds - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -147,5 +144,4 @@ begin
QSFP_LED => qsfp_led
);
-
end tb;
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
index a530afa74809babba8055285f9fb5aad83d1bdde..cb584d11aa0e0042a81cb707dfd96b766ad3e4aa 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/tb_unb2c_test_10GbE.vhd
@@ -23,11 +23,9 @@
library IEEE, unb2c_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2c_test_10GbE is
end tb_unb2c_test_10GbE;
-
architecture tb of tb_unb2c_test_10GbE is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
@@ -35,4 +33,3 @@ begin
g_design_name => "unb2c_test_10GbE"
);
end tb;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
index e3fba92d2d4cc3e9687c89476d4062c2117e734e..b7c61245b6954414a2676567fe16525d2d3faf27 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_10GbE/unb2c_test_10GbE.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2c_test_10GbE is
generic (
g_design_name : string := "unb2c_test_10GbE";
@@ -52,7 +51,6 @@ entity unb2c_test_10GbE is
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0);
TESTIO : inout std_logic_vector(c_unb2c_board_aux.testio_w - 1 downto 0);
-
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
ETH_SGIN : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
@@ -91,9 +89,7 @@ entity unb2c_test_10GbE is
);
end unb2c_test_10GbE;
-
architecture str of unb2c_test_10GbE is
-
begin
u_revision : entity unb2c_test_lib.unb2c_test
generic map (
@@ -119,7 +115,6 @@ begin
ID => ID,
TESTIO => TESTIO,
-
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
index 4e3e8e0939b830e2986637d575ca3f6affe36e2e..55beabab75a339e670927d19901f167e8763a5b5 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/tb_unb2c_test_1GbE_I.vhd
@@ -45,13 +45,10 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_unb2c_test_1GbE_I is
end tb_unb2c_test_1GbE_I;
-
architecture tb of tb_unb2c_test_1GbE_I is
-
signal clk : std_logic := '0';
signal pps : std_logic := '0';
signal wdi : std_logic := '0';
@@ -59,9 +56,7 @@ architecture tb of tb_unb2c_test_1GbE_I is
signal eth_clk : std_logic_vector(1 downto 0) := "00";
signal eth_sgin : std_logic_vector(1 downto 0);
signal eth_sgout : std_logic_vector(1 downto 0);
-
begin
-
clk <= not clk after 5 ns;
eth_clk(0) <= not eth_clk(0) after 8 ns;
eth_clk(1) <= not eth_clk(1) after 8 ns;
@@ -94,6 +89,4 @@ begin
QSFP_LED => open
);
-
end tb;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
index 9bf4c129f9cee9e8d867332f6fcb3e3af482bca7..14e29aca56f9ea10d188ec35f58018de0f5a4bc8 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_I/unb2c_test_1GbE_I.vhd
@@ -31,7 +31,6 @@ use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2c_test_1GbE_I is
generic (
g_design_name : string := "unb2c_test_1GbE_I";
@@ -56,7 +55,6 @@ entity unb2c_test_1GbE_I is
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0);
TESTIO : inout std_logic_vector(c_unb2c_board_aux.testio_w - 1 downto 0);
-
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
ETH_SGIN : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
@@ -66,9 +64,7 @@ entity unb2c_test_1GbE_I is
);
end unb2c_test_1GbE_I;
-
architecture str of unb2c_test_1GbE_I is
-
begin
u_revision : entity unb2c_test_lib.unb2c_test
generic map (
@@ -94,7 +90,6 @@ begin
ID => ID,
TESTIO => TESTIO,
-
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
index 6332e970cddd8c403ecdff7ad7fb7864f6fc2e44..0d481eb3274a34a366c02f8695af0bfb8629374b 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/tb_unb2c_test_1GbE_II.vhd
@@ -47,13 +47,10 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_unb2c_test_1GbE_II is
end tb_unb2c_test_1GbE_II;
-
architecture tb of tb_unb2c_test_1GbE_II is
-
signal clk : std_logic := '0';
signal pps : std_logic := '0';
signal wdi : std_logic := '0';
@@ -61,9 +58,7 @@ architecture tb of tb_unb2c_test_1GbE_II is
signal eth_clk : std_logic_vector(1 downto 0) := "00";
signal eth_sgin : std_logic_vector(1 downto 0);
signal eth_sgout : std_logic_vector(1 downto 0);
-
begin
-
clk <= not clk after 5 ns;
eth_clk(0) <= not eth_clk(0) after 8 ns;
eth_clk(1) <= not eth_clk(1) after 8 ns;
@@ -89,7 +84,6 @@ begin
ID => "00000000",
TESTIO => OPEN,
-
-- 1GbE Control Interface
ETH_CLK => eth_clk,
ETH_SGIN => eth_sgin,
@@ -97,6 +91,4 @@ begin
QSFP_LED => open
);
-
end tb;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
index 262eef85b92cb97fd8040cfbcce46e1a9db1e58d..850e616ac8d293cfa7d82aa9392fc18e0437cbd5 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_1GbE_II/unb2c_test_1GbE_II.vhd
@@ -31,7 +31,6 @@ use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2c_test_1GbE_II is
generic (
g_design_name : string := "unb2c_test_1GbE_II";
@@ -56,7 +55,6 @@ entity unb2c_test_1GbE_II is
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0);
TESTIO : inout std_logic_vector(c_unb2c_board_aux.testio_w - 1 downto 0);
-
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
ETH_SGIN : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
@@ -66,9 +64,7 @@ entity unb2c_test_1GbE_II is
);
end unb2c_test_1GbE_II;
-
architecture str of unb2c_test_1GbE_II is
-
begin
u_revision : entity unb2c_test_lib.unb2c_test
generic map (
@@ -94,7 +90,6 @@ begin
ID => ID,
TESTIO => TESTIO,
-
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
index 0527b55ab7a9bc699e6a879761e257741a05c892..d25bb0a613465f7b9704239e7a84e9784d285b76 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/tb_unb2c_test_ddr.vhd
@@ -23,11 +23,9 @@
library IEEE, unb2c_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2c_test_ddr is
end tb_unb2c_test_ddr;
-
architecture tb of tb_unb2c_test_ddr is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
@@ -35,4 +33,3 @@ begin
g_design_name => "unb2c_test_ddr"
);
end tb;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
index 193ad5ca220c34ea107373769fa5ba539ecb6752..b5b75bb185e1c4debb78015ca0aa15bec37c771b 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr/unb2c_test_ddr.vhd
@@ -28,7 +28,6 @@ use unb2c_board_lib.unb2c_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2c_test_ddr is
generic (
g_design_name : string := "unb2c_test_ddr";
@@ -53,7 +52,6 @@ entity unb2c_test_ddr is
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0);
TESTIO : inout std_logic_vector(c_unb2c_board_aux.testio_w - 1 downto 0);
-
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
ETH_SGIN : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
@@ -77,9 +75,7 @@ entity unb2c_test_ddr is
);
end unb2c_test_ddr;
-
architecture str of unb2c_test_ddr is
-
begin
u_revision : entity unb2c_test_lib.unb2c_test
generic map (
@@ -105,7 +101,6 @@ begin
ID => ID,
TESTIO => TESTIO,
-
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
index 64ff992ffdf773d4f0a3b21246274f1615a0dab1..b3a43fdf88406ee1b8f379bd616d730a44616e1f 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/tb_unb2c_test_ddr_16G.vhd
@@ -23,11 +23,9 @@
library IEEE, unb2c_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2c_test_ddr_16G is
end tb_unb2c_test_ddr_16G;
-
architecture tb of tb_unb2c_test_ddr_16G is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
@@ -35,4 +33,3 @@ begin
g_design_name => "unb2c_test_ddr_16G"
);
end tb;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
index 831cbf1f67ffc4e9cc2a85814d683588e9931406..a19523ddcae8447148730f2de4abdb640ebb17a9 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_ddr_16G/unb2c_test_ddr_16G.vhd
@@ -28,7 +28,6 @@ use unb2c_board_lib.unb2c_board_pkg.all;
use technology_lib.technology_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
-
entity unb2c_test_ddr_16G is
generic (
g_design_name : string := "unb2c_test_ddr_16G";
@@ -53,7 +52,6 @@ entity unb2c_test_ddr_16G is
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0);
TESTIO : inout std_logic_vector(c_unb2c_board_aux.testio_w - 1 downto 0);
-
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
ETH_SGIN : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
@@ -77,9 +75,7 @@ entity unb2c_test_ddr_16G is
);
end unb2c_test_ddr_16G;
-
architecture str of unb2c_test_ddr_16G is
-
begin
u_revision : entity unb2c_test_lib.unb2c_test
generic map (
@@ -105,7 +101,6 @@ begin
ID => ID,
TESTIO => TESTIO,
-
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
index 8cf3854e05ea740b7ac7586d3abb81f67a8bec1c..33951098a328a1f2fcb1ff7fef3bc337be04d581 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/tb_unb2c_test_heater.vhd
@@ -23,11 +23,9 @@
library IEEE, unb2c_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2c_test_heater is
end tb_unb2c_test_heater;
-
architecture tb of tb_unb2c_test_heater is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
@@ -35,4 +33,3 @@ begin
g_design_name => "unb2c_test_heater"
);
end tb;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
index 8b2b85ed9f8eb40f9fe46ef80754eaef733a683a..e85b07f9c188d7050e385628bf96c27e3700d884 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_heater/unb2c_test_heater.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2c_test_heater is
generic (
g_design_name : string := "unb2c_test_heater";
@@ -52,7 +51,6 @@ entity unb2c_test_heater is
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0);
TESTIO : inout std_logic_vector(c_unb2c_board_aux.testio_w - 1 downto 0);
-
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
ETH_SGIN : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
@@ -62,9 +60,7 @@ entity unb2c_test_heater is
);
end unb2c_test_heater;
-
architecture str of unb2c_test_heater is
-
begin
u_revision : entity unb2c_test_lib.unb2c_test
generic map (
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
index 3ca7e706a728bc5904c632dd4b0716b54e341887..9c8cc77e4e6b2fc803cbedbe09b9e23c893d204e 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/tb_unb2c_test_jesd204b.vhd
@@ -23,11 +23,9 @@
library IEEE, unb2c_test_lib;
use IEEE.std_logic_1164.all;
-
entity tb_unb2c_test_jesd204b is
end tb_unb2c_test_jesd204b;
-
architecture tb of tb_unb2c_test_jesd204b is
begin
u_tb_unb2c_test : entity unb2c_test_lib.tb_unb2c_test
@@ -35,4 +33,3 @@ begin
g_design_name => "unb2c_test_jesd204b"
);
end tb;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
index f8cadf1c29cb9a81a838ffac39000bb1ec475bf1..3c61c0768039e3da09c4666f29d1e74d2652bf95 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_jesd204b/unb2c_test_jesd204b.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2c_test_jesd204b is
generic (
g_design_name : string := "unb2c_test_jesd204b";
@@ -67,9 +66,7 @@ entity unb2c_test_jesd204b is
);
end unb2c_test_jesd204b;
-
architecture str of unb2c_test_jesd204b is
-
begin
u_revision : entity unb2c_test_lib.unb2c_test
generic map (
@@ -95,7 +92,6 @@ begin
ID => ID,
TESTIO => TESTIO,
-
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
diff --git a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
index b0fec68285d0c8216f661880ff5f851dfdc29a7b..85260e0c01ed2df1c82ce1c1422f4a482294a140 100644
--- a/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/revisions/unb2c_test_minimal/unb2c_test_minimal.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use unb2c_board_lib.unb2c_board_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2c_test_minimal is
generic (
g_design_name : string := "unb2c_test_minimal";
@@ -52,7 +51,6 @@ entity unb2c_test_minimal is
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0);
TESTIO : inout std_logic_vector(c_unb2c_board_aux.testio_w - 1 downto 0);
-
-- 1GbE Control Interface
ETH_CLK : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
ETH_SGIN : in std_logic_vector(c_unb2c_board_nof_eth - 1 downto 0);
@@ -62,9 +60,7 @@ entity unb2c_test_minimal is
);
end unb2c_test_minimal;
-
architecture str of unb2c_test_minimal is
-
begin
u_revision : entity unb2c_test_lib.unb2c_test
generic map (
@@ -90,7 +86,6 @@ begin
ID => ID,
TESTIO => TESTIO,
-
-- 1GbE Control Interface
ETH_clk => ETH_clk,
ETH_SGIN => ETH_SGIN,
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
index 433eec002f644a7ce32b31b475289657767a3503..468e48a1a4c0f2ce6ab7076a9494994d7bf54ba8 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/mmm_unb2c_test.vhd
@@ -40,7 +40,6 @@ use work.qsys_unb2c_test_pkg.all;
use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
use work.unb2c_test_pkg.all;
-
entity mmm_unb2c_test is
generic (
g_sim : boolean := false; -- FALSE: use SOPC; TRUE: use mm_file I/O
@@ -232,9 +231,7 @@ entity mmm_unb2c_test is
);
end mmm_unb2c_test;
-
architecture str of mmm_unb2c_test is
-
constant c_sim_node_nr : natural := g_sim_node_nr;
constant c_sim_node_type : string(1 to 2) := "FN";
@@ -275,14 +272,11 @@ architecture str of mmm_unb2c_test is
signal sim_eth_0_reg_mosi : t_mem_mosi;
signal sim_eth_1_reg_mosi : t_mem_mosi;
signal i_reset_n : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $UPE/sim.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
eth_0_mm_rst <= mm_rst;
eth_1_mm_rst <= mm_rst;
@@ -425,13 +419,11 @@ begin
end if;
end process;
-
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(mm_clk,c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
i_reset_n <= not mm_rst;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
index 3364ccf86d03fa68bee26557b443b3014109a25c..082cb255033db9026064bf00a896cde6129207ff 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/node_adc_input_and_timing_nowg.vhd
@@ -85,9 +85,7 @@ entity node_adc_input_and_timing_nowg is
);
end node_adc_input_and_timing_nowg;
-
architecture str of node_adc_input_and_timing_nowg is
-
constant c_mm_jesd_ctrl_reg : t_c_mem := (latency => 1,
adr_w => 1,
dat_w => c_word_w,
@@ -115,9 +113,7 @@ architecture str of node_adc_input_and_timing_nowg is
signal mm_jesd_ctrl_reg : std_logic_vector(c_word_w - 1 downto 0);
signal jesd204b_disable_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal jesd204b_reset : std_logic;
-
begin
-
-- The node AIT is reset at power up by mm_rst and under software control by jesd204b_reset.
-- The mm_rst internal will cause a reset on the rx_rst by the reset sequencer in the u_jesd204b.
-- The MM jesd204b_reset is intended for node AIT resynchronisation tests of the u_jesd204b.
@@ -127,6 +123,7 @@ begin
-- complete blocks, so from sop to eop.
mm_rst_internal <= mm_rst or mm_jesd_ctrl_reg(31);
+
gen_jesd_disable : for I in 0 to g_nof_streams - 1 generate
jesd204b_disable_arr(i) <= mm_jesd_ctrl_reg(i);
end generate;
@@ -207,7 +204,6 @@ begin
end process;
end generate;
-
---------------------------------------------------------------------------------------
-- Diagnostics on the bsn-framed data
-- . BSN Monitor (ToDo: can be removed as not part of the spec)
@@ -215,7 +211,6 @@ begin
-- . Data Buffer (variable depth from 1k-128k)
---------------------------------------------------------------------------------------
-
---------------------------------------------------------------------------------------
-- BSN monitor (Block Checker)
---------------------------------------------------------------------------------------
@@ -289,5 +284,4 @@ begin
out_reg => mm_jesd_ctrl_reg,
in_reg => mm_jesd_ctrl_reg
);
-
end str;
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
index e39ec207d0f4fe7ee51d9b0200eb6a61404a6f78..ee430f809c65a58a0eec86b38732fef2f3d243ea 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/qsys_unb2c_test_pkg.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package qsys_unb2c_test_pkg is
-
component qsys_unb2c_test is
port (
avs_eth_0_reset_export : out std_logic; -- export
@@ -466,4 +465,3 @@ package qsys_unb2c_test_pkg is
end component qsys_unb2c_test;
end qsys_unb2c_test_pkg;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
index 369db0c801ca7e4ad182474f8a5b9b31ce102dcb..bb282b576aae33d6e609ccf03ed4bdd039a75566 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/udp_stream.vhd
@@ -100,10 +100,7 @@ entity udp_stream is
);
end udp_stream;
-
-
architecture str of udp_stream is
-
-- Block generator
constant c_bg_ctrl : t_diag_block_gen := ('0', -- enable (disabled by default)
'0', -- enable_sync
@@ -114,7 +111,6 @@ architecture str of udp_stream is
TO_UVEC( g_bg_block_size-1, c_diag_bg_mem_high_adrs_w),
TO_UVEC( 0, c_diag_bg_bsn_init_w));
-
constant c_nof_crc_words : natural := 1;
constant c_max_nof_words_per_block : natural := g_bg_block_size;
constant c_min_nof_words_per_block : natural := 1;
@@ -133,9 +129,7 @@ architecture str of udp_stream is
signal diag_data_buf_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal diag_data_buf_snk_out_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
-
begin
-
gen_hdr_in_fields : for i in 0 to g_nof_streams - 1 generate
-- dst = src
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) downto field_lo(c_hdr_field_arr, "eth_src_mac")) <= x"00228608" & B"000" & ID(7 downto 3) & RESIZE_UVEC(ID(2 downto 0), c_byte_w);
@@ -152,7 +146,6 @@ begin
hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )) <= fifo_block_gen_src_out_arr(i).bsn(46 downto 0);
end generate;
-
-----------------------------------------------------------------------------
-- TX: Block generator and DP fifo
-----------------------------------------------------------------------------
@@ -207,7 +200,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
@@ -248,7 +240,6 @@ begin
hdr_fields_in_arr => hdr_fields_in_arr(g_nof_streams - 1 downto 0)
);
-
-----------------------------------------------------------------------------
-- RX: dp_offload_rx
-----------------------------------------------------------------------------
@@ -281,13 +272,11 @@ begin
hdr_fields_out_arr => hdr_fields_out_arr
);
-
gen_hdr_out_fields : for i in 0 to g_nof_streams - 1 generate
diag_data_buf_snk_in_arr(i).sync <= sl(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_sync") downto field_lo(c_hdr_field_arr, "usr_sync" )));
diag_data_buf_snk_in_arr(i).bsn <= RESIZE_UVEC(hdr_fields_out_arr(i)(field_hi(c_hdr_field_arr, "usr_bsn" ) downto field_lo(c_hdr_field_arr, "usr_bsn" )), c_dp_stream_bsn_w);
end generate;
-
-----------------------------------------------------------------------------
-- RX: Data buffers and BSN monitors
-----------------------------------------------------------------------------
@@ -301,8 +290,6 @@ begin
diag_data_buf_snk_in_arr(i).err <= dp_offload_rx_src_out_arr(i).err;
end generate;
-
-
u_dp_bsn_monitor : entity dp_lib.mms_dp_bsn_monitor
generic map (
g_nof_streams => g_nof_streams,
@@ -325,7 +312,6 @@ begin
in_sosi_arr => diag_data_buf_snk_in_arr(g_nof_streams - 1 downto 0)
);
-
diag_data_buf_snk_out_arr <= (others => c_dp_siso_rdy);
u_diag_data_buffer : entity diag_lib.mms_diag_data_buffer
@@ -353,6 +339,4 @@ begin
in_sync => diag_data_buf_snk_in_arr(0).sync,
in_sosi_arr => diag_data_buf_snk_in_arr
);
-
end str;
-
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index 4e407950f578f95f1396238843c3b2e574d17330..bed4ac8d3e09c468888fe4d8288a4d33e182a43e 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -38,7 +38,6 @@ use tech_ddr_lib.tech_ddr_pkg.all;
use work.unb2c_test_pkg.all;
use util_lib.util_heater_pkg.all;
-
entity unb2c_test is
generic (
g_design_name : string := "unb2c_test";
@@ -125,9 +124,7 @@ entity unb2c_test is
);
end unb2c_test;
-
architecture str of unb2c_test is
-
-- Firmware version x.y
constant c_fw_version : t_unb2c_board_fw_version := (2, 0);
constant c_mm_clk_freq : natural := c_unb2c_board_mm_clk_freq_125M;
@@ -465,9 +462,7 @@ architecture str of unb2c_test is
-- QSFP leds
signal qsfp_green_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
signal qsfp_red_led_arr : std_logic_vector(c_unb2c_board_tr_qsfp.nof_bus - 1 downto 0);
-
begin
-
assert false report "g_design_name = " & g_design_name severity NOTE;
gn_index <= TO_UINT(ID);
@@ -798,7 +793,6 @@ begin
ram_scrap_miso => ram_scrap_miso
);
-
gen_eth_0_udp : if c_use_eth_0_UDP = true generate
-- Derive MAC/IP/UDP from gn_index
gn_eth_src_mac_I <= c_base_mac & func_eth_tester_gn_index_to_mac_15_0(gn_index, 0);
@@ -854,7 +848,6 @@ begin
-- to stream UDP data via eth_0 = 1GbE-I.
end generate;
-
-- Instantiate a second 1GbE-II to check pinning and to test UDP data via a
-- dedicated 1GbE port, instead of multiplexed with M&C
gen_eth_1: if c_use_eth_1 = true generate
@@ -951,7 +944,6 @@ begin
);
end generate;
-
gen_udp_stream_10GbE : if c_use_10GbE = true and c_use_loopback = false generate
u_udp_stream_10GbE : entity work.udp_stream
generic map (
@@ -980,7 +972,6 @@ begin
reg_diag_tx_seq_mosi => reg_diag_tx_seq_10GbE_mosi,
reg_diag_tx_seq_miso => reg_diag_tx_seq_10GbE_miso,
-
-- loopback:
--dp_offload_tx_src_out_arr => dp_offload_tx_10GbE_src_out_arr,
--dp_offload_tx_src_in_arr => (OTHERS=>c_dp_siso_rdy),
@@ -993,7 +984,6 @@ begin
dp_offload_rx_snk_in_arr => dp_offload_rx_10GbE_snk_in_arr,
dp_offload_rx_snk_out_arr => dp_offload_rx_10GbE_snk_out_arr,
-
reg_bsn_monitor_mosi => reg_bsn_monitor_10GbE_mosi,
reg_bsn_monitor_miso => reg_bsn_monitor_10GbE_miso,
@@ -1006,7 +996,6 @@ begin
);
end generate;
-
gen_jesd204b : if c_use_jesd204b = true generate
u_jesd204b: entity work.node_adc_input_and_timing_nowg
generic map(
@@ -1045,7 +1034,6 @@ begin
);
end generate;
-
gen_front_10GbE : if c_use_10GbE = true generate
u_tr_10GbE_qsfp_and_ring: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- QSFP and Ring lines
generic map (
@@ -1085,7 +1073,6 @@ begin
i_serial_10G_rx_qsfp_ring_arr(i) <= serial_10G_rx_qsfp_arr(i);
end generate;
-
i_QSFP_RX(0) <= QSFP_0_RX;
i_QSFP_RX(1) <= QSFP_1_RX;
i_QSFP_RX(2) <= QSFP_2_RX;
@@ -1100,7 +1087,6 @@ begin
QSFP_4_TX <= i_QSFP_TX(4);
QSFP_5_TX <= i_QSFP_TX(5);
-
u_front_io : entity unb2c_board_lib.unb2c_board_front_io
generic map (
g_nof_qsfp_bus => c_nof_qsfp_bus
@@ -1139,7 +1125,6 @@ begin
RING_TX => i_RING_TX
);
-
gen_10gbe_back0 : if c_use_10GbE_back0 = true generate
u_tr_10GbE_back: entity unb2c_board_10gbe_lib.unb2c_board_10gbe -- BACK lines (upper)
generic map (
@@ -1171,7 +1156,6 @@ begin
);
end generate;
-
gen_back_wiring : if c_use_10GbE_back0 = true generate
gen_back0_wires: for i in 0 to c_nof_streams_back0 - 1 generate
serial_10G_tx_back_arr(i) <= i_serial_10G_tx_back0_arr(i);
@@ -1213,7 +1197,6 @@ begin
-- );
-- END GENERATE;
-
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds
generic map (
g_sim => g_sim,
@@ -1268,7 +1251,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- Interface : DDR4 MB_I and MB_II
-----------------------------------------------------------------------------
@@ -1276,7 +1258,6 @@ begin
assert func_tech_ddr_ctlr_data_w(c_ddr_MB_I) = func_tech_ddr_ctlr_data_w(c_ddr_MB_II) report "unb2c_test: DDR4 MB_I and MB_II must have the same ctlr data widths" severity FAILURE;
gen_stream_MB_I : if c_use_MB_I = true generate
-
u_mms_io_ddr_diag : entity io_ddr_lib.mms_io_ddr_diag
generic map (
-- System
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
index 4ed6dd8e64dea0f64b86c109100ed604284ce283..ecd624929ce531db8a1ed03d113ce557689377f7 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test_pkg.vhd
@@ -29,7 +29,6 @@ use common_lib.common_field_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
package unb2c_test_pkg is
-
-- dp_offload_tx (carried over from unb2a_test_pkg
--CONSTANT c_nof_hdr_fields : NATURAL := 1+3+12+4+2; -- Total header bits = 384 = 6 64b words
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 2; -- Total header bits = 384 = 6 64b words
@@ -93,9 +92,7 @@ package unb2c_test_pkg is
end unb2c_test_pkg;
-
package body unb2c_test_pkg is
-
function func_sel_revision_rec(g_design_name : string) return t_unb2c_test_config is
begin
if g_design_name = "unb2c_test_10GbE" then return c_test_10GbE;
@@ -107,7 +104,7 @@ package body unb2c_test_pkg is
elsif g_design_name = "unb2c_test_ddr_16G" then return c_test_ddr_16G;
else return c_test_minimal;
end if;
- end;
+ end;
end unb2c_test_pkg;
diff --git a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
index 23c9cf1f6129b9956e53440d7daf5f95e5682e47..a34e6633db99ec9a06cab4d836db5f2030d95324 100644
--- a/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/tb/vhdl/tb_unb2c_test.vhd
@@ -59,7 +59,6 @@ entity tb_unb2c_test is
end tb_unb2c_test;
architecture tb of tb_unb2c_test is
-
constant c_sim : boolean := true;
constant c_ddr_MB_I : t_c_tech_ddr := c_tech_ddr4_4g_1600m; -- DDR4 has no master or slave, so no need to check number of MB
@@ -131,9 +130,7 @@ architecture tb of tb_unb2c_test is
signal si_lpbk_7 : std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
signal si_lpbk_8 : std_logic_vector(c_unb2c_board_tr_back.bus_w - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -257,5 +254,4 @@ begin
mem4_in => MB_II_OU,
mem4_io => MB_II_IO
);
-
end tb;
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
index 8ae42abc8f999c6f6c4433dbfef4b2510c1369df..2b7934b9c80f06c9048de3c8e495883c7c7e611d 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/bscan2_8port_top.vhd
@@ -65,7 +65,6 @@ entity bscan2 is
end;
architecture behave of bscan2 is
-
component top_linker is
-- do not use the generic map to prevent the synthesis tool from
-- appending the number of ports to the components name.
@@ -96,7 +95,6 @@ signal LSPTDO : std_logic_vector(4 * bscan_ports - 1 downto 0);
signal LSPTRST : std_logic_vector(4 * bscan_ports - 1 downto 0);
-- output of Port Mux
signal TDO_int : std_logic;
-
begin
-- Wire up all of the tri-state controlled lines automatically
tri_state_lines : for lvar1 in 0 to (4 * bscan_ports - 1) generate
@@ -128,7 +126,6 @@ begin
MSPTRST => LSPTRST,
IDN => IDN
);
-
end behave;
--------------------------------- E O F --------------------------------------
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
index c29a1724c72da42a779ac6622583794df75ba45b..a26751236aab0e7203dc36a06fd6758f5faf50dc 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
@@ -24,9 +24,7 @@ library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
-
architecture str of jtag_top is
-
component bscan2 is
-- enter the number of BSCAN2 blocks to create. This is the only place that
-- needs to be modified to control the number of local scan ports created.
@@ -63,7 +61,6 @@ architecture str of jtag_top is
signal MSPTCK_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
signal MSPTMS_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
signal MSPTRST_BSCAN : std_logic_vector(jtag_chains - 1 downto 0);
-
begin
bscan : component bscan2
port map (
@@ -81,7 +78,6 @@ architecture str of jtag_top is
IDN => "0000"
);
-
p_jtagselect: process(TDI,MSPTDI(jtag_chains - 1 downto 0),TCK,TMS,TRST)
begin
ENABLE_SB <= '0';
@@ -148,7 +144,5 @@ architecture str of jtag_top is
TDO <= TDD;
end if;
end if;
-
end process;
end str;
-
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
index 96ea994b4e4681635f22aca38a49f3a328569f90..74bc5570a961ed53b0fcd6feed3601bfff152d3f 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/ctrl_unb2c_board.vhd
@@ -238,9 +238,7 @@ entity ctrl_unb2c_board is
);
end ctrl_unb2c_board;
-
architecture str of ctrl_unb2c_board is
-
constant c_rom_version : natural := 3; -- Only increment when something changes to the register map of rom_system_info.
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
@@ -298,9 +296,7 @@ architecture str of ctrl_unb2c_board is
attribute maxfan : integer;
attribute maxfan of dp_rst : signal is 1024;
-
begin
-
ext_clk200 <= i_ext_clk200;
xo_ethclk <= i_xo_ethclk;
xo_rst <= i_xo_rst;
@@ -349,7 +345,6 @@ begin
out_rst => i_xo_rst
);
-
-----------------------------------------------------------------------------
-- MB_I_REF_CLK --> mb_I_ref_rst
-- MB_II_REF_CLK --> mb_II_ref_rst
@@ -503,7 +498,6 @@ begin
bck_id => this_bck_id
);
-
-----------------------------------------------------------------------------
-- Red LED control
-----------------------------------------------------------------------------
@@ -517,7 +511,6 @@ begin
TESTIO(c_unb2c_board_testio_led_red) <= led_toggle_red;
end generate;
-
-----------------------------------------------------------------------------
-- Green LED control
-----------------------------------------------------------------------------
@@ -531,7 +524,6 @@ begin
TESTIO(c_unb2c_board_testio_led_green) <= led_toggle_green;
end generate;
-
------------------------------------------------------------------------------
-- Toggle red LED when unb2c_minimal is running, green LED for other designs.
------------------------------------------------------------------------------
@@ -546,7 +538,6 @@ begin
out_dat => led_toggle
);
-
------------------------------------------------------------------------------
-- WDI override
------------------------------------------------------------------------------
@@ -566,7 +557,6 @@ begin
wdi_override => wdi_override
);
-
------------------------------------------------------------------------------
-- Remote upgrade
------------------------------------------------------------------------------
@@ -644,7 +634,6 @@ begin
pps_sys => dp_pps
);
-
u_mms_unb2c_fpga_sens : entity work.mms_unb2c_fpga_sens
generic map (
g_sim => g_sim,
@@ -668,7 +657,6 @@ begin
temp_alarm => temp_alarm
);
-
------------------------------------------------------------------------------
-- Ethernet 1GbE
------------------------------------------------------------------------------
@@ -690,7 +678,6 @@ begin
i_tse_clk <= i_xo_ethclk;
end generate;
-
wire_udp_offload: for i in 0 to g_udp_offload_nof_streams - 1 generate
eth1g_udp_tx_sosi_arr(i) <= udp_tx_sosi_arr(i);
udp_tx_siso_arr(i) <= eth1g_udp_tx_siso_arr(i);
@@ -709,7 +696,6 @@ begin
--On hardware always generate 1GbE for MM control. In simulation only use 1GbE for streaming DP data offload (or on load) via 1GbE.
gen_eth: if g_sim = false or g_udp_offload = true generate
-
eth1g_st_clk <= dp_clk_in when g_udp_offload = true else i_mm_clk;
eth1g_st_rst <= dp_rst_in when g_udp_offload = true else eth1g_mm_rst;
@@ -770,5 +756,4 @@ begin
rd_dat => ram_scrap_miso.rddata(c_ram_scrap.dat_w - 1 downto 0),
rd_val => ram_scrap_miso.rdval
);
-
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
index aed541eb2bcfcc24b246a8f03eaf0955663c6349..699c38a4d2262156a5cc1fa378aeb487034d732f 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_board_system_info.vhd
@@ -61,9 +61,7 @@ entity mms_unb2c_board_system_info is
);
end mms_unb2c_board_system_info;
-
architecture str of mms_unb2c_board_system_info is
-
-- Provide different prefixes (absolute and relative) for the same path. ModelSim understands $UNB, Quartus does not.
-- Required because the work paths of ModelSim and Quartus are different.
constant c_quartus_path_prefix : string := "";
@@ -83,9 +81,7 @@ architecture str of mms_unb2c_board_system_info is
init_sl => '0');
signal i_info : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
info <= i_info;
u_unb2c_board_system_info: entity work.unb2c_board_system_info
@@ -136,6 +132,4 @@ begin
rd_dat => rom_miso.rddata(c_mm_rom.dat_w - 1 downto 0),
rd_val => rom_miso.rdval
);
-
end str;
-
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
index 856ca0601b328d72b29079731bb8adb842fa3719..6b19f5aad1f07bc80ddbdc66a4e10bde2219af4e 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/mms_unb2c_fpga_sens.vhd
@@ -29,7 +29,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use technology_lib.technology_pkg.all;
-
entity mms_unb2c_fpga_sens is
generic (
g_sim : boolean := false;
@@ -53,11 +52,8 @@ entity mms_unb2c_fpga_sens is
);
end mms_unb2c_fpga_sens;
-
architecture str of mms_unb2c_fpga_sens is
-
begin
-
u_fpga_sense: entity fpga_sense_lib.fpga_sense
generic map (
g_technology => g_technology,
@@ -77,6 +73,4 @@ begin
reg_voltage_store_mosi => reg_voltage_mosi,
reg_voltage_store_miso => reg_voltage_miso
);
-
end str;
-
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
index 8a297498d4cdfc0dbcc322e19acd09b963d91151..f50eaf95d22a55f101164441bc0734c4cf31d123 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_back_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2c_board_pkg.all;
-
entity unb2c_board_back_io is
generic (
g_nof_back_bus : natural := c_unb2c_board_tr_back.nof_bus
@@ -39,26 +38,19 @@ entity unb2c_board_back_io is
end unb2c_board_back_io;
architecture str of unb2c_board_back_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2c_board_back_bus_2arr(g_nof_back_bus - 1 downto 0);
signal si_rx_2arr : t_unb2c_board_back_bus_2arr(g_nof_back_bus - 1 downto 0);
-
begin
-
gen_buses : for i in 0 to g_nof_back_bus - 1 generate
BCK_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= BCK_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_back_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2c_board_tr_back.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_back.bus_w + j);
serial_rx_arr(i * c_unb2c_board_tr_back.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
index b49538091f8391cea84724960b3d982ef7531c02..1c0b8a5d378373cd491677a316c707a5d54e7020 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk125_pll.vhd
@@ -51,13 +51,9 @@ entity unb2c_board_clk125_pll is
);
end unb2c_board_clk125_pll;
-
architecture arria10 of unb2c_board_clk125_pll is
-
signal clk125buf : std_logic;
-
begin
-
no_clkbuf : if g_use_clkbuf = false generate
clk125buf <= clk125;
end generate;
@@ -74,7 +70,6 @@ begin
);
end generate;
-
gen_pll : if g_use_fpll = false generate
u_pll : entity tech_pll_lib.tech_pll_clk125
generic map (
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
index 5f8d74ee97b2aeecd679ad1d91e0bff719dc9025..ac16a08d1527d9590123f78b04e3bf8fe1ec08b4 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk200_pll.vhd
@@ -113,9 +113,7 @@ entity unb2c_board_clk200_pll is
);
end unb2c_board_clk200_pll;
-
architecture arria10 of unb2c_board_clk200_pll is
-
constant c_reset_len : natural := c_meta_delay_len;
signal clk200buf : std_logic;
@@ -126,9 +124,7 @@ architecture arria10 of unb2c_board_clk200_pll is
signal st_locked : std_logic;
signal st_locked_n : std_logic;
-
begin
-
st_rst200 <= i_st_rst200;
st_clk200 <= i_st_clk200;
st_clk200p <= i_st_clk200p;
@@ -218,5 +214,4 @@ begin
clk => i_st_clk400,
out_rst => st_rst400
);
-
end arria10;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
index bbf90bac978ce74399f325117161d888901406f4..71a8f3000c65aa0a7d3ed3c3ef3cee696d09c8b6 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk25_pll.vhd
@@ -49,10 +49,8 @@ entity unb2c_board_clk25_pll is
);
end unb2c_board_clk25_pll;
-
architecture arria10 of unb2c_board_clk25_pll is
begin
-
u_pll : entity tech_pll_lib.tech_pll_clk25
generic map (
g_technology => g_technology
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
index 15196c296fb2f8f284b911cc03ebbedf2f80b7cb..25dd597531db0184a247147f3cf4ae108149fc54 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_clk_rst.vhd
@@ -42,9 +42,7 @@ entity unb2c_board_clk_rst is
);
end unb2c_board_clk_rst;
-
architecture str of unb2c_board_clk_rst is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
-- XO clock domain
@@ -52,9 +50,7 @@ architecture str of unb2c_board_clk_rst is
-- SYS clock domain
signal sys_locked_n : std_logic;
-
begin
-
-- Reference clock and reset to SOPC system PLL
xo_rst_n <= not xo_rst;
@@ -82,5 +78,4 @@ begin
clk => sys_clk,
out_rst => sys_rst
);
-
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
index 38feccfe053d79dc61240371bd0be2c12b2ce377..ca19220a75b529d1a263629c316a583a70dbb275 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_front_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2c_board_pkg.all;
-
entity unb2c_board_front_io is
generic (
g_nof_qsfp_bus : natural := c_unb2c_board_tr_qsfp.nof_bus
@@ -45,32 +44,24 @@ entity unb2c_board_front_io is
end unb2c_board_front_io;
architecture str of unb2c_board_front_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2c_board_qsfp_bus_2arr(g_nof_qsfp_bus - 1 downto 0);
signal si_rx_2arr : t_unb2c_board_qsfp_bus_2arr(g_nof_qsfp_bus - 1 downto 0);
-
begin
-
gen_leds : for i in 0 to g_nof_qsfp_bus - 1 generate
QSFP_LED(i * 2) <= green_led_arr(i);
QSFP_LED(i * 2 + 1) <= red_led_arr(i);
end generate;
-
gen_buses : for i in 0 to g_nof_qsfp_bus - 1 generate
QSFP_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= QSFP_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_qsfp_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2c_board_tr_qsfp.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j);
serial_rx_arr(i * c_unb2c_board_tr_qsfp.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
index a2c00f0705c34243b841b67d09484690fd45901b..cd18bbc40cec125f81658a0fd47e06cef83951e1 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_node_ctrl.vhd
@@ -54,17 +54,13 @@ entity unb2c_board_node_ctrl is
);
end unb2c_board_node_ctrl;
-
architecture str of unb2c_board_node_ctrl is
-
constant c_reset_len : natural := 4; -- >= c_meta_delay_len from common_pkg
signal mm_locked_n : std_logic;
signal i_mm_rst : std_logic;
signal i_mm_pulse_ms : std_logic;
-
begin
-
-- Create mm_rst reset in mm_clk domain based on mm_locked
mm_rst <= i_mm_rst;
@@ -110,5 +106,4 @@ begin
wdi_in => mm_wdi_in,
wdi_out => mm_wdi_out
);
-
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
index 3393b547e5fb2e271531b32e62688b741815496a..09f3d31eb03c9dea2187fe903fad302efc866c1b 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_peripherals_pkg.vhd
@@ -42,8 +42,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package unb2c_board_peripherals_pkg is
-
-
-- *_adr_w : Actual MM address widths
-- *_dat_w : The default MM data width is c_word_w=32, otherwise it is specified in the record
type t_c_unb2c_board_peripherals_mm_reg is record
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
index e5f736645002e4d9d53b64ea82003045a093fcec..58d12477543d49583818dbc0ecda26a5527523f9 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_pkg.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
package unb2c_board_pkg is
-
-- UniBoard
constant c_unb2c_board_nof_node : natural := 4; -- number of nodes on UniBoard
constant c_unb2c_board_nof_node_w : natural := 2; -- = ceil_log2(c_unb2c_board_nof_node)
@@ -80,12 +79,10 @@ package unb2c_board_pkg is
constant c_unb2c_board_nof_sync_jesd204b : natural := 4; -- 4 channels used in unb2c lab tests, 1 for each RCU.
constant c_unb2c_board_tr_qsfp_nof_leds : natural := c_unb2c_board_tr_qsfp.nof_bus * 2; -- 2 leds per qsfp
-
type t_unb2c_board_qsfp_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2c_board_tr_qsfp.bus_w - 1 downto 0);
type t_unb2c_board_ring_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2c_board_tr_ring.bus_w - 1 downto 0);
type t_unb2c_board_back_bus_2arr is array (integer range <>) of std_logic_vector(c_unb2c_board_tr_back.bus_w - 1 downto 0);
-
-- Auxiliary
-- Test IO Interface
@@ -139,9 +136,7 @@ package unb2c_board_pkg is
end unb2c_board_pkg;
-
package body unb2c_board_pkg is
-
function func_unb2c_board_system_info(VERSION : in std_logic_vector(c_unb2c_board_aux.version_w - 1 downto 0);
ID : in std_logic_vector(c_unb2c_board_aux.id_w - 1 downto 0)) return t_c_unb2c_board_system_info is
variable v_system_info : t_c_unb2c_board_system_info;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
index d5946ebcabfb9f56663d764e42ba73e7f2835c41..47ba71e8f14fc9c3f4fd57fb24ecdaa1de4724f1 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_qsfp_leds.vhd
@@ -88,9 +88,7 @@ entity unb2c_board_qsfp_leds is
);
end unb2c_board_qsfp_leds;
-
architecture str of unb2c_board_qsfp_leds is
-
constant c_nof_ms : natural := sel_a_b(g_sim, 1, 100); -- force off for c_nof_ms and then on for at least c_nof_ms
constant c_nof_lanes : natural := g_nof_qsfp * c_quad; -- number of transceiver lanes, fixed 4 per Quad-SFP cage
@@ -103,9 +101,7 @@ architecture str of unb2c_board_qsfp_leds is
signal qsfp_on_arr : std_logic_vector(g_nof_qsfp - 1 downto 0);
signal qsfp_evt_arr : std_logic_vector(g_nof_qsfp - 1 downto 0);
-
begin
-
pulse_ms <= i_pulse_ms;
pulse_s <= i_pulse_s;
@@ -152,7 +148,6 @@ begin
end generate;
gen_user_image : if g_factory_image = false generate
-
red_led_arr <= (others => '0');
gen_green_ctrl_arr : for I in c_nof_lanes - 1 downto 0 generate
@@ -161,7 +156,6 @@ begin
end generate;
gen_green_led_arr : for I in g_nof_qsfp - 1 downto 0 generate
-
qsfp_on_arr(I) <= orv(green_on_arr( (I + 1) * c_quad - 1 downto + I * c_quad));
qsfp_evt_arr(I) <= orv(green_evt_arr((I + 1) * c_quad - 1 downto + I * c_quad));
@@ -182,5 +176,4 @@ begin
);
end generate;
end generate;
-
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
index c0098cce0947f138bc03cd516ff7cf9188c84e10..1ae3b3d7e6a67a5e4276d3a8a296b0ec36ec2984 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_ring_io.vhd
@@ -23,7 +23,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.unb2c_board_pkg.all;
-
entity unb2c_board_ring_io is
generic (
g_nof_ring_bus : natural := c_unb2c_board_tr_ring.nof_bus
@@ -38,26 +37,19 @@ entity unb2c_board_ring_io is
end unb2c_board_ring_io;
architecture str of unb2c_board_ring_io is
-
-- help signals so we can iterate through buses
signal si_tx_2arr : t_unb2c_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0);
signal si_rx_2arr : t_unb2c_board_ring_bus_2arr(g_nof_ring_bus - 1 downto 0);
-
begin
-
gen_buses : for i in 0 to g_nof_ring_bus - 1 generate
RING_TX(i) <= si_tx_2arr(i);
si_rx_2arr(i) <= RING_RX(i);
end generate;
-
gen_wire_bus : for i in 0 to g_nof_ring_bus - 1 generate
gen_wire_signals : for j in 0 to c_unb2c_board_tr_ring.bus_w - 1 generate
-
si_tx_2arr(i)(j) <= serial_tx_arr(i * c_unb2c_board_tr_ring.bus_w + j);
serial_rx_arr(i * c_unb2c_board_tr_ring.bus_w + j) <= si_rx_2arr(i)(j);
-
end generate;
end generate;
-
end;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
index dbd91d248cfb20f18a2ef31ddb32b022b7519c92..ca28bdf4878eba02b20b0cc25d2ed634eb722b75 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info.vhd
@@ -50,9 +50,7 @@ entity unb2c_board_system_info is
);
end unb2c_board_system_info;
-
architecture str of unb2c_board_system_info is
-
signal cs_sim : std_logic;
signal hw_version_reg : std_logic_vector(hw_version'range);
@@ -63,9 +61,7 @@ architecture str of unb2c_board_system_info is
signal nxt_chip_id : std_logic_vector(chip_id'range);
signal nxt_node_id : std_logic_vector(node_id'range);
signal nxt_is_node2 : std_logic;
-
begin
-
p_reg : process(clk)
begin
if rising_edge(clk) then
@@ -98,5 +94,4 @@ begin
nxt_chip_id <= id_reg(1 downto 0);
nxt_node_id <= id_reg(1 downto 0);
nxt_is_node2 <= '1' when TO_UINT(id_reg(1 downto 0)) = 2 else '0';
-
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
index 9f6723e73f32aa833f29610eeb89cd99947498e7..355bf6c3afeb7a535f5da8a5ad23e2886cc4da62 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_system_info_reg.vhd
@@ -71,9 +71,7 @@ entity unb2c_board_system_info_reg is
);
end unb2c_board_system_info_reg;
-
architecture rtl of unb2c_board_system_info_reg is
-
constant c_nof_fixed_regs : natural := 2; -- info, use_phy
constant c_nof_design_name_regs : natural := 13; -- design_name
constant c_nof_stamp_regs : natural := 2; -- date, time
@@ -100,9 +98,7 @@ architecture rtl of unb2c_board_system_info_reg is
constant c_design_name : t_slv_32_arr(0 to c_nof_design_name_regs - 1) := str_to_ascii_slv_32_arr(g_design_name, c_nof_design_name_regs);
constant c_revision_id : t_slv_32_arr(0 to c_nof_revision_id_regs - 1) := str_to_ascii_slv_32_arr(g_revision_id, c_nof_revision_id_regs);
constant c_design_note : t_slv_32_arr(0 to c_nof_design_note_regs - 1) := str_to_ascii_slv_32_arr(g_design_note, c_nof_design_note_regs);
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
variable vA : natural := 0;
begin
@@ -142,14 +138,8 @@ begin
elsif vA < c_design_note_offset + c_nof_design_note_regs then
sla_out.rddata(c_word_w - 1 downto 0) <= c_design_note(vA - c_design_note_offset);
-
end if;
-
end if;
end if;
-
end process;
-
-
end rtl;
-
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
index 53b672732f41a8174b5d8fd1d893b681070e7e44..4c53cdcc41f7c1f197a447530a4d6890ae6d0d48 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_extend.vhd
@@ -43,9 +43,7 @@ entity unb2c_board_wdi_extend is
);
end unb2c_board_wdi_extend;
-
architecture str of unb2c_board_wdi_extend is
-
signal wdi_evt : std_logic;
signal wdi_cnt : std_logic_vector(g_extend_w - 1 downto 0);
@@ -53,9 +51,7 @@ architecture str of unb2c_board_wdi_extend is
signal i_wdi_out : std_logic;
signal nxt_wdi_out : std_logic;
-
begin
-
wdi_out <= i_wdi_out;
p_clk : process(rst, clk)
@@ -94,5 +90,4 @@ begin
cnt_en => wdi_cnt_en,
count => wdi_cnt
);
-
end str;
diff --git a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
index 4a492464e0aabf3a68cc54a280784ed4597bb7e9..6c9a33e3833702e9aeffa2a846dd915129136e1f 100644
--- a/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/src/vhdl/unb2c_board_wdi_reg.vhd
@@ -43,9 +43,7 @@ entity unb2c_board_wdi_reg is
);
end unb2c_board_wdi_reg;
-
architecture rtl of unb2c_board_wdi_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
@@ -55,9 +53,7 @@ architecture rtl of unb2c_board_wdi_reg is
-- For safety, WDI override requires the following word to be written:
constant c_cmd_reconfigure : std_logic_vector(c_word_w - 1 downto 0 ) := x"B007FAC7"; -- "Boot factory"
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -82,9 +78,6 @@ begin
when others => null; -- unused MM addresses
end case;
end if;
-
end if;
end process;
-
end rtl;
-
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
index d081a13807582b6a58b027afc9a85ec6cf92945e..320d5febe60192f37cbbf7a5b57e4e152c719d76 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk125_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2c_board_clk125_pll is
end tb_unb2c_board_clk125_pll;
-
architecture tb of tb_unb2c_board_clk125_pll is
-
constant c_ext_clk_period : time := 8 ns; -- 125 MHz
signal tb_end : std_logic := '0';
@@ -48,9 +44,7 @@ architecture tb of tb_unb2c_board_clk125_pll is
signal c2_clk100 : std_logic;
signal c3_clk125 : std_logic;
signal pll_locked : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
index 3f1864bac78910e37fd76c63eb757a391c28dcb1..4a035d2eb5a0a25872bae21f0151d62c0582edde 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk200_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2c_board_clk200_pll is
end tb_unb2c_board_clk200_pll;
-
architecture tb of tb_unb2c_board_clk200_pll is
-
constant c_ext_clk_period : time := 5 ns; -- 200 MHz
constant c_clk_vec_w : natural := 6;
constant c_clk_div : natural := 32;
@@ -63,9 +59,7 @@ architecture tb of tb_unb2c_board_clk200_pll is
signal dp_clk200 : std_logic;
signal dp_rst200 : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
@@ -112,5 +106,4 @@ begin
st_clk200 => dp_clk200,
st_rst200 => dp_rst200
);
-
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
index 0e6f2a84383c454792b68cce4e5e4085306146c4..9923168e21be66ac5518393923c47ae5457e6d05 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_clk25_pll.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Simulate phase behaviour of PLL in normal mode
-- Description:
-- Usage:
@@ -31,13 +30,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2c_board_clk25_pll is
end tb_unb2c_board_clk25_pll;
-
architecture tb of tb_unb2c_board_clk25_pll is
-
constant c_ext_clk_period : time := 40 ns; -- 25 MHz
signal tb_end : std_logic := '0';
@@ -48,9 +44,7 @@ architecture tb of tb_unb2c_board_clk25_pll is
signal c2_clk100 : std_logic;
signal c3_clk125 : std_logic;
signal pll_locked : std_logic;
-
begin
-
tb_end <= '0', '1' after c_ext_clk_period * 5000;
ext_clk <= not ext_clk or tb_end after c_ext_clk_period / 2;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
index d4965685a275705766d715f764d9b72ec86f378b..a7a90847160de275f83afcbb6bb16352204cba95 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_node_ctrl.vhd
@@ -24,13 +24,10 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity tb_unb2c_board_node_ctrl is
end tb_unb2c_board_node_ctrl;
-
architecture tb of tb_unb2c_board_node_ctrl is
-
constant c_scale : natural := 100; -- scale to speed up simulation
constant c_xo_clk_period : time := 1 us; -- 1 MHz XO, slow XO to speed up simulation
@@ -62,9 +59,7 @@ architecture tb of tb_unb2c_board_node_ctrl is
signal pulse_us : std_logic;
signal pulse_ms : std_logic;
signal pulse_s : std_logic;
-
begin
-
-- run 2000 ms
mm_clk <= not mm_clk after c_mm_clk_period / 2;
@@ -95,5 +90,4 @@ begin
mm_pulse_ms => pulse_ms,
mm_pulse_s => pulse_s
);
-
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
index ef1060ab69b5328dfd609015065244cb724cae1e..9ee6059b7f62c1dc5c3ae93cc12772da27049228 100644
--- a/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board/tb/vhdl/tb_unb2c_board_qsfp_leds.vhd
@@ -46,7 +46,6 @@ entity tb_unb2c_board_qsfp_leds is
end tb_unb2c_board_qsfp_leds;
architecture tb of tb_unb2c_board_qsfp_leds is
-
constant c_clk_freq_hz : natural := 200 * 10**6;
constant c_clk_period_ns : natural := 10**9 / c_clk_freq_hz;
constant c_nof_clk_per_us : natural := 1000 / c_clk_period_ns;
@@ -84,9 +83,7 @@ architecture tb of tb_unb2c_board_qsfp_leds is
signal dbg_sop : std_logic;
signal dbg_sop_slv : std_logic_vector(c_nof_lanes - 1 downto 0);
signal dbg_sosi : t_dp_sosi;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -186,5 +183,4 @@ begin
green_led_arr => user_green_led_arr,
red_led_arr => user_red_led_arr
);
-
end tb;
diff --git a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
index 9ad00ea2491fd80b455d367b12296915ef9b7861..92199c7404a1380dffa28b1478c66a69c87469fc 100644
--- a/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
+++ b/boards/uniboard2c/libraries/unb2c_board_10gbe/src/vhdl/unb2c_board_10gbe.vhd
@@ -27,7 +27,6 @@ use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_pkg.all;
-
entity unb2c_board_10gbe is
generic (
g_sim : boolean := false;
@@ -73,13 +72,10 @@ entity unb2c_board_10gbe is
);
end unb2c_board_10gbe;
-
architecture str of unb2c_board_10gbe is
-
signal tr_ref_clk_312 : std_logic;
signal tr_ref_clk_156 : std_logic;
signal tr_ref_rst_156 : std_logic;
-
begin
u_unb2c_board_clk644_pll : entity tech_pll_lib.tech_pll_xgmii_mac_clocks
generic map (
@@ -94,7 +90,6 @@ begin
rst_312 => open
);
-
u_tr_10GbE: entity tr_10GbE_lib.tr_10GbE
generic map (
g_technology => g_technology,
@@ -140,5 +135,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
index 39e964b31d04be047b8d5bb698f5c6de196d76db..e95d9eaf75c95c18f69917a472c173b12a9cfdf2 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_mm_bridge.vhd
@@ -74,7 +74,6 @@ architecture str of axi4_lite_mm_bridge is
signal d_bvalid : std_logic := '0';
signal q_bvalid : std_logic := '0';
-
begin
i_rst <= not in_rst when g_active_low_rst else in_rst;
aresetn <= not i_rst;
@@ -116,4 +115,3 @@ begin
end if;
end process;
end str;
-
diff --git a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
index 7010309e6f82e7c3a09c9f5efa570300aa980a94..6f94af5302e237eaadbc1ee564b4dd6f46f381c3 100644
--- a/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_lite_pkg.vhd
@@ -36,7 +36,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
package axi4_lite_pkg is
-
------------------------------------------------------------------------------
-- Simple AXI4 lite memory access (for MM control interface)
------------------------------------------------------------------------------
@@ -45,7 +44,6 @@ package axi4_lite_pkg is
constant c_axi4_lite_prot_w : natural := 3;
constant c_axi4_lite_resp_w : natural := 2;
-
type t_axi4_lite_copi is record -- Controller Out Peripheral In
-- write address channel
awaddr : std_logic_vector(c_axi4_lite_address_w - 1 downto 0); -- write address
@@ -104,7 +102,6 @@ package axi4_lite_pkg is
end axi4_lite_pkg;
package body axi4_lite_pkg is
-
function func_axi4_lite_to_mm_copi(axi4_copi : t_axi4_lite_copi) return t_mem_copi is
variable v_mm_copi : t_mem_copi := c_mem_copi_rst;
begin
@@ -113,6 +110,7 @@ package body axi4_lite_pkg is
else
v_mm_copi.address := "00" & axi4_copi.araddr(c_axi4_lite_address_w - 1 downto 2); -- convert byte addressed to word addressed.
end if;
+
v_mm_copi.wrdata(c_axi4_lite_data_w - 1 downto 0) := axi4_copi.wdata;
v_mm_copi.wr := axi4_copi.awvalid;
v_mm_copi.rd := axi4_copi.arvalid;
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
index 670f3ac26a9cf696631cf4b1d420f9d6040abee6..35b1086347c509af47361b9e044acf0ed57cf023 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_dp_bridge.vhd
@@ -100,7 +100,6 @@ architecture str of axi4_stream_dp_bridge is
-- Registers
signal d_reg : t_reg := c_reg_init;
signal q_reg : t_reg := c_reg_init;
-
begin
i_rst <= not in_rst when g_active_low_rst else in_rst;
aresetn <= not i_rst;
@@ -129,7 +128,6 @@ begin
src_in => axi4_from_dp_siso
);
-
----------------------------
-- Translate AXI4 to DP
----------------------------
@@ -193,6 +191,4 @@ begin
src_out => dp_out_sosi,
src_in => dp_out_siso
);
-
end str;
-
diff --git a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
index b1c8b44e73dd0dd1b96792fb1b56765eb4fc356a..713f1ed150006f96a432c5605bc1b224c6c52d85 100644
--- a/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
+++ b/libraries/base/axi4/src/vhdl/axi4_stream_pkg.vhd
@@ -53,7 +53,6 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
package axi4_stream_pkg is
-
constant c_axi4_stream_data_w : natural := 512; -- Data width, upto 512bit for Xilinx IP
constant c_axi4_stream_user_w : natural := 70; -- User data, upto 70bit for Xilinx IP
constant c_axi4_stream_tid_w : natural := 4; -- Thread ID, upto 4bit for Xilinx IP
@@ -76,7 +75,6 @@ package axi4_stream_pkg is
tuser : std_logic_vector(c_axi4_stream_user_w - 1 downto 0); -- Tranaction user fields
end record;
-
-- Initialise signal declarations with c_axi4_stream_rst/rdy to ease the interpretation of slv fields with unused bits
constant c_axi4_siso_rst : t_axi4_siso := (tready => '0');
constant c_axi4_siso_x : t_axi4_siso := (tready => 'X');
@@ -86,7 +84,6 @@ package axi4_stream_pkg is
constant c_axi4_sosi_rst : t_axi4_sosi := (tvalid => '0', tdata => (others => '0'), tstrb => (others => '0'), tkeep => (others => '0'), tlast => '0', tid => (others => '0'), tdest => (others => '0'), tuser => (others => '0'));
constant c_axi4_sosi_x : t_axi4_sosi := ('X', (others => 'X'), (others => 'X'), (others => 'X'), 'X', (others => 'X'), (others => 'X'), (others => 'X'));
-
-- Multi port or multi register array for DP stream records
type t_axi4_siso_arr is array (integer range <>) of t_axi4_siso;
type t_axi4_sosi_arr is array (integer range <>) of t_axi4_sosi;
@@ -129,7 +126,6 @@ package axi4_stream_pkg is
signal siso_arr : in t_axi4_siso_arr;
signal ready_reg : inout std_logic_vector);
-
-- Keep part of head data and combine part of tail data, use the other sosi from head_sosi
function func_axi4_data_shift_first(head_sosi, tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_axi4_sosi;
-- Shift and combine part of previous data and this data, use the other sosi from prev_sosi
@@ -193,9 +189,7 @@ package axi4_stream_pkg is
end axi4_stream_pkg;
-
package body axi4_stream_pkg is
-
-- Check sosi.valid against siso.ready
procedure proc_axi4_siso_alert(constant c_ready_latency : in natural;
signal clk : in std_logic;
@@ -210,6 +204,7 @@ package body axi4_stream_pkg is
if sosi.tvalid = '1' and ready_reg(c_ready_latency) = '0' then
report "RL ERROR" severity FAILURE;
end if;
+
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
end if;
end proc_axi4_siso_alert;
@@ -270,7 +265,6 @@ package body axi4_stream_pkg is
return v_sosi;
end func_axi4_data_shift_first;
-
-- Shift and combine part of previous data and this data,
function func_axi4_data_shift(prev_sosi, this_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_axi4_sosi is
variable vK : natural := nof_symbols_from_this;
@@ -303,7 +297,6 @@ package body axi4_stream_pkg is
return v_sosi;
end func_axi4_data_shift;
-
-- Shift part of tail data and account for input empty
function func_axi4_data_shift_last(tail_sosi : t_axi4_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_axi4_sosi is
variable vK : natural := nof_symbols_from_tail;
@@ -332,7 +325,6 @@ package body axi4_stream_pkg is
return v_sosi;
end func_axi4_data_shift_last;
-
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
function func_axi4_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
@@ -360,7 +352,6 @@ package body axi4_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_axi4_empty_split;
-
-- Multiplex the t_axi4_sosi_arr based on the valid, assuming that at most one input is active valid.
function func_axi4_sosi_arr_mux(axi4 : t_axi4_sosi_arr) return t_axi4_sosi is
variable v_sosi : t_axi4_sosi := c_axi4_sosi_rst;
@@ -374,7 +365,6 @@ package body axi4_stream_pkg is
return v_sosi;
end func_axi4_sosi_arr_mux;
-
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_axi4_*_arr (for all elements or only for the mask[]='1' elements)
function func_axi4_stream_arr_and(axi4 : t_axi4_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(axi4'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
@@ -484,7 +474,6 @@ package body axi4_stream_pkg is
return func_axi4_stream_arr_or(axi4, c_mask, str);
end func_axi4_stream_arr_or;
-
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_axi4_stream_arr_set(axi4 : t_axi4_siso_arr; slv : std_logic_vector; str : string) return t_axi4_siso_arr is
variable v_axi4 : t_axi4_siso_arr(axi4'range) := axi4; -- default
@@ -544,7 +533,6 @@ package body axi4_stream_pkg is
return v_ctrl;
end func_axi4_stream_arr_get;
-
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
function func_axi4_stream_arr_select(sel : std_logic_vector; a, b : t_axi4_siso) return t_axi4_siso_arr is
variable v_axi4 : t_axi4_siso_arr(sel'range);
@@ -778,4 +766,3 @@ package body axi4_stream_pkg is
end func_axi4_stream_tkeep_to_dp_empty;
end axi4_stream_pkg;
-
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
index d2cdd4decc10e24aad39acc43317fe323e524f68..d4cc4a03ccb806bb9eec3cd9fd20759ea80e4d95 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_lite_mm_bridge.vhd
@@ -58,7 +58,6 @@ entity tb_axi4_lite_mm_bridge is
end tb_axi4_lite_mm_bridge;
architecture tb of tb_axi4_lite_mm_bridge is
-
constant c_mm_clk_period : time := 40 ns;
constant c_reset_len : natural := 4;
@@ -82,9 +81,7 @@ architecture tb of tb_axi4_lite_mm_bridge is
signal axi_copi : t_axi4_lite_copi;
signal axi_cipo : t_axi4_lite_cipo;
-
begin
-
mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * c_reset_len;
diff --git a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
index 6f715815a123ee22211be9af05f2e79d202887a6..ca7be826cff4b337bf5af9b2cbf58ae17568e978 100644
--- a/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_axi4_stream_dp_bridge.vhd
@@ -40,9 +40,7 @@ entity tb_axi4_stream_dp_bridge is
);
end tb_axi4_stream_dp_bridge;
-
architecture tb of tb_axi4_stream_dp_bridge is
-
-- TX ready latency to DUT chain
constant c_tx_void : natural := sel_a_b(g_dp_rl, 1, 0); -- used to avoid empty range VHDL warnings when g_dp_rl=0
@@ -114,9 +112,7 @@ architecture tb of tb_axi4_stream_dp_bridge is
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := sel_a_b(g_dp_rl = g_axi4_rl, TO_UVEC(18953, c_dp_data_w), TO_UVEC(19279, c_dp_data_w));
signal exp_empty : std_logic_vector(c_dp_stream_empty_w - 1 downto 0);
signal exp_channel : std_logic_vector(c_dp_channel_w - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -198,5 +194,4 @@ begin
out_val <= dut_out_sosi.valid;
out_sop <= dut_out_sosi.sop;
out_eop <= dut_out_sosi.eop;
-
end tb;
diff --git a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
index c1b95ec75746dacf73a9ea5eda7477df7d7039fb..28f6ea68f5fde2c46683b3d4ba106953bf33f54e 100644
--- a/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
+++ b/libraries/base/axi4/tb/vhdl/tb_tb_axi4_stream_dp_bridge.vhd
@@ -27,15 +27,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_axi4_stream_dp_bridge is
end tb_tb_axi4_stream_dp_bridge;
-
architecture tb of tb_tb_axi4_stream_dp_bridge is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 2
-- > run -all --> OK
@@ -46,5 +43,4 @@ begin
u_dp_1_axi4_1 : entity work.tb_axi4_stream_dp_bridge generic map (1, 1);
u_dp_0_axi4_0 : entity work.tb_axi4_stream_dp_bridge generic map (0, 0);
u_dp_0_axi4_1 : entity work.tb_axi4_stream_dp_bridge generic map (0, 1);
-
end tb;
diff --git a/libraries/base/common/src/vhdl/avs_common_mm.vhd b/libraries/base/common/src/vhdl/avs_common_mm.vhd
index fb5f3f1a7e5c5055b2d9bfeba4dde0fe693329ba..3739dffc6fb10c697d1d436f1579c27e7bb02644 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm.vhd
@@ -60,10 +60,8 @@ entity avs_common_mm is
);
end avs_common_mm;
-
architecture wrap of avs_common_mm is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -73,5 +71,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
index 297b27dc3a6a17ffe3805a60eb792b8fb8485840..1f9b9ac8d31a13d1c3507010069245c86a3f0cb6 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_irq.vhd
@@ -61,10 +61,8 @@ entity avs_common_mm_irq is
);
end avs_common_mm_irq;
-
architecture wrap of avs_common_mm_irq is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -76,5 +74,4 @@ begin
avs_mem_readdata <= coe_readdata_export;
ins_interrupt_irq <= coe_irq_export; -- can not use coe_interrupt_export as name, because *_interrupt_* is already the MM side name
-
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
index de9a302e223bab7eb2a352ff9f08bcfb841922a8..474b078567a7d8ecbae615e7da9c6b113fcd5064 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency0.vhd
@@ -61,10 +61,8 @@ entity avs_common_mm_readlatency0 is
);
end avs_common_mm_readlatency0;
-
architecture wrap of avs_common_mm_readlatency0 is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -75,5 +73,4 @@ begin
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
avs_mem_waitrequest <= coe_waitrequest_export;
-
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
index f88458d8594d7642b15c72c445fef0db4b35ce8a..a3cdecdfc319d2832ee3ab0f55d1f30e0a154953 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency2.vhd
@@ -58,10 +58,8 @@ entity avs_common_mm_readlatency2 is
);
end avs_common_mm_readlatency2;
-
architecture wrap of avs_common_mm_readlatency2 is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -71,5 +69,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd b/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
index 3d6d8a6cb4b3bc1ca5c3b922da78ae49adbc7d01..c07a16f315a1e24926a52571010dcebd847b7358 100644
--- a/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_mm_readlatency4.vhd
@@ -58,10 +58,8 @@ entity avs_common_mm_readlatency4 is
);
end avs_common_mm_readlatency4;
-
architecture wrap of avs_common_mm_readlatency4 is
begin
-
-- wires
coe_reset_export <= csi_system_reset;
coe_clk_export <= csi_system_clk;
@@ -71,5 +69,4 @@ begin
coe_writedata_export <= avs_mem_writedata;
coe_read_export <= avs_mem_read;
avs_mem_readdata <= coe_readdata_export;
-
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
index 72762cb6dc2947396ad6c57072f8a84dc7391f1d..bdf118db203240608da8269776a38fd9b01df640 100644
--- a/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_ram_crw_crw.vhd
@@ -21,7 +21,6 @@
-- (AVS Wrapper)
-
-- Derived from LOFAR cfg_single_reg
--
-- Usage:
@@ -31,7 +30,6 @@
-- 3) Leave out_reg OPEN for read only register.
-- 4) Connect wr_adr and rd_adr to have a shared address bus register.
-
library IEEE;
use IEEE.std_logic_1164.all;
use work.common_mem_pkg.all;
@@ -69,11 +67,8 @@ entity avs_common_ram_crw_crw is
end avs_common_ram_crw_crw;
architecture wrap of avs_common_ram_crw_crw is
-
constant c_avs_memrec : t_c_mem := (g_latency, g_adr_w, g_dat_w, g_nof_dat, g_init_sl);
-
begin
-
u_common_ram_crw_crw : entity work.common_ram_crw_crw
generic map(
g_ram => c_avs_memrec,
@@ -99,5 +94,4 @@ begin
rd_val_a => OPEN,
rd_val_b => coe_rd_val_export
);
-
end wrap;
diff --git a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
index 741bec45158b186848ee14040123c6bcae31c471..dda794990475e9aefaf176f3c733ca25536ea4f0 100644
--- a/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/avs_common_reg_r_w.vhd
@@ -21,7 +21,6 @@
-- (AVS Wrapper)
-
-- Derived from LOFAR cfg_single_reg
--
-- Usage:
@@ -31,7 +30,6 @@
-- 3) Leave out_reg OPEN for read only register.
-- 4) Connect wr_adr and rd_adr to have a shared address bus register.
-
library IEEE;
use IEEE.std_logic_1164.all;
use work.common_pkg.all;
@@ -64,11 +62,8 @@ entity avs_common_reg_r_w is
end avs_common_reg_r_w;
architecture wrap of avs_common_reg_r_w is
-
constant c_avs_memrec : t_c_mem := (g_latency, g_adr_w, g_dat_w, g_nof_dat, g_init_sl);
-
begin
-
common_reg_r_w : entity work.common_reg_r_w
generic map(
g_reg => c_avs_memrec,
@@ -90,5 +85,4 @@ begin
out_reg => coe_out_reg_export,
in_reg => coe_in_reg_export
);
-
end wrap;
diff --git a/libraries/base/common/src/vhdl/common_acapture.vhd b/libraries/base/common/src/vhdl/common_acapture.vhd
index ab606348035f2c9ceaf9d82e7e2987f389999438..cd7ccca147cefb9c3a43031cac01e9f006b9feb4 100644
--- a/libraries/base/common/src/vhdl/common_acapture.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture.vhd
@@ -57,13 +57,9 @@ entity common_acapture is
);
end;
-
architecture str of common_acapture is
-
signal i_in_cap : std_logic;
-
begin
-
in_cap <= i_in_cap;
-- pipeline input (all in input clock domain)
@@ -92,5 +88,4 @@ begin
din => i_in_cap,
dout => out_cap
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_acapture_slv.vhd b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
index c36ff806084586dae768d90bf54b30545789d8ea..04aa1970550e15f5ae0aececbf10ef805c9ac595 100644
--- a/libraries/base/common/src/vhdl/common_acapture_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_acapture_slv.vhd
@@ -45,14 +45,10 @@ entity common_acapture_slv is
);
end;
-
architecture str of common_acapture_slv is
-
-- Provide in_cap to be able to view timing between out_clk and in_cap in Wave window
signal in_cap : std_logic_vector(in_dat'range);
-
begin
-
gen_slv: for I in in_dat'range generate
u_acap : entity work.common_acapture
generic map (
diff --git a/libraries/base/common/src/vhdl/common_accumulate.vhd b/libraries/base/common/src/vhdl/common_accumulate.vhd
index f3a2fb991f5c9b8490041ff86782ce74f1bf9c7e..f891ae560a8572449a100e2decf05c2ba05d161f 100644
--- a/libraries/base/common/src/vhdl/common_accumulate.vhd
+++ b/libraries/base/common/src/vhdl/common_accumulate.vhd
@@ -45,15 +45,11 @@ entity common_accumulate is
);
end common_accumulate;
-
architecture rtl of common_accumulate is
-
constant c_acc_w : natural := out_dat'length;
signal result : std_logic_vector(c_acc_w - 1 downto 0);
-
begin
-
process(rst, clk)
begin
if rst = '1' then
@@ -81,5 +77,4 @@ begin
end process;
out_dat <= result;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_add_sub.vhd b/libraries/base/common/src/vhdl/common_add_sub.vhd
index 88f16152e03e5de27043be33c787e86108b0e205..62efa07c4d9682dbd8c1b8c7721ab17225a65af4 100644
--- a/libraries/base/common/src/vhdl/common_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_add_sub.vhd
@@ -43,7 +43,6 @@ entity common_add_sub is
end common_add_sub;
architecture str of common_add_sub is
-
constant c_res_w : natural := g_in_dat_w + 1;
signal in_a_p : std_logic_vector(in_a'range);
@@ -53,9 +52,7 @@ architecture str of common_add_sub is
signal sel_add_p : std_logic;
signal result_p : std_logic_vector(c_res_w - 1 downto 0);
-
begin
-
in_add <= '1' when g_direction = "ADD" or (g_direction = "BOTH" and sel_add = '1') else '0';
no_input_reg : if g_pipeline_input = 0 generate -- wired input
@@ -79,6 +76,7 @@ begin
gen_signed : if g_representation = "SIGNED" generate
result_p <= ADD_SVEC(in_a_p, in_b_p, c_res_w) when sel_add_p = '1' else SUB_SVEC(in_a_p, in_b_p, c_res_w);
end generate;
+
gen_unsigned : if g_representation = "UNSIGNED" generate
result_p <= ADD_UVEC(in_a_p, in_b_p, c_res_w) when sel_add_p = '1' else SUB_UVEC(in_a_p, in_b_p, c_res_w);
end generate;
@@ -96,5 +94,4 @@ begin
in_dat => result_p(result'range),
out_dat => result
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_add_symbol.vhd b/libraries/base/common/src/vhdl/common_add_symbol.vhd
index 9cc606cd2bad63f0b9a426a5b428c4acb64ba048..5472ab24a520321e4d79867d46b065d7c24ab83b 100644
--- a/libraries/base/common/src/vhdl/common_add_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_add_symbol.vhd
@@ -57,18 +57,14 @@ entity common_add_symbol is
);
end common_add_symbol;
-
architecture str of common_add_symbol is
-
type t_symbol_arr is array (integer range <>) of std_logic_vector(g_symbol_w - 1 downto 0);
signal in_a_arr : t_symbol_arr(g_nof_symbols - 1 downto 0);
signal in_b_arr : t_symbol_arr(g_nof_symbols - 1 downto 0);
signal sum_dat_arr : t_symbol_arr(g_nof_symbols - 1 downto 0);
signal sum_data : std_logic_vector(g_nof_symbols * g_symbol_w - 1 downto 0);
-
begin
-
gen_symbols : for I in g_nof_symbols - 1 downto 0 generate
-- map input vector to arr
in_a_arr(I) <= in_a((I + 1) * g_symbol_w - 1 downto I * g_symbol_w);
@@ -128,5 +124,4 @@ begin
in_dat => in_eop,
out_dat => out_eop
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_adder_staged.vhd b/libraries/base/common/src/vhdl/common_adder_staged.vhd
index a9ad2faf48a76c241e3c06f94529925458941cbc..fe3c110aa9c35162249b14efd8e3566f6c0e5ab4 100644
--- a/libraries/base/common/src/vhdl/common_adder_staged.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_staged.vhd
@@ -38,7 +38,6 @@ use common_lib.common_pkg.all;
-- . Synthesizing common_top.vhd shows that even a 64b adder can run at 500 MHz
-- on Stratix IV so this multi stage adder is not needed.
-
entity common_adder_staged is
generic (
g_dat_w : natural;
@@ -57,9 +56,7 @@ entity common_adder_staged is
);
end common_adder_staged;
-
architecture str of common_adder_staged is
-
constant c_pipeline : natural := g_pipeline_input + g_pipeline_output;
constant c_nof_adder : natural := g_dat_w / g_adder_w + sel_a_b(g_dat_w mod g_adder_w = 0, 0, 1);
@@ -84,9 +81,7 @@ architecture str of common_adder_staged is
-- Pipeline control signals, map to slv to be able to use common_pipeline
signal in_val_slv : std_logic_vector(0 downto 0);
signal out_val_slv : std_logic_vector(0 downto 0);
-
begin
-
assert not(g_pipeline_output < c_nof_adder and g_adder_w < g_dat_w)
report "common_adder_staged: internal adder width < output adder width is only possible for pipeline >= nof adder"
severity FAILURE;
@@ -156,7 +151,6 @@ begin
------------------------------------------------------------------------------
gen_multi : if g_pipeline_output >= c_nof_adder and g_adder_w < g_dat_w generate
-
-- resize input length to multiple of g_adder_w
vec_dat_a <= RESIZE_SVEC(reg_dat_a, c_nof_adder * g_adder_w);
vec_dat_b <= RESIZE_SVEC(reg_dat_b, c_nof_adder * g_adder_w);
@@ -232,7 +226,6 @@ begin
);
end generate;
-
------------------------------------------------------------------------------
-- Parallel output control pipeline
------------------------------------------------------------------------------
@@ -254,5 +247,4 @@ begin
in_val_slv(0) <= in_val;
out_val <= out_val_slv(0);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_adder_tree.vhd b/libraries/base/common/src/vhdl/common_adder_tree.vhd
index 067ef083022ed34fde48e9f38f3fee782e906115..7d95c7b027a51d4b8950a204350a2dfc3463bd16 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree.vhd
@@ -36,7 +36,6 @@ use IEEE.std_logic_1164.all;
-- for g_nof_inputs = 1 to match the bit growth of a parallel adder in the
-- same stage when g_nof_inputs is odd.
-
entity common_adder_tree is
generic (
g_representation : string := "SIGNED";
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
index 71fe3fb65cc4b0d4aae2602ce8fc70c3e8f496cf..ece19109a02fba5b375d21bd4325a91e3215ac31 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_recursive.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use work.common_pkg.all;
architecture recursive of common_adder_tree is
-
-- common_add_sub pipelining
constant c_pipeline_in : natural := 0;
constant c_pipeline_out : natural := g_pipeline;
@@ -75,9 +74,7 @@ architecture recursive of common_adder_tree is
signal sum_h2 : std_logic_vector(c_sum_h2_w - 1 downto 0);
signal result : std_logic_vector(c_sum_w - 1 downto 0);
-
begin
-
leaf_pipe : if g_nof_inputs = 1 generate
u_reg : entity work.common_pipeline
generic map (
@@ -183,5 +180,4 @@ begin
end generate;
sum <= RESIZE_SVEC(result, g_sum_w) when g_representation = "SIGNED" else RESIZE_UVEC(result, g_sum_w);
-
end recursive;
diff --git a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
index 3c98a1d554921ce8e2668f3c98fc88711f27ad85..579de011dc92e04ab491bea1fa48c23370b155f9 100644
--- a/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
+++ b/libraries/base/common/src/vhdl/common_adder_tree_a_str.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use work.common_pkg.all;
architecture str of common_adder_tree is
-
-- common_add_sub pipelining
constant c_pipeline_in : natural := 0;
constant c_pipeline_out : natural := g_pipeline;
@@ -52,9 +51,7 @@ architecture str of common_adder_tree is
type t_stage_arr is array (integer range <>) of std_logic_vector(c_N * c_sum_w - 1 downto 0);
signal adds : t_stage_arr(-1 to c_nof_stages - 1);
-
begin
-
-- The tabel below lists how many two port adders (+) and one port pipes (.)
-- to match the adder latency, there are at each stage of the adder tree.
--
diff --git a/libraries/base/common/src/vhdl/common_areset.vhd b/libraries/base/common/src/vhdl/common_areset.vhd
index 2430164b99078d0d50f17dfa4669fa4a991d3404..13c3a2454c660456b76f0b0f3bfc1d6da2f559bb 100644
--- a/libraries/base/common/src/vhdl/common_areset.vhd
+++ b/libraries/base/common/src/vhdl/common_areset.vhd
@@ -31,7 +31,6 @@
-- Remarks:
-- . The in_rst can also synchronise other signals than a reset, e.g. a locked signal from a PLL.
-
library IEEE;
use IEEE.std_logic_1164.all;
use work.common_pkg.all;
@@ -50,16 +49,12 @@ entity common_areset is
);
end;
-
architecture str of common_areset is
-
constant c_out_rst_level : std_logic := g_rst_level;
constant c_out_rst_level_n : std_logic := not g_rst_level;
signal i_rst : std_logic;
-
begin
-
i_rst <= in_rst when g_in_rst_level = '1' else not in_rst;
u_async : entity work.common_async
@@ -73,5 +68,4 @@ begin
din => c_out_rst_level_n,
dout => out_rst
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_async.vhd b/libraries/base/common/src/vhdl/common_async.vhd
index bbfe66d1103e2cb9b9b4f0b5dfbc3b42d98c1717..e4a037445b3ae691e19928183db6d9b16ceb4ab2 100644
--- a/libraries/base/common/src/vhdl/common_async.vhd
+++ b/libraries/base/common/src/vhdl/common_async.vhd
@@ -41,17 +41,13 @@ entity common_async is
);
end;
-
architecture rtl of common_async is
-
signal din_meta : std_logic_vector(0 to g_delay_len - 1) := (others => g_rst_level);
-- Synthesis constraint to ensure that register is kept in this instance region
attribute preserve : boolean;
attribute preserve of din_meta : signal is true;
-
begin
-
p_clk : process (rst, clk)
begin
if g_rising_edge = true then
@@ -72,5 +68,4 @@ begin
end process;
dout <= din_meta(din_meta'high);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_async_slv.vhd b/libraries/base/common/src/vhdl/common_async_slv.vhd
index a43771f1d991b6be271afb98d5900e6a53f471c2..1ff3d1454aa4e77e1fa5d8d5ecb3baf01b0638a1 100644
--- a/libraries/base/common/src/vhdl/common_async_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_async_slv.vhd
@@ -43,7 +43,6 @@ end;
architecture str of common_async_slv is
begin
-
gen_slv: for I in dout'range generate
u_common_async : entity work.common_async
generic map (
diff --git a/libraries/base/common/src/vhdl/common_bit_delay.vhd b/libraries/base/common/src/vhdl/common_bit_delay.vhd
index bb7cc3dc9511320322bf22d4a3e087b89a5817c2..2f3dc51f730b5771ed3e96042eddf0bd2008d950 100644
--- a/libraries/base/common/src/vhdl/common_bit_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_bit_delay.vhd
@@ -51,13 +51,10 @@ entity common_bit_delay is
end entity common_bit_delay;
architecture rtl of common_bit_delay is
-
-- Use index (0) as combinatorial input and index(1:g_depth) for the shift
-- delay, in this way the shift_reg type can support all g_depth >= 0
signal shift_reg : std_logic_vector(0 to g_depth) := (others => '0');
-
begin
-
shift_reg(0) <= in_bit;
out_bit <= shift_reg(g_depth);
@@ -76,5 +73,4 @@ begin
end if;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_blockreg.vhd b/libraries/base/common/src/vhdl/common_blockreg.vhd
index c850060bf08fa3c22b5efdd02584968d4da3ff71..dafbf3163e97e2d30a30e1a304fe6e60c2980d23 100755
--- a/libraries/base/common/src/vhdl/common_blockreg.vhd
+++ b/libraries/base/common/src/vhdl/common_blockreg.vhd
@@ -60,9 +60,7 @@ entity common_blockreg is
);
end common_blockreg;
-
architecture str of common_blockreg is
-
signal i_out_val : std_logic;
signal usedw : std_logic_vector(ceil_log2(g_block_size+1) - 1 downto 0);
@@ -71,16 +69,13 @@ architecture str of common_blockreg is
signal out_cnt : std_logic_vector(ceil_log2(g_block_size) - 1 downto 0);
signal nxt_out_cnt : std_logic_vector(ceil_log2(g_block_size) - 1 downto 0);
-
begin
-
gen_bypass: if g_block_size = 1 generate
out_dat <= in_dat;
out_val <= in_val;
end generate;
gen_block_out: if g_block_size > 1 generate
-
out_val <= i_out_val;
u_fifo : entity work.common_fifo_sc
diff --git a/libraries/base/common/src/vhdl/common_clip.vhd b/libraries/base/common/src/vhdl/common_clip.vhd
index 67bff34b13bed0297be2ee1b5af0bdd81f7b2f21..3f83c3d3a8f2e3619b68628d4eb50e844afd8fb4 100644
--- a/libraries/base/common/src/vhdl/common_clip.vhd
+++ b/libraries/base/common/src/vhdl/common_clip.vhd
@@ -53,9 +53,7 @@ entity common_clip is
);
end;
-
architecture rtl of common_clip is
-
constant c_s_full_scale_w : natural := g_full_scale'length + 1;
constant c_u_full_scale_w : natural := g_full_scale'length;
@@ -73,9 +71,7 @@ architecture rtl of common_clip is
signal pipe_in : std_logic_vector(c_dat_w downto 0);
signal pipe_out : std_logic_vector(c_dat_w downto 0);
-
begin
-
p_clip : process(in_dat, enable)
begin
nxt_clip_dat <= in_dat;
@@ -137,5 +133,4 @@ begin
out_ovr <= pipe_out(pipe_out'high);
out_dat <= pipe_out(pipe_out'high - 1 downto 0);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
index a95588c5d2d1f988d7539ac3b9f481209570f168..246e57815e02004d836e322758e8a0a0fa722060 100644
--- a/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_active_detector.vhd
@@ -44,9 +44,7 @@ entity common_clock_active_detector is
);
end common_clock_active_detector;
-
architecture str of common_clock_active_detector is
-
constant c_delay_len : natural := c_meta_delay_len;
constant c_dp_detect_period_w : natural := ceil_log2(g_dp_detect_period);
@@ -74,9 +72,7 @@ architecture str of common_clock_active_detector is
signal nxt_dp_clk_interval : std_logic_vector(c_dp_clk_cnt_w - 1 downto 0);
signal i_dp_in_clk_detected : std_logic;
signal nxt_dp_in_clk_detected : std_logic;
-
begin
-
u_common_counter_in_clk : entity work.common_counter
generic map (
g_width => g_in_period_w
@@ -154,5 +150,4 @@ begin
r_stable => dp_in_clk_stable,
r_stable_ack => dp_in_clk_stable_ack
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
index 5b0ac7e4a9bb2694aa7ed9493de63136f7b79aee..b44ac564c54ada7d1b705da5abfb70621982ca9f 100644
--- a/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
+++ b/libraries/base/common/src/vhdl/common_clock_phase_detector.vhd
@@ -113,9 +113,7 @@ entity common_clock_phase_detector is
);
end common_clock_phase_detector;
-
architecture str of common_clock_phase_detector is
-
constant c_period_len : natural := 2 * g_clk_factor;
constant c_delay_len : natural := ceil_div(g_meta_delay_len, c_period_len) * c_period_len + 1 + g_offset_delay_len; -- detect clock phase relation independent of g_meta_delay_len
@@ -128,9 +126,7 @@ architecture str of common_clock_phase_detector is
signal in_phs_dly : std_logic_vector(g_clk_factor - 1 downto 0);
signal phs_evt : std_logic;
signal nxt_phase_det : std_logic;
-
begin
-
-- Capture the in_clk in the clk domain
u_async : entity work.common_async
generic map (
@@ -149,6 +145,7 @@ begin
gen_r_wire : if g_rising_edge = true generate
in_phs <= in_phs_cap;
end generate;
+
gen_fr_reg : if g_rising_edge = false generate
in_phs <= g_phase_rst_level when rst = '1' else in_phs_cap when rising_edge(clk); -- get from f to r
end generate;
@@ -164,5 +161,4 @@ begin
nxt_phase_det <= not phs_evt;
phase <= in_phs;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
index a2b8f798479cfb1095a0502c6648a83127e9733d..51192d7b4cfa2b8384e059dc685887e0e1ea59d6 100644
--- a/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_add_sub.vhd
@@ -22,7 +22,6 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity common_complex_add_sub is
generic (
g_direction : string := "ADD"; -- or "SUB"
@@ -44,7 +43,6 @@ entity common_complex_add_sub is
);
end common_complex_add_sub;
-
architecture str of common_complex_add_sub is
begin
add_re : entity work.common_add_sub
diff --git a/libraries/base/common/src/vhdl/common_complex_round.vhd b/libraries/base/common/src/vhdl/common_complex_round.vhd
index 43a764a4a5db602052a60038f33d05bdcc5fd431..b365d78a728e29d04f4c6392d1368faa057cd1d2 100644
--- a/libraries/base/common/src/vhdl/common_complex_round.vhd
+++ b/libraries/base/common/src/vhdl/common_complex_round.vhd
@@ -42,10 +42,8 @@ entity common_complex_round is
);
end;
-
architecture str of common_complex_round is
begin
-
re: entity work.common_round
generic map (
g_representation => g_representation,
diff --git a/libraries/base/common/src/vhdl/common_components_pkg.vhd b/libraries/base/common/src/vhdl/common_components_pkg.vhd
index dd4a3306c8a524ccbcb57485db140ef6c111ec61..ba5e04a595382f2f4586cf619f49c9088b596572 100644
--- a/libraries/base/common/src/vhdl/common_components_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_components_pkg.vhd
@@ -29,7 +29,6 @@ use work.common_mem_pkg.all;
-- Remarks:
package common_components_pkg is
-
component common_pipeline is
generic (
g_representation : string := "SIGNED"; -- or "UNSIGNED"
@@ -68,6 +67,5 @@ package common_components_pkg is
end common_components_pkg;
-
package body common_components_pkg is
end common_components_pkg;
diff --git a/libraries/base/common/src/vhdl/common_counter.vhd b/libraries/base/common/src/vhdl/common_counter.vhd
index 904c0c3f3bb3e855535bd128eaa84aeebf78abe5..e5a449527e4e92286d1a16288bdd937d53aacd50 100644
--- a/libraries/base/common/src/vhdl/common_counter.vhd
+++ b/libraries/base/common/src/vhdl/common_counter.vhd
@@ -36,7 +36,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.common_pkg.all;
-
entity common_counter is
generic (
g_latency : natural := 1; -- default 1 for registered count output, use 0 for immediate combinatorial count output
@@ -60,15 +59,11 @@ entity common_counter is
);
end common_counter;
-
architecture rtl of common_counter is
-
signal reg_count : std_logic_vector(count'range) := TO_SVEC(g_init, g_width); -- in case rst is not used
signal nxt_count : std_logic_vector(count'range) := TO_SVEC(g_init, g_width); -- to avoid Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE, when using unsigned()
signal comb_count : std_logic_vector(count'range) := TO_SVEC(g_init, g_width); -- to avoid Warning: NUMERIC_STD.">=": metavalue detected, returning FALSE, when using unsigned()
-
begin
-
comb_count <= nxt_count;
count <= comb_count when g_latency = 0 else reg_count;
@@ -101,5 +96,4 @@ begin
nxt_count <= INCR_UVEC(reg_count, g_step_size);
end if;
end process;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
index 8f5ba4e07e65e886acc49c47c850984ffcc10ecf..a89e287f0db450947d3f56c963cfedf0de9b350d 100644
--- a/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/src/vhdl/common_create_strobes_from_valid.vhd
@@ -71,9 +71,7 @@ entity common_create_strobes_from_valid is
);
end common_create_strobes_from_valid;
-
architecture rtl of common_create_strobes_from_valid is
-
type t_state is record -- function state registers
val_cnt : natural range 0 to g_nof_clk_per_sync - 1;
blk_cnt : natural range 0 to g_nof_clk_per_block - 1;
@@ -94,9 +92,7 @@ architecture rtl of common_create_strobes_from_valid is
signal o : t_outputs := c_outputs_rst; -- zero latency outputs
signal p : t_outputs := c_outputs_rst; -- pipelined outputs
-
begin
-
-- p_state
q <= d when rising_edge(clk);
@@ -144,7 +140,6 @@ begin
-- Result
d <= v;
-
end process;
-- Output
@@ -156,5 +151,4 @@ begin
out_sync <= o.out_sync when g_pipeline = false else p.out_sync;
out_sync1 <= '0' when g_pipeline = false else o.out_sync;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_ddio_in.vhd b/libraries/base/common/src/vhdl/common_ddio_in.vhd
index ce2db6d1e634e34a45fd0955706a2e4bfcfd92b3..4a1e3e3d6ce1ceaa3c5293c857a6152c54fd22e1 100644
--- a/libraries/base/common/src/vhdl/common_ddio_in.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_in.vhd
@@ -40,10 +40,8 @@ entity common_ddio_in is
);
end common_ddio_in;
-
architecture str of common_ddio_in is
begin
-
u_ddio_in : entity tech_iobuf_lib.tech_iobuf_ddio_in
generic map (
g_technology => g_technology,
@@ -57,5 +55,4 @@ begin
out_dat_hi => out_dat_hi,
out_dat_lo => out_dat_lo
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddio_out.vhd b/libraries/base/common/src/vhdl/common_ddio_out.vhd
index e98e80cdeae47e4e38ad128f2f0f867ed6096400..1806830f51293749c4f2ae4e6e1ddfd79f16ce4a 100644
--- a/libraries/base/common/src/vhdl/common_ddio_out.vhd
+++ b/libraries/base/common/src/vhdl/common_ddio_out.vhd
@@ -40,10 +40,8 @@ entity common_ddio_out is
);
end common_ddio_out;
-
architecture str of common_ddio_out is
begin
-
u_ddio_out : entity tech_iobuf_lib.tech_iobuf_ddio_out
generic map (
g_technology => g_technology,
@@ -57,5 +55,4 @@ begin
in_dat_lo => in_dat_lo,
out_dat => out_dat
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_ddreg.vhd b/libraries/base/common/src/vhdl/common_ddreg.vhd
index db5716fb75ab27878d68a0660cfca35b42ffa1c3..74638cc7e16c677257c6e2b8b9d7b9690be4212e 100644
--- a/libraries/base/common/src/vhdl/common_ddreg.vhd
+++ b/libraries/base/common/src/vhdl/common_ddreg.vhd
@@ -88,14 +88,10 @@ entity common_ddreg_r is
);
end common_ddreg_r;
-
architecture str of common_ddreg_r is
-
signal in_dat_r : std_logic;
signal in_dat_d : std_logic;
-
begin
-
u_in : entity work.common_async
generic map (
g_delay_len => g_in_delay_len
@@ -122,7 +118,6 @@ begin
);
end str;
-
--------------------------------------------------------------------------------
-- common_ddreg_f
--------------------------------------------------------------------------------
@@ -146,14 +141,10 @@ entity common_ddreg_f is
);
end common_ddreg_f;
-
architecture str of common_ddreg_f is
-
signal in_dat_r : std_logic;
signal in_dat_d : std_logic;
-
begin
-
u_in : entity work.common_async
generic map (
g_delay_len => g_in_delay_len
@@ -179,10 +170,8 @@ begin
din => in_dat_d,
dout => out_dat_f
);
-
end str;
-
--------------------------------------------------------------------------------
-- common_ddreg_fr
--------------------------------------------------------------------------------
@@ -200,19 +189,13 @@ entity common_ddreg_fr is
);
end common_ddreg_fr;
-
architecture str of common_ddreg_fr is
-
signal in_dat_d : std_logic;
-
begin
-
in_dat_d <= in_dat_f when falling_edge(clk); -- input at falling edge
out_dat_r <= in_dat_d when rising_edge(clk); -- Output at rising edge
-
end str;
-
--------------------------------------------------------------------------------
-- common_ddreg
--------------------------------------------------------------------------------
@@ -238,13 +221,9 @@ entity common_ddreg is
);
end common_ddreg;
-
architecture str of common_ddreg is
-
signal out_dat_f : std_logic;
-
begin
-
-- out_dat_hi
u_ddreg_hi : entity work.common_ddreg_r
generic map (
diff --git a/libraries/base/common/src/vhdl/common_ddreg_slv.vhd b/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
index abcff1433b73329d56256eb778c418f389dcf547..3b8b40e132784aac1480b8d0e0fd7aa23629f713 100644
--- a/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
+++ b/libraries/base/common/src/vhdl/common_ddreg_slv.vhd
@@ -42,10 +42,8 @@ entity common_ddreg_slv is
);
end common_ddreg_slv;
-
architecture str of common_ddreg_slv is
begin
-
gen_slv: for I in in_dat'range generate
u_ddreg : entity work.common_ddreg
generic map (
diff --git a/libraries/base/common/src/vhdl/common_debounce.vhd b/libraries/base/common/src/vhdl/common_debounce.vhd
index 3029172fccfe28040b194dbca61207d712cb8f28..fa2d76a017ad2a9af1f4caed0cf0cf83ca0ab8d4 100644
--- a/libraries/base/common/src/vhdl/common_debounce.vhd
+++ b/libraries/base/common/src/vhdl/common_debounce.vhd
@@ -47,9 +47,7 @@ entity common_debounce is
);
end common_debounce;
-
architecture rtl of common_debounce is
-
constant c_latency_w : natural := ceil_log2(g_latency + 1);
signal cnt : std_logic_vector(c_latency_w - 1 downto 0); -- use cnt = g_latency to stop the counter
@@ -62,9 +60,7 @@ architecture rtl of common_debounce is
signal prev_d : std_logic := g_init_level;
signal i_q_out : std_logic := g_init_level;
signal nxt_q_out : std_logic;
-
begin
-
q_out <= i_q_out;
p_clk : process (rst, clk)
@@ -114,5 +110,4 @@ begin
cnt_en => cnt_en,
count => cnt
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_deinterleave.vhd b/libraries/base/common/src/vhdl/common_deinterleave.vhd
index 5926f3e5233e6c5d7bb1329a84b8e2973e62ad4e..50f29010351f5d58aa9581d8291645d8cba186ef 100644
--- a/libraries/base/common/src/vhdl/common_deinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_deinterleave.vhd
@@ -52,7 +52,6 @@ entity common_deinterleave is
end;
architecture rtl of common_deinterleave is
-
-----------------------------------------------------------------------------
-- Multiplexer input selection control
-----------------------------------------------------------------------------
@@ -68,9 +67,7 @@ architecture rtl of common_deinterleave is
constant c_demux_val_cnt_w : natural := ceil_log2(g_block_size+1);
signal demux_val_cnt : std_logic_vector(c_demux_val_cnt_w - 1 downto 0);
signal nxt_demux_val_cnt : std_logic_vector(c_demux_val_cnt_w - 1 downto 0);
-
begin
-
u_demux : entity work.common_demultiplexer
generic map (
g_nof_out => g_nof_out,
@@ -151,6 +148,4 @@ begin
);
end generate;
end generate;
-
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_delay.vhd b/libraries/base/common/src/vhdl/common_delay.vhd
index 20475a681d58150259afdd203a2086a4c6b420de..0e72b7574362dbdef1c24d911acd3d84a04258ce 100644
--- a/libraries/base/common/src/vhdl/common_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_delay.vhd
@@ -41,15 +41,12 @@ entity common_delay is
end entity common_delay;
architecture rtl of common_delay is
-
-- Use index (0) as combinatorial input and index(1:g_depth) for the shift
-- delay, in this way the t_dly_arr type can support all g_depth >= 0
type t_dly_arr is array (0 to g_depth) of std_logic_vector(g_dat_w - 1 downto 0);
signal shift_reg : t_dly_arr := (others => (others => '0'));
-
begin
-
shift_reg(0) <= in_dat;
out_dat <= shift_reg(g_depth);
@@ -64,5 +61,4 @@ begin
end if;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_demultiplexer.vhd b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
index 5de2f9c789787fd7b52430fd81e7f1d2fd9b0f73..52f37b9cd5be508a913914ed8705e79346678cc1 100644
--- a/libraries/base/common/src/vhdl/common_demultiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_demultiplexer.vhd
@@ -50,7 +50,6 @@ entity common_demultiplexer is
end;
architecture rtl of common_demultiplexer is
-
constant c_sel_w : natural := out_sel'length;
signal in_dat_reg : std_logic_vector(in_dat'range);
@@ -60,9 +59,7 @@ architecture rtl of common_demultiplexer is
signal sel_dat : std_logic_vector(g_nof_out * g_dat_w - 1 downto 0);
signal sel_val : std_logic_vector(g_nof_out - 1 downto 0);
-
begin
-
-- pipeline input
u_pipe_in_dat : common_pipeline generic map ("SIGNED", g_pipeline_in, 0, g_dat_w, g_dat_w) port map (rst, clk, '1', '0', '1', in_dat, in_dat_reg);
u_pipe_in_val : common_pipeline_sl generic map ( g_pipeline_in, 0, false) port map (rst, clk, '1', '0', '1', in_val, in_val_reg);
@@ -91,5 +88,4 @@ begin
-- pipeline output
u_pipe_out_dat : common_pipeline generic map ("SIGNED", g_pipeline_out, 0, g_nof_out * g_dat_w, g_nof_out * g_dat_w) port map (rst, clk, '1', '0', '1', sel_dat, out_dat);
u_pipe_out_val : common_pipeline generic map ("SIGNED", g_pipeline_out, 0, g_nof_out , g_nof_out ) port map (rst, clk, '1', '0', '1', sel_val, out_val);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_duty_cycle.vhd b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
index f5d7de3075fb8642601cde555ba3812567a87024..8c09e6292f07279763381f58bd8325d475a8520f 100644
--- a/libraries/base/common/src/vhdl/common_duty_cycle.vhd
+++ b/libraries/base/common/src/vhdl/common_duty_cycle.vhd
@@ -25,8 +25,6 @@
-- : :
-- :<-active->:
-
-
-- :<-s_idle->:<-----s_idle------>:
-- :__________: :_________
-- dc_out ____| |___________________| |________
@@ -61,7 +59,6 @@ entity common_duty_cycle is
end;
architecture rtl of common_duty_cycle is
-
constant c_cycle_cnt_w : natural := ceil_log2(g_per_cnt + 1);
type t_state_enum is (s_idle, s_assert, s_deassert);
@@ -73,9 +70,7 @@ architecture rtl of common_duty_cycle is
end record;
signal r, nxt_r : t_reg;
-
begin
-
p_comb : process(rst, dc_out_en, dc_per_cnt, dc_act_cnt, r)
variable v : t_reg;
begin
@@ -122,6 +117,4 @@ begin
end process;
dc_out <= r.dc_pulse when dc_out_en = '1' else g_dis_lvl when rst = '0' else g_rst_lvl;
-
end rtl;
-
diff --git a/libraries/base/common/src/vhdl/common_evt.vhd b/libraries/base/common/src/vhdl/common_evt.vhd
index ea7fef958b777da30fd4d92cbb43fbb71cbd2747..c4ad6d2bfd1d34bebf41b8a3b41fc5ccfa381303 100644
--- a/libraries/base/common/src/vhdl/common_evt.vhd
+++ b/libraries/base/common/src/vhdl/common_evt.vhd
@@ -38,15 +38,11 @@ entity common_evt is
);
end common_evt;
-
architecture rtl of common_evt is
-
signal in_sig_prev : std_logic := '0';
signal sig_evt : std_logic;
signal sig_evt_n : std_logic;
-
begin
-
-- Create previous in_sig
p_clk : process(rst, clk)
begin
@@ -84,5 +80,4 @@ begin
end if;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_fanout.vhd b/libraries/base/common/src/vhdl/common_fanout.vhd
index abe0e582cbdca8250b3c187afb2564eddf9b0a0d..77143e1487c43d7c0147c90824b0c54df06afb42 100644
--- a/libraries/base/common/src/vhdl/common_fanout.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout.vhd
@@ -49,11 +49,8 @@ entity common_fanout is
);
end common_fanout;
-
architecture str of common_fanout is
-
begin
-
gen_fanout : for i in g_nof_output - 1 downto 0 generate
u_pipe_en : entity work.common_pipeline_sl
generic map (
diff --git a/libraries/base/common/src/vhdl/common_fanout_tree.vhd b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
index 28fc5b496e43c34b814b020ac2240c9eb70a558c..d0dcc9ba25c5e0b9d486220db465275b95f96fe4 100644
--- a/libraries/base/common/src/vhdl/common_fanout_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_fanout_tree.vhd
@@ -99,7 +99,6 @@ entity common_fanout_tree is
end common_fanout_tree;
architecture str of common_fanout_tree is
-
constant c_nof_output : natural := g_nof_output_per_cell**g_nof_stages;
-- Define t_natural_arr range
@@ -112,9 +111,7 @@ architecture str of common_fanout_tree is
signal stage_en_vec_arr : t_stage_sl_vec_arr( -1 to g_nof_stages - 1) := (others => (others => '0'));
signal stage_val_vec_arr : t_stage_sl_vec_arr( -1 to g_nof_stages - 1) := (others => (others => '0'));
signal stage_dat_vec_arr : t_stage_dat_vec_arr(-1 to g_nof_stages - 1) := (others => (others => '0'));
-
begin
-
gen_tree : if g_nof_output > 1 generate
-- Input wires
stage_en_vec_arr( -1)(0) <= in_en;
diff --git a/libraries/base/common/src/vhdl/common_field_pkg.vhd b/libraries/base/common/src/vhdl/common_field_pkg.vhd
index bdf62486d904f06895e177df6a224a5059318d45..7f3d90b4ee7ab330bff244ff5f96f986c9824c87 100644
--- a/libraries/base/common/src/vhdl/common_field_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_field_pkg.vhd
@@ -39,9 +39,7 @@ use work.common_str_pkg.all;
-- . Field widths are variable
-- Remarks:
-
package common_field_pkg is
-
constant c_common_field_name_len : natural := 64;
constant c_common_field_default_len : natural := 256;
@@ -85,9 +83,7 @@ package common_field_pkg is
end common_field_pkg;
-
package body common_field_pkg is
-
function field_name_pad(name: string) return string is
begin
return pad(name, c_common_field_name_len, ' ');
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc.vhd b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
index 73e41b481f3b626a907e1c12db4377c31cadf88b..08ad5365defe15e0e22c3acc25a08d01082688be 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc.vhd
@@ -51,9 +51,7 @@ entity common_fifo_dc is
);
end common_fifo_dc;
-
architecture str of common_fifo_dc is
-
constant c_nof_words : natural := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
signal wr_rst : std_logic;
@@ -64,9 +62,7 @@ architecture str of common_fifo_dc is
signal emp : std_logic;
signal nxt_rd_val : std_logic;
-
begin
-
-- Control logic copied from LOFAR common_fifo_dc(virtex4).vhd
-- Need to make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf)
@@ -139,5 +135,4 @@ begin
);
proc_common_fifo_asserts("common_fifo_dc", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
index b98ceaf2bbe14238b262cffc6899d7c9efc06ee4..f94b9e105487bac831a533128a1ecf0bfb35e6b0 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_lock_control.vhd
@@ -101,9 +101,7 @@ entity common_fifo_dc_lock_control is
);
end common_fifo_dc_lock_control;
-
architecture rtl of common_fifo_dc_lock_control is
-
constant c_fifo_latency : natural := 10; -- large enough to ensure that the FIFO filling has started, but small enough such that the FIFO is not filled yet
constant c_fill_level_max : natural := 2**rd_usedw'length - 1;
@@ -130,9 +128,7 @@ architecture rtl of common_fifo_dc_lock_control is
signal fill_level : natural range 0 to c_fill_level_max;
signal nxt_fill_level : natural;
-
begin
-
dc_locked <= i_dc_locked;
p_rd_clk: process(rd_clk, rd_rst)
@@ -249,5 +245,4 @@ begin
r_stable => dc_stable,
r_stable_ack => dc_stable_ack
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
index 6290c8f0b57688fd612c7d0ac6c446df7ac0512f..32aaf05a36d63454b735525c1fa03e4e4248b8b4 100644
--- a/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_dc_mixed_widths.vhd
@@ -70,9 +70,7 @@ entity common_fifo_dc_mixed_widths is
);
end common_fifo_dc_mixed_widths;
-
architecture str of common_fifo_dc_mixed_widths is
-
constant c_nof_words : natural := 2**ceil_log2(g_nof_words); -- ensure size is power of 2 for dual clock FIFO
signal wr_rst : std_logic;
@@ -83,9 +81,7 @@ architecture str of common_fifo_dc_mixed_widths is
signal emp : std_logic;
signal nxt_rd_val : std_logic;
-
begin
-
-- Control logic copied from LOFAR common_fifo_dc(virtex4).vhd
-- Need to make sure the reset lasts at least 3 cycles (see fifo_generator_ug175.pdf).
@@ -156,5 +152,4 @@ begin
);
proc_common_fifo_asserts("common_fifo_dc_mixed_widths", g_note_is_ful, g_fail_rd_emp, wr_rst, wr_clk, ful, wr_en, rd_clk, emp, rd_en);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_fifo_rd.vhd b/libraries/base/common/src/vhdl/common_fifo_rd.vhd
index b977e8e0e4765f7f9c4ce4b7ba0d5271c7900685..25ec1cdeeb7cab0401ae200f71b7ac99550c8592 100644
--- a/libraries/base/common/src/vhdl/common_fifo_rd.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_rd.vhd
@@ -32,7 +32,6 @@ use work.common_pkg.all;
-- . There is no need for a rd_emp output signal, because a show ahead FIFO
-- will have rd_val='0' when it is empty.
-
entity common_fifo_rd is
generic (
g_dat_w : natural := 18
@@ -51,12 +50,8 @@ entity common_fifo_rd is
);
end common_fifo_rd;
-
architecture wrap of common_fifo_rd is
-
-
begin
-
u_rl0 : entity work.common_rl_decrease
generic map (
g_adapt => true,
@@ -74,5 +69,4 @@ begin
src_out_dat => rd_dat,
src_out_val => rd_val
);
-
end wrap;
diff --git a/libraries/base/common/src/vhdl/common_fifo_sc.vhd b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
index fed8be82f92cfd0534867d93395dceea4b88fe71..302f5c2225f88fc1a3bcc4abdbcfc0fd4951156d 100644
--- a/libraries/base/common/src/vhdl/common_fifo_sc.vhd
+++ b/libraries/base/common/src/vhdl/common_fifo_sc.vhd
@@ -55,9 +55,7 @@ entity common_fifo_sc is
);
end common_fifo_sc;
-
architecture str of common_fifo_sc is
-
constant c_use_eab : string := sel_a_b(g_use_lut, "OFF", "ON"); -- when g_use_lut=TRUE then force using LUTs via Altera eab="OFF", else default to ram_block_type = "AUTO"
constant c_fifo_af_latency : natural := 1; -- pipeline register wr_aful
@@ -76,9 +74,7 @@ architecture str of common_fifo_sc is
signal nxt_wr_aful : std_logic;
signal nxt_rd_val : std_logic;
-
begin
-
-- Control logic copied from common_fifo_sc(virtex4).vhd
gen_fifo_rst : if g_reset = true generate
@@ -95,6 +91,7 @@ begin
out_rst => fifo_rst
);
end generate;
+
no_fifo_rst : if g_reset = false generate
fifo_rst <= rst;
end generate;
@@ -125,6 +122,7 @@ begin
nxt_fifo_wr_dat <= wr_dat;
nxt_fifo_wr_en <= wr_req and not fifo_init; -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
end generate;
+
no_init : if g_init = false generate
fifo_wr_dat <= wr_dat;
fifo_wr_en <= wr_req; -- check on NOT full is not necessary according to fifo_generator_ug175.pdf
@@ -173,5 +171,4 @@ begin
);
proc_common_fifo_asserts("common_fifo_sc", g_note_is_ful, g_fail_rd_emp, fifo_rst, clk, fifo_full, fifo_wr_en, clk, fifo_empty, fifo_rd_en);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
index 8bc6d474dc11fd840c1be2f3f86a29af8cc38590..9eeeeaf25c53d7446fd40f8a5406a5a442f58b2f 100644
--- a/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
+++ b/libraries/base/common/src/vhdl/common_flank_to_pulse.vhd
@@ -32,13 +32,9 @@ entity common_flank_to_pulse is
);
end common_flank_to_pulse;
-
architecture str of common_flank_to_pulse is
-
signal flank_in_dly : std_logic;
-
begin
-
p_in_dly : process(rst, clk)
begin
if rst = '1' then
@@ -49,7 +45,4 @@ begin
end process;
pulse_out <= flank_in and not(flank_in_dly);
-
end str;
-
-
diff --git a/libraries/base/common/src/vhdl/common_frame_busy.vhd b/libraries/base/common/src/vhdl/common_frame_busy.vhd
index 00161c8b47d06afa7adb203e87a4ed42d6815688..6357f11447baea056b928859533a88bc5aee4781 100644
--- a/libraries/base/common/src/vhdl/common_frame_busy.vhd
+++ b/libraries/base/common/src/vhdl/common_frame_busy.vhd
@@ -40,15 +40,12 @@ entity common_frame_busy is
);
end common_frame_busy;
-
architecture str of common_frame_busy is
-
signal in_frm : std_logic;
signal nxt_in_frm : std_logic;
signal i_frame_busy : std_logic;
begin
-
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -65,5 +62,4 @@ begin
frame_busy <= i_frame_busy;
frame_idle <= not i_frame_busy;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_init.vhd b/libraries/base/common/src/vhdl/common_init.vhd
index 2028dcae21a181b77f9d141ddd87931500e39798..0dbfdf1c99393accdae15efcd5f7650ee4307150 100644
--- a/libraries/base/common/src/vhdl/common_init.vhd
+++ b/libraries/base/common/src/vhdl/common_init.vhd
@@ -51,9 +51,7 @@ entity common_init is
);
end;
-
architecture rtl of common_init is
-
signal cnt : std_logic_vector(g_latency_w downto 0); -- use cnt(g_latency_w) to stop the counter
signal cnt_en : std_logic;
signal prev_cnt_en : std_logic;
@@ -62,10 +60,7 @@ architecture rtl of common_init is
signal hold_reg : std_logic;
signal init_reg : std_logic;
signal nxt_init_reg : std_logic;
-
begin
-
-
p_clk : process (rst, clk)
begin
if rst = '1' then
@@ -98,5 +93,4 @@ begin
cnt_en => cnt_en,
count => cnt
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_inout.vhd b/libraries/base/common/src/vhdl/common_inout.vhd
index 7dd8551283657a3205150c397a50462c4478b35f..ba4efdbf26440dd4fc149816a28fd4c1247db5e9 100644
--- a/libraries/base/common/src/vhdl/common_inout.vhd
+++ b/libraries/base/common/src/vhdl/common_inout.vhd
@@ -33,13 +33,9 @@ entity common_inout is
);
end common_inout;
-
architecture rtl of common_inout is
-
begin
-
dat_inout <= 'Z' when dat_out_en = '0' else dat_out_to_line;
dat_in_from_line <= not (not dat_inout); -- do via NOT(NOT) for simulation to force 'H' -> '1' and 'L' --> '0'
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_int2float.vhd b/libraries/base/common/src/vhdl/common_int2float.vhd
index 4f66730799522dc1f7523b20e62a1f0f2d5e8935..2bcf2c8ee4500fd42d78192f0f1140ec4697de3a 100644
--- a/libraries/base/common/src/vhdl/common_int2float.vhd
+++ b/libraries/base/common/src/vhdl/common_int2float.vhd
@@ -59,15 +59,11 @@ entity common_int2float is
);
end common_int2float;
-
architecture rtl of common_int2float is
-
signal reg_dat : std_logic_vector(in_dat'range);
signal nxt_reg_dat : std_logic_vector(in_dat'range);
signal nxt_out_dat : std_logic_vector(out_dat'range);
-
begin
-
-- registers
gen_reg_input : if g_pipeline = 2 generate
p_reg_input : process(clk)
@@ -79,9 +75,11 @@ begin
end if;
end process;
end generate;
+
no_reg_input : if g_pipeline = 1 generate
reg_dat <= in_dat;
end generate;
+
assert g_pipeline = 1 or g_pipeline = 2
report "common_int2float: pipeline value not supported"
severity FAILURE;
@@ -110,5 +108,4 @@ begin
end if;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
index 00926e2bcd2663db3964f5b4b5036e106a033474..42890418c20ba63f325edd89b045fcd291aed20f 100644
--- a/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_interface_layers_pkg.vhd
@@ -25,7 +25,6 @@ use common_lib.common_pkg.all;
use IEEE.numeric_std.all;
package common_interface_layers_pkg is
-
------------------------------------------------------------------------------
-- XAUI
------------------------------------------------------------------------------
@@ -62,11 +61,9 @@ package common_interface_layers_pkg is
type t_xgmii_dc_arr is array(integer range <>) of std_logic_vector(c_xgmii_w - 1 downto 0);
type t_xgmii_d_arr is array(integer range <>) of std_logic_vector(c_xgmii_data_w - 1 downto 0);
type t_xgmii_c_arr is array(integer range <>) of std_logic_vector(c_xgmii_nof_lanes - 1 downto 0);
-
end common_interface_layers_pkg;
package body common_interface_layers_pkg is
-
-- Refer to the 10GBASE-R PHY IP Core section of the Altera Transceiver PHY IP Core User Guide
-- (November 2011) page 3-11: SDR XGMII Tx Interface for the proper mapping.
@@ -151,4 +148,3 @@ package body common_interface_layers_pkg is
end;
end common_interface_layers_pkg;
-
diff --git a/libraries/base/common/src/vhdl/common_interleave.vhd b/libraries/base/common/src/vhdl/common_interleave.vhd
index 6b2cb0e6bd3a6129287296837dd350bf46a4f690..11645c0f290e5b3c585ee51f7c6fb72b080e4210 100644
--- a/libraries/base/common/src/vhdl/common_interleave.vhd
+++ b/libraries/base/common/src/vhdl/common_interleave.vhd
@@ -54,7 +54,6 @@ entity common_interleave is
end;
architecture rtl of common_interleave is
-
type t_dat_arr is array (integer range <>) of std_logic_vector(g_dat_w - 1 downto 0);
type t_val_arr is array (integer range <>) of std_logic;
@@ -98,9 +97,7 @@ architecture rtl of common_interleave is
signal mux_in_val : std_logic;
signal nxt_mux_in_val : std_logic;
-
begin
-
-----------------------------------------------------------------------------
-- Wire SLV -> Array
-----------------------------------------------------------------------------
@@ -155,7 +152,6 @@ begin
in_dat => slv(bkr_out_val_arr(i)),
sl(out_dat) => piped_bkr_out_val_arr(i)
);
-
end generate;
-----------------------------------------------------------------------------
@@ -231,5 +227,4 @@ begin
mux_val_cnt <= nxt_mux_val_cnt;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_interval_monitor.vhd b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
index be26be9693b00717976bcc8c1a6ab24c113a6457..0056a8bce9da6f6ed79166ed515bd0f4f0373d4e 100644
--- a/libraries/base/common/src/vhdl/common_interval_monitor.vhd
+++ b/libraries/base/common/src/vhdl/common_interval_monitor.vhd
@@ -46,16 +46,12 @@ entity common_interval_monitor is
);
end common_interval_monitor;
-
architecture rtl of common_interval_monitor is
-
signal i_clk_cnt : std_logic_vector(interval_cnt'range);
signal nxt_clk_cnt : std_logic_vector(interval_cnt'range);
signal i_interval_cnt : std_logic_vector(interval_cnt'range);
signal nxt_interval_cnt : std_logic_vector(interval_cnt'range);
-
begin
-
interval_cnt <= i_interval_cnt;
clk_cnt <= i_clk_cnt;
@@ -88,5 +84,4 @@ begin
nxt_clk_cnt <= INCR_UVEC(i_clk_cnt, 1);
end if;
end process;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_led_controller.vhd b/libraries/base/common/src/vhdl/common_led_controller.vhd
index 145a4047130c1415143e9a2f78bb99caaf506519..b0d2adbb0ec2383dad7d4deeb1e30d69849942ba 100644
--- a/libraries/base/common/src/vhdl/common_led_controller.vhd
+++ b/libraries/base/common/src/vhdl/common_led_controller.vhd
@@ -52,9 +52,7 @@ entity common_led_controller is
);
end common_led_controller;
-
architecture rtl of common_led_controller is
-
type t_state is (s_idle, s_off, s_on);
signal state : t_state;
@@ -68,9 +66,7 @@ architecture rtl of common_led_controller is
signal nxt_cnt : natural;
signal nxt_led : std_logic;
-
begin
-
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -126,5 +122,4 @@ begin
end case;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
index 6e8d384cd4920a37ef705067d33fd17a39c89189..3f11c037e9a5958791241439b19654ea710b8fff 100644
--- a/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_lfsr_sequences_pkg.vhd
@@ -35,7 +35,6 @@ use IEEE.numeric_std.all;
use work.common_pkg.all;
package common_lfsr_sequences_pkg is
-
constant c_common_lfsr_max_nof_feedbacks : natural := 6;
constant c_common_lfsr_first : natural := 1; -- also support n = 1 and 2 in addition to n >= 3
@@ -125,7 +124,6 @@ package common_lfsr_sequences_pkg is
(0,0,0,0, 71,65 ), -- 71
(0,0, 72,66,25,19)); -- 72
-
-- Procedure for calculating the next PSRG and COUNTER sequence value
procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
constant g_incr : in integer;
@@ -142,12 +140,9 @@ package common_lfsr_sequences_pkg is
-- . initialized lfsr with (OTHERS=>'0')
-- . use lfsr(lfsr'HIGH) as random bit
function func_common_random(lfsr : std_logic_vector) return std_logic_vector;
-
end common_lfsr_sequences_pkg;
-
package body common_lfsr_sequences_pkg is
-
procedure common_lfsr_nxt_seq(constant c_lfsr_nr : in natural;
constant g_incr : in integer;
in_en : in std_logic;
@@ -173,6 +168,7 @@ package body common_lfsr_sequences_pkg is
if c_common_lfsr_sequences(c_lfsr_nr)(I) /= 0 then
v_feedback := v_feedback xor prsg(c_common_lfsr_sequences(c_lfsr_nr)(I) - 1);
end if;
+
end loop;
nxt_prsg(0) <= not v_feedback;
diff --git a/libraries/base/common/src/vhdl/common_math_pkg.vhd b/libraries/base/common/src/vhdl/common_math_pkg.vhd
index 36c466055611dd9186ca5cb9ff493d480d2191b8..2dfec614b7bf5b0c4097f7f3de7a92e5be8ff8a0 100644
--- a/libraries/base/common/src/vhdl/common_math_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_math_pkg.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2017
@@ -39,7 +38,6 @@ use work.common_pkg.all;
use work.common_lfsr_sequences_pkg.all;
package common_math_pkg is
-
-- Function to create the cos/sin lookup table with amplitude, frequency and phase
-- . N is number of samples in the lookup table, [0:N-1] = [0:N> = [0:2pi*FREQ>
-- . +round(ampl) is the maximum integer value and -round(ampl) the minimum integer value
@@ -81,13 +79,9 @@ package common_math_pkg is
function common_math_create_look_up_table_phasor(N, W : positive; AMPL, FREQ, PHI : real) return t_slv_32_arr; -- range 0 TO N-1
function common_math_create_random_arr(N, W : positive; seed : natural) return t_integer_arr;
-
-
end common_math_pkg;
-
package body common_math_pkg is
-
function common_math_create_look_up_table_cos(N : positive; AMPL, FREQ, PHI : real) return t_nat_integer_arr is
variable v_table : t_nat_integer_arr(N - 1 downto 0);
variable v_angle : real;
@@ -97,6 +91,7 @@ package body common_math_pkg is
v_angle := (MATH_2_PI * FREQ * real(I) / real(N) + PHI) mod MATH_2_PI;
v_table(I) := integer(ROUND(AMPL * COS(v_angle)));
end loop;
+
return v_table;
end;
@@ -193,6 +188,4 @@ package body common_math_pkg is
return v_rand_arr;
end;
-
end common_math_pkg;
-
diff --git a/libraries/base/common/src/vhdl/common_mem_demux.vhd b/libraries/base/common/src/vhdl/common_mem_demux.vhd
index 200a1d56202b2c2f59848b70c8a0284ee7c79472..26692341887b313712ead728d2c962313facef82 100644
--- a/libraries/base/common/src/vhdl/common_mem_demux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_demux.vhd
@@ -49,7 +49,6 @@
--
-------------------------------------------------------------------------------
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -71,16 +70,13 @@ entity common_mem_demux is
end common_mem_demux;
architecture rtl of common_mem_demux is
-
constant c_index_w : natural := ceil_log2(g_nof_mosi);
constant c_total_addr_w : natural := c_index_w + g_mult_addr_w;
signal index_arr : t_natural_arr(0 to g_rd_latency);
signal index_rw : natural; -- read or write access
signal index_rd : natural; -- read response
-
begin
-
gen_single : if g_nof_mosi = 1 generate
mosi <= mosi_arr(0);
miso_arr(0) <= miso;
@@ -123,5 +119,4 @@ begin
miso_arr(index_rd) <= miso;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_mem_mux.vhd b/libraries/base/common/src/vhdl/common_mem_mux.vhd
index 59b667360e9115dfa5d4a86c1be2ade64b1b94f9..17b494471e212fc87aba6ec98cc93e3f892d930f 100644
--- a/libraries/base/common/src/vhdl/common_mem_mux.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_mux.vhd
@@ -56,7 +56,6 @@
--
-------------------------------------------------------------------------------
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -79,16 +78,13 @@ entity common_mem_mux is
end common_mem_mux;
architecture rtl of common_mem_mux is
-
constant c_index_w : natural := ceil_log2(g_nof_mosi);
constant c_total_addr_w : natural := c_index_w + g_mult_addr_w;
signal index_arr : t_natural_arr(0 to g_rd_latency);
signal index_rw : natural; -- read or write access
signal index_rd : natural; -- read response
-
begin
-
gen_single : if g_broadcast = false and g_nof_mosi = 1 generate
mosi_arr(0) <= mosi;
miso <= miso_arr(0);
diff --git a/libraries/base/common/src/vhdl/common_mem_pkg.vhd b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
index 728550b3880eaa13d56523a5fa7f69bc04cf0ee2..9f035bdfd442ab3c23d9086666076bdfbb92b927 100644
--- a/libraries/base/common/src/vhdl/common_mem_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_mem_pkg.vhd
@@ -53,7 +53,6 @@ use IEEE.numeric_std.all;
use work.common_pkg.all;
package common_mem_pkg is
-
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
constant c_mem_address_w : natural := 32; -- address range (suits 32-bit processor)
constant c_mem_data_w : natural := 72; -- data width (suit up to 8 bytes, that can also be 9 bit bytes)
@@ -165,7 +164,6 @@ package common_mem_pkg is
type t_mem_ctlr_miso_arr is array (integer range <>) of t_mem_ctlr_miso;
type t_mem_ctlr_mosi_arr is array (integer range <>) of t_mem_ctlr_mosi;
-
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_ctlr_miso or t_mem_ctlr_mosi field width
function TO_MEM_CTLR_ADDRESS( n : integer) return std_logic_vector; -- unsigned, use integer to support 32 bit range
function TO_MEM_CTLR_DATA( n : integer) return std_logic_vector; -- unsigned
@@ -175,7 +173,6 @@ package common_mem_pkg is
function RESIZE_MEM_CTLR_DATA( vec : std_logic_vector) return std_logic_vector; -- unsigned
function RESIZE_MEM_CTLR_BURSTSIZE(vec : std_logic_vector) return std_logic_vector; -- unsigned
-
------------------------------------------------------------------------------
-- RAM block memory and MM register defintions
------------------------------------------------------------------------------
@@ -196,7 +193,6 @@ package common_mem_pkg is
constant c_mem_reg_init_w : natural := 1 * 256 * 32; -- >= largest expected value of dat_w*nof_dat (256 * 32 bit = 1k byte)
-
------------------------------------------------------------------------------
-- Functions to swap endianess
------------------------------------------------------------------------------
@@ -206,7 +202,6 @@ package common_mem_pkg is
end common_mem_pkg;
package body common_mem_pkg is
-
-- Reset only the control fields of the MM record
function RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) return t_mem_mosi is
variable v_mosi : t_mem_mosi := mosi;
@@ -357,7 +352,6 @@ package body common_mem_pkg is
return RESIZE_UVEC(vec, c_mem_ctlr_burstsize_w);
end RESIZE_MEM_CTLR_BURSTSIZE;
-
-- Functions to swap endianess
function func_mem_swap_endianess(mm : t_mem_miso; sz : natural) return t_mem_miso is
variable v_mm : t_mem_miso;
diff --git a/libraries/base/common/src/vhdl/common_multiplexer.vhd b/libraries/base/common/src/vhdl/common_multiplexer.vhd
index 5dd92bd24a2d9f0715084b8c154c79562737a53a..b93832dae068851bc8936653675248c181a0aceb 100644
--- a/libraries/base/common/src/vhdl/common_multiplexer.vhd
+++ b/libraries/base/common/src/vhdl/common_multiplexer.vhd
@@ -48,9 +48,7 @@ entity common_multiplexer is
end;
architecture str of common_multiplexer is
-
begin
-
u_select_symbol : entity work.common_select_symbol
generic map (
g_pipeline_in => g_pipeline_in,
@@ -71,5 +69,4 @@ begin
out_symbol => out_dat,
out_val => out_val
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
index d713e18b3d53f6069cfb908ffd497d2608071dca..904b55d3dfea5b58117775a3e898fc8e8f8bc44d 100644
--- a/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_layers_pkg.vhd
@@ -29,7 +29,6 @@ use work.common_pkg.all;
use work.common_field_pkg.all;
package common_network_layers_pkg is
-
-- All *_len constants are in nof octets = nof bytes = c_8 bits
------------------------------------------------------------------------------
@@ -358,12 +357,9 @@ package common_network_layers_pkg is
function func_network_ip_header_checksum(field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector;
-
end common_network_layers_pkg;
-
package body common_network_layers_pkg is
-
function func_network_ip_header_checksum(field_arr : t_common_field_arr; hdr_fields_slv : std_logic_vector) return std_logic_vector is
-- function to calculate the ip header checksum based on a header field array.
constant c_cin_w : natural := 4; -- bit width of carry
diff --git a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
index fde102c9ecacd9c3e36c4968336a23632ed37580..32587a2affb491938595856dac431fd419cf9822 100644
--- a/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_network_total_header_pkg.vhd
@@ -56,7 +56,6 @@ use work.common_pkg.all;
use work.common_network_layers_pkg.all;
package common_network_total_header_pkg is
-
-- Define total network header that fits all relevant packets in common_network_layers_pkg, because they have the same total header length
constant c_network_total_header_arp_len : natural := c_network_eth_header_len + c_network_arp_data_len; -- = 14 + 28 = 42
constant c_network_total_header_icmp_len : natural := c_network_eth_header_len + c_network_ip_header_len + c_network_icmp_header_len; -- = 14 + 20 + 8 = 42
@@ -279,14 +278,9 @@ package common_network_total_header_pkg is
function func_network_total_header_no_align_response_udp( udp_arr : t_network_total_header_32b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr;
function func_network_total_header_no_align_response_udp( udp_arr : t_network_total_header_64b_arr; mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_64b_arr;
-
-
-
end common_network_total_header_pkg;
-
package body common_network_total_header_pkg is
-
-- Assume the total header has been padded with the word align field to have the udp payload at a 32b or 64b boundary
-- Map the 11 32b words or 6 64b longwords from the total header to the header field records
@@ -884,8 +878,6 @@ package body common_network_total_header_pkg is
return v_response;
end;
-
-
-- Construct the response headers for headers without word align padding
function func_network_total_header_no_align_response_eth(eth_arr : t_network_total_header_32b_arr;
mac_addr : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0)) return t_network_total_header_32b_arr is
@@ -1050,7 +1042,4 @@ package body common_network_total_header_pkg is
return v_response;
end;
-
-
-
end common_network_total_header_pkg;
diff --git a/libraries/base/common/src/vhdl/common_operation.vhd b/libraries/base/common/src/vhdl/common_operation.vhd
index 7eb620884ed62a2a1844e03f3e115a4c1a68dee7..d807bdcd3ff29a5a83b4e57ebeeb343a42b91753 100644
--- a/libraries/base/common/src/vhdl/common_operation.vhd
+++ b/libraries/base/common/src/vhdl/common_operation.vhd
@@ -43,9 +43,7 @@ entity common_operation is
);
end common_operation;
-
architecture rtl of common_operation is
-
function func_default(operation, representation : string; w : natural) return std_logic_vector is
constant c_smin : std_logic_vector(w - 1 downto 0) := '1' & c_slv0(w - 2 downto 0);
constant c_umin : std_logic_vector(w - 1 downto 0) := c_slv0(w - 1 downto 0);
@@ -82,9 +80,7 @@ architecture rtl of common_operation is
signal a : std_logic_vector(g_dat_w - 1 downto 0);
signal b : std_logic_vector(g_dat_w - 1 downto 0);
signal nxt_result : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
nxt_a <= in_a when in_en_a = '1' else func_default(g_operation, g_representation, g_dat_w);
nxt_b <= in_b when in_en_b = '1' else func_default(g_operation, g_representation, g_dat_w);
@@ -119,5 +115,4 @@ begin
in_dat => nxt_result,
out_dat => result
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_operation_tree.vhd b/libraries/base/common/src/vhdl/common_operation_tree.vhd
index ffdac00b13cc0f72c161f2de7759167ba6645a44..0ad7a72e6a505ae3d16858522dab7aae34254de7 100644
--- a/libraries/base/common/src/vhdl/common_operation_tree.vhd
+++ b/libraries/base/common/src/vhdl/common_operation_tree.vhd
@@ -59,7 +59,6 @@ entity common_operation_tree is
end common_operation_tree;
architecture str of common_operation_tree is
-
-- operation pipelining
constant c_pipeline_in : natural := 0;
constant c_pipeline_out : natural := g_pipeline;
@@ -74,9 +73,7 @@ architecture str of common_operation_tree is
signal stage_arr : t_stage_arr(-1 to c_nof_stages - 1) := (others => (others => '0'));
signal stage_en_arr : t_stage_en_arr(-1 to c_nof_stages - 1) := (others => (others => '1'));
-
begin
-
gen_tree : if g_nof_inputs > 1 generate
-- Input wires
stage_arr(-1) <= in_data_vec;
@@ -106,11 +103,9 @@ begin
-- In case two adjacent inputs are disbaled, the result of their operation should be disabled in the next stage as well.
-- Therfor a logic OR creates the stage_en vector for the next stage.
stage_en_arr(j)(i) <= stage_en_arr(j - 1)(2 * i) or stage_en_arr(j - 1)(2 * i + 1);
-
end generate;
gen_pipe : if ((c_N + (2**j) - 1) / (2**j)) mod 2 /= 0 generate
-
-- In case of an odd number of inputs the enable of the last input should ripple through
-- to the place where the data is connected to a common_operation block.
stage_en_arr(j)(c_N / (2**(j + 1))) <= in_en_vec(g_nof_inputs - 1);
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index a8b67ad0fd740551c3db29a3f1654b58ee8b88f4..4bc889b7fe958710a094a72551dec6fe230a54ea 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -78,9 +78,7 @@ entity common_paged_ram_crw_crw is
);
end common_paged_ram_crw_crw;
-
architecture rtl of common_paged_ram_crw_crw is
-
type t_page_sel_arr is array (integer range <>) of natural range 0 to g_nof_pages - 1;
constant c_page_addr_w : natural := ceil_log2(g_page_sz);
@@ -158,9 +156,7 @@ architecture rtl of common_paged_ram_crw_crw is
-- g_str = "use_ofs" :
signal buf_adr_a : std_logic_vector(c_buf_addr_w - 1 downto 0);
signal buf_adr_b : std_logic_vector(c_buf_addr_w - 1 downto 0);
-
begin
-
-- page select (for all) and page address offset (for use_ofs)
p_reg_a : process (rst_a, clk_a)
begin
@@ -223,7 +219,6 @@ begin
end if;
end process;
-
gen_mux : if g_str = "use_mux" generate
gen_pages : for I in 0 to g_nof_pages - 1 generate
u_ram : entity work.common_ram_crw_crw
@@ -309,7 +304,6 @@ begin
mem_adr_b <= TO_UVEC(page_sel_b, c_mem_nof_pages_w) & adr_b;
end generate; -- gen_adr
-
gen_ofs : if g_str = "use_ofs" generate
u_buf : entity work.common_ram_crw_crw
generic map (
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
index ec36a9d874df834235eb10e2a1e08dd0b960d951..254a426c535fa4f92dbcb191a1fb9a21c1e7ecb5 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_r_w.vhd
@@ -59,11 +59,8 @@ entity common_paged_ram_r_w is
);
end common_paged_ram_r_w;
-
architecture str of common_paged_ram_r_w is
-
begin
-
u_rw_rw : entity work.common_paged_ram_rw_rw
generic map (
g_technology => g_technology,
@@ -95,5 +92,4 @@ begin
rd_dat_b => rd_dat,
rd_val_b => rd_val
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
index 425c99ae71efd749904f67aacba7ed06ff3c8bb5..22dc9992af4ac0225fe7caa13e1f6f108312a1b3 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
@@ -65,11 +65,8 @@ entity common_paged_ram_rw_rw is
);
end common_paged_ram_rw_rw;
-
architecture str of common_paged_ram_rw_rw is
-
begin
-
u_crw_crw : entity work.common_paged_ram_crw_crw
generic map (
g_technology => g_technology,
@@ -104,5 +101,4 @@ begin
rd_dat_b => rd_dat_b,
rd_val_b => rd_val_b
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
index 01e3a408e3d0814718889a51ba1819c46b0000e0..4c253131235954b6e58b1a55d0afa6eb6a4f19ec 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_w_rr.vhd
@@ -62,11 +62,8 @@ entity common_paged_ram_w_rr is
);
end common_paged_ram_w_rr;
-
architecture str of common_paged_ram_w_rr is
-
begin
-
u_ww_rr : entity work.common_paged_ram_ww_rr
generic map (
g_technology => g_technology,
@@ -97,5 +94,4 @@ begin
rd_dat_b => rd_dat_b,
rd_val_b => rd_val_b
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
index 02889f16454e757f687f9e6e5e72220ca2d30935..8a0e60be2e9fc87e21176f90504d5e47ff4fd7d8 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_ww_rr.vhd
@@ -67,9 +67,7 @@ entity common_paged_ram_ww_rr is
);
end common_paged_ram_ww_rr;
-
architecture rtl of common_paged_ram_ww_rr is
-
constant c_sel_latency : natural := g_pipeline_in + g_ram_rd_latency;
constant c_rd_latency : natural := g_pipeline_in + g_ram_rd_latency + g_pipeline_out;
@@ -124,9 +122,7 @@ architecture rtl of common_paged_ram_ww_rr is
signal nxt_rd_val_a : std_logic;
signal nxt_rd_dat_b : std_logic_vector(g_data_w - 1 downto 0);
signal nxt_rd_val_b : std_logic;
-
begin
-
-- page select
p_reg : process (rst, clk)
begin
@@ -216,5 +212,4 @@ begin
u_pipe_rd_dat_b : common_pipeline generic map ("SIGNED", g_pipeline_out, 0, g_data_w, g_data_w) port map (rst, clk, clken, '0', '1', nxt_rd_dat_b, rd_dat_b);
u_pipe_rd_val_a : common_pipeline_sl generic map ( g_pipeline_out, 0, false) port map (rst, clk, clken, '0', '1', nxt_rd_val_a, rd_val_a);
u_pipe_rd_val_b : common_pipeline_sl generic map ( g_pipeline_out, 0, false) port map (rst, clk, clken, '0', '1', nxt_rd_val_b, rd_val_b);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_paged_reg.vhd b/libraries/base/common/src/vhdl/common_paged_reg.vhd
index bfb3cc4aeb6ba25e3392f655515b425acab91e40..1e02358fc6f748f42a4df1a020cf466479a27893 100644
--- a/libraries/base/common/src/vhdl/common_paged_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_reg.vhd
@@ -44,15 +44,11 @@ entity common_paged_reg is
);
end common_paged_reg;
-
architecture str of common_paged_reg is
-
type t_data is array (natural range <>) of std_logic_vector(out_dat'range);
signal reg_dat : t_data(g_nof_pages downto 0) := (others => (others => '0'));
-
begin
-
-- Wire input to first page and last page to output
reg_dat(g_nof_pages) <= wr_dat;
out_dat <= reg_dat(0);
diff --git a/libraries/base/common/src/vhdl/common_peak.vhd b/libraries/base/common/src/vhdl/common_peak.vhd
index 1765183b3309e4f04cf259822d622939bdac36b4..0e71cf50f5c2e11aad3e36c8b8879bcfe664f825 100644
--- a/libraries/base/common/src/vhdl/common_peak.vhd
+++ b/libraries/base/common/src/vhdl/common_peak.vhd
@@ -47,20 +47,16 @@ entity common_peak is
end common_peak;
architecture rtl of common_peak is
-
type reg_type is record
peak : std_logic_vector(g_dat_w - 1 downto 0);
out_val : std_logic;
end record;
signal r, rin : reg_type;
-
begin
-
p_comb : process(r, rst, in_val, in_dat, in_clear)
variable v : reg_type;
begin
-
v := r;
if in_val = '1' then
@@ -81,7 +77,6 @@ begin
end if;
rin <= v;
-
end process;
p_regs : process(clk)
@@ -93,5 +88,4 @@ begin
out_val <= r.out_val;
out_dat <= r.peak;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pipeline.vhd b/libraries/base/common/src/vhdl/common_pipeline.vhd
index 5da5682ea02d8fe386f0b1a9a5eabec616577e6f..27d000cd2b1f9cf65557a442b6bd99b5524a5484 100644
--- a/libraries/base/common/src/vhdl/common_pipeline.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline.vhd
@@ -42,17 +42,13 @@ entity common_pipeline is
);
end common_pipeline;
-
architecture rtl of common_pipeline is
-
constant c_reset_value : std_logic_vector(out_dat'range) := TO_SVEC(g_reset_value, out_dat'length);
type t_out_dat is array (natural range <>) of std_logic_vector(out_dat'range);
signal out_dat_p : t_out_dat(0 to g_pipeline) := (others => c_reset_value);
-
begin
-
gen_pipe_n : if g_pipeline > 0 generate
p_clk : process(clk, rst)
begin
@@ -74,5 +70,4 @@ begin
RESIZE_UVEC(in_dat, out_dat'length) when g_representation = "UNSIGNED";
out_dat <= out_dat_p(g_pipeline);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
index feb5ac17967ad6886ff86ffe8c80342b103cc905..5965cde936445198449e97e2e441b7ffb0b657e3 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_integer.vhd
@@ -41,14 +41,10 @@ entity common_pipeline_integer is
);
end common_pipeline_integer;
-
architecture str of common_pipeline_integer is
-
signal in_dat_slv : std_logic_vector(g_dat_w - 1 downto 0);
signal out_dat_slv : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
in_dat_slv <= TO_SVEC(in_dat, g_dat_w) when g_representation = "SIGNED" else TO_UVEC(in_dat, g_dat_w);
out_dat <= TO_SINT(out_dat_slv) when g_representation = "SIGNED" else TO_UINT(out_dat_slv);
@@ -69,5 +65,4 @@ begin
in_dat => in_dat_slv,
out_dat => out_dat_slv
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
index ce8d7d5e9d85923bb36c26fe82e48a074cd84f29..971946f8d493a5ab394837cabc938ac36ed547f9 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_natural.vhd
@@ -40,14 +40,10 @@ entity common_pipeline_natural is
);
end common_pipeline_natural;
-
architecture str of common_pipeline_natural is
-
signal in_dat_slv : std_logic_vector(g_dat_w - 1 downto 0);
signal out_dat_slv : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
in_dat_slv <= TO_UVEC(in_dat, g_dat_w);
out_dat <= TO_UINT(out_dat_slv);
@@ -68,5 +64,4 @@ begin
in_dat => in_dat_slv,
out_dat => out_dat_slv
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
index a4afcd92de6251b686fcc71067b55ad1d35ff25c..0d592b72419de476307bb184b4820be12f7ae97a 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_sl.vhd
@@ -41,14 +41,10 @@ entity common_pipeline_sl is
);
end common_pipeline_sl;
-
architecture str of common_pipeline_sl is
-
signal in_dat_slv : std_logic_vector(0 downto 0);
signal out_dat_slv : std_logic_vector(0 downto 0);
-
begin
-
in_dat_slv(0) <= in_dat when g_out_invert = false else not in_dat;
out_dat <= out_dat_slv(0);
@@ -69,5 +65,4 @@ begin
in_dat => in_dat_slv,
out_dat => out_dat_slv
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
index edb63c6f5979668aadc3b5ec28210a0a30359633..8d883bbf79825eb22ceaac144aab055bc737e26a 100644
--- a/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_pipeline_symbol.vhd
@@ -53,16 +53,12 @@ entity common_pipeline_symbol is
);
end common_pipeline_symbol;
-
architecture str of common_pipeline_symbol is
-
type t_symbol_arr is array (integer range <>) of std_logic_vector(g_symbol_w - 1 downto 0);
signal in_dat_arr : t_symbol_arr(g_nof_symbols - 1 downto 0);
signal out_dat_arr : t_symbol_arr(g_nof_symbols - 1 downto 0);
-
begin
-
gen_symbols : for I in g_nof_symbols - 1 downto 0 generate
-- map input vector to arr
in_dat_arr(I) <= in_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w);
diff --git a/libraries/base/common/src/vhdl/common_pkg.vhd b/libraries/base/common/src/vhdl/common_pkg.vhd
index 6a03dd4febeac90b23ead718456473be75f5d8d0..e1c2f98ffbcb2ba3cbf1ce2ba0ceff36e2e5250c 100644
--- a/libraries/base/common/src/vhdl/common_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_pkg.vhd
@@ -32,7 +32,6 @@ use IEEE.numeric_std.all;
use IEEE.math_real.all;
package common_pkg is
-
-- CONSTANT DECLARATIONS ----------------------------------------------------
-- some integers
@@ -176,7 +175,6 @@ package common_pkg is
clken : std_logic; -- := '1';
end record;
-
-- FUNCTION DECLARATIONS ----------------------------------------------------
-- All functions assume [high downto low] input ranges
@@ -595,7 +593,6 @@ package common_pkg is
end common_pkg;
package body common_pkg is
-
function pow2(n : natural) return natural is
begin
return 2**n;
@@ -760,7 +757,6 @@ package body common_pkg is
return r;
end;
-
function to_sl(n: in boolean) return std_logic is
begin
if n = true then
@@ -2128,7 +2124,6 @@ package body common_pkg is
return TO_SREAL(svec) / 2.0**REAL(resolution_w);
end;
-
function RESIZE_NUM(u : unsigned; w : natural) return unsigned is
begin
-- left extend with '0' or remove MSbits and keep LS part (= u[w-1:0])
@@ -2264,7 +2259,6 @@ package body common_pkg is
return std_logic_vector(RESIZE_NUM(unsigned(l_vec), res_w) - unsigned(r_vec));
end;
-
function ADD_SVEC(l_vec : std_logic_vector; r_vec : std_logic_vector) return std_logic_vector is
begin
return ADD_SVEC(l_vec, r_vec, l_vec'length);
@@ -2311,7 +2305,6 @@ package body common_pkg is
return (a_im * b_re + a_re * b_im);
end;
-
function COMPLEX_RADIUS(re, im : real) return real is
begin
-- Must use ABS() with ** of real, because (negative)**2.0 yields error and value 0.0.
@@ -2397,7 +2390,6 @@ package body common_pkg is
return COMPLEX_IM(real(ampl), real(phase), false);
end;
-
function SHIFT_UVEC(vec : std_logic_vector; shift : integer) return std_logic_vector is
begin
if shift < 0 then
@@ -2893,7 +2885,6 @@ package body common_pkg is
return str((i + 1) * width - 1 downto i * width);
end;
-
function nat_arr_to_concat_slv(nat_arr: t_natural_arr; nof_elements: natural) return std_logic_vector is
variable v_concat_slv : std_logic_vector(nof_elements * 32 - 1 downto 0) := (others => '0');
begin
@@ -2903,7 +2894,6 @@ package body common_pkg is
return v_concat_slv;
end;
-
------------------------------------------------------------------------------
-- common_fifo_*
------------------------------------------------------------------------------
@@ -2933,7 +2923,6 @@ package body common_pkg is
--synthesis translate_on
end procedure proc_common_fifo_asserts;
-
------------------------------------------------------------------------------
-- common_fanout_tree
------------------------------------------------------------------------------
@@ -2954,7 +2943,6 @@ package body common_pkg is
return v_stage_pipeline_arr;
end function func_common_fanout_tree_pipelining;
-
------------------------------------------------------------------------------
-- common_reorder_symbol
------------------------------------------------------------------------------
@@ -3116,4 +3104,3 @@ package body common_pkg is
end proc_common_dclk_generate_sclk;
end common_pkg;
-
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay.vhd b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
index 906cf0d0ec8ede4b1511cb946158bb52607748fb..66ffa0296b87fcc73b80afe230f814cc1e23d0f7 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay.vhd
@@ -44,7 +44,6 @@ entity common_pulse_delay is
end entity common_pulse_delay;
architecture str of common_pulse_delay is
-
constant c_pulse_delay_max_width : natural := ceil_log2(g_pulse_delay_max + 1);
signal pulse_delay_reg : std_logic_vector(c_pulse_delay_max_width - 1 downto 0);
@@ -54,9 +53,7 @@ architecture str of common_pulse_delay is
signal common_counter_count : std_logic_vector(c_pulse_delay_max_width - 1 downto 0);
signal nxt_pulse_out : std_logic;
-
begin
-
-------------------------------------------------------------------------------
-- Switch to start counter @ pulse_in, and stop counter @ pulse_out.
-------------------------------------------------------------------------------
@@ -132,5 +129,4 @@ begin
pulse_delay_reg <= nxt_pulse_delay_reg;
end if;
end process;
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
index 4e51dd1e6b03b50e601619218a24cb31304a7128..f4e02fa89d7abea93b3391c150b08aa2e35abee7 100644
--- a/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_delay_reg.vhd
@@ -48,9 +48,7 @@ entity common_pulse_delay_reg is
);
end common_pulse_delay_reg;
-
architecture rtl of common_pulse_delay_reg is
-
constant c_nof_mm_regs : natural := 1;
constant c_mm_reg : t_c_mem := (latency => 1,
@@ -60,9 +58,7 @@ architecture rtl of common_pulse_delay_reg is
init_sl => '0');
signal mm_pulse_delay : std_logic_vector(ceil_log2(g_pulse_delay_max) - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -138,8 +134,6 @@ begin
out_dat => pulse_delay,
out_new => open
);
-
end generate; -- gen_common_reg_cross_domain
end rtl;
-
diff --git a/libraries/base/common/src/vhdl/common_pulse_extend.vhd b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
index 05cf366e9965902fd6c533892595b184f083621a..23b38e1ebf0c4f404cd18e126280c803865b4914 100644
--- a/libraries/base/common/src/vhdl/common_pulse_extend.vhd
+++ b/libraries/base/common/src/vhdl/common_pulse_extend.vhd
@@ -47,9 +47,7 @@ entity common_pulse_extend is
);
end common_pulse_extend;
-
architecture rtl of common_pulse_extend is
-
constant c_cnt_w : natural := sel_a_b(g_nof_cycles > 1, ceil_log2(g_nof_cycles), g_extend_w);
signal cnt : std_logic_vector(c_cnt_w - 1 downto 0) := (others => '0');
@@ -57,9 +55,7 @@ architecture rtl of common_pulse_extend is
signal cnt_is_0 : std_logic;
signal i_ep_out : std_logic := g_rst_level;
signal nxt_ep_out : std_logic;
-
begin
-
-- Extend ep_out active for 2**g_extend_w cycles longer than p_in active
-- Inactive p_in for less than 2**g_extend_w cycles will get lost in ep_out
@@ -94,6 +90,4 @@ begin
end if;
end if;
end process;
-
end architecture;
-
diff --git a/libraries/base/common/src/vhdl/common_pulser.vhd b/libraries/base/common/src/vhdl/common_pulser.vhd
index b6b6c7efee9f0891be3a588adf5f6a594c9380f1..5100346bb59a6726d1cc421478d65f3a9a367455 100644
--- a/libraries/base/common/src/vhdl/common_pulser.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser.vhd
@@ -51,9 +51,7 @@ entity common_pulser is
);
end common_pulser;
-
architecture rtl of common_pulser is
-
constant c_pulse_period_w : natural := ceil_log2(g_pulse_period + 1);
-- Map g_pulse_phase = phs natural range to equivalent integer range of c_pulse_init that is used by g_init of common_counter to avoid truncation warning for conversion to slv
@@ -66,9 +64,7 @@ architecture rtl of common_pulser is
signal cnt_en : std_logic;
signal cnt_clr : std_logic;
signal cnt_period : std_logic;
-
begin
-
p_clk : process(clk, rst)
begin
if rst = '1' then
@@ -99,5 +95,4 @@ begin
cnt_en => cnt_en,
count => cnt
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
index 20b4ac30b877d2ffc371d1e9508613c351d60b10..0afbe95fb9133a89cdcb03bb99ac462450ea5fda 100644
--- a/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/src/vhdl/common_pulser_us_ms_s.vhd
@@ -42,9 +42,7 @@ entity common_pulser_us_ms_s is
);
end common_pulser_us_ms_s;
-
architecture str of common_pulser_us_ms_s is
-
signal pulse_us_pp : std_logic; -- register to align with pulse_ms
signal pulse_us_p : std_logic; -- register to align with pulse_s
signal pulse_us_reg : std_logic; -- output register
@@ -56,9 +54,7 @@ architecture str of common_pulser_us_ms_s is
signal pulse_s_reg : std_logic; -- output register
signal i_pulse_s : std_logic;
-
begin
-
-- register output pulses to ease timing closure
pulse_us <= '0' when rst = '1' else i_pulse_us when rising_edge(clk);
pulse_ms <= '0' when rst = '1' else i_pulse_ms when rising_edge(clk);
@@ -117,5 +113,4 @@ begin
pulse_clr => sync,
pulse_out => pulse_s_reg
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
index b158278dca7df1e822c791f383b941b66b4f1b0f..748ab33ce8c261631aac84288dcbb92af25d7976 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
@@ -49,11 +49,8 @@ entity common_ram_cr_cw is
);
end common_ram_cr_cw;
-
architecture str of common_ram_cr_cw is
-
begin
-
-- Dual clock domain
-- Use port a only for write in write clock domain
-- Use port b only for read in read clock domain
@@ -84,5 +81,4 @@ begin
rd_val_a => OPEN,
rd_val_b => rd_val
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
index 5c39e5783809c16fdc25f84f0c6c196e9f1914c5..b2a595644f4227a84650c31fb80f51690131f4b9 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw_ratio.vhd
@@ -50,11 +50,8 @@ entity common_ram_cr_cw_ratio is
);
end common_ram_cr_cw_ratio;
-
architecture str of common_ram_cr_cw_ratio is
-
begin
-
-- Dual clock domain
-- Use port a only for write in write clock domain
-- Use port b only for read in read clock domain
@@ -86,5 +83,4 @@ begin
rd_val_a => OPEN,
rd_val_b => rd_val
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
index 1e75acda7023d5edc070213c594344847dc361c1..c49f6b39570dc76f0c7b6fd735cd7c36971c46a1 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
@@ -53,11 +53,8 @@ entity common_ram_crw_cr is
);
end common_ram_crw_cr;
-
architecture str of common_ram_crw_cr is
-
begin
-
-- Dual clock domain
-- Use port a for read/write in MM clock domain
-- Use port b for read only in ST clock domain
@@ -88,5 +85,4 @@ begin
rd_val_a => mm_rd_val,
rd_val_b => st_rd_val
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
index d0fca90bc6a35bd4a9864c9e96daa7b10f31c831..acdfa0d2196449f5df82793998de66d4e9972299 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
@@ -54,9 +54,7 @@ entity common_ram_crw_crw is
);
end common_ram_crw_crw;
-
architecture str of common_ram_crw_crw is
-
constant c_rd_latency : natural := sel_a_b(g_ram.latency < 2, g_ram.latency, 2); -- handle read latency 1 or 2 in RAM
constant c_pipeline : natural := sel_a_b(g_ram.latency > c_rd_latency, g_ram.latency - c_rd_latency, 0); -- handle rest of read latency > 2 in pipeline
@@ -69,9 +67,7 @@ architecture str of common_ram_crw_crw is
signal ram_rd_en_b : std_logic_vector(0 downto 0);
signal ram_rd_val_a : std_logic_vector(0 downto 0);
signal ram_rd_val_b : std_logic_vector(0 downto 0);
-
begin
-
assert g_ram.latency >= 1
report "common_ram_crw_crw : only support read latency >= 1"
severity FAILURE;
@@ -186,5 +182,4 @@ begin
in_dat => ram_rd_en_b,
out_dat => ram_rd_val_b
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
index c86ae8119daf4a1a729d95023a0d07e2bb1cb4da..c9930f48926ce557ab8fe1ff32714b7b1c50df1a 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
@@ -54,9 +54,7 @@ entity common_ram_crw_crw_ratio is
);
end common_ram_crw_crw_ratio;
-
architecture str of common_ram_crw_crw_ratio is
-
constant c_ram : t_c_mem := g_ram_a; -- use shared parameters from port a parameter
constant c_rd_latency : natural := sel_a_b(c_ram.latency < 2, c_ram.latency, 2); -- handle read latency 1 or 2 in RAM
@@ -71,9 +69,7 @@ architecture str of common_ram_crw_crw_ratio is
signal ram_rd_en_b : std_logic_vector(0 downto 0);
signal ram_rd_val_a : std_logic_vector(0 downto 0);
signal ram_rd_val_b : std_logic_vector(0 downto 0);
-
begin
-
assert c_ram.latency >= 1
report "common_ram_crw_crw_ratio : only support read latency >= 1"
severity FAILURE;
@@ -169,5 +165,4 @@ begin
in_dat => ram_rd_en_b,
out_dat => ram_rd_val_b
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
index 11d283a57a2a11b9548e7110d26c8d476ae6d599..021d7638b8b23a59533f0351265c05eef94eb68a 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
@@ -52,11 +52,8 @@ entity common_ram_crw_cw is
);
end common_ram_crw_cw;
-
architecture str of common_ram_crw_cw is
-
begin
-
-- Dual clock domain
-- Use port a for read/write in MM clock domain
-- Use port b for write only in ST clock domain
@@ -87,5 +84,4 @@ begin
rd_val_a => mm_rd_val,
rd_val_b => open
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_ram_r_w.vhd b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
index d703c059afb352706c15bf8922c86a0d675e4011..099cbb831f41c08a2e55c313e2b7b28045b7eafd 100644
--- a/libraries/base/common/src/vhdl/common_ram_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_r_w.vhd
@@ -45,11 +45,8 @@ entity common_ram_r_w is
);
end common_ram_r_w;
-
architecture str of common_ram_r_w is
-
begin
-
-- Use port a only for write
-- Use port b only for read
@@ -77,6 +74,4 @@ begin
rd_val_a => OPEN,
rd_val_b => rd_val
);
-
end str;
-
diff --git a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
index 6877523f97612188b9e5cd9a5b9c5f1812df2098..5c333e54056b31e78ac718e495a8ddde09ab4440 100644
--- a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
@@ -50,11 +50,8 @@ entity common_ram_rw_rw is
);
end common_ram_rw_rw;
-
architecture str of common_ram_rw_rw is
-
begin
-
-- Use only one clock domain
u_crw_crw : entity work.common_ram_crw_crw
@@ -84,5 +81,4 @@ begin
rd_val_a => rd_val_a,
rd_val_b => rd_val_b
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
index ba5edc3b8853a9e918d2cb51ee7e9a0a2b0121c0..84e56f935c2a68e0df66662259b81b45ba48ab43 100644
--- a/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_cross_domain.vhd
@@ -56,9 +56,7 @@ entity common_reg_cross_domain is
);
end common_reg_cross_domain;
-
architecture rtl of common_reg_cross_domain is
-
constant c_dat : std_logic_vector(in_dat'range) := g_out_dat_init(in_dat'range);
------------------------------------------------------------------------------
@@ -89,9 +87,7 @@ architecture rtl of common_reg_cross_domain is
signal out_en : std_logic;
signal i_out_dat : std_logic_vector(c_dat'range) := c_dat; -- register init without physical reset
signal nxt_out_dat : std_logic_vector(c_dat'range);
-
begin
-
out_dat <= i_out_dat;
------------------------------------------------------------------------------
@@ -139,7 +135,6 @@ begin
in_buf <= in_buf_reg;
end generate;
-
-- handshake control of the clock domain crossing by u_cross_req
-- hold any subsequent in_new during cross domain busy to ensure that the out_dat will get the latest value of in_dat
p_state : process(state, prev_state, reg_new, in_new_hold, cross_busy)
@@ -196,5 +191,4 @@ begin
-- some clock cycles after the cross_req the in_buf data is stable for sure
nxt_out_dat <= in_buf when out_en = '1' else i_out_dat;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w.vhd b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
index 571de7cad28fca4a4d84f316636db05cf1561a42..f58ac2c3b00cdd510b8e66cf4c204ea9fe6261fd 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w.vhd
@@ -79,9 +79,7 @@ entity common_reg_r_w is
);
end common_reg_r_w;
-
architecture rtl of common_reg_r_w is
-
constant c_rd_latency : natural := 1;
constant c_pipeline : natural := g_reg.latency - c_rd_latency;
constant c_pipe_dat_w : natural := 1 + g_reg.dat_w; -- pipeline rd_val & rd_dat together
@@ -104,9 +102,7 @@ architecture rtl of common_reg_r_w is
signal int_rd_val : std_logic;
signal nxt_rd_dat : std_logic_vector(rd_dat'range);
signal nxt_rd_val : std_logic;
-
begin
-
out_reg <= i_out_reg;
-- View as reg_arr
@@ -134,7 +130,6 @@ begin
rd_dat <= pipe_dat_out(pipe_dat_out'high - 1 downto 0);
rd_val <= pipe_dat_out(pipe_dat_out'high);
-
p_reg : process (rst, clk)
begin
if rst = '1' then
@@ -156,7 +151,6 @@ begin
end if;
end process;
-
p_control : process (rd_en, int_rd_dat, rd_adr, in_reg, i_out_reg, wr_adr, wr_en, wr_dat)
begin
nxt_rd_val <= rd_en; -- rd_val depends only on rd_en, so for an out of range address the old rd_dat is output
@@ -183,5 +177,4 @@ begin
end loop;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
index f6d2ba975a58545b308c7394f905381f44ed39bd..63e5a8a45f785fbcf29bfdfeb5bd1d10de4eb889 100644
--- a/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
+++ b/libraries/base/common/src/vhdl/common_reg_r_w_dc.vhd
@@ -86,9 +86,7 @@ entity common_reg_r_w_dc is
);
end common_reg_r_w_dc;
-
architecture str of common_reg_r_w_dc is
-
-- Registers in mm_clk domain
signal vector_wr_arr : std_logic_vector( g_reg.nof_dat - 1 downto 0);
signal vector_rd_arr : std_logic_vector( g_reg.nof_dat - 1 downto 0);
@@ -102,9 +100,7 @@ architecture str of common_reg_r_w_dc is
signal wr_pulse : std_logic;
signal toggle : std_logic;
signal out_new_i : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
------------------------------------------------------------------------------
@@ -134,7 +130,6 @@ begin
in_reg => in_vector
);
-
------------------------------------------------------------------------------
-- Transfer register value between mm_clk and st_clk domain.
-- If the function of the register ensures that the value will not be used
@@ -161,7 +156,6 @@ begin
end generate; -- no_cross
gen_cross : if g_cross_clock_domain = true generate
-
gen_rdback : if g_readback = true generate
in_vector <= in_reg;
end generate;
@@ -243,5 +237,4 @@ begin
end generate;
end generate; -- gen_cross
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_reinterleave.vhd b/libraries/base/common/src/vhdl/common_reinterleave.vhd
index 524f0a9e46e13c783dce9e38a55b9584fbbd8439..af7766e68e562ad2f6d8ce40eeb6e64249340bce 100644
--- a/libraries/base/common/src/vhdl/common_reinterleave.vhd
+++ b/libraries/base/common/src/vhdl/common_reinterleave.vhd
@@ -54,9 +54,7 @@ entity common_reinterleave is
);
end;
-
architecture rtl of common_reinterleave is
-
type t_dat_arr is array (integer range <>) of std_logic_vector(g_dat_w - 1 downto 0);
type t_val_arr is array (integer range <>) of std_logic;
@@ -133,9 +131,7 @@ architecture rtl of common_reinterleave is
-----------------------------------------------------------------------------
signal inter_out_dat_arr : t_dat_arr(c_nof_inter - 1 downto 0);
signal inter_out_val : std_logic_vector(c_nof_inter - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Deinterleavers and their input wiring
-----------------------------------------------------------------------------
diff --git a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
index 43b0801d19c4d85e44eb88540ae2ffbe2ce784a7..a3bcf0c3c6197039c53a3c0b602214b64311ac37 100644
--- a/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_reorder_symbol.vhd
@@ -86,7 +86,6 @@ use work.common_pkg.all;
-- bits that are not used in subsequent stages will get removed from the
-- pipeline select_2arr.
-
entity common_reorder_symbol is
generic (
g_nof_input : natural := 4;
@@ -116,9 +115,7 @@ entity common_reorder_symbol is
);
end common_reorder_symbol;
-
architecture rtl of common_reorder_symbol is
-
constant c_N : natural := largest(g_nof_input, g_nof_output); -- nof stages of the reorder network
constant c_pipeline_arr : t_natural_arr(0 to c_N) := g_pipeline_arr; -- force range [0:c_N]
@@ -144,9 +141,7 @@ architecture rtl of common_reorder_symbol is
signal select_2arr : t_select_2arr(-1 to c_N) := (others => (others => 0));
signal reorder_2arr : t_symbol_2arr(-1 to c_N) := (others => (others => (others => '0')));
signal nxt_reorder_2arr : t_symbol_2arr( 1 to c_N) := (others => (others => (others => '0')));
-
begin
-
------------------------------------------------------------------------------
-- Map the input to stage I=-1 with optional input pipelining to stage I=0
------------------------------------------------------------------------------
@@ -189,7 +184,6 @@ begin
);
end generate;
-
------------------------------------------------------------------------------
-- Reorder network for c_N inputs to the c_N outputs
------------------------------------------------------------------------------
@@ -233,7 +227,6 @@ begin
end generate;
end generate;
-
------------------------------------------------------------------------------
-- Map the stage I=c_N to the output
------------------------------------------------------------------------------
@@ -242,7 +235,6 @@ begin
out_data((J + 1) * g_symbol_w - 1 downto J * g_symbol_w) <= reorder_2arr(c_N)(J);
end generate;
-
------------------------------------------------------------------------------
-- Pipeline the optional data control lines
------------------------------------------------------------------------------
@@ -290,5 +282,4 @@ begin
in_dat => in_sync,
out_dat => out_sync
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_requantize.vhd b/libraries/base/common/src/vhdl/common_requantize.vhd
index e733f007047b8d0a782e241634fb222780106bac..e60f590d7815b90b0e1557ba8c46ce476d4bf25a 100644
--- a/libraries/base/common/src/vhdl/common_requantize.vhd
+++ b/libraries/base/common/src/vhdl/common_requantize.vhd
@@ -78,9 +78,7 @@ entity common_requantize is
);
end;
-
architecture str of common_requantize is
-
-- Use c_lsb_w > 0 to remove LSBits and support c_lsb < 0 to shift in zero value LSbits as a gain
constant c_lsb_w : natural := sel_a_b(g_lsb_w > 0, g_lsb_w, 0);
constant c_gain_w : natural := sel_a_b(g_lsb_w < 0, -g_lsb_w, 0);
@@ -91,9 +89,7 @@ architecture str of common_requantize is
signal res_dat : std_logic_vector(g_out_dat_w - 1 downto 0); -- resulting out_dat after removing the g_msb_w number of MSBits
signal gain_dat : std_logic_vector(g_out_dat_w + c_gain_w - 1 downto 0) := (others => '0'); -- fill extra LSBits with '0' instead of extending MSbits
-
begin
-
assert g_gain_w = 0 report "common_requantize: must use g_gain_w = 0, because gain is now supported via negative g_lsb_w." severity FAILURE;
-- Remove LSBits using ROUND or TRUNCATE
@@ -138,5 +134,4 @@ begin
gain_dat(g_out_dat_w + c_gain_w - 1 downto c_gain_w) <= res_dat;
out_dat <= RESIZE_SVEC(gain_dat, out_dat'length) when g_representation = "SIGNED" else RESIZE_UVEC(gain_dat, out_dat'length);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_request.vhd b/libraries/base/common/src/vhdl/common_request.vhd
index 083480a2c4573994f5f8f22712fe0a5e7d10b96a..47506edcb2d00aede4aa954346662fb2fe040c3f 100644
--- a/libraries/base/common/src/vhdl/common_request.vhd
+++ b/libraries/base/common/src/vhdl/common_request.vhd
@@ -34,7 +34,6 @@ entity common_request is
);
end common_request;
-
-- Request control:
-- . All inputs and outputs are registered
-- . A new request is indicated by in_req going from 0 to 1
@@ -43,7 +42,6 @@ end common_request;
-- . The output request is a pulse as indicated by the postfix '_evt'
architecture rtl of common_request is
-
signal sync_reg : std_logic;
signal in_req_reg : std_logic;
signal in_req_prev : std_logic;
@@ -52,9 +50,7 @@ architecture rtl of common_request is
signal out_req : std_logic;
signal out_req_prev : std_logic;
signal nxt_out_req_evt : std_logic;
-
begin
-
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -94,5 +90,4 @@ begin
out_req <= req_pending and sync_reg;
nxt_out_req_evt <= out_req and not out_req_prev;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_resize.vhd b/libraries/base/common/src/vhdl/common_resize.vhd
index 07d3bc37ca2887b133bc68710b955df7576a4c52..04ae5e8e6d7e24e1b028e370d9eb5384af5e3686 100644
--- a/libraries/base/common/src/vhdl/common_resize.vhd
+++ b/libraries/base/common/src/vhdl/common_resize.vhd
@@ -44,9 +44,7 @@ entity common_resize is
);
end;
-
architecture rtl of common_resize is
-
-- Clipping is only necessary when g_out_dat_w<g_in_dat_w.
constant c_clip : boolean := g_clip and (g_out_dat_w < g_in_dat_w);
@@ -65,9 +63,7 @@ architecture rtl of common_resize is
signal res_dat : std_logic_vector(out_dat'range);
signal res_vec : std_logic_vector(g_out_dat_w downto 0);
signal out_vec : std_logic_vector(g_out_dat_w downto 0);
-
begin
-
u_input_pipe : entity work.common_pipeline -- pipeline input
generic map (
g_representation => "SIGNED",
@@ -134,5 +130,4 @@ begin
out_ovr <= out_vec(g_out_dat_w);
out_dat <= out_vec(g_out_dat_w - 1 downto 0);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
index 9794be857f47cd11810dedae1c2bbcfe9eaf05c5..783c41fe81b80a148ad6234c1c93734d06a68e4a 100644
--- a/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
+++ b/libraries/base/common/src/vhdl/common_reverse_n_data.vhd
@@ -70,9 +70,7 @@ entity common_reverse_n_data is
);
end common_reverse_n_data;
-
architecture str of common_reverse_n_data is
-
constant c_pipeline_total : natural := g_pipeline_demux_in + g_pipeline_demux_out +
g_reverse_len - 1 +
g_pipeline_mux_in + g_pipeline_mux_out;
@@ -90,9 +88,7 @@ architecture str of common_reverse_n_data is
signal reverse_data_vec : std_logic_vector(g_reverse_len * g_data_w - 1 downto 0);
signal reverse_val_vec : std_logic_vector(g_reverse_len - 1 downto 0);
signal reverse_val : std_logic;
-
begin
-
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -247,5 +243,4 @@ begin
out_dat => out_data,
out_val => out_val -- = in_val delayed by c_pipeline_total
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_rl_decrease.vhd b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
index c7c12eb69c1d7cdc1b162e7e5a5fd3ab7eb8810b..41fa78b5592b069f56ad68357d26dd59ed469649 100644
--- a/libraries/base/common/src/vhdl/common_rl_decrease.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_decrease.vhd
@@ -31,7 +31,6 @@ use IEEE.std_logic_1164.all;
-- . A show ahead FIFO with RL=0 does not need a rd_emp output signal, because
-- with RL=0 the rd_val='0' when it is empty (so emp <= NOT rd_val).
-
entity common_rl_decrease is
generic (
g_adapt : boolean := true; -- default when TRUE then decrease sink RL 1 to source RL 0, else then implement wires
@@ -51,9 +50,7 @@ entity common_rl_decrease is
);
end common_rl_decrease;
-
architecture rtl of common_rl_decrease is
-
-- Internally use streaming record for the SOSI, for the SISO.ready directly use src_in_ready
type t_sosi is record -- Source Out or Sink In
data : std_logic_vector(g_dat_w - 1 downto 0);
@@ -71,9 +68,7 @@ architecture rtl of common_rl_decrease is
-- The default FIFO has ready latency RL = 1, need to use input RL + 1 words for the buf array, to go to output RL = 0 for show ahead FIFO
signal buf : t_sosi_arr(1 downto 0);
signal nxt_buf : t_sosi_arr(1 downto 0);
-
begin
-
gen_wires : if g_adapt = false generate
snk_out_ready <= src_in_ready;
@@ -139,5 +134,4 @@ begin
end if;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_rl_increase.vhd b/libraries/base/common/src/vhdl/common_rl_increase.vhd
index 84317884ec5a19ce4fd4617e0c07bfc64ce4f1ef..43f002b9f52d79aa5edfe7446f93a04c2d66ad3c 100644
--- a/libraries/base/common/src/vhdl/common_rl_increase.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_increase.vhd
@@ -56,17 +56,13 @@ entity common_rl_increase is
);
end common_rl_increase;
-
architecture rtl of common_rl_increase is
-
signal ready_reg : std_logic;
signal hold_dat : std_logic_vector(g_dat_w - 1 downto 0) := (others => '0');
signal nxt_hold_dat : std_logic_vector(g_dat_w - 1 downto 0);
signal hold_val : std_logic;
-
begin
-
gen_wires : if g_adapt = false generate
snk_out_ready <= src_in_ready;
diff --git a/libraries/base/common/src/vhdl/common_rl_register.vhd b/libraries/base/common/src/vhdl/common_rl_register.vhd
index 0744e5f19a276d959e284312e1d35e21a86c7b46..1a4f287ddc18dc343c2966e1a6b7f638901cf2cb 100644
--- a/libraries/base/common/src/vhdl/common_rl_register.vhd
+++ b/libraries/base/common/src/vhdl/common_rl_register.vhd
@@ -37,7 +37,6 @@ use IEEE.std_logic_1164.all;
-- Otherwise a new valid snk_in_dat that arrives with RL = 0 will already
-- set src_out_dat before src_out_val becomes valid due to src_in_ready.
-
entity common_rl_register is
generic (
g_adapt : boolean := true; -- default when TRUE then register RL 1 --> 0 --> 1, else then implement wires
@@ -58,15 +57,11 @@ entity common_rl_register is
);
end common_rl_register;
-
architecture str of common_rl_register is
-
signal reg_ready : std_logic;
signal reg_dat : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_val : std_logic;
-
begin
-
u_rl0 : entity common_lib.common_rl_decrease
generic map (
g_adapt => g_adapt,
@@ -103,5 +98,4 @@ begin
src_out_dat => src_out_dat,
src_out_val => src_out_val
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_rom.vhd b/libraries/base/common/src/vhdl/common_rom.vhd
index f899344c7cce850fa52201563cf8cbc9ec666c2d..0637ea290b9316b419f9c35700dd1fab8ec7cac6 100644
--- a/libraries/base/common/src/vhdl/common_rom.vhd
+++ b/libraries/base/common/src/vhdl/common_rom.vhd
@@ -41,11 +41,8 @@ entity common_rom is
);
end common_rom;
-
architecture str of common_rom is
-
begin
-
-- Only use the read port
u_r_w : entity work.common_ram_r_w
@@ -66,5 +63,4 @@ begin
rd_dat => rd_dat,
rd_val => rd_val
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_round.vhd b/libraries/base/common/src/vhdl/common_round.vhd
index 16c232b6efd9d281a1095c689bf079da3a45fbf5..6f7aae19d2d8a1ef6b16dcab4e354766cf3e076c 100644
--- a/libraries/base/common/src/vhdl/common_round.vhd
+++ b/libraries/base/common/src/vhdl/common_round.vhd
@@ -25,7 +25,6 @@ use ieee.numeric_std.all;
use work.common_pkg.all;
entity common_round is
-
--
-- ISE XST results for rounding 36b --> 18b:
-- int clip --> slices FFs LUTs
@@ -38,7 +37,6 @@ entity common_round is
-- 4b*4b=8b->4b the maximum product is 15*15=225 <= 255-8, so wrapping will never occur.
-- When g_round = FALSE then truncate (= remove) the LSbits and then g_round_clip and g_round_even are dont care.
--
-
generic (
g_representation : string := "SIGNED"; -- SIGNED (round +-0.5 away from zero to +- infinity) or UNSIGNED rounding (round 0.5 up to + inifinity)
g_round : boolean := true; -- when TRUE round the input, else truncate the input
@@ -57,16 +55,12 @@ entity common_round is
);
end;
-
architecture rtl of common_round is
-
constant c_remove_w : integer := g_in_dat_w - g_out_dat_w;
signal reg_dat : std_logic_vector(in_dat'range);
signal res_dat : std_logic_vector(out_dat'range);
-
begin
-
u_input_pipe : entity work.common_pipeline
generic map (
g_representation => g_representation,
@@ -85,6 +79,7 @@ begin
no_s : if c_remove_w <= 0 and g_representation = "SIGNED" generate
res_dat <= RESIZE_SVEC(reg_dat, g_out_dat_w);
end generate;
+
no_u : if c_remove_w <= 0 and g_representation = "UNSIGNED" generate
res_dat <= RESIZE_UVEC(reg_dat, g_out_dat_w);
end generate;
@@ -94,9 +89,11 @@ begin
gen_s : if c_remove_w > 0 and g_round = true and g_representation = "SIGNED" generate
res_dat <= s_round(reg_dat, c_remove_w, g_round_clip, g_round_even);
end generate;
+
gen_u : if c_remove_w > 0 and g_round = true and g_representation = "UNSIGNED" generate
res_dat <= u_round(reg_dat, c_remove_w, g_round_clip, g_round_even);
end generate;
+
-- . truncating
gen_t : if c_remove_w > 0 and g_round = false generate
res_dat <= truncate(reg_dat, c_remove_w);
@@ -115,5 +112,4 @@ begin
in_dat => res_dat,
out_dat => out_dat
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
index 8d03b932cf0387e79eb7d3e458e270cea6f823ca..9c5981c47a625208abe8bff59d3d2a1b8e7c6185 100644
--- a/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
+++ b/libraries/base/common/src/vhdl/common_select_m_symbols.vhd
@@ -68,9 +68,7 @@ entity common_select_m_symbols is
);
end common_select_m_symbols;
-
architecture str of common_select_m_symbols is
-
constant c_sel_w : natural := ceil_log2(g_nof_input);
type t_symbol_arr is array (integer range <>) of std_logic_vector(g_symbol_w - 1 downto 0);
@@ -91,9 +89,7 @@ architecture str of common_select_m_symbols is
signal out_sop_arr : std_logic_vector(g_nof_output - 1 downto 0);
signal out_eop_arr : std_logic_vector(g_nof_output - 1 downto 0);
signal out_sync_arr : std_logic_vector(g_nof_output - 1 downto 0);
-
begin
-
-- pipeline input
u_pipe_in_data : common_pipeline generic map ("SIGNED", g_pipeline_in, 0, in_data'LENGTH, in_data'length) port map (rst, clk, '1', '0', '1', in_data, in_data_reg);
u_pipe_in_select : common_pipeline generic map ("SIGNED", g_pipeline_in, 0, in_select'LENGTH, in_select'length) port map (rst, clk, '1', '0', '1', in_select, in_select_reg);
@@ -147,5 +143,4 @@ begin
out_sop <= out_sop_arr(0);
out_eop <= out_eop_arr(0);
out_sync <= out_sync_arr(0);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_select_symbol.vhd b/libraries/base/common/src/vhdl/common_select_symbol.vhd
index 2b52a29174c5495b424bc82d53521d937d1e6362..117fb8c133e1a1f783e09ff7e4e48e2764fc0146 100644
--- a/libraries/base/common/src/vhdl/common_select_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_select_symbol.vhd
@@ -62,18 +62,14 @@ entity common_select_symbol is
);
end common_select_symbol;
-
architecture rtl of common_select_symbol is
-
constant c_pipeline : natural := g_pipeline_in + g_pipeline_out;
signal in_data_reg : std_logic_vector(in_data'range);
signal in_sel_reg : std_logic_vector(in_sel'range);
signal sel_symbol : std_logic_vector(g_symbol_w - 1 downto 0);
-
begin
-
-- pipeline input
u_pipe_in_data : common_pipeline generic map ("SIGNED", g_pipeline_in, 0, in_data'LENGTH, in_data'length) port map (rst, clk, '1', '0', '1', in_data, in_data_reg);
u_pipe_in_sel : common_pipeline generic map ("SIGNED", g_pipeline_in, 0, g_sel_w, g_sel_w) port map (rst, clk, '1', '0', '1', in_sel, in_sel_reg);
@@ -104,5 +100,4 @@ begin
u_pipe_out_sop : common_pipeline_sl generic map (c_pipeline, 0, false) port map (rst, clk, '1', '0', '1', in_sop, out_sop);
u_pipe_out_eop : common_pipeline_sl generic map (c_pipeline, 0, false) port map (rst, clk, '1', '0', '1', in_eop, out_eop);
u_pipe_out_sync : common_pipeline_sl generic map (c_pipeline, 0, false) port map (rst, clk, '1', '0', '1', in_sync, out_sync);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_shiftram.vhd b/libraries/base/common/src/vhdl/common_shiftram.vhd
index 81c47fa48f20e7de283fddf00bc44fe8312703ed..382a87a482c9a6c1d4976ea96cbbb0fa2357cdf5 100644
--- a/libraries/base/common/src/vhdl/common_shiftram.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftram.vhd
@@ -78,9 +78,7 @@ entity common_shiftram is
);
end common_shiftram;
-
architecture rtl of common_shiftram is
-
-- RAM constants
constant c_ram_rl : natural := 1;
constant c_ram_addr_w : natural := ceil_log2(g_nof_words);
@@ -144,9 +142,7 @@ architecture rtl of common_shiftram is
'0');
signal r3, nxt_r3 : t_reg_3 := c_reg_3_defaults;
-
begin
-
-----------------------------------------------------------------------------
-- Register stage 0
-----------------------------------------------------------------------------
@@ -189,7 +185,6 @@ begin
else
v.ram_wr_shift_incr := false;
end if;
-
end if;
if rst = '1' then
@@ -227,7 +222,6 @@ begin
v_shift_diff := TO_UINT(r1.ram_rd_shift) - TO_UINT(r0.ram_wr_shift) + 1;
v.ram_rd_addr := INCR_UVEC(r1.ram_rd_addr, v_shift_diff);
end if;
-
end if;
if rst = '1' then
@@ -291,7 +285,6 @@ begin
-- Register stage 3 (optional)
-----------------------------------------------------------------------------
gen_output_invalid: if g_output_invalid_during_shift_incr = true generate
-
r3 <= nxt_r3 when rising_edge(clk);
p_comb_2 : process(rst, r2, r3, data_in_shift, ram_data_out, ram_data_out_val)
@@ -319,7 +312,6 @@ begin
data_out_shift <= r3.data_out_shift;
data_out <= r3.data_out;
data_out_val <= r3.data_out_val;
-
end generate;
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg.vhd b/libraries/base/common/src/vhdl/common_shiftreg.vhd
index 4eccd0fb42c81d39e8528edefe60b78bbcda62a7..e18a57174abfb7bb2165f3de14ee4fab9b2e8780 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg.vhd
@@ -70,9 +70,7 @@ entity common_shiftreg is
);
end common_shiftreg;
-
architecture str of common_shiftreg is
-
type t_data_arr is array (integer range <>) of std_logic_vector(g_dat_w - 1 downto 0);
constant c_cnt_w : natural := out_cnt'length;
@@ -101,9 +99,7 @@ architecture str of common_shiftreg is
signal i_out_val_vec : std_logic_vector(g_nof_dat - 1 downto 0);
signal i_out_sop_vec : std_logic_vector(g_nof_dat - 1 downto 0);
signal i_out_eop_vec : std_logic_vector(g_nof_dat - 1 downto 0);
-
begin
-
no_sreg : if g_nof_dat = 1 generate
-- directly assign the inputs to avoid NULL array warning in gen_sreg
data_vec <= in_dat;
@@ -253,5 +249,4 @@ begin
in_dat => in_cnt,
out_dat => out_cnt
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
index 3d1b500febc0bd900ef695d4880254519aadb264..e5a3137af0c6d1c0e6042f3dca9df27e67ddeefd 100644
--- a/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_shiftreg_symbol.vhd
@@ -57,16 +57,12 @@ entity common_shiftreg_symbol is
);
end common_shiftreg_symbol;
-
architecture str of common_shiftreg_symbol is
-
type t_symbol_arr is array (integer range <>) of std_logic_vector(g_symbol_w - 1 downto 0);
signal in_dat_arr : t_symbol_arr(g_nof_symbols - 1 downto 0);
signal out_dat_arr : t_symbol_arr(g_nof_symbols - 1 downto 0);
-
begin
-
gen_symbols : for I in g_nof_symbols - 1 downto 0 generate
-- map input vector to arr
in_dat_arr(I) <= in_data((I + 1) * g_symbol_w - 1 downto I * g_symbol_w);
diff --git a/libraries/base/common/src/vhdl/common_spulse.vhd b/libraries/base/common/src/vhdl/common_spulse.vhd
index 61d8e90541d9042d6c527a85c720a6c0e9f4efdb..d24c3034ffcd6324b9ec560e263f210e7531e273 100644
--- a/libraries/base/common/src/vhdl/common_spulse.vhd
+++ b/libraries/base/common/src/vhdl/common_spulse.vhd
@@ -52,7 +52,6 @@ entity common_spulse is
end;
architecture rtl of common_spulse is
-
signal in_level : std_logic;
signal meta_level : std_logic_vector(0 to g_delay_len - 1);
signal out_level : std_logic;
@@ -60,9 +59,7 @@ architecture rtl of common_spulse is
signal meta_ack : std_logic_vector(0 to g_delay_len - 1);
signal pulse_ack : std_logic;
signal nxt_out_pulse : std_logic;
-
begin
-
capture_in_pulse : entity work.common_switch
port map (
clk => in_clk,
@@ -106,5 +103,4 @@ begin
end process;
nxt_out_pulse <= out_level and not prev_out_level;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_stable_delayed.vhd b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
index e9ac7533ea50a33411d78cb05aee0fe3c8285cba..e9d5ae319709f9be85beb7a352cb700302200cbf 100644
--- a/libraries/base/common/src/vhdl/common_stable_delayed.vhd
+++ b/libraries/base/common/src/vhdl/common_stable_delayed.vhd
@@ -54,18 +54,14 @@ entity common_stable_delayed is
);
end common_stable_delayed;
-
architecture rtl of common_stable_delayed is
-
signal p_in : std_logic;
signal p_stable : std_logic;
signal cnt_clr : std_logic;
signal cnt_en : std_logic;
signal cnt : std_logic_vector(g_delayed_w - 1 downto 0);
-
begin
-
-- Map r to internal p, to be able to internally operate with active level is '1'
p_in <= r_in when g_active_level = '1' else not r_in;
r_stable <= p_stable when g_active_level = '1' else not p_stable;
@@ -94,5 +90,4 @@ begin
cnt_en => cnt_en,
count => cnt
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_stable_monitor.vhd b/libraries/base/common/src/vhdl/common_stable_monitor.vhd
index 157a2a96745eac7eeb360ebcc54df5887b5163ed..fe41dae0f857445322c145c13d8219879b3819a4 100644
--- a/libraries/base/common/src/vhdl/common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/common_stable_monitor.vhd
@@ -43,15 +43,11 @@ entity common_stable_monitor is
);
end common_stable_monitor;
-
architecture rtl of common_stable_monitor is
-
signal nxt_r_stable : std_logic;
signal r_evt : std_logic;
signal r_evt_occured : std_logic;
-
begin
-
p_clk: process(clk, rst)
begin
if rst = '1' then
@@ -89,5 +85,4 @@ begin
switch_low => r_stable_ack,
out_level => r_evt_occured
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_str_pkg.vhd b/libraries/base/common/src/vhdl/common_str_pkg.vhd
index af8f915c7b5c3f24fbdefeb1ff28d4b0eb7bf5bd..e309a4d10a00d1432c3c166ae1b0bc0174f251c9 100644
--- a/libraries/base/common/src/vhdl/common_str_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_str_pkg.vhd
@@ -36,7 +36,6 @@ use IEEE.std_logic_textio.all;
use common_lib.common_pkg.all;
package common_str_pkg is
-
type t_str_4_arr is array (integer range <>) of string(1 to 4);
function nof_digits(number: natural) return natural;
@@ -63,11 +62,9 @@ package common_str_pkg is
function str_to_ascii_slv_8_arr( s: string) return t_slv_8_arr;
function str_to_ascii_slv_32_arr( s: string) return t_slv_32_arr;
function str_to_ascii_slv_32_arr( s: string; arr_size : natural) return t_slv_32_arr;
-
end common_str_pkg;
package body common_str_pkg is
-
function nof_digits(number: natural) return natural is
-- Returns number of digits in a natural number. Only used in string processing, so defined here.
-- log10(0) is not allowed so:
@@ -82,6 +79,7 @@ package body common_str_pkg is
else
return 1;
end if;
+
end;
function nof_digits_int(number: integer) return natural is
@@ -326,4 +324,3 @@ package body common_str_pkg is
end;
end common_str_pkg;
-
diff --git a/libraries/base/common/src/vhdl/common_switch.vhd b/libraries/base/common/src/vhdl/common_switch.vhd
index 9b3ecd744d81661ebd52edee6ab8dbde5f84b1c1..ae38d1382f21e2ae23aba02ed97605269fef8c1b 100644
--- a/libraries/base/common/src/vhdl/common_switch.vhd
+++ b/libraries/base/common/src/vhdl/common_switch.vhd
@@ -50,12 +50,9 @@ entity common_switch is
end;
architecture rtl of common_switch is
-
signal switch_level : std_logic := g_rst_level;
signal nxt_switch_level : std_logic;
-
begin
-
gen_wire : if g_or_high = false and g_and_low = false generate
out_level <= switch_level;
end generate;
diff --git a/libraries/base/common/src/vhdl/common_toggle.vhd b/libraries/base/common/src/vhdl/common_toggle.vhd
index fbe06ef8dd74c55becfe0367d700a54efd0f0d97..79d9a4a67ddc74f473f6e32c5175c0d3a6f05218 100644
--- a/libraries/base/common/src/vhdl/common_toggle.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle.vhd
@@ -38,16 +38,13 @@ entity common_toggle is
end;
architecture rtl of common_toggle is
-
signal prev_in_dat : std_logic;
signal in_hld : std_logic;
signal in_evt : std_logic;
signal i_out_dat : std_logic;
signal nxt_out_dat : std_logic;
-
begin
-
out_dat <= i_out_dat;
p_reg : process(rst, clk)
@@ -83,5 +80,4 @@ begin
-- Toggle output at in_dat event
nxt_out_dat <= not i_out_dat when in_evt = '1' else i_out_dat;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_toggle_align.vhd b/libraries/base/common/src/vhdl/common_toggle_align.vhd
index f557c23e53d9030ba71953412639dacd250b09ae..6739bf67d4c9fb7a678f09ad4605353dd19c1daa 100644
--- a/libraries/base/common/src/vhdl/common_toggle_align.vhd
+++ b/libraries/base/common/src/vhdl/common_toggle_align.vhd
@@ -51,7 +51,6 @@ entity common_toggle_align is
end;
architecture rtl of common_toggle_align is
-
signal prev_in_toggle : std_logic;
signal in_toggle_revt : std_logic;
@@ -60,9 +59,7 @@ architecture rtl of common_toggle_align is
signal nxt_cnt : natural;
signal nxt_out_toggle : std_logic;
-
begin
-
p_reg : process(rst, clk)
begin
if rst = '1' then
@@ -108,5 +105,4 @@ begin
in_dat => nxt_out_toggle,
out_dat => out_toggle
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_transpose.vhd b/libraries/base/common/src/vhdl/common_transpose.vhd
index 671247e9e93efbb31037635dfa7f312328eefcf9..0408bdf4864644e09e5870dee67dca9bfa2b7820 100644
--- a/libraries/base/common/src/vhdl/common_transpose.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose.vhd
@@ -62,9 +62,7 @@ entity common_transpose is
);
end common_transpose;
-
architecture str of common_transpose is
-
constant c_sel_w : natural := ceil_log2(g_nof_data);
constant c_nof_data_max : natural := 8;
@@ -90,9 +88,7 @@ architecture str of common_transpose is
signal hold_val : std_logic;
signal hold_eop : std_logic;
signal hold_sel : std_logic_vector(c_sel_w - 1 downto 0);
-
begin
-
u_sreg_data : entity common_lib.common_shiftreg
generic map (
g_pipeline => g_pipeline_shiftreg,
@@ -294,5 +290,4 @@ begin
out_symbol => out_addr
);
-
end str;
diff --git a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
index 86173325be1b083e333ec58d83abd97bfe7bebdc..bd6fc252d0e666f29c1a638464bf5ea0fa850c8c 100644
--- a/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
+++ b/libraries/base/common/src/vhdl/common_transpose_symbol.vhd
@@ -66,9 +66,7 @@ entity common_transpose_symbol is
);
end common_transpose_symbol;
-
architecture rtl of common_transpose_symbol is
-
constant c_nof_symbols : natural := g_nof_data;
constant c_symbol_w : natural := g_data_w / c_nof_symbols;
@@ -79,9 +77,7 @@ architecture rtl of common_transpose_symbol is
signal trans_symbol_2arr : t_symbol_2arr(g_nof_data - 1 downto 0);
signal trans_data : std_logic_vector(g_nof_data * g_data_w - 1 downto 0);
-
begin
-
no_transpose : if g_nof_data = 1 generate
trans_data <= in_data;
end generate;
@@ -148,5 +144,4 @@ begin
in_dat => in_eop,
out_dat => out_eop
);
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_variable_delay.vhd b/libraries/base/common/src/vhdl/common_variable_delay.vhd
index 122814e4575fc65abb90cb287175137c24d7f370..10ddd4a1eb095fa4ea55cbca134a0ee91d16e85f 100644
--- a/libraries/base/common/src/vhdl/common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/common_variable_delay.vhd
@@ -46,14 +46,12 @@ entity common_variable_delay is
end common_variable_delay;
architecture rtl of common_variable_delay is
-
signal i_out_pulse : std_logic;
signal nxt_out_pulse : std_logic;
signal cnt_en : std_logic;
signal nxt_cnt_en : std_logic;
signal delay_cnt : natural;
signal nxt_delay_cnt : natural;
-
begin
out_pulse <= i_out_pulse;
@@ -97,5 +95,4 @@ begin
delay_cnt <= nxt_delay_cnt;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
index 17f2092f415373c5bdf102b270fde2623e7096d0..4327b27652223a0cb41674eee9732cb927ee961c 100644
--- a/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
+++ b/libraries/base/common/src/vhdl/common_wideband_data_scope.vhd
@@ -61,19 +61,16 @@ entity common_wideband_data_scope is
);
end common_wideband_data_scope;
-
architecture beh of common_wideband_data_scope is
-
signal SCLKi : std_logic; -- sampling clk, for simulation only
signal scope_cnt : natural;
signal scope_dat : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
sim_only : if g_sim = true generate
use_sclk : if g_use_sclk = true generate
SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
end generate;
+
gen_sclk : if g_use_sclk = false generate
proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
end generate;
@@ -100,5 +97,4 @@ begin
out_dat <= scope_dat;
out_int <= TO_SINT(scope_dat);
end generate;
-
end beh;
diff --git a/libraries/base/common/src/vhdl/common_zip.vhd b/libraries/base/common/src/vhdl/common_zip.vhd
index 67b5952382358a0e8ce9becacd96bcb7cf1fa5d5..2bb1bd6abda1cba1f7929db7668139cb7b6f749d 100644
--- a/libraries/base/common/src/vhdl/common_zip.vhd
+++ b/libraries/base/common/src/vhdl/common_zip.vhd
@@ -44,7 +44,6 @@ entity common_zip is
end common_zip;
architecture rtl of common_zip is
-
type t_dat_arr is array (natural range <>) of std_logic_vector(out_dat'range);
type reg_type is record
@@ -55,13 +54,10 @@ architecture rtl of common_zip is
end record;
signal r, rin : reg_type;
-
begin
-
comb : process(r, rst, in_val, in_dat_arr)
variable v : reg_type;
begin
-
v := r;
v.out_val := '0'; -- Default the output valid signal is low.
@@ -88,7 +84,6 @@ begin
end if;
rin <= v;
-
end process comb;
regs : process(clk)
@@ -100,5 +95,4 @@ begin
out_dat <= r.out_dat;
out_val <= r.out_val;
-
end rtl;
diff --git a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
index ca32557a718f349cc1846dfc9fb17ca8a7bd0682..ea0228354d9411895fb7453fa07eb334c6e49ac8 100644
--- a/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_pulse_delay.vhd
@@ -49,13 +49,9 @@ entity mms_common_pulse_delay is
);
end mms_common_pulse_delay;
-
architecture str of mms_common_pulse_delay is
-
signal pulse_delay : std_logic_vector(ceil_log2(g_pulse_delay_max) - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- common_pulse_delay
------------------------------------------------------------------------------
@@ -90,6 +86,4 @@ begin
sla_in => reg_mosi,
sla_out => reg_miso
);
-
end str;
-
diff --git a/libraries/base/common/src/vhdl/mms_common_reg.vhd b/libraries/base/common/src/vhdl/mms_common_reg.vhd
index 8857a3c267e2d4aee89cec3c0d2488bdb382ffef..56fb4f3865a2cbee12747a9ffa69878e1bf7856b 100644
--- a/libraries/base/common/src/vhdl/mms_common_reg.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_reg.vhd
@@ -27,7 +27,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
-
entity mms_common_reg is
generic (
-- TYPE t_c_mem IS RECORD
@@ -58,13 +57,9 @@ entity mms_common_reg is
);
end mms_common_reg;
-
architecture str of mms_common_reg is
-
constant c_init_reg : std_logic_vector(c_mem_reg_init_w - 1 downto 0) := (others => g_mm_reg.init_sl);
-
begin
-
u_common_reg_r_w_dc : entity work.common_reg_r_w_dc
generic map (
g_cross_clock_domain => true,
@@ -89,6 +84,4 @@ begin
in_reg => in_reg,
out_reg => out_reg
);
-
end str;
-
diff --git a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
index 0d43f61630f8224c35b51186098dac868d9ada4f..c1bf30f4e766887b13fc92adceb1eca0088d0ebe 100644
--- a/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_stable_monitor.vhd
@@ -27,7 +27,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
-
entity mms_common_stable_monitor is
generic (
g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
@@ -48,9 +47,7 @@ entity mms_common_stable_monitor is
);
end mms_common_stable_monitor;
-
architecture str of mms_common_stable_monitor is
-
-- Define the actual size of the MM slave register
constant c_nof_dat : natural := ceil_div(g_nof_input, c_word_w);
constant c_adr_w : natural := ceil_log2(c_nof_dat);
@@ -68,9 +65,7 @@ architecture str of mms_common_stable_monitor is
signal st_stable_ack : std_logic;
signal in_reg : std_logic_vector(c_nof_dat * c_word_w - 1 downto 0);
-
begin
-
u_mm_reg : entity work.common_reg_r_w_dc
generic map (
g_cross_clock_domain => g_cross_clock_domain,
@@ -113,4 +108,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
index 46fb0e574533d432626f7eb0775a193b24cdb9e9..57d388d15f500b1d3cc92f08eec27ff3e0db3556 100644
--- a/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
+++ b/libraries/base/common/src/vhdl/mms_common_variable_delay.vhd
@@ -49,17 +49,13 @@ entity mms_common_variable_delay is
);
end mms_common_variable_delay;
-
architecture str of mms_common_variable_delay is
-
constant c_enable_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, 1, 1, '0');
signal enable_reg : std_logic_vector(c_enable_mem_reg.dat_w * c_enable_mem_reg.nof_dat - 1 downto 0);
signal enable : std_logic := '0';
-
begin
-
trigger_en <= sl(enable_reg); -- also provide enable as OUT
enable <= sl(enable_reg);
@@ -91,5 +87,4 @@ begin
in_reg => enable_reg,
out_reg => enable_reg
);
-
end;
diff --git a/libraries/base/common/tb/vhdl/tb_common_acapture.vhd b/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
index 526dcc1b23ce0e27f0663c6aa43d6b43512dedf0..615f744bf26f4ae82be111d02e59c66eca2c4aa5 100644
--- a/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_acapture.vhd
@@ -35,9 +35,7 @@ use work.tb_common_pkg.all;
entity tb_common_acapture is
end tb_common_acapture;
-
architecture tb of tb_common_acapture is
-
constant in_clk_period : time := 10 ns;
constant out_clk_period : time := 7 ns;
@@ -52,9 +50,7 @@ architecture tb of tb_common_acapture is
signal in_dat : std_logic;
signal out_cap : std_logic;
-
begin
-
in_clk <= not in_clk or tb_end after in_clk_period / 2;
out_clk <= not out_clk or tb_end after out_clk_period / 2;
@@ -89,5 +85,4 @@ begin
out_clk => out_clk,
out_cap => out_cap
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
index 99e634373c92190d890a82cac1b160e51777d4b9..b415d4357756ff863f60880ad9b48e35103bd05a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_add_sub.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.common_pkg.all;
-
entity tb_common_add_sub is
generic (
g_direction : string := "SUB"; -- "SUB", "ADD" or "BOTH"
@@ -36,9 +35,7 @@ entity tb_common_add_sub is
);
end tb_common_add_sub;
-
architecture tb of tb_common_add_sub is
-
constant clk_period : time := 10 ns;
constant c_pipeline : natural := g_pipeline_in + g_pipeline_out;
@@ -66,9 +63,7 @@ architecture tb of tb_common_add_sub is
signal out_result : std_logic_vector(g_out_dat_w - 1 downto 0); -- combinatorial result
signal result_expected : std_logic_vector(g_out_dat_w - 1 downto 0); -- pipelined results
signal result_rtl : std_logic_vector(g_out_dat_w - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
-- run 1 us or -all
@@ -173,5 +168,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
index 1a99bf170c553ec0f06e60937d88edc2711c676e..1686b6f4e3b5512fe8e5fa259922b31b52fd688d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_adder_tree.vhd
@@ -36,7 +36,6 @@ use IEEE.numeric_std.all;
use work.common_pkg.all;
use work.tb_common_pkg.all;
-
entity tb_common_adder_tree is
generic (
g_representation : string := "SIGNED";
@@ -47,9 +46,7 @@ entity tb_common_adder_tree is
);
end tb_common_adder_tree;
-
architecture tb of tb_common_adder_tree is
-
constant clk_period : time := 10 ns;
constant c_data_vec_w : natural := g_nof_inputs * g_symbol_w;
@@ -101,9 +98,7 @@ architecture tb of tb_common_adder_tree is
signal result_expected : std_logic_vector(g_sum_w - 1 downto 0); -- expected pipelined sum
signal result_dut : std_logic_vector(g_sum_w - 1 downto 0); -- DUT sum
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
@@ -193,5 +188,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_async.vhd b/libraries/base/common/tb/vhdl/tb_common_async.vhd
index 5ca9fad4cfec9cf7e3f839a01d9b8c830cf9dfaa..e6bf4e8c47b7a208b4e4d6abfb3a60764fe56a5a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_async.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_async.vhd
@@ -35,9 +35,7 @@ use work.tb_common_pkg.all;
entity tb_common_async is
end tb_common_async;
-
architecture tb of tb_common_async is
-
constant clk_period : time := 10 ns;
constant c_delay_len : natural := 3;
@@ -52,9 +50,7 @@ architecture tb of tb_common_async is
signal out_async : std_logic;
signal out_areset : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
p_in_stimuli : process
@@ -107,5 +103,4 @@ begin
clk => clk,
out_rst => out_areset
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
index 0eb908d2109ba910b0b67fbd35da7070fc096274..27265014b5ad9e222bcebc9c4ddc8cb5d4f3ff86 100644
--- a/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_clock_phase_detector.vhd
@@ -39,9 +39,7 @@ entity tb_common_clock_phase_detector is
);
end tb_common_clock_phase_detector;
-
architecture tb of tb_common_clock_phase_detector is
-
constant c_clk_factor_num : natural := sel_a_b(g_clk_factor >= 1.0, integer(g_clk_factor), 1);
constant c_clk_factor_den : natural := sel_a_b(g_clk_factor < 1.0, integer(1.0 / g_clk_factor), 1);
@@ -66,9 +64,7 @@ architecture tb of tb_common_clock_phase_detector is
signal phase_r_det : std_logic;
signal phase_f : std_logic;
signal phase_f_det : std_logic;
-
begin
-
in_clk <= not (in_clk and in_en) or tb_end after in_clk_period / 2;
clk <= not clk or tb_end after clk_period / 2;
@@ -117,5 +113,4 @@ begin
phase => phase_f,
phase_det => phase_f_det
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_counter.vhd b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
index 945ccb8ca8effe7539d741e715b667c33a4c94db..ff4e5fd21d1e654375919064c2f6f76452eb05a3 100644
--- a/libraries/base/common/tb/vhdl/tb_common_counter.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_counter.vhd
@@ -28,7 +28,6 @@ entity tb_common_counter is
end tb_common_counter;
architecture tb of tb_common_counter is
-
constant clk_period : time := 10 ns;
constant c_cnt_init : natural := 3;
@@ -43,9 +42,7 @@ architecture tb of tb_common_counter is
signal load : std_logic_vector(c_cnt_w - 1 downto 0) := TO_UVEC(c_cnt_init, c_cnt_w);
signal count : std_logic_vector(c_cnt_w - 1 downto 0);
signal cnt_max : std_logic_vector(c_cnt_w - 1 downto 0);
-
begin
-
clk <= not clk after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
@@ -105,7 +102,4 @@ begin
load => load,
count => count
);
-
end tb;
-
-
diff --git a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
index d72f974ea3608efcf8ef1912108b1bf03200b959..c42ebccaeef4d30440159588d01a6d5368aab779 100644
--- a/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_create_strobes_from_valid.vhd
@@ -38,7 +38,6 @@ entity tb_common_create_strobes_from_valid is
end tb_common_create_strobes_from_valid;
architecture tb of tb_common_create_strobes_from_valid is
-
constant clk_period : time := 10 ns;
constant c_nof_block_per_sync_max : natural := ceil_div(g_nof_clk_per_sync, g_nof_clk_per_block);
@@ -56,9 +55,7 @@ architecture tb of tb_common_create_strobes_from_valid is
signal out_eop : std_logic;
signal out_sync : std_logic;
signal out_val_cnt : natural := 0;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
p_in_stimuli : process
@@ -138,5 +135,4 @@ begin
out_eop => out_eop,
out_sync => out_sync
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd b/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
index 662e1596a87c643d60a3d3b07aed34bb3b0ae7ee..c333692fd14602eaa911499a8f7c072ae5dde85e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_ddreg.vhd
@@ -35,9 +35,7 @@ use work.tb_common_pkg.all;
entity tb_common_ddreg_slv is
end tb_common_ddreg_slv;
-
architecture tb of tb_common_ddreg_slv is
-
constant in_clk_period : time := 5 ns;
constant c_tb_interval : natural := 100;
@@ -52,9 +50,7 @@ architecture tb of tb_common_ddreg_slv is
signal out_dat : std_logic_vector(2 * c_in_dat_w - 1 downto 0);
signal out_dat_hi : std_logic_vector(c_in_dat_w - 1 downto 0);
signal out_dat_lo : std_logic_vector(c_in_dat_w - 1 downto 0);
-
begin
-
in_clk <= not in_clk or tb_end after in_clk_period / 2;
out_clk <= not out_clk when rising_edge(in_clk);
@@ -84,5 +80,4 @@ begin
);
out_dat <= out_dat_hi & out_dat_lo;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
index 02b9ab8552e9cd32e3674f164b0efcc6ee466bad..bbd52cac8588a2a541d69c918273605e757c32f8 100644
--- a/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_debounce.vhd
@@ -45,7 +45,6 @@ entity tb_common_debounce is
end tb_common_debounce;
architecture tb of tb_common_debounce is
-
constant clk_period : time := 10 ns;
constant c_rst_level_both : std_logic := '0'; -- choose any reset level, because both levels are equivalent
@@ -66,9 +65,7 @@ architecture tb of tb_common_debounce is
signal q_high : std_logic;
signal q_both : std_logic;
signal q_low : std_logic;
-
begin
-
-- run 20 us
clk <= not clk or tb_end after clk_period / 2;
diff --git a/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd b/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
index e3f154712cc9f0e92ddf10a146e619473b048539..861bc4118fbebc6162953117875173f6d8be663c 100644
--- a/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_duty_cycle.vhd
@@ -29,7 +29,6 @@ entity tb_common_duty_cycle is
end tb_common_duty_cycle;
architecture tb of tb_common_duty_cycle is
-
constant c_clk_period : time := 10 ns;
constant c_dc_max_period_cnt : natural := 30;
@@ -43,9 +42,7 @@ architecture tb of tb_common_duty_cycle is
signal dc_out_en : std_logic;
signal dc_out : std_logic;
-
begin
-
-----------------------------------------------------------------------------
-- Stimuli
-----------------------------------------------------------------------------
@@ -130,5 +127,4 @@ begin
dc_out_en => dc_out_en,
dc_out => dc_out
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
index 3622a2762e1b171dddb781ea3017486ca97269f5..d5b732914c646908c5fe68787948e8d0aeaca8e5 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fanout_tree.vhd
@@ -47,9 +47,7 @@ entity tb_common_fanout_tree is
);
end tb_common_fanout_tree;
-
architecture tb of tb_common_fanout_tree is
-
constant clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -85,9 +83,7 @@ architecture tb of tb_common_fanout_tree is
signal ref_en_vec : std_logic_vector(g_nof_output - 1 downto 0);
signal ref_val_vec : std_logic_vector(g_nof_output - 1 downto 0);
signal ref_dat_arr : t_data_arr( g_nof_output - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
@@ -155,5 +151,4 @@ begin
end if;
end process;
end generate;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
index c250de09b6f78f3fb7eb9ced351b1d0ea3bbaebf..59082dfeef4c8bc1dd5781dee5c4cb58863e24e6 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_dc_mixed_widths.vhd
@@ -31,7 +31,6 @@ use IEEE.numeric_std.all;
use work.common_pkg.all;
use work.tb_common_pkg.all;
-
entity tb_common_fifo_dc_mixed_widths is
generic (
g_wr_clk_freq : positive := 1; -- normalized write clock frequency
@@ -42,9 +41,7 @@ entity tb_common_fifo_dc_mixed_widths is
);
end tb_common_fifo_dc_mixed_widths;
-
architecture tb of tb_common_fifo_dc_mixed_widths is
-
constant clk_period : time := 10 ns;
constant c_run_interval : natural := 2**g_wr_dat_w;
@@ -60,17 +57,13 @@ architecture tb of tb_common_fifo_dc_mixed_widths is
signal wr_ful : std_logic;
signal wr_usedw : std_logic_vector(ceil_log2(c_wr_fifo_nof_words) - 1 downto 0);
-
signal rd_clk : std_logic := '0';
signal rd_dat : std_logic_vector(g_rd_dat_w - 1 downto 0);
signal rd_req : std_logic;
signal rd_val : std_logic;
signal rd_emp : std_logic;
signal rd_usedw : std_logic_vector(ceil_log2(c_wr_fifo_nof_words * g_wr_dat_w / g_rd_dat_w) - 1 downto 0);
-
-
begin
-
rst <= '1', '0' after clk_period * 7;
wr_clk <= not wr_clk or tb_end after g_rd_clk_freq * clk_period / 2;
@@ -129,5 +122,4 @@ begin
rdusedw => rd_usedw,
rd_val => rd_val
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
index 359890d7f2f997e990b73be7bad6ab05446af2fc..ca6a2b06dc61fe3b6d1cbd86332354e23a0b5115 100644
--- a/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_fifo_rd.vhd
@@ -26,7 +26,6 @@ use work.common_pkg.all;
use work.common_lfsr_sequences_pkg.all;
use work.tb_common_pkg.all;
-
entity tb_common_fifo_rd is
generic (
g_random_control : boolean := true -- use TRUE for random rd_req control
@@ -36,7 +35,6 @@ end tb_common_fifo_rd;
-- Run -all, observe rd_dat in wave window
architecture tb of tb_common_fifo_rd is
-
constant clk_period : time := 10 ns;
constant c_dat_w : natural := 16;
constant c_fifo_rl : natural := 1; -- FIFO has RL = 1
@@ -59,9 +57,7 @@ architecture tb of tb_common_fifo_rd is
signal verify_en : std_logic := '1';
signal prev_rd_req : std_logic;
signal prev_rd_dat : std_logic_vector(c_dat_w - 1 downto 0);
-
begin
-
rst <= '1', '0' after clk_period * 7;
clk <= not clk or tb_end after clk_period / 2;
tb_end <= '0', '1' after 20 us;
@@ -81,7 +77,6 @@ begin
-- Verify dut output stream ready - valid relation, prev_rd_req is an auxiliary signal needed by the proc
proc_common_verify_valid(c_read_rl, clk, verify_en, rd_req, prev_rd_req, rd_val);
-
u_dut : entity work.common_fifo_rd
generic map (
g_dat_w => c_dat_w
@@ -98,5 +93,4 @@ begin
rd_dat => rd_dat,
rd_val => rd_val
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd b/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
index 46fb3f4e277fb6111dce98e1e51e7a47158f6748..4a83e2948f94468b7774b9c71d3b7244063d25b2 100644
--- a/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_flank_to_pulse.vhd
@@ -28,16 +28,13 @@ entity tb_common_flank_to_pulse is
end tb_common_flank_to_pulse;
architecture tb of tb_common_flank_to_pulse is
-
constant clk_period : time := 10 ns;
signal rst : std_logic;
signal clk : std_logic := '0';
signal flank_in : std_logic;
signal pulse_out : std_logic;
-
begin
-
clk <= not clk after clk_period / 2;
p_in_stimuli : process
@@ -64,5 +61,4 @@ begin
flank_in => flank_in,
pulse_out => pulse_out
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
index c87848367e2fb8cebc991a0e5c40c3e5bc09612b..2acc79d324a88d3e76b47d8984d2dc304d8a1e0a 100644
--- a/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_gcd.vhd
@@ -33,9 +33,7 @@ entity tb_common_gcd is
end tb_common_gcd;
architecture tb of tb_common_gcd is
-
begin
-
assert gcd( 0, 10) = 10 report "Wrong gcd( 0, 10)" severity ERROR;
assert gcd( 1, 1) = 1 report "Wrong gcd( 1, 1)" severity ERROR;
assert gcd(10, 1) = 1 report "Wrong gcd(10, 1)" severity ERROR;
@@ -46,5 +44,4 @@ begin
assert gcd(15, 5) = 5 report "Wrong gcd(15, 5)" severity ERROR;
assert gcd(17, 17) = 17 report "Wrong gcd(17, 17)" severity ERROR;
assert gcd(17, 4) = 1 report "Wrong gcd(17, 4)" severity ERROR;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_init.vhd b/libraries/base/common/tb/vhdl/tb_common_init.vhd
index 5c6503ab7cb5cdf16895cbc13e6ff688b0212236..04488cf09601e7ff617f3ebb9eb48547810a22a5 100644
--- a/libraries/base/common/tb/vhdl/tb_common_init.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_init.vhd
@@ -28,7 +28,6 @@ entity tb_common_init is
end tb_common_init;
architecture tb of tb_common_init is
-
constant c_reset_len : natural := 3;
constant c_latency_w : natural := 4;
@@ -38,9 +37,7 @@ architecture tb of tb_common_init is
signal clk : std_logic := '0';
signal hold : std_logic;
signal init : std_logic;
-
begin
-
clk <= not clk after clk_period / 2;
u_reset : entity work.common_areset
@@ -64,5 +61,4 @@ begin
hold => hold,
init => init
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
index bc1482793c7b1ee98a83ce7f2f3d10ea81f4a7de..507ce94cc18fa3fec3f1ba96fe11e5b77d49d721 100644
--- a/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_int2float.vhd
@@ -7,7 +7,6 @@ entity tb_common_int2float is
end tb_common_int2float;
architecture tb of tb_common_int2float is
-
constant clk_period : time := 10 ns;
-- use smaller values to ease use of 32 bit integers
@@ -37,9 +36,7 @@ architecture tb of tb_common_int2float is
signal nxt_out_dat_value : integer;
signal out_exp_value : std_logic := '0';
signal out_diff_value : integer := 0;
-
begin
-
clk <= not clk after clk_period / 2;
p_dly : process(clk)
@@ -94,5 +91,4 @@ begin
in_dat => in_dat,
out_dat => out_dat
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
index fcc72043a2f861cbb85643aeb39d527321b6a136..48aad92238cd56c41c2075e933483188d60eb988 100644
--- a/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_iobuf_in.vhd
@@ -19,7 +19,6 @@
--
-------------------------------------------------------------------------------
-
-- Usage:
-- > as 10
-- > run 10 us
@@ -34,7 +33,6 @@ entity tb_common_iobuf_in is
end tb_common_iobuf_in;
architecture tb of tb_common_iobuf_in is
-
constant clk_period : time := 10 ns;
constant c_width : natural := 8;
@@ -47,9 +45,7 @@ architecture tb of tb_common_iobuf_in is
signal in_dat : std_logic_vector(c_width - 1 downto 0) := (others => '0');
signal out_dat : std_logic_vector(c_width - 1 downto 0);
-
begin
-
clk <= not clk after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -66,5 +62,4 @@ begin
in_dat => in_dat,
out_dat => out_dat
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
index 4eb4886d2ff5280e988df8029411b104d6bb2522..3934f37a7c894d0f54dd11c524adf3e3442c4466 100644
--- a/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_led_controller.vhd
@@ -39,7 +39,6 @@ entity tb_common_led_controller is
end tb_common_led_controller;
architecture tb of tb_common_led_controller is
-
constant c_pulse_us : natural := 10;
constant c_1000 : natural := 10; -- use eg 10 instead of 1000 to speed up simulation
constant c_led_nof_ms : natural := 3;
@@ -60,9 +59,7 @@ architecture tb of tb_common_led_controller is
signal dbg_evt : natural;
signal LED : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -123,7 +120,6 @@ begin
out_dat => toggle_ms
);
-
u_common_led_controller : entity work.common_led_controller
generic map (
g_nof_ms => c_led_nof_ms
@@ -139,5 +135,4 @@ begin
-- led output
led => LED
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_log.vhd b/libraries/base/common/tb/vhdl/tb_common_log.vhd
index 1e7937f5731438ceee15caf4a3f9a8d88d55ed81..a93bcbce954186193242527335308a3e5cad1243 100644
--- a/libraries/base/common/tb/vhdl/tb_common_log.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_log.vhd
@@ -31,7 +31,6 @@ end tb_common_log;
architecture tb of tb_common_log is
begin
-
p_log : process
constant c_range : t_integer_arr := (99, 100, 101, 127, 128, 129);
variable vI : natural;
@@ -65,5 +64,4 @@ begin
end loop;
wait;
end process;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
index 0a4b58aee9c866025c41d598c663533a6cd5e644..76794c62a8d87f21ef51923b4c998ac31900e934 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_mux.vhd
@@ -38,9 +38,7 @@ end tb_common_mem_mux;
-- > as 10
-- > run -all
-
architecture tb of tb_common_mem_mux is
-
constant clk_period : time := 10 ns;
constant c_data_w : natural := 32;
@@ -57,9 +55,7 @@ architecture tb of tb_common_mem_mux is
signal miso_arr : t_mem_miso_arr(g_nof_mosi - 1 downto 0);
signal mosi : t_mem_mosi;
signal miso : t_mem_miso;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 5;
@@ -122,5 +118,4 @@ begin
mosi => mosi,
miso => miso
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
index e03840a5344aab212ecbefb7bc347793f69995ea..94e5f10bbfb7a530bd28415974f67c6a6872c6fe 100644
--- a/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_mem_pkg.vhd
@@ -25,9 +25,7 @@ use IEEE.std_logic_1164.all;
use work.common_pkg.all;
use work.common_mem_pkg.all;
-
package tb_common_mem_pkg is
-
------------------------------------------------------------------------------
-- MM bus access functions
------------------------------------------------------------------------------
@@ -96,12 +94,9 @@ package tb_common_mem_pkg is
signal mm_mosi : out t_mem_mosi;
signal mm_miso : in t_mem_miso;
signal data_arr : out t_slv_32_arr);
-
end tb_common_mem_pkg;
-
package body tb_common_mem_pkg is
-
------------------------------------------------------------------------------
-- Private functions
------------------------------------------------------------------------------
@@ -175,7 +170,6 @@ package body tb_common_mem_pkg is
proc_mm_access(mm_clk, mm_mosi.wr);
end proc_mem_mm_bus_wr;
-
-- Read data request to the MM bus
-- Use proc_mem_mm_bus_rd_latency() to wait for the MM MISO rd_data signal
-- to show the data after some read latency
@@ -204,7 +198,6 @@ package body tb_common_mem_pkg is
for I in 0 to c_rd_latency - 1 loop wait until rising_edge(mm_clk); end loop;
end proc_mem_mm_bus_rd_latency;
-
-- Write array of data words to the memory
procedure proc_mem_write_ram(constant offset : in natural;
constant nof_data : in natural;
diff --git a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
index e579fe51f6c07d29edcb11f66bd2f11d849ff95a..f07dd4db303e5d24c65f76b4c677f1a9cc2c8085 100644
--- a/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_multiplexer.vhd
@@ -50,7 +50,6 @@ entity tb_common_multiplexer is
end tb_common_multiplexer;
architecture tb of tb_common_multiplexer is
-
constant clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -91,9 +90,7 @@ architecture tb of tb_common_multiplexer is
signal prev_out_dat : std_logic_vector(g_dat_w - 1 downto 0);
signal pipe_dat_vec : std_logic_vector(0 to (c_pipeline_total + 1) * g_dat_w - 1);
signal pipe_val_vec : std_logic_vector(0 to (c_pipeline_total + 1) * 1 - 1);
-
begin
-
------------------------------------------------------------------------------
-- Stimuli
------------------------------------------------------------------------------
@@ -184,7 +181,6 @@ begin
out_val => out_val
);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -192,5 +188,4 @@ begin
proc_common_verify_data(c_rl, clk, verify_en, ready, out_val, out_dat, prev_out_dat); -- verify out_dat assuming incrementing data
proc_common_verify_latency("data", c_pipeline_total, clk, verify_en, in_dat, pipe_dat_vec, out_dat); -- verify out_dat using delayed input
proc_common_verify_latency("valid", c_pipeline_total, clk, verify_en, in_val, pipe_val_vec, out_val); -- verify out_val using delayed input
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
index 3c38959ed582fed1e7699c00772996590a62c3c3..255bb24dd4a17b7baa968cc131b13373a62edccf 100644
--- a/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_operation_tree.vhd
@@ -35,7 +35,6 @@ use work.common_pkg.all;
use work.common_lfsr_sequences_pkg.all;
use work.tb_common_pkg.all;
-
entity tb_common_operation_tree is
generic (
g_operation : string := "MAX"; -- supported operations "MAX", "MIN"
@@ -46,9 +45,7 @@ entity tb_common_operation_tree is
);
end tb_common_operation_tree;
-
architecture tb of tb_common_operation_tree is
-
constant clk_period : time := 10 ns;
constant c_dat_w : natural := 8;
@@ -124,9 +121,7 @@ architecture tb of tb_common_operation_tree is
signal result : std_logic_vector(c_dat_w - 1 downto 0); -- dut result
signal expected : std_logic_vector(c_dat_w - 1 downto 0); -- expected pipelined result
signal expected_val : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
@@ -228,5 +223,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
index c5d8fe20ffc60956aeb650c477820b5e87248684..ae4a886e08c4f51afa526f2c194d00ee358f71be 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_crw_crw.vhd
@@ -37,12 +37,10 @@ use work.tb_common_pkg.all;
-- > as 10
-- > run -all
-
entity tb_common_paged_ram_crw_crw is
end tb_common_paged_ram_crw_crw;
architecture tb of tb_common_paged_ram_crw_crw is
-
constant clk_period : time := 10 ns;
constant c_data_w : natural := 8;
@@ -85,9 +83,7 @@ architecture tb of tb_common_paged_ram_crw_crw is
signal prev_mux_rd_dat_b : std_logic_vector(c_data_w - 1 downto 0);
signal prev_adr_rd_dat_b : std_logic_vector(c_data_w - 1 downto 0);
signal prev_ofs_rd_dat_b : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= not clk and not tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -239,5 +235,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
index 1f160763464e09e3ce4ada805d42162983900da4..5b632a2f4c0e81444eba462f60002dd8d5d24a98 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_ww_rr.vhd
@@ -38,7 +38,6 @@ use work.tb_common_pkg.all;
-- > as 10
-- > run -all
-
entity tb_common_paged_ram_ww_rr is
generic (
g_pipeline_in : natural := 0; -- >= 0
@@ -48,7 +47,6 @@ entity tb_common_paged_ram_ww_rr is
end tb_common_paged_ram_ww_rr;
architecture tb of tb_common_paged_ram_ww_rr is
-
constant clk_period : time := 10 ns;
constant c_nof_blocks : natural := 4;
@@ -118,9 +116,7 @@ architecture tb of tb_common_paged_ram_ww_rr is
signal wwrr_result_dat_b : std_logic_vector(c_data_w - 1 downto 0);
signal prev_wwrr_result_dat_a : std_logic_vector(c_data_w - 1 downto 0);
signal prev_wwrr_result_dat_b : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= not clk and not tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 2;
@@ -274,5 +270,4 @@ begin
-- Double write - double read:
proc_common_verify_data(c_rl, clk, verify_en, ready, wwrr_rd_val_a, wwrr_result_dat_a, prev_wwrr_result_dat_a);
proc_common_verify_data(c_rl, clk, verify_en, ready, wwrr_rd_val_b, wwrr_result_dat_b, prev_wwrr_result_dat_b);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
index fe6d6b34151a1af170c2b2377a8aa55aece71529..de11904870898ab5668afb9fe86fa7601b1e149f 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pkg.vhd
@@ -36,9 +36,7 @@ use std.textio.all; -- for boolean, integer file IO
use IEEE.std_logic_textio.all; -- for std_logic, std_logic_vector file IO
use work.common_pkg.all;
-
package tb_common_pkg is
-
-- Constants
-- For common_reg_r_w_dc.vhd with c_meta_delay_len = 3 and internal g_readback = TRUE a
@@ -48,7 +46,6 @@ package tb_common_pkg is
-- = c_common_cross_clock_domain_latency * 2.
constant c_common_cross_clock_domain_latency : natural := 20;
-
-- Wait for some time or until
procedure proc_common_wait_some_cycles(signal clk : in std_logic;
c_nof_cycles : in natural);
@@ -129,7 +126,6 @@ package tb_common_pkg is
procedure proc_common_timeout_failure(constant c_timeout : in time;
signal tb_end : in std_logic);
-
-- Stop simulation using severity FAILURE when g_tb_end=TRUE, else for use in multi tb report as severity NOTE
procedure proc_common_stop_simulation(signal tb_end : in std_logic);
@@ -151,7 +147,6 @@ package tb_common_pkg is
signal ready : in std_logic;
signal out_valid : out std_logic);
-
-- Wait for clock domain crossing latency, e.g. for MM readback after MM write
procedure proc_common_wait_cross_clock_domain_latency(signal mm_clk : in std_logic;
signal st_clk : in std_logic;
@@ -339,12 +334,9 @@ package tb_common_pkg is
function func_find_char_in_string(in_string: string; find_char: character) return integer;
function func_find_string_in_string(in_string: string; find_string: string) return boolean;
-
end tb_common_pkg;
-
package body tb_common_pkg is
-
------------------------------------------------------------------------------
-- PROCEDURE: Wait some clock cycles
------------------------------------------------------------------------------
@@ -833,7 +825,6 @@ package body tb_common_pkg is
proc_common_gen_data(c_rl, c_init, 1, rst, clk, enable, ready, out_data, out_valid);
end proc_common_gen_data;
-
------------------------------------------------------------------------------
-- PROCEDURE: Generate frame control
------------------------------------------------------------------------------
@@ -889,7 +880,6 @@ package body tb_common_pkg is
proc_common_wait_some_cycles(clk, c_flush_len);
end proc_common_eop_flush;
-
------------------------------------------------------------------------------
-- PROCEDURE: Verify incrementing data
------------------------------------------------------------------------------
@@ -918,7 +908,6 @@ package body tb_common_pkg is
end if;
end proc_common_verify_data;
-
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT output valid
-- . only support ready latency c_rl = 0 or 1
@@ -945,7 +934,6 @@ package body tb_common_pkg is
end if;
end proc_common_verify_valid;
-
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT input to output latency
------------------------------------------------------------------------------
@@ -974,7 +962,6 @@ package body tb_common_pkg is
end if;
end proc_common_verify_latency;
-
-- for SLV data
procedure proc_common_verify_latency(constant c_str : in string; -- e.g. "data"
constant c_latency : in natural;
@@ -1181,7 +1168,6 @@ package body tb_common_pkg is
end if;
end proc_common_readline_file;
-
------------------------------------------------------------------------------
-- PROCEDURE: Closes a file.
------------------------------------------------------------------------------
@@ -1443,4 +1429,3 @@ package body tb_common_pkg is
end function func_find_string_in_string;
end tb_common_pkg;
-
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
index 0743eff398a0c01e87c0364527c210a9b7129c2f..5a9bddeddedb9ae751ca72a87ba36627f5e2c3b8 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_delay.vhd
@@ -38,7 +38,6 @@ entity tb_common_pulse_delay is
end tb_common_pulse_delay;
architecture tb of tb_common_pulse_delay is
-
-----------------------------------------------------------------------------
-- common_pulse_delay parameters
-----------------------------------------------------------------------------
@@ -83,9 +82,7 @@ architecture tb of tb_common_pulse_delay is
signal nxt_pulse_delay_reg : std_logic_vector(c_pulse_delay_max_w - 1 downto 0);
signal nxt_pulse_count : natural;
signal nxt_pulse_delay_count : natural;
-
begin
-
-----------------------------------------------------------------------------
-- Clock & reset
-----------------------------------------------------------------------------
@@ -164,6 +161,4 @@ begin
pulse_delay_count <= nxt_pulse_delay_count;
end if;
end process;
-
end tb;
-
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd b/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
index 57b2c858be8c1d1bbf37091e7ef06e0b5ab89862..514326c77b65fcf2a9d36af9e687916ea7ab87dd 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulse_extend.vhd
@@ -33,7 +33,6 @@ entity tb_common_pulse_extend is
end tb_common_pulse_extend;
architecture tb of tb_common_pulse_extend is
-
constant clk_period : time := 10 ns;
constant c_extend_w : natural := 3;
@@ -45,9 +44,7 @@ architecture tb of tb_common_pulse_extend is
signal clk : std_logic := '0';
signal pulse_in : std_logic;
signal pulse_out : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
p_in_stimuli : process
@@ -86,5 +83,4 @@ begin
p_in => pulse_in,
ep_out => pulse_out
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
index e66980b99633df9cd80a65765ffa323b9dd4eed1..4dec90a01d91961ed20959663c2c3cf99dde740f 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser.vhd
@@ -29,7 +29,6 @@ entity tb_common_pulser is
end tb_common_pulser;
architecture tb of tb_common_pulser is
-
constant clk_period : time := 40 ns;
constant c_reset_len : natural := 3;
@@ -45,9 +44,7 @@ architecture tb of tb_common_pulser is
signal pulse_ms_via_pulse_en : std_logic;
signal pulse_ms_clr : std_logic;
-
begin
-
-- as 3
-- run 7 ms
@@ -118,5 +115,4 @@ begin
pulse_clr => pulse_ms_clr,
pulse_out => pulse_ms_via_pulse_en
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
index 73b51cfc433bfdf763d5ba16ba9d719744643581..7f99b1261041ed636b8ed5cf4dce8255d9cec6f7 100644
--- a/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_pulser_us_ms_s.vhd
@@ -38,7 +38,6 @@ entity tb_common_pulser_us_ms_s is
end tb_common_pulser_us_ms_s;
architecture tb of tb_common_pulser_us_ms_s is
-
constant c_pulse_us : natural := 10;
constant c_1000 : natural := 10; -- use eg 10 instead of 1000 to speed up simulation
@@ -52,9 +51,7 @@ architecture tb of tb_common_pulser_us_ms_s is
signal pulse_us : std_logic;
signal pulse_ms : std_logic;
signal pulse_s : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -105,5 +102,4 @@ begin
pulse_ms => pulse_ms, -- pulses after every g_pulse_us*g_pulse_ms clock cycles
pulse_s => pulse_s -- pulses after every g_pulse_us*g_pulse_ms*g_pulse_s clock cycles
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
index b1d3dbe6d1dea79a278b412deba84dffcfef0ecf..5cdd3da0d1cc1fbe34409b08b9119736c56381ab 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reg_cross_domain.vhd
@@ -28,7 +28,6 @@ entity tb_common_reg_cross_domain is
end tb_common_reg_cross_domain;
architecture tb of tb_common_reg_cross_domain is
-
--CONSTANT in_clk_period : TIME := 10 ns;
constant in_clk_period : time := 17 ns;
constant out_clk_period : time := 17 ns;
@@ -58,9 +57,7 @@ architecture tb of tb_common_reg_cross_domain is
signal in_dat : std_logic_vector(c_dat_w - 1 downto 0);
signal out_dat : std_logic_vector(c_dat_w - 1 downto 0);
signal out_new : std_logic;
-
begin
-
in_clk <= not in_clk after in_clk_period / 2;
out_clk <= not out_clk after out_clk_period / 2;
@@ -132,5 +129,4 @@ begin
out_dat => out_dat,
out_new => out_new -- when '1' then the out_dat was updated with in_dat due to in_new
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
index e6aaf8a6fc425a6b57f1a84be27eadd5cb00cab2..842665e03eaef6b8cf5ee40cc701ac970ca4d0ff 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reinterleave.vhd
@@ -44,7 +44,6 @@ entity tb_common_reinterleave is
end;
architecture rtl of tb_common_reinterleave is
-
type t_dat_arr is array (integer range <>) of std_logic_vector(g_dat_w - 1 downto 0);
type t_val_arr is array (integer range <>) of std_logic;
@@ -96,9 +95,7 @@ architecture rtl of tb_common_reinterleave is
-- REVERSE FUNCTION output array
signal rev_out_dat_arr : t_dat_arr(g_nof_in - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Standard TB clocking, RST and control
-----------------------------------------------------------------------------
@@ -200,5 +197,4 @@ begin
rev_out_dat_arr(i) <= rev_out_dat( i * g_dat_w + g_dat_w - 1 downto i * g_dat_w);
end generate;
-
end rtl;
diff --git a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
index 5d6a184eb845bdc66bb6d29f1480158b4905368b..a2e3cb2e3b6db3b0c8b783dabb56c78052c1d16e 100644
--- a/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_reorder_symbol.vhd
@@ -59,7 +59,6 @@ entity tb_common_reorder_symbol is
end tb_common_reorder_symbol;
architecture tb of tb_common_reorder_symbol is
-
constant clk_period : time := 10 ns;
-- Stimuli constants
@@ -120,9 +119,7 @@ architecture tb of tb_common_reorder_symbol is
signal exp_sop : std_logic;
signal exp_eop : std_logic;
signal exp_sync : std_logic;
-
begin
-
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
@@ -315,5 +312,4 @@ begin
in_dat => in_sync,
out_dat => exp_sync
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
index 9976c8b1568069c56605b782e39bdca532ee5629..2eb0d6329b4ee81480ef6c1b11b5a7ffaa7711c3 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl.vhd
@@ -44,7 +44,6 @@ use work.common_pkg.all;
use work.common_lfsr_sequences_pkg.all;
use work.tb_common_pkg.all;
-
entity tb_common_rl is
generic (
g_nof_blocks : natural := 1000; -- nof blocks to simulate
@@ -60,7 +59,6 @@ end tb_common_rl;
-- Run 20 us, observe src_out_dat in wave window
architecture tb of tb_common_rl is
-
constant clk_period : time := 10 ns;
constant c_dat_w : natural := 16;
@@ -112,9 +110,7 @@ architecture tb of tb_common_rl is
signal prev_rl_decrease_out_dat : std_logic_vector(c_dat_w - 1 downto 0);
signal prev_rl_increase_in_ready : std_logic;
signal prev_rl_increase_out_dat : std_logic_vector(c_dat_w - 1 downto 0);
-
begin
-
rst <= '1', '0' after clk_period * 7;
clk <= not clk or tb_end after clk_period / 2;
@@ -134,7 +130,6 @@ begin
-- Generate FIFO input with c_gen_rl = 1 and counter data starting at 0
proc_common_gen_data(c_gen_rl, 0, rst, clk, enable, fifo_out_ready, fifo_in_dat, fifo_in_val);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -148,7 +143,6 @@ begin
proc_common_verify_valid(c_rl_decrease_rl, clk, verify_en, rl_decrease_in_ready, prev_rl_decrease_in_ready, rl_decrease_out_val);
proc_common_verify_valid(c_rl_increase_rl, clk, verify_en, rl_increase_in_ready, prev_rl_increase_in_ready, rl_increase_out_val);
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -196,7 +190,6 @@ begin
src_out_val => rl_decrease_out_val
);
-
-- RL 0 --> 1
u_rl_increase : entity work.common_rl_increase
generic map (
@@ -216,5 +209,4 @@ begin
src_out_dat => rl_increase_out_dat,
src_out_val => rl_increase_out_val
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
index badacc5236eb9272f7f7e7d6e77c87c7ffaf07dd..f6a168912820278e61ea99cf63f3ae8d3dc15bde 100644
--- a/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_rl_register.vhd
@@ -36,7 +36,6 @@ use work.common_pkg.all;
use work.common_lfsr_sequences_pkg.all;
use work.tb_common_pkg.all;
-
entity tb_common_rl_register is
generic (
g_nof_blocks : natural := 1000; -- nof blocks to simulate
@@ -51,7 +50,6 @@ end tb_common_rl_register;
-- Run 20 us, observe src_out_dat in wave window
architecture tb of tb_common_rl_register is
-
constant clk_period : time := 10 ns;
constant c_dat_w : natural := 16;
@@ -93,9 +91,7 @@ architecture tb of tb_common_rl_register is
signal prev_fifo_out_dat : std_logic_vector(c_dat_w - 1 downto 0);
signal prev_rl_register_in_ready : std_logic;
signal prev_rl_register_out_dat : std_logic_vector(c_dat_w - 1 downto 0);
-
begin
-
rst <= '1', '0' after clk_period * 7;
clk <= not clk or tb_end after clk_period / 2;
@@ -115,7 +111,6 @@ begin
-- Generate FIFO input with c_gen_rl = 1 and counter data starting at 0
proc_common_gen_data(c_gen_rl, 0, rst, clk, enable, fifo_out_ready, fifo_in_dat, fifo_in_val);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -127,7 +122,6 @@ begin
proc_common_verify_valid(c_fifo_rl, clk, verify_en, fifo_in_ready, prev_fifo_in_ready, fifo_out_val);
proc_common_verify_valid(c_rl_register_rl, clk, verify_en, rl_register_in_ready, prev_rl_register_in_ready, rl_register_out_val);
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -175,5 +169,4 @@ begin
src_out_dat => rl_register_out_dat,
src_out_val => rl_register_out_val
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
index d7aca1f8176da8e3e02a8f0cc5826402448cf0f2..5fc43a60f2effd7296ebfdefaa345d0a7e5ac0e3 100644
--- a/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_select_m_symbols.vhd
@@ -48,7 +48,6 @@ entity tb_common_select_m_symbols is
end tb_common_select_m_symbols;
architecture tb of tb_common_select_m_symbols is
-
constant clk_period : time := 10 ns;
-- Stimuli constants
@@ -103,9 +102,7 @@ architecture tb of tb_common_select_m_symbols is
signal exp_sop : std_logic;
signal exp_eop : std_logic;
signal exp_sync : std_logic;
-
begin
-
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
@@ -267,5 +264,4 @@ begin
in_dat => in_sync,
out_dat => exp_sync
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
index a177c30446e6986dd4c579d924c66f7adea4bead..14f400a91f88f8431654ee96caa00765690b2398 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftram.vhd
@@ -43,7 +43,6 @@ entity tb_common_shiftram is
end tb_common_shiftram;
architecture tb of tb_common_shiftram is
-
constant clk_period : time := 10 ns;
constant c_shift_w : natural := ceil_log2(g_nof_words);
@@ -69,9 +68,7 @@ architecture tb of tb_common_shiftram is
signal ver_data_toggle : std_logic;
signal ver_data_en : std_logic;
signal ver_data_rdy : std_logic := '1';
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
@@ -162,5 +159,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
index 6ef434b87dced6fd68bb1a822c42508e2a5e9dd7..306d94849f22786bb7666f0ca151d0a51fe9b173 100644
--- a/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_shiftreg.vhd
@@ -41,7 +41,6 @@ entity tb_common_shiftreg is
end tb_common_shiftreg;
architecture tb of tb_common_shiftreg is
-
constant clk_period : time := 10 ns;
constant c_cnt_w : natural := ceil_log2(g_nof_dat);
@@ -78,9 +77,7 @@ architecture tb of tb_common_shiftreg is
signal verify_en : std_logic := '0';
signal ready : std_logic := '1';
signal prev_out_dat : std_logic_vector(g_dat_w - 1 downto 0) := (others => '1');
-
begin
-
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
@@ -187,5 +184,4 @@ begin
-- Verification
proc_common_verify_data(1, clk, verify_en, ready, out_val, out_dat, prev_out_dat);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_spulse.vhd b/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
index c8e5d4a023aaf7be879d47f573758b647b57ef0f..70dfeed5e020ecfcb2ecce4ef8e520fb893d4348 100644
--- a/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_spulse.vhd
@@ -35,7 +35,6 @@ entity tb_common_spulse is
end tb_common_spulse;
architecture tb of tb_common_spulse is
-
constant c_meta_delay : natural := 2;
--CONSTANT in_clk_period : TIME := 10 ns;
@@ -48,9 +47,7 @@ architecture tb of tb_common_spulse is
signal out_clk : std_logic := '0';
signal in_pulse : std_logic;
signal out_pulse : std_logic;
-
begin
-
in_clk <= not in_clk after in_clk_period / 2;
out_clk <= not out_clk after out_clk_period / 2;
@@ -88,5 +85,4 @@ begin
out_rst => out_rst,
out_pulse => out_pulse
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_switch.vhd b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
index 9200eaae3176aabbe0875670a6d371efea700f69..457290cb5c787750f4466b1c972a8bd425fbcab8 100644
--- a/libraries/base/common/tb/vhdl/tb_common_switch.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_switch.vhd
@@ -40,9 +40,7 @@ end tb_common_switch;
-- . g_or_high
-- . g_and_low
-
architecture tb of tb_common_switch is
-
constant clk_period : time := 10 ns;
constant c_nof_generics : natural := 3;
@@ -77,9 +75,7 @@ architecture tb of tb_common_switch is
signal dbg_prio_hi_or_and : std_logic;
signal out_level : std_logic_vector(0 to c_nof_dut - 1);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
p_in_stimuli : process
diff --git a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
index fa6aae58d7b45da35c9ec41c4c78e2863bce5f88..30de6415c851352612305aeb5f88fc3e38221e26 100644
--- a/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_to_sreal.vhd
@@ -46,12 +46,10 @@ use IEEE.std_logic_1164.all;
use IEEE.math_real.all;
use work.common_pkg.all;
-
entity tb_common_to_sreal is
end tb_common_to_sreal;
architecture tb of tb_common_to_sreal is
-
constant clk_period : time := 10 ns;
constant c_resolution_w : natural := 5;
@@ -76,9 +74,7 @@ architecture tb of tb_common_to_sreal is
begin
for I in 0 to c_nof_cycles - 1 loop wait until rising_edge(clk); end loop;
end proc_wait_some_cycles;
-
begin
-
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
diff --git a/libraries/base/common/tb/vhdl/tb_common_toggle.vhd b/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
index b1eb5283aed1e26b0e2bbe73178365b1f4e820b3..fb66383f1a555d8d0fc05702fec2f6a3db27fd37 100644
--- a/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_toggle.vhd
@@ -19,7 +19,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Test bench for common_toggle.vhd
-- Usage:
-- > as 10
@@ -35,7 +34,6 @@ entity tb_common_toggle is
end tb_common_toggle;
architecture tb of tb_common_toggle is
-
constant clk_period : time := 10 ns;
constant c_nof_toggles : natural := 5;
@@ -46,9 +44,7 @@ architecture tb of tb_common_toggle is
signal in_dat : std_logic;
signal in_val : std_logic;
signal out_toggle : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 7 * clk_period;
@@ -112,5 +108,4 @@ begin
in_val => in_val,
out_dat => out_toggle
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd b/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
index b8658765ef81cbeb155592dbfdf8d8d8b2e683d8..e1509488886a238b53c5689b7f54435171269abe 100644
--- a/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_toggle_align.vhd
@@ -35,7 +35,6 @@ entity tb_common_toggle_align is
end tb_common_toggle_align;
architecture tb of tb_common_toggle_align is
-
constant clk_period : time := 10 ns;
constant c_interval : natural := 10;
@@ -49,9 +48,7 @@ architecture tb of tb_common_toggle_align is
signal in_align : std_logic;
signal in_toggle : std_logic;
signal out_toggle : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 7 * clk_period;
@@ -140,5 +137,4 @@ begin
in_toggle => in_toggle,
out_toggle => out_toggle
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
index 176ebc3051b585444cca0693402d8804ef40974f..922093695f4ad3b5ecea723503355b9ca98df9f0 100644
--- a/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_transpose.vhd
@@ -46,7 +46,6 @@ entity tb_common_transpose is
end tb_common_transpose;
architecture tb of tb_common_transpose is
-
constant clk_period : time := 10 ns;
constant c_pipeline : natural := g_pipeline_shiftreg + g_pipeline_transpose + g_pipeline_select;
@@ -104,9 +103,7 @@ architecture tb of tb_common_transpose is
signal ready : std_logic := '1';
signal prev_out_addr : std_logic_vector(g_addr_w - 1 downto 0) := (others => '1');
signal prev_out_data : std_logic_vector(g_data_w - 1 downto 0) := (others => '1');
-
begin
-
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
@@ -265,5 +262,4 @@ begin
-- Verification p_verify
proc_common_verify_data(1, clk, verify_en, ready, out_val, out_addr, prev_out_addr);
proc_common_verify_data(1, clk, verify_en, ready, out_val, out_data, prev_out_data);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd b/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
index 9dd8ce887d7ee83b3446e2f75b4d9bd4343f3040..7bef3d07b04b22a23836855cf1c84aa3fc1f7a41 100644
--- a/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_transpose_symbol.vhd
@@ -39,7 +39,6 @@ entity tb_common_transpose_symbol is
end tb_common_transpose_symbol;
architecture tb of tb_common_transpose_symbol is
-
constant clk_period : time := 10 ns;
constant c_symbol_w : natural := g_data_w / g_nof_data;
@@ -75,9 +74,7 @@ architecture tb of tb_common_transpose_symbol is
signal exp_sop : std_logic;
signal exp_eop : std_logic;
signal exp_data_vec : std_logic_vector(g_nof_data * g_data_w - 1 downto 0);
-
begin
-
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
@@ -204,5 +201,4 @@ begin
in_dat => in_eop,
out_dat => exp_eop
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
index fa8c3c137ffc8fd9b70873fb81ebadf5729354cb..e83313ab6c22d2cff4fc02624756da9f8a84821d 100644
--- a/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_variable_delay.vhd
@@ -25,7 +25,6 @@
-- . see common_variable_delay
-- --------------------------------------------------------------------------
-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -37,7 +36,6 @@ entity tb_common_variable_delay is
end tb_common_variable_delay;
architecture tb of tb_common_variable_delay is
-
constant c_clk_period : time := 10 ns;
constant c_trigger_interval : natural := 40; -- in clk's
constant c_trigger_latency : natural := 1; -- in clk's
@@ -61,9 +59,7 @@ architecture tb of tb_common_variable_delay is
-- and when the delay is not busy
signal triggers_cnt : natural := 0;
signal exp_triggers_cnt : natural := c_delay_arr'length;
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 4;
@@ -118,7 +114,4 @@ begin
in_pulse => trigger,
out_pulse => trigger_dly
);
-
end tb;
-
-
diff --git a/libraries/base/common/tb/vhdl/tb_common_zip.vhd b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
index ad0e3a4497f20437cf2e65b9ba0b6b600d9812c4..5dd2390947c3888e8d984f4ca02987e3f5e12370 100644
--- a/libraries/base/common/tb/vhdl/tb_common_zip.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_zip.vhd
@@ -35,7 +35,6 @@ use work.common_pkg.all;
use work.common_lfsr_sequences_pkg.all;
use work.tb_common_pkg.all;
-
entity tb_common_zip is
generic (
g_nof_streams : natural := 3; -- Number of input streams to be zipped
@@ -43,9 +42,7 @@ entity tb_common_zip is
);
end tb_common_zip;
-
architecture tb of tb_common_zip is
-
constant clk_period : time := 10 ns;
constant c_rl : natural := 1; -- Read Latency = 1
@@ -62,7 +59,6 @@ architecture tb of tb_common_zip is
signal ena_mask : std_logic := '1';
signal enable : std_logic := '1';
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 7 * clk_period;
tb_end <= '0', '1' after 1 us;
@@ -92,6 +88,4 @@ begin
out_val => out_val,
out_dat => out_dat
);
-
end tb;
-
diff --git a/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd b/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
index 062ea3a05baf744ff60756492195adc29275fcd1..352ac9ae479ec356510e109d8fa68a7e444f5cba 100644
--- a/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
+++ b/libraries/base/common/tb/vhdl/tb_delta_cycle_demo.vhd
@@ -89,12 +89,10 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity tb_delta_cycle_demo is
end tb_delta_cycle_demo;
architecture tb of tb_delta_cycle_demo is
-
constant clk_period : time := 10 ns;
signal tb_end : std_logic := '0';
@@ -103,9 +101,7 @@ architecture tb of tb_delta_cycle_demo is
signal data : std_logic := '0';
signal d1 : std_logic;
signal d2 : std_logic;
-
begin
-
-- Stimuli
clk1 <= not clk1 or tb_end after clk_period / 2;
clk2 <= clk1;
@@ -133,5 +129,4 @@ begin
end process;
tb_end <= '0', '1' after 1 us;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
index d5ad7b2d0b41075346f7967a624c260e88da309e..93022fd6a2b4ad09ec80851a04d49f1816a61e74 100644
--- a/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
+++ b/libraries/base/common/tb/vhdl/tb_mms_common_variable_delay.vhd
@@ -106,6 +106,4 @@ begin
trigger => trigger,
trigger_dly => trigger_dly
);
-
end tb;
-
diff --git a/libraries/base/common/tb/vhdl/tb_requantize.vhd b/libraries/base/common/tb/vhdl/tb_requantize.vhd
index 292bc82c7404ba559742a3c5817dd4b1e73231d8..68fd97cdd1457e0e60a444f7718ecbf7cccf736f 100644
--- a/libraries/base/common/tb/vhdl/tb_requantize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_requantize.vhd
@@ -44,7 +44,6 @@ entity tb_requantize is
end tb_requantize;
architecture tb of tb_requantize is
-
constant clk_period : time := 10 ns;
constant c_output_file_dir : string := "data/";
@@ -103,9 +102,7 @@ architecture tb of tb_requantize is
signal rst : std_logic;
constant c_init : std_logic_vector(in_dat'range) := (others => '0');
-
begin
-
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
@@ -463,5 +460,4 @@ begin
out_val => OPEN,
out_eof => open
);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_resize.vhd b/libraries/base/common/tb/vhdl/tb_resize.vhd
index 103347252dfb11683bcfd306144cc21f5b5fc776..01c561206458156c024ae06aeb2b78d6676ef6ae 100644
--- a/libraries/base/common/tb/vhdl/tb_resize.vhd
+++ b/libraries/base/common/tb/vhdl/tb_resize.vhd
@@ -50,7 +50,6 @@ entity tb_resize is
end tb_resize;
architecture tb of tb_resize is
-
constant clk_period : time := 10 ns;
constant c_pipeline_input : natural := 0;
@@ -87,9 +86,7 @@ architecture tb of tb_resize is
constant g_clip_umax : natural := 2**g_out_dat_w - 1;
constant g_clip_smax : natural := 2**(g_out_dat_w - 1) - 1;
constant g_clip_smin : integer := -2**(g_out_dat_w - 1);
-
begin
-
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
@@ -239,7 +236,6 @@ begin
-- RESIZE_NUM() in common_pkg.vhd is always equivalent to lowrange
assert signed(resize_num_sdat) = signed(lowrange_sdat) report "Wrong resize_num_sdat /= lowrange_sdat" severity ERROR;
assert unsigned(resize_num_udat) = unsigned(lowrange_udat) report "Wrong resize_num_udat /= lowrange_udat" severity ERROR;
-
end if;
end process;
diff --git a/libraries/base/common/tb/vhdl/tb_round.vhd b/libraries/base/common/tb/vhdl/tb_round.vhd
index 025a5ed2822f8feea8722df33e4c9fa6fa01573a..59813adae6bea5dcd004310721f07947af8b203b 100644
--- a/libraries/base/common/tb/vhdl/tb_round.vhd
+++ b/libraries/base/common/tb/vhdl/tb_round.vhd
@@ -48,7 +48,6 @@ entity tb_round is
end tb_round;
architecture tb of tb_round is
-
constant clk_period : time := 10 ns;
constant c_pipeline_input : natural := 0;
@@ -238,9 +237,7 @@ architecture tb of tb_round is
signal fs_ureal_round_half_up_clip : real := 0.0;
signal fs_ureal_round_half_even : real := 0.0;
signal fs_ureal_round_half_even_clip : real := 0.0;
-
begin
-
-- Stimuli
clk <= not clk or tb_end after clk_period / 2;
@@ -355,7 +352,6 @@ begin
out_dat => fs_signed_round_half_even_clip
);
-
-----------------------------------------------------------------------------
-- UNSIGNED DUTs
-----------------------------------------------------------------------------
@@ -628,5 +624,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
index f26ba9b443d6c7fa2b806add2f665ceae8c748fc..7d7001e00c70289cbc19599507292e353d3f4b06 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_add_sub.vhd
@@ -43,5 +43,4 @@ begin
u_both_add_5_6 : entity work.tb_common_add_sub generic map ("BOTH", '1', 0, 2, 5, 6);
u_both_sub_5_5 : entity work.tb_common_add_sub generic map ("BOTH", '0', 0, 2, 5, 5);
u_both_sub_5_6 : entity work.tb_common_add_sub generic map ("BOTH", '0', 0, 2, 5, 6);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
index 5db16f18732b130fc897063d812444c8f1f98cf9..b24e0b6dacd38a4c5b06961d049e09b0724b9084 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_create_strobes_from_valid.vhd
@@ -32,7 +32,6 @@ end tb_tb_common_create_strobes_from_valid;
architecture tb of tb_tb_common_create_strobes_from_valid is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_pipeline : BOOLEAN := FALSE;
-- g_in_val_gaps : BOOLEAN := FALSE;
-- g_nof_clk_per_sync : NATURAL := 17;
@@ -44,5 +43,4 @@ begin
u_fractional_interval : entity work.tb_common_create_strobes_from_valid generic map (false, false, 17, 7);
u_fractional_interval_with_gaps : entity work.tb_common_create_strobes_from_valid generic map (false, true, 17, 7);
u_fractional_interval_with_gaps_pipe : entity work.tb_common_create_strobes_from_valid generic map ( true, true, 17, 7);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
index 3d130abe3391b7068c17d007bfc36a2cf4755a8d..d76e0e916dab65fdcc25e62784fa8e02406fb119 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_fanout_tree.vhd
@@ -48,5 +48,4 @@ begin
u_val_3_3_27_incr : entity work.tb_common_fanout_tree generic map (false, true, 3, 3, 27, (1, 3, 9), (2, 1, 0));
u_val_4_3_75_incr : entity work.tb_common_fanout_tree generic map (false, true, 4, 3, 75, (1, 3, 9, 27), (2, 1, 0));
u_val_8_2_256_equal : entity work.tb_common_fanout_tree generic map (false, true, 8, 2, 256, array_init(1,8), array_init(1,2));
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
index 7c6305bf7c81b8eb9f675ae055e960df83fb3ba8..64bfdbd9cc9226ae3d796e42feeb727418b6cce0 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_multiplexer.vhd
@@ -51,5 +51,4 @@ begin
u_demux_mux_p0101 : entity work.tb_common_multiplexer generic map (0, 1, 4, 0, 1, 8, true, 500);
u_demux_mux_p1234_nof_1 : entity work.tb_common_multiplexer generic map (1, 2, 1, 3, 4, 8, true, 500);
u_demux_mux_p1234_nof_5 : entity work.tb_common_multiplexer generic map (1, 2, 5, 3, 4, 8, true, 500);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
index b540247419c751f6dd2c4bf844722156b4a8a752..238655a6c46242c876c819de5a50976a430f2ac6 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_operation_tree.vhd
@@ -55,5 +55,4 @@ begin
u_umin_0 : entity work.tb_common_operation_tree generic map ("MIN", "UNSIGNED", 0, 1, 5);
u_umin_1 : entity work.tb_common_operation_tree generic map ("MIN", "UNSIGNED", 1, 1, 7);
u_umin_1_1_8 : entity work.tb_common_operation_tree generic map ("MIN", "UNSIGNED", 1, 1, 8);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
index 8e92623818da99b27afd65da96552fdd7b57e89d..4a6aa138cac61b38b8c5527351ec791461b52570 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_paged_ram_ww_rr.vhd
@@ -49,5 +49,4 @@ begin
u_even_pipe_1_1 : entity work.tb_common_paged_ram_ww_rr generic map (1, 1, 10);
u_odd_pipe_0_1 : entity work.tb_common_paged_ram_ww_rr generic map (0, 1, 11);
u_odd_pipe_1_1 : entity work.tb_common_paged_ram_ww_rr generic map (1, 1, 11);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
index 9af7279df958eccdeb1c04492b2df3249e82b588..a7ad45d86a59d33c68a26d34797258534b826947 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reinterleave.vhd
@@ -30,8 +30,5 @@ entity tb_tb_common_reinterleave is
end;
architecture rtl of tb_tb_common_reinterleave is
-
-
begin
-
end rtl;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
index 743ed42a04b3a780b08cc63cdc2257ec51dd03e4..309b4f2b8c154f874014d7e79b7fc408992e882b 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_reorder_symbol.vhd
@@ -58,5 +58,4 @@ begin
u_4_4_sel_033333_p00000 : entity work.tb_common_reorder_symbol generic map (4, 4, 8, (0,3,3,3,3,3), (0,0,0,0,0));
u_5_5_sel_3333333333_p000000 : entity work.tb_common_reorder_symbol generic map (5, 5, 8, (3,3,3,3,3,3,3,3,3,3), (0,0,0,0,0,0));
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
index 0e5227f17c95dc18c9c235807a4f67b3673e4bde..297df49506fa275b644a311a1da67b66528c504a 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl.vhd
@@ -27,11 +27,9 @@ entity tb_tb_common_rl is
end tb_tb_common_rl;
architecture tb of tb_tb_common_rl is
-
constant c_nof_blocks : natural := 1000;
constant c_fifo_size : natural := 64;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-- Usage:
-- > as 2
@@ -49,5 +47,4 @@ begin
u_random_fifo_sc_decr_0_incr_1_t : entity work.tb_common_rl generic map (c_nof_blocks, true, true, c_fifo_size, true, true, true);
u_random_fifo_sc_decr_0 : entity work.tb_common_rl generic map (c_nof_blocks, true, true, c_fifo_size, true, false, false);
u_random_fifo_sc : entity work.tb_common_rl generic map (c_nof_blocks, true, true, c_fifo_size, false, false, true);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
index 3e6a3c19fb4ef401c69dccd5b02757fe09a6cee8..77863f33c08dc86ddb65e1d38873fe6cf8682686 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_rl_register.vhd
@@ -27,11 +27,9 @@ entity tb_tb_common_rl_register is
end tb_tb_common_rl_register;
architecture tb of tb_tb_common_rl_register is
-
constant c_nof_blocks : natural := 1000;
constant c_fifo_size : natural := 64;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-- Usage:
-- > as 2
@@ -46,5 +44,4 @@ begin
u_random_fifo_sc_reg_f : entity work.tb_common_rl_register generic map (c_nof_blocks, true, true, c_fifo_size, false);
u_random_fifo_sc_reg_t : entity work.tb_common_rl_register generic map (c_nof_blocks, true, true, c_fifo_size, true);
u_random_fifo_sc : entity work.tb_common_rl_register generic map (c_nof_blocks, true, true, c_fifo_size, true);
-
end tb;
diff --git a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
index 69f7d62d7fe153354eb080707fdce0224c9e2446..3fd334e1a175212ea76ce8c0417c682c6b59fa60 100644
--- a/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
+++ b/libraries/base/common/tb/vhdl/tb_tb_common_transpose.vhd
@@ -33,7 +33,6 @@ end tb_tb_common_transpose;
architecture tb of tb_tb_common_transpose is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_pipeline_shiftreg : NATURAL := 0;
-- | g_pipeline_transpose : NATURAL := 0;
-- | | g_pipeline_hold : NATURAL := 0;
@@ -50,5 +49,4 @@ begin
u_4_16 : entity common_lib.tb_common_transpose generic map(0, 0, 0, 1, 4, 16);
u_4_16p : entity common_lib.tb_common_transpose generic map(1, 2, 3, 1, 4, 16);
-
end tb;
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
index f569e4a935da3ecb99e9ae4b16856da59829f485..7ecc20e1be586ac59a46ce8c50b1090c84109256 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
@@ -73,9 +73,7 @@ entity common_complex_mult is
);
end common_complex_mult;
-
architecture str of common_complex_mult is
-
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
-- MegaWizard IP ip_stratixiv_complex_mult was generated with latency c_dsp_latency = 3
@@ -86,9 +84,7 @@ architecture str of common_complex_mult is
signal result_re : std_logic_vector(g_out_p_w - 1 downto 0);
signal result_im : std_logic_vector(g_out_p_w - 1 downto 0);
-
begin
-
-- User specificied latency must be >= MegaWizard IP dsp_mult_add2 latency
assert c_pipeline >= c_dsp_latency
report "tech_complex_mult: pipeline value not supported"
@@ -163,6 +159,4 @@ begin
in_dat => std_logic_vector(result_im),
out_dat => out_pi
);
-
-
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
index ff35daacc5b42b6c4b06b66e6f67733c2e362469..1d2064de811449511e1c7f5d9785b3a976d13b07 100644
--- a/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_complex_mult_add.vhd
@@ -57,7 +57,6 @@ end common_complex_mult_add;
-- Pipeling should be done in the multiplier or adder entity.
architecture str of common_complex_mult_add is
-
constant c_conjugate : boolean := false;
constant c_direction : string := "ADD";
constant c_pipeline_in : natural := 0; -- input pipelining 0 or 1
@@ -70,9 +69,7 @@ architecture str of common_complex_mult_add is
signal add_inr : std_logic_vector(g_out_p_w - 1 downto 0);
signal add_ini : std_logic_vector(g_out_p_w - 1 downto 0);
-
begin
-
-- u_complex_mult : entity work.common_complex_mult(stratix4) -- requires sum of g_pipeline >= 3
u_complex_mult : entity work.common_complex_mult -- suits sum of g_pipeline >= 0
generic map (
@@ -137,13 +134,10 @@ begin
in_b => add_ini,
result => out_sumi
);
-
end str;
-
-- The rtl architecture follows the syntax that is given as example by Altera for inferring the DSP blocks.
architecture rtl of common_complex_mult_add is
-
constant c_prod_w : natural := g_in_a_w + g_in_b_w;
signal ar_reg : signed(g_in_a_w - 1 downto 0);
@@ -156,9 +150,7 @@ architecture rtl of common_complex_mult_add is
signal pi : signed(c_prod_w - 1 downto 0);
signal sumr : signed(g_out_p_w - 1 downto 0);
signal sumi : signed(g_out_p_w - 1 downto 0);
-
begin
-
process (clk, rst, clken)
begin
if(rst = '1') then -- asynchronous reset
@@ -186,12 +178,9 @@ begin
sumr <= RESIZE_NUM(pr, g_out_p_w) + RESIZE_NUM(signed(in_chr), g_out_p_w); -- Add the chain_in real part to the real product
sumi <= RESIZE_NUM(pi, g_out_p_w) + RESIZE_NUM(signed(in_chi), g_out_p_w); -- Add the chain_in imaginary part to the imaginary product
-
end if;
end process;
out_sumr <= std_logic_vector(sumr);
out_sumi <= std_logic_vector(sumi);
-
end rtl;
-
diff --git a/libraries/base/common_mult/src/vhdl/common_mult.vhd b/libraries/base/common_mult/src/vhdl/common_mult.vhd
index b4050a065ddfbbf2bb36d72b6482e975885f453f..e533209b2a9c53ec2a53e523cca4009ddc4b843f 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult.vhd
@@ -65,16 +65,13 @@ entity common_mult is
end common_mult;
architecture str of common_mult is
-
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_output;
-- Extra output pipelining using common_pipeline is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
signal result : std_logic_vector(out_p'range); -- stage dependent on g_pipeline_output being 0 or 1
-
begin
-
u_mult : entity tech_mult_lib.tech_mult
generic map(
g_technology => g_technology,
@@ -128,5 +125,4 @@ begin
in_dat => std_logic_vector(result),
out_dat => out_p
);
-
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
index a46453b38417e652c4bba38dc63b14eb67bf1ed3..9c70318d26846e4a5ced66e809acd9d64cf61149 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add.vhd
@@ -61,9 +61,7 @@ begin
-- SEVERITY FAILURE;
end common_mult_add;
-
architecture rtl of common_mult_add is
-
constant c_prod_w : natural := g_in_a_w + g_in_b_w;
constant c_sum_w : natural := c_prod_w + 1;
@@ -75,9 +73,7 @@ architecture rtl of common_mult_add is
signal prod1 : signed(c_prod_w - 1 downto 0);
signal result : signed(c_sum_w - 1 downto 0);
signal nxt_result : signed(c_sum_w - 1 downto 0);
-
begin
-
out_dat <= std_logic_vector(resize(result, out_dat'length));
p_clk : process (clk)
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
index 821a0f00a71243741b7efcf9694223ed388d3382..397a229a0b61e78e80b832e2d0e7a31606fcc191 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add2.vhd
@@ -65,13 +65,10 @@ entity common_mult_add2 is
end common_mult_add2;
architecture str of common_mult_add2 is
-
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
signal result : std_logic_vector(res'range);
-
begin
-
u_mult_add2 : entity tech_mult_lib.tech_mult_add2
generic map(
g_technology => g_technology,
@@ -113,5 +110,4 @@ begin
in_dat => result,
out_dat => res
);
-
end str;
diff --git a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
index 56a3b6da68fb122019064fe6c08b9f033db6777f..088c8ccc9de1ba7caac16f910f081742e8edb794 100644
--- a/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
+++ b/libraries/base/common_mult/src/vhdl/common_mult_add4.vhd
@@ -70,13 +70,10 @@ entity common_mult_add4 is
end common_mult_add4;
architecture str of common_mult_add4 is
-
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
signal result : std_logic_vector(res'range);
-
begin
-
u_mult_add4 : entity tech_mult_lib.tech_mult_add4
generic map(
g_technology => g_technology,
@@ -120,5 +117,4 @@ begin
in_dat => result,
out_dat => res
);
-
end str;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
index 45a7f60398cfb980fd23b4ca77d9e7f7987fc88c..bd0dec1fcb3901fe47473d489bf296e7f83c68a7 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
@@ -35,7 +35,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use common_lib.common_str_pkg.all;
use common_lib.tb_common_pkg.all;
-
entity tb_common_complex_mult is
generic (
g_variant : string := "IP"; -- "RTL" or "IP"
@@ -48,9 +47,7 @@ entity tb_common_complex_mult is
);
end tb_common_complex_mult;
-
architecture tb of tb_common_complex_mult is
-
constant clk_period : time := 10 ns;
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
@@ -96,9 +93,7 @@ architecture tb of tb_common_complex_mult is
signal dbg_in_dat_w : natural := g_in_dat_w;
signal dbg_conjugate_b : boolean := g_conjugate_b;
signal dbg_pipeline : natural := c_pipeline;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
random <= func_common_random(random) when rising_edge(clk);
@@ -303,5 +298,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
index a2d5185bb1d2ec55f5298830e2dcd6009c2c7a1c..811b71ec89ccee4aec11d0f464f4c09d4cc58ed4 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult.vhd
@@ -33,7 +33,6 @@ use technology_lib.technology_select_pkg.all;
use common_lib.common_pkg.all;
use common_lib.tb_common_pkg.all;
-
entity tb_common_mult is
generic (
g_in_dat_w : natural := 7;
@@ -46,7 +45,6 @@ entity tb_common_mult is
end tb_common_mult;
architecture tb of tb_common_mult is
-
constant clk_period : time := 10 ns;
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_output;
constant c_nof_mult : natural := 2; -- fixed
@@ -112,9 +110,7 @@ architecture tb of tb_common_mult is
signal uresult_arr_rtl : std_logic_vector(g_nof_mult * g_out_dat_w - 1 downto 0);
signal sresult_arr_ip : std_logic_vector(g_nof_mult * g_out_dat_w - 1 downto 0);
signal uresult_arr_ip : std_logic_vector(g_nof_mult * g_out_dat_w - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
-- run 1 us
@@ -346,5 +342,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
index 22c75a7df41371bdc284a0ee601460acac58c707..b2e150e364f970ccc4aa55aaf78c046ef66dbde4 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_common_mult_add2.vhd
@@ -32,7 +32,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_common_mult_add2 is
generic (
g_technology : natural := c_tech_select_default;
@@ -48,9 +47,7 @@ entity tb_common_mult_add2 is
);
end tb_common_mult_add2;
-
architecture tb of tb_common_mult_add2 is
-
constant clk_period : time := 10 ns;
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
constant c_nof_mult : natural := 2; -- fixed
@@ -97,9 +94,7 @@ architecture tb of tb_common_mult_add2 is
signal out_result : std_logic_vector(g_out_dat_w - 1 downto 0); -- combinatorial result
signal result_expected : std_logic_vector(g_out_dat_w - 1 downto 0); -- pipelined results
signal result_rtl : std_logic_vector(g_out_dat_w - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
-- run 1 us
@@ -195,7 +190,6 @@ begin
out_dat => result_expected
);
-
u_dut_rtl : entity work.common_mult_add2
generic map (
g_in_a_w => g_in_dat_w,
@@ -226,5 +220,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
index 65c3e0f31ac8fd9be3aaf1f9dff04ed18c447a5d..a8b7dfd246c23d01cad3ff677bd4397cfa55d4c2 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd
@@ -44,7 +44,6 @@ begin
-- g_pipeline_adder : NATURAL := 1;
-- g_pipeline_output : NATURAL := 1
-
-- IP variants
u_ip_18b : entity work.tb_common_complex_mult generic map ("IP", 18, false, 1, 0, 1, 1);
u_ip_18b_conj : entity work.tb_common_complex_mult generic map ("IP", 18, true, 1, 0, 1, 1);
@@ -59,5 +58,4 @@ begin
u_rtl_27b : entity work.tb_common_complex_mult generic map ("RTL", 27, false, 1, 0, 1, 1);
u_rtl_18b_conj : entity work.tb_common_complex_mult generic map ("RTL", 18, true, 1, 0, 1, 1);
u_rtl_27b_conj : entity work.tb_common_complex_mult generic map ("RTL", 27, true, 1, 0, 1, 1);
-
end tb;
diff --git a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
index 96dfc359e242fce2b9d338c9926b33f3d2dc8ed0..d08b84661010615219ddb40fb60a75f2f8d6e2ce 100644
--- a/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
+++ b/libraries/base/common_mult/tb/vhdl/tb_tb_common_mult.vhd
@@ -39,7 +39,6 @@ begin
-- g_pipeline_product : NATURAL := 1;
-- g_pipeline_output : NATURAL := 1
-
-- Vary g_out_dat_w
u_mult_7_12_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 12, 2, 1, 1, 1); -- truncate extra bit
u_mult_7_13_nof_2_pipe_1_1_1 : entity work.tb_common_mult generic map (7, 13, 2, 1, 1, 1); -- truncate double sign bit
@@ -55,5 +54,4 @@ begin
u_mult_7_11_nof_1_pipe_1_0_0 : entity work.tb_common_mult generic map (7, 11, 2, 1, 0, 0);
u_mult_7_11_nof_1_pipe_0_1_0 : entity work.tb_common_mult generic map (7, 11, 2, 0, 1, 0);
u_mult_7_11_nof_1_pipe_0_0_1 : entity work.tb_common_mult generic map (7, 11, 2, 0, 0, 1);
-
end tb;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen.vhd b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
index 75fa9d31774837ca71789cea9f02866067623c12..7163a9b310a821795ca5beac075d067d72bf765b 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen.vhd
@@ -98,11 +98,9 @@ entity diag_block_gen is
out_siso : in t_dp_siso := c_dp_siso_rdy;
out_sosi : out t_dp_sosi
);
-
end diag_block_gen;
architecture rtl of diag_block_gen is
-
type state_type is (s_idle, s_block, s_gap);
type reg_type is record
@@ -125,9 +123,7 @@ architecture rtl of diag_block_gen is
signal r, rin : reg_type;
signal out_sosi_i : t_dp_sosi := c_dp_sosi_rst; -- Signal used to assign reset values to output
signal xon_reg : std_logic := '0';
-
begin
-
-- xon is not clk cycle timing critical, so can use register xon to ease timing closure
xon_reg <= out_siso.xon when rising_edge(clk);
@@ -139,7 +135,6 @@ begin
variable v_mem_low_adrs : natural;
variable v_mem_high_adrs : natural;
begin
-
v_samples_per_packet := TO_UINT(r.ctrl_hold.samples_per_packet);
v_gapsize := TO_UINT(r.ctrl_hold.gapsize);
v_blocks_per_sync := TO_UINT(r.ctrl_hold.blocks_per_sync);
@@ -256,7 +251,6 @@ begin
when others =>
v.state := s_idle;
-
end case;
if rst = '1' then
@@ -277,7 +271,6 @@ begin
end if;
rin <= v;
-
end process;
p_regs : process(rst, clk)
@@ -302,5 +295,4 @@ begin
buf_rden <= r.rd_ena;
ctrl_hold <= r.ctrl_hold;
-
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
index 99425a108c692ce0d3828b1017e41ba81a3a0e0e..018ca44aef18e5794d40feaa22ddabc49ca2b3a5 100644
--- a/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_block_gen_reg.vhd
@@ -19,7 +19,6 @@
--
-------------------------------------------------------------------------------
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -44,13 +43,10 @@ entity diag_block_gen_reg is
end diag_block_gen_reg;
architecture rtl of diag_block_gen_reg is
-
constant c_adrs_width : positive := c_diag_bg_reg_adr_w;
signal mm_bg_ctrl : t_diag_block_gen := g_diag_block_gen_rst;
signal dp_bg_ctrl : t_diag_block_gen := g_diag_block_gen_rst;
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -162,5 +158,4 @@ begin
end generate; -- gen_crossing
bg_ctrl <= dp_bg_ctrl;
-
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_bypass.vhd b/libraries/base/diag/src/vhdl/diag_bypass.vhd
index 481b79c224216119c955820a8068f8aa894f1df3..506398a3d59c6fdb2bcd1ba0deeea9033a145842 100644
--- a/libraries/base/diag/src/vhdl/diag_bypass.vhd
+++ b/libraries/base/diag/src/vhdl/diag_bypass.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity diag_bypass is
generic (
g_in_dat_w : natural := 12;
@@ -57,17 +56,13 @@ entity diag_bypass is
);
end diag_bypass;
-
architecture rtl of diag_bypass is
-
signal nxt_out_dat_x : std_logic_vector(out_dat_x'range);
signal nxt_out_dat_y : std_logic_vector(out_dat_y'range);
signal nxt_out_val : std_logic;
signal nxt_out_sync : std_logic;
signal bypass_en_reg : std_logic;
-
begin
-
mod_in_dat_x <= RESIZE_SVEC(in_dat_x, mod_in_dat_x'length);
mod_in_dat_y <= RESIZE_SVEC(in_dat_y, mod_in_dat_y'length);
mod_in_val <= in_val;
@@ -88,7 +83,6 @@ begin
end if;
end process;
-
output_switch_proc : process (bypass_en, mod_out_dat_x, mod_out_val, mod_out_sync,
in_dat_x, in_val, in_sync, mod_out_dat_y, in_dat_y)
begin
@@ -105,7 +99,6 @@ begin
end if;
end process;
-
clock_gating_proc : process (bypass_en, clk)
begin
mod_clk <= clk;
@@ -118,5 +111,4 @@ begin
end if;
-- synthesis translate_on
end process;
-
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
index 6e1e27f9e8c15a57b0a464084ba846d200d68527..f0211b988e02efcb26a0db4e683659a837eb458c 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer.vhd
@@ -79,9 +79,7 @@ entity diag_data_buffer is
);
end diag_data_buffer;
-
architecture rtl of diag_data_buffer is
-
constant c_mm_factor : natural := ceil_div(g_data_w, c_word_w); -- must be a power of 2 multiple
constant c_nof_data_mm : natural := g_nof_data * c_mm_factor;
@@ -126,9 +124,7 @@ architecture rtl of diag_data_buffer is
signal sync_cnt_clr : std_logic := '0';
signal sync_cnt : std_logic_vector(c_word_w - 1 downto 0); -- Nof times buffer has been written
signal word_cnt : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
-
begin
-
assert c_mm_factor = 2**true_log2(c_mm_factor) report "Only support mixed width data that uses a power of 2 multiple." severity FAILURE;
ram_mm_miso <= i_ram_mm_miso;
@@ -261,6 +257,4 @@ begin
cnt_clr => sync_cnt_clr,
count => sync_cnt
);
-
end rtl;
-
diff --git a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
index ad85335ca7085cf0d68fd5275396c1f10426796a..278e607ea21c93de95a9e902c8e8020b5a4aa49a 100644
--- a/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/diag_data_buffer_dev.vhd
@@ -101,9 +101,7 @@ entity diag_data_buffer_dev is
);
end diag_data_buffer_dev;
-
architecture rtl of diag_data_buffer_dev is
-
constant c_version : natural := 1;
constant c_mm_factor : natural := ceil_div(g_data_w, c_word_w); -- must be a power of 2 multiple
@@ -164,9 +162,7 @@ architecture rtl of diag_data_buffer_dev is
end record;
signal r, rin : reg_type;
-
begin
-
assert c_mm_factor = 2**true_log2(c_mm_factor) report "Only support mixed width data that uses a power of 2 multiple." severity FAILURE;
out_wr_done <= nxt_wr_done;
@@ -195,7 +191,6 @@ begin
-- Determine the write trigger in SYNC MODE and ARM MODE
use_in_sync : if g_use_in_sync = true generate
-
comb : process(st_rst, r, in_sync, rd_last_st, reg_sync_delay, arm_enable, valid_cnt)
variable v : reg_type;
begin
@@ -232,7 +227,6 @@ begin
when others =>
v.state := s_idle;
-
end case;
if st_rst = '1' then
@@ -241,7 +235,6 @@ begin
end if;
rin <= v;
-
end process comb;
regs : process(st_clk)
@@ -372,7 +365,4 @@ begin
cnt_clr => in_sync,
count => valid_cnt
);
-
end rtl;
-
-
diff --git a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
index 85e13db8baaa08d8b8f53b2c409d5c672911e0db..cccb660269ccd0b07ac18b1f035d3a4168cc7ede 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_generator.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
-- Purpose: Generate a stream of frames with test sequence data.
-- Description:
-- Each frame has g_frame_len words of out_dat. The test data can be PRSG or
@@ -37,7 +36,6 @@ use common_lib.common_pkg.all;
-- Remark:
-- . This component can be easily mapped to standard MM and ST interfaces.
-
entity diag_frm_generator is
generic (
g_sel : std_logic := '1'; -- '0' = PRSG, '1' = COUNTER
@@ -73,9 +71,7 @@ entity diag_frm_generator is
);
end diag_frm_generator;
-
architecture str of diag_frm_generator is
-
constant c_init : natural := 0; -- first data word of first frame that is generated after diag_en = '1'
constant c_frame_len_w : natural := ceil_log2(g_frame_len);
@@ -90,9 +86,7 @@ architecture str of diag_frm_generator is
signal i_out_sop : std_logic;
signal i_out_eop : std_logic;
-
begin
-
out_sop <= i_out_sop;
out_eop <= i_out_eop;
out_empty <= diag_frame_empty;
@@ -185,5 +179,4 @@ begin
out_sop => i_out_sop,
out_eop => i_out_eop
);
-
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
index 9a01db05af0b7513f1345d9641f79ca0eb441992..1993a7509844865d3d8727e06c807a64d203b910 100644
--- a/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
+++ b/libraries/base/diag/src/vhdl/diag_frm_monitor.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
-- Purpose: Monitor a stream of frames with test sequence data.
-- Description:
-- Each frame is marked by an active in_eop. The in_sop is not needed and the
@@ -42,7 +41,6 @@ use common_lib.common_pkg.all;
-- Remark:
-- . This component can be easily mapped to standard MM and ST interfaces.
-
entity diag_frm_monitor is
generic (
g_frame_cnt_w : natural := 32
@@ -63,9 +61,7 @@ entity diag_frm_monitor is
);
end diag_frm_monitor;
-
architecture str of diag_frm_monitor is
-
signal diag_en_revt : std_logic;
signal frame_cnt : std_logic_vector(diag_frame_cnt'range);
@@ -75,9 +71,7 @@ architecture str of diag_frm_monitor is
signal frm_eop : std_logic;
signal frm_error : std_logic;
-
begin
-
p_clk : process (rst, clk)
begin
if rst = '1' then
@@ -138,5 +132,4 @@ begin
cnt_en => frm_error,
count => error_cnt
);
-
end str;
diff --git a/libraries/base/diag/src/vhdl/diag_pkg.vhd b/libraries/base/diag/src/vhdl/diag_pkg.vhd
index 9c72a414e2d49dee9a1db1f18f6d9d9855e110c8..8f88945551725e4a93ed9d88fd2714e027a73f0e 100644
--- a/libraries/base/diag/src/vhdl/diag_pkg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.math_real.all;
use common_lib.common_pkg.all;
package diag_pkg is
-
-----------------------------------------------------------------------------
-- PHY interface tests (e.g. for ethernet, transceivers, lvds, memory)
-----------------------------------------------------------------------------
@@ -50,7 +49,6 @@ package diag_pkg is
constant c_diag_test_result_error : natural := 3; -- test received valid data, but the value was wrong for one or more
constant c_diag_test_result_illegal : natural := 4; -- exception, condition that can not occur in the logic
-
-----------------------------------------------------------------------------
-- Waveform Generator
-----------------------------------------------------------------------------
@@ -224,7 +222,6 @@ package diag_pkg is
end diag_pkg;
package body diag_pkg is
-
function sel_a_b(sel : boolean; a, b : t_diag_block_gen) return t_diag_block_gen is
begin
if sel = true then
@@ -232,6 +229,7 @@ package body diag_pkg is
else
return b;
end if;
+
end;
function func_diag_bg_ctrl_integer_to_slv(bg_ctrl_int : t_diag_block_gen_integer) return t_diag_block_gen is
diff --git a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
index 617a63b397638aeb6e1b5b66b2df08d0d23b9e1b..4bf373e254343579497acde7c1872eda9cc6fd26 100644
--- a/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_rx_seq.vhd
@@ -129,9 +129,7 @@ entity diag_rx_seq is
);
end diag_rx_seq;
-
architecture rtl of diag_rx_seq is
-
constant c_lfsr_nr : natural := g_dat_w - c_common_lfsr_first;
constant c_diag_res_latency : natural := 3;
@@ -189,9 +187,7 @@ architecture rtl of diag_rx_seq is
signal diff_detect : std_logic := '0';
signal nxt_diff_detect : std_logic;
signal diff_hold : std_logic;
-
begin
-
diag_dis <= not diag_en;
diag_sample <= i_diag_sample;
diag_sample_diff <= i_diag_sample_diff;
@@ -207,6 +203,7 @@ begin
end if;
end process;
end generate;
+
no_input_reg : if g_input_reg = false generate
in_val_reg <= in_val;
in_dat_reg <= in_dat;
@@ -399,7 +396,6 @@ begin
diff_res <= (others => diff_hold); -- convert diff_hold to diff_res slv format as used for g_use_steps=FALSE
end generate;
-
------------------------------------------------------------------------------
-- Report valid diag_res
------------------------------------------------------------------------------
@@ -417,7 +413,6 @@ begin
end if;
end process;
-
------------------------------------------------------------------------------
-- Count number of valid input data
------------------------------------------------------------------------------
diff --git a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
index 99abf4c04321cd6585ceaf3c55c6ad1aa9756ba5..0f392a8179f1357c5ecf7e6848dbb7b576332d25 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_frm.vhd
@@ -43,7 +43,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
-- Remark:
-- . This component can be easily mapped to standard MM and ST interfaces.
-
entity diag_tx_frm is
generic (
g_sel : std_logic := '1'; -- '0' = PRSG, '1' = COUNTER
@@ -75,9 +74,7 @@ entity diag_tx_frm is
);
end diag_tx_frm;
-
architecture rtl of diag_tx_frm is
-
constant c_lfsr_nr : natural := g_dat_w - c_common_lfsr_first;
signal i_diag_ready : std_logic;
@@ -96,9 +93,7 @@ architecture rtl of diag_tx_frm is
signal nxt_out_val : std_logic;
signal nxt_out_sop : std_logic;
signal nxt_out_eop : std_logic;
-
begin
-
diag_ready <= i_diag_ready;
p_clk : process (rst, clk)
@@ -170,5 +165,4 @@ begin
out_dat => out_dat,
out_val => open
);
-
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
index bb4be8bda0edf1bd4e740fd74ac2461af121037a..6b00fcfb0d0b1643d8b08c7fc35da4f3376c0045 100644
--- a/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/diag_tx_seq.vhd
@@ -67,9 +67,7 @@ entity diag_tx_seq is
);
end diag_tx_seq;
-
architecture rtl of diag_tx_seq is
-
constant c_lfsr_nr : natural := g_dat_w - c_common_lfsr_first;
signal diag_dis : std_logic;
@@ -82,9 +80,7 @@ architecture rtl of diag_tx_seq is
signal nxt_out_dat : std_logic_vector(out_dat'range);
signal nxt_out_val : std_logic;
-
begin
-
diag_dis <= not diag_en;
p_clk : process (rst, clk)
@@ -149,5 +145,4 @@ begin
cnt_en => nxt_out_val,
count => out_cnt
);
-
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_wg.vhd b/libraries/base/diag/src/vhdl/diag_wg.vhd
index 557165d10fe99841ef2dea64d1f9dcd0f57c6f5f..93592adee83c80033b3e9f51e3de6b6070170d7a 100644
--- a/libraries/base/diag/src/vhdl/diag_wg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg.vhd
@@ -87,9 +87,7 @@ entity diag_wg is
);
end diag_wg;
-
architecture rtl of diag_wg is
-
constant c_mult_pipeline_input : natural := 1; -- 0 or 1
constant c_mult_pipeline_product : natural := 1; -- 0 or 1
constant c_mult_pipeline_output : natural := 0; -- >= 0
@@ -165,9 +163,7 @@ architecture rtl of diag_wg is
signal nxt_out_dat : std_logic_vector(out_dat'range);
signal nxt_out_val : std_logic;
signal nxt_out_sync : std_logic;
-
begin
-
mon_ctrl <= i_mon_ctrl;
registers : process(clk, rst)
@@ -467,5 +463,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
index 76c0f064a83104ed0bd2610856b1f92c42bc0d9a..bb2657dbd84c20cf1fc44d553717566f55a69238 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband.vhd
@@ -75,9 +75,7 @@ entity diag_wg_wideband is
);
end diag_wg_wideband;
-
architecture str of diag_wg_wideband is
-
constant c_buf : t_c_mem := (latency => 1,
adr_w => g_buf_addr_w,
dat_w => g_buf_dat_w, -- fit DSP multiply 18x18 element
@@ -100,9 +98,7 @@ architecture str of diag_wg_wideband is
signal st_rd : std_logic_vector(0 to g_wideband_factor - 1);
signal st_rdval : std_logic_vector(0 to g_wideband_factor - 1);
signal st_rddata : t_buf_dat_arr(0 to g_wideband_factor - 1);
-
begin
-
assert c_buf_file /= "UNUSED" report "diag_wg_wideband : no buffer waveform file available" severity FAILURE;
-- MM write same to all g_wideband_factor waveform buffers
diff --git a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
index 33c2b9598d7044bf010f65c7958c50ee9a45ae9b..b0d7b45dc644122ff823691236470fd37bf97c8e 100644
--- a/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
+++ b/libraries/base/diag/src/vhdl/diag_wg_wideband_reg.vhd
@@ -67,9 +67,7 @@ entity diag_wg_wideband_reg is
);
end diag_wg_wideband_reg;
-
architecture rtl of diag_wg_wideband_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 2,
@@ -84,9 +82,7 @@ architecture rtl of diag_wg_wideband_reg is
signal mm_mon_ctrl : t_diag_wg;
-- Registers in st_clk domain
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
diff --git a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
index 0a3d83d233c1b88d44256ec700df2b1ec724ef9f..60095ffc8cd08aad6673de21d5b4b13f759ecbe8 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_block_gen.vhd
@@ -92,7 +92,6 @@
-- the DB mms_diag_data_buffer.vhd.
-- . A nice new feature would be to support a BG burst of N blocks.
-
library IEEE, common_lib, technology_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -149,7 +148,6 @@ entity mms_diag_block_gen is
end mms_diag_block_gen;
architecture rtl of mms_diag_block_gen is
-
constant c_buf : t_c_mem := (latency => 1,
adr_w => g_buf_addr_w,
dat_w => g_buf_dat_w,
@@ -187,9 +185,7 @@ architecture rtl of mms_diag_block_gen is
signal mux_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
signal mux_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- BG
-----------------------------------------------------------------------------
@@ -293,7 +289,6 @@ begin
end generate;
end generate;
-
---------------------------------------------------------------------------
-- No multiplexer, so only one input or no input at all
---------------------------------------------------------------------------
@@ -308,11 +303,11 @@ begin
(others => c_dp_sosi_rst);
end generate;
-
-----------------------------------------------------------------------------
-- Multiplex user input and BG
-----------------------------------------------------------------------------
gen_dp_mux : if c_use_mux = true generate -- so g_use_usr_input and g_use_bg are both TRUE
+
gen_streams : for I in 0 to g_nof_streams - 1 generate
-- Add user xon flow control if the user input does not already support it
u_dp_xonoff : entity dp_lib.dp_xonoff
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
index 750bea9c85d5febbd2bcb3591636168722642ed9..481104862a93ecb6f5472cdc59622b9bff0f40c0 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer.vhd
@@ -107,7 +107,6 @@ entity mms_diag_data_buffer is
end mms_diag_data_buffer;
architecture str of mms_diag_data_buffer is
-
constant c_buf_mm_factor : natural := ceil_div(g_data_w, c_word_w);
constant c_buf_nof_data_mm : natural := g_buf_nof_data * c_buf_mm_factor;
@@ -123,9 +122,7 @@ architecture str of mms_diag_data_buffer is
signal reg_data_buf_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal reg_data_buf_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
no_db : if g_use_db = false generate
ram_data_buf_miso <= c_mem_miso_rst;
reg_data_buf_miso <= c_mem_miso_rst;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
index 799e3fdc23b44a3e14adace1686d9d27cd6fd6cd..6bfbb0dab81cfb0eead674bfed767537174eca87 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_data_buffer_dev.vhd
@@ -108,7 +108,6 @@ entity mms_diag_data_buffer_dev is
end mms_diag_data_buffer_dev;
architecture str of mms_diag_data_buffer_dev is
-
constant c_buf_mm_factor : natural := ceil_div(g_data_w, c_word_w);
constant c_buf_nof_data_mm : natural := g_buf_nof_data * c_buf_mm_factor;
@@ -124,9 +123,7 @@ architecture str of mms_diag_data_buffer_dev is
signal reg_data_buf_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal reg_data_buf_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
no_db : if g_use_db = false generate
ram_data_buf_miso <= c_mem_miso_rst;
reg_data_buf_miso <= c_mem_miso_rst;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
index 6c879f1d142d7cf01d6e9fd9443d7b5804bb5ab8..f3c7d796454e03e08a8990fb66ca7c26beabd44d 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_rx_seq.vhd
@@ -127,9 +127,7 @@ entity mms_diag_rx_seq is
);
end mms_diag_rx_seq;
-
architecture str of mms_diag_rx_seq is
-
-- Define MM slave register size
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => c_diag_seq_rx_reg_adr_w,
@@ -182,13 +180,10 @@ architecture str of mms_diag_rx_seq is
signal stat_res_ok_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
signal stat_res_val_n_arr : std_logic_vector(g_nof_streams - 1 downto 0);
-
begin
-
assert g_data_w >= g_seq_dat_w report "mms_diag_rx_seq: g_data_w < g_seq_dat_w is not allowed." severity FAILURE;
gen_nof_streams: for I in 0 to g_nof_streams - 1 generate
-
-- no unreplicate needed
gen_one : if g_data_w = g_seq_dat_w generate
rx_seq_arr(I) <= rx_snk_in_arr(i).data(g_seq_dat_w - 1 downto 0);
@@ -306,18 +301,4 @@ begin
mosi_arr => reg_mosi_arr,
miso_arr => reg_miso_arr
);
-
end str;
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
index 24fdcbad2484d3012d8f0fc25242875326728aa6..879b31e63223a9fea3b2d43bb5e8465c5d81e3be 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_tx_seq.vhd
@@ -149,7 +149,6 @@
-- which can be useful to ensure that reading e.g. address 2**g_seq_dat_w
-- yields a different CNTR value than reading 2**(g_seq_dat_w+1).
-
library IEEE, common_lib, dp_lib; -- init value for out_dat when diag_en = '0'
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -184,9 +183,7 @@ entity mms_diag_tx_seq is
);
end mms_diag_tx_seq;
-
architecture str of mms_diag_tx_seq is
-
-- Define MM slave register size
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => c_diag_seq_tx_reg_adr_w,
@@ -386,16 +383,3 @@ begin
end generate;
end str;
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
index dfa264de60824c749d1c01639e20b8d85761dc5a..f23fda685ab1f622c0321940856a5ca84a576d68 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband.vhd
@@ -77,14 +77,10 @@ entity mms_diag_wg_wideband is
);
end mms_diag_wg_wideband;
-
architecture str of mms_diag_wg_wideband is
-
signal st_wg_ctrl : t_diag_wg; -- write
signal st_mon_ctrl : t_diag_wg; -- read
-
begin
-
u_mm_reg : entity work.diag_wg_wideband_reg
generic map (
g_cross_clock_domain => g_cross_clock_domain
@@ -146,5 +142,4 @@ begin
out_val => out_val,
out_sync => out_sync
);
-
end str;
diff --git a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
index f7d439ef968b31b24d027d0e42fede31ff655b67..aa5b1be2c4a74ae4c5562355099407b9ae6428c3 100644
--- a/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
+++ b/libraries/base/diag/src/vhdl/mms_diag_wg_wideband_arr.vhd
@@ -75,9 +75,7 @@ entity mms_diag_wg_wideband_arr is
);
end mms_diag_wg_wideband_arr;
-
architecture str of mms_diag_wg_wideband_arr is
-
constant c_reg_adr_w : natural := 2;
signal reg_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
@@ -89,9 +87,7 @@ architecture str of mms_diag_wg_wideband_arr is
signal wg_dat : std_logic_vector(g_nof_streams * g_wideband_factor * g_buf_dat_w - 1 downto 0);
signal wg_val : std_logic_vector(g_nof_streams * g_wideband_factor - 1 downto 0);
signal wg_sync : std_logic_vector(g_nof_streams * g_wideband_factor - 1 downto 0);
-
begin
-
u_common_mem_mux_reg : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -151,7 +147,6 @@ begin
out_sync => wg_sync((I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )
);
-
-- wire the wg signals to sosi outputs
-- This is done as per the method used in unb1_bn_capture_input (Apertif)
-- . all wideband samples will be valid in parallel, so using vector_or() or vector_and() is fine
@@ -162,8 +157,6 @@ begin
out_sosi_arr(I).err <= TO_DP_ERROR(0) when
vector_or(wg_ovr( (I + 1) * g_wideband_factor - 1 downto I * g_wideband_factor )) = '0' else
TO_DP_ERROR(2**7); -- pass ADC or WG overflow info on as an error signal
-
-
end generate;
end str;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
index e35441f5e3baf297a0a2f45e1d1661220f8a42b1..4ec82902c6ca8e98b25b9a1fada143f717c71bd9 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_block_gen.vhd
@@ -55,9 +55,7 @@ entity tb_diag_block_gen is
);
end tb_diag_block_gen;
-
architecture tb of tb_diag_block_gen is
-
constant clk_period : time := 10 ns;
constant c_timeout : natural := 1000;
constant c_offtime : natural := 200;
@@ -76,7 +74,6 @@ architecture tb of tb_diag_block_gen is
constant c_cntr_incr : integer := 1;
constant c_cntr_arr : t_slv_32_arr(c_buf.nof_dat - 1 downto 0) := flip(array_init(c_cntr_init, c_buf.nof_dat, c_cntr_incr));
-
-- Phasor: exp(j*angle) = cos(angle) + j*sin(angle)
-- A complex FFT of N points has N bins or channels: ch = -N/2:0:N/2-1.
-- To create an FFT input phasor with frequency in the middle of a channel use FREQ = ch.
@@ -147,9 +144,7 @@ architecture tb of tb_diag_block_gen is
signal last_size : natural;
signal exp_size : natural;
signal cnt_size : natural;
-
begin
-
rst <= '1', '0' after clk_period * 10;
clk <= not clk or tb_end after clk_period / 2;
@@ -279,6 +274,4 @@ begin
out_siso_bg.ready <= '1' when g_flow_control_verify = e_active else
random(random'high) when g_flow_control_verify = e_random else
toggle when g_flow_control_verify = e_pulse;
-
end tb;
-
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
index 6a0e60f20e69eddc1b24b635d4c87d87a5707f98..730f6e6fd09da0c50d49770af15a43ab66d7cb46 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_data_buffer_dev.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -51,7 +50,6 @@ use mm_lib.mm_file_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.diag_pkg.all;
-
entity tb_diag_data_buffer is
generic(
g_nof_streams : positive := 2; -- = 16
@@ -61,7 +59,6 @@ entity tb_diag_data_buffer is
end tb_diag_data_buffer;
architecture tb of tb_diag_data_buffer is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -138,9 +135,7 @@ architecture tb of tb_diag_data_buffer is
signal s_init : std_logic;
signal nof_valids : natural;
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -162,7 +157,6 @@ begin
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
----------------------------------------------------------------------------
-- Stimuli: Block gen data send to memory
----------------------------------------------------------------------------
@@ -286,5 +280,4 @@ begin
in_sync => bg_sosi_arr(0).sync,
in_sosi_arr => bg_sosi_arr
);
-
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
index 321cc22b9fc9d59239e826cd8d33768e8d2c5dc5..0156020ba1138a03ae236d87d53eddbba45c1bfb 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_generator.vhd
@@ -34,7 +34,6 @@ entity tb_diag_frm_generator is
end tb_diag_frm_generator;
architecture tb of tb_diag_frm_generator is
-
constant c_period : time := 100 ns;
constant c_nof_cycles : natural := 200;
@@ -68,9 +67,7 @@ architecture tb of tb_diag_frm_generator is
signal seq_empty : std_logic_vector(c_empty_w - 1 downto 0); -- nof empty symbols in last out_dat word marked by out_eop
signal init_dat : std_logic_vector(c_dat_w - 1 downto 0);
-
begin
-
rst <= '1', '0' after c_period / 10;
clk <= not clk or tb_end after c_period / 2;
@@ -178,6 +175,4 @@ begin
if seq_val = '1' and unsigned(seq_dat) > unsigned(init_dat) then assert unsigned(prev_seq_dat) = unsigned(seq_dat) - 1 report "Wrong seq_dat"; end if;
end if;
end process;
-
end tb;
-
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
index 723af721049072dddc22572d8d46282847006612..ef5aa9aa48e93ec8f7de2ecba6b89e29951dab31 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_frm_monitor.vhd
@@ -34,7 +34,6 @@ entity tb_diag_frm_monitor is
end tb_diag_frm_monitor;
architecture tb of tb_diag_frm_monitor is
-
constant c_period : time := 100 ns;
constant c_nof_cycles : natural := 200;
@@ -71,9 +70,7 @@ architecture tb of tb_diag_frm_monitor is
signal hld_frame_cnt : natural;
signal init_dat : std_logic_vector(c_dat_w - 1 downto 0);
-
begin
-
rst <= '1', '0' after c_period / 10;
clk <= not clk or tb_end after c_period / 2;
@@ -157,7 +154,6 @@ begin
out_eop => seq_eop
);
-
u_frm_mon : entity work.diag_frm_monitor
generic map (
g_frame_cnt_w => c_frame_cnt_w
@@ -177,7 +173,6 @@ begin
in_error => seq_error
);
-
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
p_verify_generator : process(clk)
@@ -199,6 +194,4 @@ begin
if seq_val = '1' and unsigned(seq_dat) > unsigned(init_dat) then assert unsigned(prev_seq_dat) = unsigned(seq_dat) - 1 report "Wrong seq_dat"; end if;
end if;
end process;
-
end tb;
-
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
index c9fbf5bb56e57acdd91476dba4e083ef3780b5ce..9d1b3946753ba9eae94ac0768778b91611cb23a9 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_pkg.vhd
@@ -35,7 +35,6 @@ use dp_lib.tb_dp_pkg.all;
use work.diag_pkg.all;
package tb_diag_pkg is
-
-- Test modes for diag seq
type t_tb_diag_seq_mode_enum is (
s_off,
@@ -192,7 +191,6 @@ package tb_diag_pkg is
end tb_diag_pkg;
package body tb_diag_pkg is
-
procedure proc_diag_seq_read_all(constant c_stream : in natural;
signal mm_clk : in std_logic;
signal tx_miso : in t_mem_miso;
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd b/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
index 1bc0566e9ea12bb6392b95b28622256543245745..e34799d1dcbe04b9a48f2fbb2651bc366f212a2c 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_regression.vhd
@@ -28,14 +28,12 @@
-- > as 3
-- > run -all
-
library IEEE;
use IEEE.std_logic_1164.all;
entity tb_diag_regression is
end tb_diag_regression;
-
architecture tb of tb_diag_regression is
begin
-- Single tb
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
index 0355c249d61adc395785b6181e8f2e488adbcf27..35316f212a397ab0d11e1ec96573a1e7135f494a 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_rx_seq.vhd
@@ -37,7 +37,6 @@ use work.diag_pkg.all;
-- . The tb can verify rx_steps other than +1 by using g_tx_cnt_incr, it can
-- only verify one of the c_diag_seq_rx_reg_nof_steps at a time.
-
entity tb_diag_rx_seq is
generic (
g_tx_cnt_incr : integer := -7;
@@ -49,7 +48,6 @@ entity tb_diag_rx_seq is
end tb_diag_rx_seq;
architecture tb of tb_diag_rx_seq is
-
constant c_period : time := 100 ns;
constant c_nof_cycles : natural := 100;
constant c_latency : natural := 2;
@@ -80,9 +78,7 @@ architecture tb of tb_diag_rx_seq is
signal diag_res_val : std_logic;
signal expected_res : std_logic_vector(c_diag_res_w - 1 downto 0);
-
begin
-
rst <= '1', '0' after c_period / 10;
clk <= not clk or tb_end after c_period / 2;
@@ -300,6 +296,4 @@ begin
end if;
end if;
end process;
-
end tb;
-
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
index ce4be53f02ee35f2f41077ae3e5e8d95e9aba9e4..d526a763f07a372d583673d579eb1e007570c098 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_frm.vhd
@@ -29,7 +29,6 @@ entity tb_diag_tx_frm is
end tb_diag_tx_frm;
architecture tb of tb_diag_tx_frm is
-
constant c_period : time := 100 ns;
constant c_nof_cycles : natural := 83; -- use prime number to avoid periodicity with sequence data, which can confuse interpretating the data
@@ -54,9 +53,7 @@ architecture tb of tb_diag_tx_frm is
signal seq_val : std_logic;
signal seq_sop : std_logic;
signal seq_eop : std_logic;
-
begin
-
rst <= '1', '0' after c_period / 10;
clk <= not clk after c_period / 2;
@@ -181,7 +178,6 @@ begin
out_eop => seq_eop
);
-
prev_seq_dat <= seq_dat when rising_edge(clk) and seq_val = '1';
p_verify : process(clk)
@@ -197,6 +193,4 @@ begin
if seq_val = '1' and unsigned(seq_dat) > c_init then assert unsigned(prev_seq_dat) = unsigned(seq_dat) - 1 report "Wrong seq_dat"; end if;
end if;
end process;
-
end tb;
-
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
index 0247eb2740daa5cd3f38275702227327bdef3301..a172bb172d22a2ec0f08150157428394181ee8a2 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_tx_seq.vhd
@@ -34,7 +34,6 @@ entity tb_diag_tx_seq is
end tb_diag_tx_seq;
architecture tb of tb_diag_tx_seq is
-
constant c_period : time := 100 ns;
constant c_nof_cycles : natural := 83; -- use prime number to avoid periodicity with sequence data, which can confuse interpretating the data
@@ -49,9 +48,7 @@ architecture tb of tb_diag_tx_seq is
signal diag_req : std_logic;
signal seq_dat : std_logic_vector(c_dat_w - 1 downto 0);
signal seq_val : std_logic;
-
begin
-
rst <= '1', '0' after c_period / 10;
clk <= not clk or tb_end after c_period / 2;
@@ -119,6 +116,4 @@ begin
out_dat => seq_dat,
out_val => seq_val
);
-
end tb;
-
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
index 9853faafcf7d86df488b127feab8df19c19ed106..db0f7c42fe152b2ed7565cf2c64ee70674aa00b7 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg.vhd
@@ -36,7 +36,6 @@ use work.diag_pkg.all;
-- . run 10 us to see CALC mode waveform output at proper automatic scale
-- . run 100 us to see SINGLE and REPEAT mode waveform output at proper automatic scale
-
entity tb_diag_wg is
generic (
g_buf_adr_w : natural := 10; -- Waveform buffer address width (requires corresponding c_buf_file)
@@ -46,7 +45,6 @@ entity tb_diag_wg is
end tb_diag_wg;
architecture tb of tb_diag_wg is
-
constant c_clk_freq : natural := 200 * 10**6; -- Hz
constant c_clk_period : time := (10**9 / c_clk_freq) * 1 ns;
@@ -60,7 +58,6 @@ architecture tb of tb_diag_wg is
sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 18, "data/diag_sin_1024x18.hex",
sel_a_b(c_buf.adr_w = 10 and c_buf.dat_w = 8, "data/diag_sin_1024x8.hex", "UNUSED")));
-
constant c_wg_nof_samples : natural := c_buf.nof_dat; -- must be <= c_buf.nof_dat
constant c_wg_gain_w : natural := 1; -- Normalized range [0 1> maps to fixed point range [0:2**c_diag_wg_ampl_w>
-- . use gain 2**0 = 1 to have fulle scale without clipping
@@ -99,10 +96,7 @@ architecture tb of tb_diag_wg is
signal wg_dat : std_logic_vector(c_buf.dat_w - 1 downto 0);
signal wg_val : std_logic;
signal wg_sync : std_logic;
-
-
begin
-
rst <= '1', '0' after c_clk_period / 10;
clk <= not clk or tb_end after c_clk_period / 2;
@@ -258,6 +252,4 @@ begin
out_val => wg_val,
out_sync => wg_sync
);
-
end tb;
-
diff --git a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
index e91f7354c6484d13b55320c71ceec0fa3651ecf5..8521629f7d0dbcaf8913ce9dbdb4c9504dd19d68 100644
--- a/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_diag_wg_wideband.vhd
@@ -48,7 +48,6 @@ entity tb_diag_wg_wideband is
end tb_diag_wg_wideband;
architecture tb of tb_diag_wg_wideband is
-
constant c_clk_freq : natural := 200; -- MHz
constant c_clk_period : time := (10**6 / c_clk_freq) * 1 ps;
@@ -107,9 +106,7 @@ architecture tb of tb_diag_wg_wideband is
signal sample_dat : std_logic_vector(g_buf_dat_w - 1 downto 0);
signal sample_val : std_logic;
signal sample_sync : std_logic;
-
begin
-
rst <= '1', '0' after c_clk_period / 10;
clk <= not clk or tb_end after c_clk_period / 2;
@@ -263,7 +260,6 @@ begin
wait;
end process;
-
u_wideband_wg : entity work.diag_wg_wideband
generic map (
-- Wideband parameters
@@ -324,6 +320,4 @@ begin
sample_sync <= wg_sync(sample_cnt);
end if;
end process;
-
end tb;
-
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
index 05e007d5bb00291131bfc37a2a8d3f182aa143cb..f18f50f775d9317d6b96af634b670d2b0abf2c81 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_block_gen.vhd
@@ -54,7 +54,6 @@ entity tb_mms_diag_block_gen is
end tb_mms_diag_block_gen;
architecture tb of tb_mms_diag_block_gen is
-
constant clk_period : time := 10 ns;
constant c_verify_usr_rflow : boolean := g_flow_control_verify /= e_active;
@@ -127,9 +126,7 @@ architecture tb of tb_mms_diag_block_gen is
signal verify_data_en : std_logic := '0';
signal verify_tx_seq_en : std_logic := '0';
signal verify_no_bg_buffer_ram_en : std_logic := '0';
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 5;
@@ -211,7 +208,6 @@ begin
wait;
end process;
-
-------------------------------------------------
-- User input modelled by another BG
-------------------------------------------------
@@ -440,5 +436,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
index 0efb8a4a81f03b739d7f75526f1cd1b155de80d6..57222de7e020adf7b3ca690ef9292a3d09157086 100644
--- a/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_mms_diag_seq.vhd
@@ -26,7 +26,6 @@
-- > as 10
-- > run -all
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -54,7 +53,6 @@ entity tb_mms_diag_seq is
end entity tb_mms_diag_seq;
architecture str of tb_mms_diag_seq is
-
constant mm_clk_period : time := 8 ns; -- 125 MHz
constant dp_clk_period : time := 5 ns; -- 200 MHz
constant c_random_w : natural := 16;
@@ -89,9 +87,7 @@ architecture str of tb_mms_diag_seq is
signal force_replicate_error : std_logic;
signal rx_snk_in_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
mm_rst <= '1', '0' after mm_clk_period * 5;
dp_rst <= mm_rst when rising_edge(dp_clk);
@@ -114,7 +110,6 @@ begin
-- Stimuli
------------------------------------------------------------------------------
-
p_stimuli_and_verify : process
-- Cannot use non static rd_reg_arr(I) variable index in procedure argument, therefor use constant index rd_reg_arr(c_st_0) or rd_reg_arr(c_st_1).
constant c_st_0 : natural := 0;
@@ -285,7 +280,6 @@ begin
end if;
end process;
-
u_mms_diag_tx_seq: entity WORK.mms_diag_tx_seq
generic map(
g_mm_broadcast => g_mm_broadcast_tx,
@@ -342,5 +336,4 @@ begin
rx_snk_in_arr(0).data(g_seq_dat_w) <= not tx_src_out_arr(0).data(g_seq_dat_w);
end if;
end process;
-
end architecture str;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
index 7dc5753126a188a2bc03c7d89b6d046999697520..6417e9d67f26ab6f9751be29c46d4892b68e9377 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_block_gen.vhd
@@ -35,13 +35,9 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_diag_block_gen is
end tb_tb_diag_block_gen;
-
architecture tb of tb_tb_diag_block_gen is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- -- specific
@@ -57,5 +53,4 @@ begin
u_bg_ready : entity work.tb_diag_block_gen generic map (e_random, 96, 10, 32, 7, 32, false);
u_bg_minimal_gap_0 : entity work.tb_diag_block_gen generic map (e_active, 2, 1, 0, 7, 32, false);
u_bg_minimal_gap_1 : entity work.tb_diag_block_gen generic map (e_active, 2, 1, 1, 7, 32, false);
-
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
index 2eca397d4c6435e4f0d8702b701e61a04856e02b..09ecb0650a2a86b472f7f15fc096efcd0147a150 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_diag_rx_seq.vhd
@@ -26,11 +26,9 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_diag_rx_seq is
end tb_tb_diag_rx_seq;
-
architecture tb of tb_tb_diag_rx_seq is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_tx_cnt_incr : INTEGER := 1;
-- g_tx_mod : INTEGER := 0;
-- g_rx_use_steps : BOOLEAN := TRUE;
@@ -43,5 +41,4 @@ begin
u_diag_steps_tx_mod : entity work.tb_diag_rx_seq generic map ( 1, 255, true, (1, 2, 1, 1), 8); -- rx_step = 2**g_seq_dat_w - tx_mod + g_tx_cnt_incr = 256 - 255 + 1 = 2
u_diag_steps_tx_mod_incr_7 : entity work.tb_diag_rx_seq generic map ( 7, 255, true, (7, 8, 7, 7), 8); -- rx_step = 2**g_seq_dat_w - tx_mod + g_tx_cnt_incr = 256 - 255 + 7 = 8
u_diag_steps_tx_mod_incr_5 : entity work.tb_diag_rx_seq generic map ( 5, 127, true, (5, 134, 5, 5), 8); -- rx_step = 2**g_seq_dat_w - tx_mod + g_tx_cnt_incr = 256 - 127 + 5 = 134
-
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
index 5365f236bc5f640cb6cbfcdc8a8ee29f94e68af1..812024f273884f4a11e9362a4315ccb056723c59 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_block_gen.vhd
@@ -34,15 +34,11 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_mms_diag_block_gen is
end tb_tb_mms_diag_block_gen;
-
architecture tb of tb_tb_mms_diag_block_gen is
-
constant c_nof_repeat : natural := 2;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_use_usr_input : BOOLEAN := TRUE;
-- g_use_bg : BOOLEAN := TRUE;
-- g_use_tx_seq : BOOLEAN := FALSE;
@@ -67,6 +63,4 @@ begin
u_usr_tx_seq_random_stream_0 : entity work.tb_mms_diag_block_gen generic map ( true, false, true, true, false, e_random, 2, 2, 0); -- stream 1 is active, so both e_random and e_active are tested
u_bg_no_buffer_ram : entity work.tb_mms_diag_block_gen generic map (false, true, false, false, false, e_active, 1, 2, 0);
-
-
end tb;
diff --git a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
index edb55d1e354413c9c1b7c224afcd4040c6005d0e..416cb26dec25e7b533578aa08175cf62ed7db77b 100644
--- a/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
+++ b/libraries/base/diag/tb/vhdl/tb_tb_mms_diag_seq.vhd
@@ -27,11 +27,9 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_mms_diag_seq is
end tb_tb_mms_diag_seq;
-
architecture tb of tb_tb_mms_diag_seq is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random flow control
-- g_nof_streams : NATURAL := 2;
-- g_use_steps : BOOLEAN := FALSE;
@@ -45,5 +43,4 @@ begin
u_2_streams_mm_multiplex : entity work.tb_mms_diag_seq generic map (e_active, 2, false, false, 40, 32);
u_1_stream_mm_steps_w : entity work.tb_mms_diag_seq generic map (e_random, 1, true, false, 40, 15);
-
end tb;
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
index 969c2edca0385a81d724708c71e757723e192b5b..2fceec4f1a5a59d0e6a04d0a1d485ec702535944 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics.vhd
@@ -75,9 +75,7 @@ entity diagnostics is
);
end diagnostics;
-
architecture str of diagnostics is
-
constant c_min_dat_w : natural := 8;
constant c_max_dat_w : natural := 32;
constant c_sub_stream_dat_w : natural := split_w(g_dat_w, c_min_dat_w, c_max_dat_w); -- Calculate appropriate data width of internal streams
@@ -112,9 +110,7 @@ architecture str of diagnostics is
signal rx_clk : std_logic_vector(g_nof_streams - 1 downto 0);
signal rx_rst : std_logic_vector(g_nof_streams - 1 downto 0);
-
begin
-
gen_separate_clk : if g_separate_clk = true generate
tx_clk <= src_clk;
tx_rst <= src_rst;
@@ -124,7 +120,6 @@ begin
end generate;
gen_nof_streams : for i in 0 to g_nof_streams - 1 generate
-
gen_one_clk : if g_separate_clk = false generate
tx_clk(i) <= clk;
tx_rst(i) <= rst;
@@ -171,7 +166,6 @@ begin
tx_diag_req(i) <= tx_siso_arr(i).ready and tx_siso_arr(i).xon;
gen_bg : if g_block_len > 0 generate
-
u_dp_block_gen: entity dp_lib.dp_block_gen
generic map (
g_nof_data => g_block_len,
@@ -196,7 +190,6 @@ begin
tx_sosi_arr(i).channel <= tx_bg_sosi_arr(i).channel;
tx_bg_siso_arr(i).ready <= tx_siso_arr(i).ready;
-
end generate;
gen_nof_substreams : for j in c_nof_substreams - 1 downto 0 generate
@@ -243,7 +236,6 @@ begin
rx_siso_arr(i).ready <= '1'; -- snk_diag_en(i);
rx_siso_arr(i).xon <= '1'; -- snk_diag_en(i);
-
u_tx_dpmon : entity dp_lib.dp_mon
generic map (
g_latency => 1
@@ -281,8 +273,5 @@ begin
clr => snk_val_cnt_clr(i),
word_cnt => snk_val_cnt(i)
);
-
end generate;
-
end str;
-
diff --git a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
index 30a9492f498c3a0cb13bf2cae086f5b9eea9df07..6fd9e3ac98be7dc3c51517b8c11c03d38582c56d 100644
--- a/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/diagnostics_reg.vhd
@@ -63,9 +63,7 @@ entity diagnostics_reg is
);
end diagnostics_reg;
-
architecture rtl of diagnostics_reg is
-
constant c_nof_registers : natural := 40; -- src_cnt and snk_cnt registers should be variable in size....but the CASE process makes that difficult.
constant c_mm_reg : t_c_mem := (latency => 1,
@@ -94,10 +92,7 @@ architecture rtl of diagnostics_reg is
signal i_snk_clk : std_logic_vector(g_nof_streams - 1 downto 0);
signal i_snk_rst : std_logic_vector(g_nof_streams - 1 downto 0);
-
-
begin
-
gen_sep_clk : if g_separate_clk = true generate
i_src_clk <= src_clk;
i_src_rst <= src_rst;
@@ -261,7 +256,6 @@ begin
------------------------------------------------------------------------------
gen_g_nof_streams_asyncs : for i in 0 to g_nof_streams - 1 generate
-
u_async_src_en : entity common_lib.common_async
generic map (
g_rst_level => '0'
@@ -357,7 +351,6 @@ begin
-- mm_snk_diag_val(i) <= st_snk_diag_val(i);
-- mm_snk_diag_res(i) <= st_snk_diag_res(i);
-
end generate;
u_cross_domain_snk_diag_val : entity common_lib.common_reg_cross_domain
@@ -383,5 +376,4 @@ begin
out_dat => mm_snk_diag_res,
out_new => open
);
-
end rtl;
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
index 19e0c35d620640ab7458a55c1c4796124640b4af..3f93466da3deca5dc5c350011a771d610a795da3 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger.vhd
@@ -60,9 +60,7 @@ entity mm_rx_logger is
);
end mm_rx_logger;
-
architecture str of mm_rx_logger is
-
constant c_data_wr_rd_ratio : natural := g_dat_w / c_word_w;
constant c_dpmm_fifo_wr_depth : natural := 16;
constant c_data_dpmm_fifo_rd_depth : natural := c_data_wr_rd_ratio * c_dpmm_fifo_wr_depth;
@@ -106,10 +104,7 @@ architecture str of mm_rx_logger is
signal mm_trig_en_evt : std_logic;
signal mm_trig_dis_evt : std_logic;
-
-
begin
-
-- ============== logged 'data' data path (256 bits of data as example) =======================================================
-- |
-- 256 /----------\ 256 /---------\ 256 /---------------\ 32 /---------------\
@@ -258,9 +253,4 @@ begin
rx_trig_nof_logged_words => mm_trig_nof_logged_words,
mm_data_usedw => data_mm_rd_usedw
);
-
-
-
end str;
-
-
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
index fa5179537326217983128a0348cb0a23c2876efb..fb6107194a79b5345849866333b306241a0f3e83 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_reg.vhd
@@ -51,9 +51,7 @@ entity mm_rx_logger_reg is
);
end mm_rx_logger_reg;
-
architecture rtl of mm_rx_logger_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(8),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
@@ -68,9 +66,7 @@ architecture rtl of mm_rx_logger_reg is
signal mm_ovr : std_logic;
signal mm_log_en_evt : std_logic;
signal mm_log_dis_evt : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -209,6 +205,4 @@ begin
rx_trig_nof_words <= mm_trig_nof_words;
mm_trig_nof_logged_words <= rx_trig_nof_logged_words;
-
end rtl;
-
diff --git a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
index d1334a75b7eeba6e9a101c67cc412d725164117c..cfe4fe951f828fd7bdd7b8fe289fac2d394e31ea 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_rx_logger_trig.vhd
@@ -26,7 +26,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
entity mm_rx_logger_trig is
-
port (
clk : in std_logic;
rst : in std_logic;
@@ -40,9 +39,7 @@ entity mm_rx_logger_trig is
);
end mm_rx_logger_trig;
-
architecture str of mm_rx_logger_trig is
-
signal i_log_cnt : std_logic_vector(c_word_w - 1 downto 0);
signal nxt_log_cnt : std_logic_vector(c_word_w - 1 downto 0);
@@ -51,9 +48,7 @@ architecture str of mm_rx_logger_trig is
signal state : t_state_enum;
signal nxt_state : t_state_enum;
signal prev_state : t_state_enum;
-
begin
-
log_cnt <= i_log_cnt;
p_clk : process(rst, clk)
@@ -106,9 +101,6 @@ begin
when others => -- s_init
log_en <= '0';
nxt_state <= s_idle;
-
end case;
end process;
-
end str;
-
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
index 634096505ca91dcac247fc92732cc055f3173fb6..6f31fd34b9a9b09fcd37b8ace2fa311475040de6 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer.vhd
@@ -56,9 +56,7 @@ entity mm_tx_framer is
);
end mm_tx_framer;
-
architecture str of mm_tx_framer is
-
constant c_wr_rd_ratio : natural := g_dat_out_w / c_word_w;
constant c_wr_fifo_depth : natural := g_rd_fifo_depth * c_wr_rd_ratio;
@@ -70,9 +68,7 @@ architecture str of mm_tx_framer is
signal fifo_out_sosi : t_dp_sosi;
signal release : std_logic := '0';
-
begin
-
master_release <= release;
u_data_dp_fifo_from_mm : entity dp_lib.dp_fifo_from_mm
@@ -135,7 +131,4 @@ begin
tx_release => release
);
-
-
end str;
-
diff --git a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
index 04b094cc99826af2a574e1ec486abd24d448a991..97ef6ed9f100d8c45d1336f8928e7f2762218ead 100644
--- a/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mm_tx_framer_reg.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -46,9 +45,7 @@ entity mm_tx_framer_reg is
);
end mm_tx_framer_reg;
-
architecture rtl of mm_tx_framer_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(2),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
@@ -56,9 +53,7 @@ architecture rtl of mm_tx_framer_reg is
init_sl => '0');
-- Registers in mm_clk domain
signal mm_release : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -131,6 +126,4 @@ begin
din => mm_release,
dout => tx_release
);
-
end rtl;
-
diff --git a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
index 5d3278f5c19547706c5e2c72021d595831d7b580..a1c02e233098a2c5af52e6a1ce68cf92b02410cc 100644
--- a/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
+++ b/libraries/base/diagnostics/src/vhdl/mms_diagnostics.vhd
@@ -65,9 +65,7 @@ entity mms_diagnostics is
);
end mms_diagnostics;
-
architecture str of mms_diagnostics is
-
signal src_diag_en : std_logic_vector(g_nof_streams - 1 downto 0);
signal src_diag_md : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -82,9 +80,7 @@ architecture str of mms_diagnostics is
signal snk_val_cnt : t_slv_32_arr(g_nof_streams - 1 downto 0);
signal snk_val_cnt_clr : std_logic_vector(g_nof_streams - 1 downto 0);
-
begin
-
src_en_out <= src_diag_en;
snk_en_out <= snk_diag_en;
@@ -157,7 +153,4 @@ begin
st_snk_diag_val => snk_diag_res_val,
st_snk_diag_res => snk_diag_res
);
-
-
end str;
-
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
index b77389110ee5b188f9a11ff38fc5940961f34685..4df9f42fa1e970a993f3cb0115e8d9cde1271639 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics.vhd
@@ -38,7 +38,6 @@ entity tb_diagnostics is
end entity tb_diagnostics;
architecture str of tb_diagnostics is
-
constant c_sim : boolean := true;
constant clk_period : time := 5 ns; -- 200 MHz
@@ -59,16 +58,13 @@ architecture str of tb_diagnostics is
signal src_diag_en : std_logic_vector(c_nof_streams - 1 downto 0);
signal src_val_cnt : t_slv_32_arr(c_nof_streams - 1 downto 0);
-
begin
-
-- Run for 1us
rst <= '0' after 100 ns;
clk <= not clk or tb_end after clk_period / 2;
gen_tb_processes: for i in 0 to c_nof_streams - 1 generate
-
p_stimuli : process
begin
for rpt in 0 to 1 loop
@@ -95,7 +91,6 @@ architecture str of tb_diagnostics is
wait until rising_edge(clk);
snk_diag_en(i) <= '0';
-
end loop;
wait for 100 ns;
tb_end <= '1';
@@ -128,8 +123,4 @@ architecture str of tb_diagnostics is
src_diag_md => (others => '1'),
src_val_cnt => src_val_cnt
);
-
-
end architecture str;
-
-
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
index 384ec351176e50eb3989f7a6fd021bfe9aa5cab4..796aeba35b4cfc5f86b12b1aa6ac3f6a783a4873 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_diagnostics_trnb_pkg.vhd
@@ -29,7 +29,6 @@ use common_lib.tb_common_pkg.all;
use common_lib.tb_common_mem_pkg.all;
package tb_diagnostics_trnb_pkg is
-
type t_e_diagnostics_trnb_mode is (e_prbs, e_counter);
-- Global procedures
@@ -60,13 +59,9 @@ package tb_diagnostics_trnb_pkg is
signal mm_mosi : out t_mem_mosi);
-- Private procedures
-
-
end tb_diagnostics_trnb_pkg;
-
package body tb_diagnostics_trnb_pkg is
-
------------------------------------------------------------------------------
-- PROCEDURE: Set all gx to default mode PRBS
------------------------------------------------------------------------------
@@ -83,7 +78,6 @@ package body tb_diagnostics_trnb_pkg is
proc_mem_mm_bus_wr(20, 0, mm_clk, mm_mosi); -- set sink mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_rx_set_mode_prbs;
-
------------------------------------------------------------------------------
-- PROCEDURE: Set the masked gx to mode COUNTER and set the unmasked gx to
-- default mode PRBS
@@ -103,7 +97,6 @@ package body tb_diagnostics_trnb_pkg is
proc_mem_mm_bus_wr(20, c_nof_gx_mask, mm_clk, mm_mosi); -- set source mode 0 = PRBS, 1 = COUNTER
end procedure proc_diagnostics_trnb_rx_set_mode_counter;
-
------------------------------------------------------------------------------
-- PROCEDURE: Run a diagnostic measurement and verify the result
------------------------------------------------------------------------------
@@ -151,5 +144,4 @@ package body tb_diagnostics_trnb_pkg is
proc_common_wait_some_cycles(mm_clk, c_mm_clk_1us * c_diag_off_interval);
end procedure proc_diagnostics_trnb_run_and_verify;
-
end tb_diagnostics_trnb_pkg;
diff --git a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
index 6bbfe2505386eeed076ead7bad59de8db442c0f3..9500074a594f10eb0193d53b0478c7a074c12758 100644
--- a/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
+++ b/libraries/base/diagnostics/tb/vhdl/tb_mm_tx_framer.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2011
@@ -34,7 +33,6 @@ entity tb_mm_tx_framer is
end tb_mm_tx_framer;
architecture tb of tb_mm_tx_framer is
-
constant c_mm_clk_period : time := 8 ns; -- 125 MHz MM clock, altpll in SOPC will make this from the ETH 25 MHz XO clock
constant c_tx_clk_period : time := 6.4 ns; -- 156.25 MHz
@@ -62,9 +60,7 @@ architecture tb of tb_mm_tx_framer is
signal sla_data_out : std_logic_vector(31 downto 0);
signal mst_release : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -176,6 +172,4 @@ begin
data_out => sla_data_out,
slave_release => mst_release
);
-
end tb;
-
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
index 937e8c43bb1d77b6781c11edb3c94845bcae6749..8e84c4b54cefa76aca3a7e8fbfb249f343f8a738 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/mmm_unb1_dp_offload.vhd
@@ -125,7 +125,6 @@ entity mmm_unb1_dp_offload is
end mmm_unb1_dp_offload;
architecture str of mmm_unb1_dp_offload is
-
-- Clocks
signal i_mm_clk : std_logic := '1';
signal i_tse_clk : std_logic := '1';
@@ -168,9 +167,7 @@ architecture str of mmm_unb1_dp_offload is
signal i_eth1g_reg_miso : t_mem_miso;
signal sim_eth1g_reg_mosi : t_mem_mosi;
-
begin
-
mm_clk <= i_mm_clk;
eth1g_tse_clk <= i_tse_clk;
dp_clk <= i_dp_clk;
@@ -179,7 +176,6 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
i_dp_clk <= not i_dp_clk after c_dp_clk_period / 2;
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
i_tse_clk <= not i_tse_clk after c_tech_tse_clk_period / 2;
@@ -258,7 +254,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
----------------------------------------------------------------------------
diff --git a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
index 8586285c2860f952f033ba2e10578c37e76e1974..52877cb0357bc723d4edcafd150e1e950d0a9733 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/src/vhdl/unb1_dp_offload.vhd
@@ -74,9 +74,7 @@ entity unb1_dp_offload is
);
end unb1_dp_offload;
-
architecture str of unb1_dp_offload is
-
constant c_design_name : string := "unb1_dp_offload";
constant c_nof_streams : natural := 1;
constant c_data_w : natural := c_tech_tse_data_w;
@@ -203,9 +201,7 @@ architecture str of unb1_dp_offload is
signal dp_fifo_fill_src_out_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
signal dp_fifo_fill_src_in_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- TX: Block generator
-----------------------------------------------------------------------------
@@ -544,5 +540,4 @@ begin
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso
);
-
end str;
diff --git a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
index 6b2673d5ee2b0dd0ab2009bbb63f7533925b3301..9faac986ed33160b6a3cb042cdb017a7fc23d1df 100644
--- a/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
+++ b/libraries/base/dp/designs/unb1_dp_offload/tb/vhdl/tb_unb1_dp_offload.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -49,7 +48,6 @@ entity tb_unb1_dp_offload is
end tb_unb1_dp_offload;
architecture tb of tb_unb1_dp_offload is
-
constant c_sim : boolean := true;
constant c_unb1_board_nr : natural := 0; -- UniBoard 0
@@ -72,9 +70,7 @@ architecture tb of tb_unb1_dp_offload is
signal VERSION : std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0) := c_version;
signal ID : std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0) := c_id;
-
begin
-
----------------------------------------------------------------------------
-- Externally generated clocks
----------------------------------------------------------------------------
@@ -99,5 +95,4 @@ begin
ETH_SGIN => eth_lpbk,
ETH_SGOUT => eth_lpbk
);
-
end tb;
diff --git a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
index 18d0aa9b688445d468057a3f7eaaee73f2193bfc..2c4615062225e116938992f2938b63e0af3a1bfd 100644
--- a/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
+++ b/libraries/base/dp/src/vhdl/dp_barrel_shift.vhd
@@ -45,9 +45,7 @@ entity dp_barrel_shift is
);
end dp_barrel_shift;
-
architecture str of dp_barrel_shift is
-
type t_reg is record
src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
shift_out : std_logic_vector(ceil_log2(g_nof_streams) - 1 downto 0);
@@ -57,9 +55,7 @@ architecture str of dp_barrel_shift is
(others => '0') );
signal r, nxt_r : t_reg := c_reg_defaults;
-
begin
-
r <= nxt_r when rising_edge(clk);
p_comb : process(rst, r, snk_in_arr, shift_in)
@@ -77,5 +73,4 @@ begin
nxt_r <= v;
end process;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
index 057eaddc3324a0d9fd94ddbef400fa754350dfc2..96e84bff329d7f69694decb02a38a5b9c9ec8825 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
@@ -97,9 +97,7 @@ entity dp_block_from_mm is
);
end dp_block_from_mm;
-
architecture rtl of dp_block_from_mm is
-
constant c_mem_size : natural := g_step_size * g_nof_data;
type t_reg is record
@@ -132,9 +130,7 @@ architecture rtl of dp_block_from_mm is
signal out_eop : std_logic;
signal out_sync : std_logic;
signal out_bsn : std_logic_vector(g_bsn_w - 1 downto 0);
-
begin
-
last_mm_address <= g_step_size * (g_nof_data - 1) + g_data_size + start_address - 1;
mm_address <= start_address + r.data_index + r.step_address; -- default word order per g_user_size
mm_address_rev <= start_address + r.word_index + r.step_address; -- reverse word order per g_user_size
@@ -253,5 +249,4 @@ begin
nxt_r <= v;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
index 92774c9804cf1b1e0fc64ea13068066d95430292..a5dbf8136b58958fbfc2b228b8f53ed13d73e326 100644
--- a/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_from_mm_dc.vhd
@@ -77,7 +77,6 @@ entity dp_block_from_mm_dc is
end dp_block_from_mm_dc;
architecture str of dp_block_from_mm_dc is
-
constant c_packet_size : natural := g_nof_data * g_data_size;
-- Fit one packet in FIFO, and less than two, to avoid filling the FIFO with
@@ -103,9 +102,7 @@ architecture str of dp_block_from_mm_dc is
signal start_address_slv : std_logic_vector(c_start_addr_w - 1 downto 0) := (others => '0');
signal mm_start_address_slv : std_logic_vector(c_start_addr_w - 1 downto 0) := (others => '0');
signal mm_start_address : natural := 0;
-
begin
-
-- Use g_delay_len = c_meta_delay_len + 4 for start_pulse and g_delay_len =
-- c_meta_delay_len for the other signals. The + 4 ensures that the other
-- signals are already stable in the mm_clk domain, when the mm_start_pulse
@@ -236,6 +233,4 @@ begin
out_sosi <= dp_out_sosi;
dp_out_siso <= out_siso;
-
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen.vhd b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
index b5df7fc890f4df5d2349bf4e621fa9839ac787a1..a9f997127f73a8d6713931cab1ede931fe4f6546 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen.vhd
@@ -62,7 +62,6 @@
-- . Alternatively consider using dp_block_gen_valid_arr.vhd or
-- dp_block_reshape.vhd.
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -96,9 +95,7 @@ entity dp_block_gen is
);
end dp_block_gen;
-
architecture rtl of dp_block_gen is
-
type t_state is (s_sop, s_data, s_eop);
type t_reg is record -- local registers
@@ -116,9 +113,7 @@ architecture rtl of dp_block_gen is
-- Define the local registers in t_reg record
signal r : t_reg;
signal nxt_r : t_reg;
-
begin
-
snk_out.ready <= src_in.ready when g_use_src_in = true else '1'; -- force snk_out.ready = '1' when src_in.ready is not used
snk_out.xon <= src_in.xon; -- always pass on siso.xon
@@ -227,5 +222,4 @@ begin
end if;
end case;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
index 8d2d582a9e2eb8366bb94fb5732351381ea9254e..0abb80fa529abc405fd5e652a2418086253a1683 100644
--- a/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_gen_valid_arr.vhd
@@ -167,9 +167,7 @@ entity dp_block_gen_valid_arr is
);
end dp_block_gen_valid_arr;
-
architecture rtl of dp_block_gen_valid_arr is
-
-- Check consistancy of the parameters, the function return value is void, because always true or abort due to failure
function parameter_asserts(g_check_input_sync : boolean; g_nof_pages_bsn : natural) return boolean is
begin
@@ -207,9 +205,7 @@ architecture rtl of dp_block_gen_valid_arr is
-- Define the local registers in t_reg record
signal r : t_reg;
signal nxt_r : t_reg;
-
begin
-
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -352,5 +348,4 @@ begin
-- Combine input data with the same out_put info and output ctrl for all streams
nxt_src_out_arr <= func_dp_stream_arr_combine_data_info_ctrl(snk_in_arr, out_sosi, out_sosi);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
index 46e39a01fb291825183e70abe4a737fd92fe33d8..5e1dce61c28cd8686f0af5b7fc9d5db06be4f3af 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape.vhd
@@ -97,9 +97,7 @@ entity dp_block_reshape is
);
end dp_block_reshape;
-
architecture str of dp_block_reshape is
-
constant c_nof_counters : natural := 2; -- counter [0] is used for block reshape and valid index,
-- counter [1] is only used for sop_index
constant c_nof_block_per_sync : natural := sel_a_b(g_input_nof_data_per_sync > g_reshape_nof_data_per_blk,
@@ -111,9 +109,7 @@ architecture str of dp_block_reshape is
signal cnt_sosi_arr : t_dp_sosi_arr(c_nof_counters - 1 downto 0);
signal input_src_out : t_dp_sosi;
-
begin
-
u_dp_counter : entity work.dp_counter
generic map (
g_nof_counters => c_nof_counters,
@@ -145,5 +141,4 @@ begin
src_out.sop <= cnt_sosi_arr(0).sop;
src_out.eop <= cnt_sosi_arr(0).eop;
end process;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
index d5af701f4cd7bc8cee3a78f2b5c262adc53206ae..d0d7039eca77f37147710560ded3f457982c4f40 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_arr.vhd
@@ -60,9 +60,7 @@ entity dp_block_reshape_arr is
);
end dp_block_reshape_arr;
-
architecture str of dp_block_reshape_arr is
-
signal in_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal in_siso_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
@@ -73,9 +71,7 @@ architecture str of dp_block_reshape_arr is
signal out_siso : t_dp_siso;
signal out_index_2arr_2 : t_natural_2arr_2(g_nof_streams - 1 downto 0); -- [1] sop index, [0] valid index per stream
-
begin
-
-- Dependent on g_shared_control use stream(0) to control all streams or use separate control per stream
in_sosi <= snk_in_arr(0);
in_siso <= in_siso_arr(0);
@@ -150,5 +146,4 @@ begin
-- Wire index arr
src_index_2arr_2 <= out_index_2arr_2 when g_shared_control = false else (others => out_index_2arr_2(0));
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
index ca7a6337cdaeb763c6ec9d6fa488751dc5ddb1cb..2934cf719e37345e6970b6e9ab2353f0db9fd976 100644
--- a/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_reshape_sync.vhd
@@ -92,9 +92,7 @@ entity dp_block_reshape_sync is
);
end dp_block_reshape_sync;
-
architecture str of dp_block_reshape_sync is
-
constant c_reshape_nof_data_per_sync : natural := g_reshape_nof_data_per_blk * g_reshape_nof_blk_per_sync;
-- If g_input_nof_data_per_sync <= c_reshape_nof_data_per_sync then c_nof_output_sync_per_input_sync = 1, else the
@@ -131,9 +129,7 @@ architecture str of dp_block_reshape_sync is
signal local_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
signal reg_output_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
signal reg_global_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
-
begin
-
u_dp_counter : entity work.dp_counter
generic map (
g_nof_counters => c_nof_counters,
@@ -159,6 +155,7 @@ begin
gen_sync_index : if c_nof_output_sync_per_input_sync > 1 generate
sync_index <= TO_UINT(cnt_sosi_arr(2).data);
end generate;
+
sop_index <= TO_UINT(cnt_sosi_arr(1).data);
valid_index <= TO_UINT(cnt_sosi_arr(0).data);
@@ -215,5 +212,4 @@ begin
-- No need to pipeline output for gen_reshape_bsn, because does not have so much combinatorial logic
src_out <= reshape_sosi;
reshape_siso <= src_in;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_block_resize.vhd b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
index 1ffc044acceb1a6e79053af8014472042813eb71..db89a827502ab817b05dbe32f386bf4a6b1f0b75 100644
--- a/libraries/base/dp/src/vhdl/dp_block_resize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_resize.vhd
@@ -61,21 +61,17 @@ entity dp_block_resize is
);
end dp_block_resize;
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.dp_stream_pkg.all;
architecture rtl of dp_block_resize is
-
signal cnt_reg : natural range 0 to g_input_block_size-1;
signal cnt : natural;
signal sop_sosi_reg : t_dp_sosi;
signal sop_sosi : t_dp_sosi;
signal block_sosi : t_dp_sosi;
-
begin
-
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -143,5 +139,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_select.vhd b/libraries/base/dp/src/vhdl/dp_block_select.vhd
index 0682c23741123a6215b294adb0b4c802bb25d90e..773adcfb0d7a252de34f76baf399f7701a04fd35 100644
--- a/libraries/base/dp/src/vhdl/dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_select.vhd
@@ -73,21 +73,17 @@ entity dp_block_select is
);
end dp_block_select;
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.dp_stream_pkg.all;
architecture rtl of dp_block_select is
-
signal cnt_reg : natural range 0 to true_log_pow2(g_nof_blocks_per_sync);
signal cnt : natural;
signal sync_sosi_reg : t_dp_sosi; -- hold snk_in.bsn
signal sync_sosi : t_dp_sosi; -- hold snk_in.bsn
signal block_sosi : t_dp_sosi;
-
begin
-
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -157,5 +153,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
index 530ee3a4659dc63a9b2f8237bca37a7bdeec9168..0c1cb305606823ade252d499f0f6e54719c9547b 100644
--- a/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_to_mm.vhd
@@ -47,9 +47,7 @@ entity dp_block_to_mm is
);
end dp_block_to_mm;
-
architecture rtl of dp_block_to_mm is
-
constant c_mem_size : natural := g_step_size * g_nof_data;
type t_reg is record
@@ -63,7 +61,6 @@ architecture rtl of dp_block_to_mm is
signal r : t_reg;
signal d : t_reg;
signal address : natural := 0;
-
begin
address <= start_address + r.word_index + r.step_index;
@@ -108,5 +105,4 @@ begin
d.step_index <= 0;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
index 545d9c06bf0cfc5f2d6f3d1e65cf21e31546e41b..a9a587e8e43db9ad4f0e69d1abf47775d610c930 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_bsn_at_sync.vhd
@@ -90,7 +90,6 @@ entity dp_block_validate_bsn_at_sync is
end dp_block_validate_bsn_at_sync;
architecture rtl of dp_block_validate_bsn_at_sync is
-
constant c_nof_regs : natural := 3;
constant c_clear_adr : natural := c_nof_regs - 1;
-- Define the actual size of the MM slave register
@@ -118,9 +117,7 @@ architecture rtl of dp_block_validate_bsn_at_sync is
signal bsn_at_sync_reg : std_logic_vector(g_bsn_w - 1 downto 0);
signal block_sosi : t_dp_sosi;
-
begin
-
mm_cnt_clr <= (reg_mosi.rd or reg_mosi.wr) when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_clear_adr else '0';
u_common_spulse : entity common_lib.common_spulse
port map (
@@ -229,7 +226,6 @@ begin
if in_sosi.sop = '1' then
out_valid <= '1'; -- Packets with channel unequal to g_check_channel are always valid
end if;
-
end if;
bsn_ok <= v_bsn_ok; -- bsn_ok is used to indicate if the bsn is correct for the entire sync period of g_check_channel.
bsn_at_sync <= v_bsn_at_sync; -- register to store the bsn at sync of bs_sosi.
@@ -269,5 +265,4 @@ begin
-- ST source
src_out => out_sosi
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
index 505401f8be1f86de49f02851c4c6f88d4bd1c7dc..32c4a07830c6a5f317ef2d24be6d37f6d5332ca0 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_channel.vhd
@@ -57,14 +57,11 @@ entity dp_block_validate_channel is
end dp_block_validate_channel;
architecture rtl of dp_block_validate_channel is
-
signal remove_blk : std_logic;
signal remove_blk_reg : std_logic := '0';
signal remove_sosi : t_dp_sosi;
signal keep_sosi : t_dp_sosi;
-
begin
-
assert g_mode = "=" or g_mode = "<" or g_mode = ">" report "g_mode must be one of three options: '=', '<' or '>'" severity ERROR;
gen_equal : if g_mode = "=" generate -- remove all blocks with ch = remove_channel
remove_blk <= remove_blk_reg when in_sosi.sop = '0' else
@@ -102,7 +99,6 @@ begin
keep_sosi.sop <= in_sosi.sop and not remove_blk;
keep_sosi.eop <= in_sosi.eop and not remove_blk;
keep_sosi.sync <= in_sosi.sync and not remove_blk;
-
end process;
u_pipe_remove : entity work.dp_pipeline
@@ -130,5 +126,4 @@ begin
-- ST source
src_out => out_keep_sosi
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
index c44962c7f76985562412e3a59c3125b9203f28a8..96b89286a11c2ef375bd06a7eb2b0189f41ebf85 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_err.vhd
@@ -119,7 +119,6 @@ entity dp_block_validate_err is
end dp_block_validate_err;
architecture rtl of dp_block_validate_err is
-
constant c_nof_err_ok : natural := ceil_div(g_max_block_size, g_min_block_size);
constant c_nof_regs : natural := g_nof_err_counts + 1 + 2 + 1;
constant c_clear_adr : natural := c_nof_regs - 1;
@@ -164,9 +163,7 @@ architecture rtl of dp_block_validate_err is
signal block_sosi : t_dp_sosi;
signal block_siso : t_dp_siso;
signal block_sosi_piped : t_dp_sosi;
-
begin
-
mm_cnt_clr <= (reg_mosi.rd or reg_mosi.wr) when TO_UINT(reg_mosi.address(c_mm_reg.adr_w - 1 downto 0)) = c_clear_adr else '0';
u_common_spulse : entity common_lib.common_spulse
port map (
@@ -376,5 +373,4 @@ begin
src_out.eop <= block_sosi_piped.eop and out_valid;
src_out.sync <= block_sosi_piped.sync and out_valid;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
index cd6316d9a2eb5da07e6455f8ade1bba05d875436..d523cc1506b921a52ff9e8f18b7ad7ee970946b8 100644
--- a/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
+++ b/libraries/base/dp/src/vhdl/dp_block_validate_length.vhd
@@ -64,13 +64,10 @@ entity dp_block_validate_length is
end dp_block_validate_length;
architecture rtl of dp_block_validate_length is
-
signal cnt_reg : natural;
signal cnt : natural;
signal block_sosi : t_dp_sosi;
-
begin
-
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -127,5 +124,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
index 7f12910cd4d34ac12e852015ec4bc0fbf001472d..f8c6daeaf27d4dc1e0a86bd3b0f4d462fa7e7f8f 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align.vhd
@@ -158,9 +158,7 @@ entity dp_bsn_align is
);
end dp_bsn_align;
-
architecture rtl of dp_bsn_align is
-
constant c_timeout_max : natural := largest(g_xoff_timeout, g_sop_timeout);
constant c_timeout_w : natural := ceil_log2(c_timeout_max + 1);
@@ -218,9 +216,7 @@ architecture rtl of dp_bsn_align is
signal hold_src_in_arr : t_dp_siso_arr(g_nof_input - 1 downto 0);
signal src_in : t_dp_siso;
-
begin
-
snk_out_arr <= i_snk_out_arr;
src_out_arr <= r.src_out_arr;
@@ -312,6 +308,7 @@ begin
gen_reg : if c_bsn_actual_pipeline = 1 generate
nxt_r.pend_sop_all(0) <= func_dp_stream_arr_and(pend_src_buf_arr, r.in_en_arr, "SOP");
end generate;
+
gen_pipe : if c_bsn_actual_pipeline > 1 generate
nxt_r.pend_sop_all <= func_dp_stream_arr_and(pend_src_buf_arr, r.in_en_arr, "SOP") & r.pend_sop_all(c_bsn_actual_pipeline-1 downto 1);
end generate;
@@ -504,5 +501,4 @@ begin
end if;
end case;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
index f33ad05275808ac7a65f1e0ab043b6e38784362e..e2f93b3baf63e0f68a8f584f62748b3f2ab159ec 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_reg.vhd
@@ -39,7 +39,6 @@
-- | enable_input.. = [0] | g_nof_inputs-1
-- |-----------------------------------------------------------------------|
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -67,9 +66,7 @@ entity dp_bsn_align_reg is
);
end dp_bsn_align_reg;
-
architecture str of dp_bsn_align_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_nof_input),
@@ -83,9 +80,7 @@ architecture str of dp_bsn_align_reg is
-- Registers in st_clk domain
signal out_en_arr_reg : std_logic_vector(g_nof_input * c_word_w - 1 downto 0); -- := (OTHERS => '1');
signal reg_wr_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '0');
-
begin
-
u_reg : entity common_lib.common_reg_r_w_dc
generic map (
g_cross_clock_domain => g_cross_clock_domain,
@@ -119,4 +114,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
index f2b7d843e48cd02baa10380fc34e8b82906348bb..9042f050f7797b53fec3194857d70a0b6aac009c 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_align_v2.vhd
@@ -54,7 +54,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity dp_bsn_align_v2 is
generic (
g_nof_streams : natural := 2; -- >= 2, number of input and output streams
@@ -92,9 +91,7 @@ entity dp_bsn_align_v2 is
);
end dp_bsn_align_v2;
-
architecture rtl of dp_bsn_align_v2 is
-
-- Circular buffer per stream, size is next power of 2 that fits
constant c_buffer_nof_blocks : natural := true_log_pow2(1 + g_nof_aligners_max * g_bsn_latency_max);
@@ -220,9 +217,7 @@ architecture rtl of dp_bsn_align_v2 is
signal dbg_rd_latency : natural := g_rd_latency;
signal dbg_c_buffer_nof_blocks : natural := c_buffer_nof_blocks;
signal dbg_c_product_w : natural := c_product_w;
-
begin
-
-- Output mm_sosi, also when g_use_mm_output = FALSE.
mm_sosi <= r.mm_sosi;
@@ -522,5 +517,4 @@ begin
-- ST source
src_out_arr => out_sosi_arr
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
index 3b3ca696b9ef42f0f01c0f29772ea17255ce78e4..fe7e3680603b023a0f66d06a3ef9fe760958e123 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_delay.vhd
@@ -81,9 +81,7 @@ entity dp_bsn_delay is
);
end dp_bsn_delay;
-
architecture rtl of dp_bsn_delay is
-
type t_bsn_arr is array (integer range <>) of std_logic_vector(g_bsn_w - 1 downto 0);
signal hold_sync : std_logic;
@@ -95,9 +93,7 @@ architecture rtl of dp_bsn_delay is
signal bsn_reg : std_logic_vector(g_bsn_w - 1 downto 0);
signal nxt_bsn_reg : std_logic_vector(g_bsn_w - 1 downto 0);
-
begin
-
p_clk : process(clk, rst)
begin
if rst = '1' then
@@ -137,6 +133,4 @@ begin
out_sync <= sync_dly(g_nof_block_latency) when out_release = '1' else '0'; -- combinatorial pulse
nxt_bsn_reg <= bsn_dly(g_nof_block_latency) when out_release = '1' else bsn_reg; -- register the BSN to hold it during the output block
out_bsn <= bsn_reg;
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
index 93f37c407908e6bd331aabfabcccd4f644a9899b..e32360c2085b7c1ce82fb1c07541d21957308aba 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor.vhd
@@ -46,7 +46,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use work.dp_stream_pkg.all;
-
entity dp_bsn_monitor is
generic (
g_sync_timeout : natural := 200 * 10**6; -- choose >= nof clk cycles per sync period
@@ -79,9 +78,7 @@ entity dp_bsn_monitor is
);
end dp_bsn_monitor;
-
architecture rtl of dp_bsn_monitor is
-
constant c_sync_timeout_w : natural := ceil_log2(g_sync_timeout);
constant c_bsn_w : natural := mon_bsn_at_sync'length;
constant c_cnt_sop_w : natural := mon_nof_sop'length;
@@ -140,9 +137,7 @@ architecture rtl of dp_bsn_monitor is
signal nxt_mon_bsn_first : std_logic_vector(c_bsn_w - 1 downto 0);
signal nxt_mon_bsn_first_cycle_cnt : std_logic_vector(c_word_w - 1 downto 0);
signal nxt_current_bsn : std_logic_vector(c_bsn_w - 1 downto 0);
-
begin
-
mon_sync <= sync;
mon_sync_timeout <= sync_timeout;
mon_ready_stable <= i_mon_ready_stable;
@@ -338,8 +333,4 @@ begin
cnt_en => '1',
count => cnt_cycle
);
-
end rtl;
-
-
-
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
index 39e9921aeb104003353782805322d099614f069e..1eab6bd1e082841b8170239f4c1d338304203622 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg.vhd
@@ -45,7 +45,6 @@
-- | bsn_first_cycle_cnt[31: 0] | 8
-- |-----------------------------------------------------------------------|
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -82,9 +81,7 @@ entity dp_bsn_monitor_reg is
);
end dp_bsn_monitor_reg;
-
architecture str of dp_bsn_monitor_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 4,
@@ -94,9 +91,7 @@ architecture str of dp_bsn_monitor_reg is
-- Registers in st_clk domain
signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
-
begin
-
-- Register mapping
mon_reg( 3 - 1 downto 0) <= mon_sync_timeout & mon_ready_stable & mon_xon_stable;
mon_reg(1 * c_word_w - 1 downto 3) <= (others => '0');
@@ -132,5 +127,4 @@ begin
in_reg => mon_reg, -- read only
out_reg => open -- no write
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
index fb0a4c4edf99d748411dd55f7c98fb73c5d0ca23..6f01dc61b677e6f289406c5eae62ebb6a52fb33c 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_reg_v2.vhd
@@ -77,9 +77,7 @@ entity dp_bsn_monitor_reg_v2 is
);
end dp_bsn_monitor_reg_v2;
-
architecture str of dp_bsn_monitor_reg_v2 is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 3,
@@ -89,9 +87,7 @@ architecture str of dp_bsn_monitor_reg_v2 is
-- Registers in st_clk domain
signal mon_reg : std_logic_vector(c_mm_reg.nof_dat * c_mm_reg.dat_w - 1 downto 0) := (others => '0');
-
begin
-
-- Register mapping
mon_reg( 3 - 1 downto 0) <= mon_sync_timeout & mon_ready_stable & mon_xon_stable;
mon_reg(1 * c_word_w - 1 downto 3) <= (others => '0');
@@ -126,5 +122,4 @@ begin
in_reg => mon_reg, -- read only
out_reg => open -- no write
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
index fc3841cc1c867db5b72787bfb809d994d1135650..339533f55ebd8422d8fff957ae7cfeee69b0e07c 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_monitor_v2.vhd
@@ -45,7 +45,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use work.dp_stream_pkg.all;
-
entity dp_bsn_monitor_v2 is
generic (
g_sync_timeout : natural := 200 * 10**6; -- choose >= nof clk cycles per sync period
@@ -76,9 +75,7 @@ entity dp_bsn_monitor_v2 is
);
end dp_bsn_monitor_v2;
-
architecture rtl of dp_bsn_monitor_v2 is
-
constant c_sync_timeout_w : natural := ceil_log2(g_sync_timeout);
constant c_bsn_w : natural := mon_bsn_at_sync'length;
constant c_cnt_sop_w : natural := mon_nof_sop'length;
@@ -144,9 +141,7 @@ architecture rtl of dp_bsn_monitor_v2 is
signal nxt_mon_nof_valid : std_logic_vector(c_cnt_valid_w - 1 downto 0);
signal nxt_mon_latency : std_logic_vector(c_cnt_latency_w - 1 downto 0);
signal nxt_current_bsn : std_logic_vector(c_bsn_w - 1 downto 0);
-
begin
-
mon_sync <= sync;
mon_sync_timeout <= sync_timeout;
mon_ready_stable <= i_mon_ready_stable;
@@ -340,8 +335,4 @@ begin
cnt_en => '1',
count => cnt_latency
);
-
end rtl;
-
-
-
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
index 11f30ee77740950263ee93f14c9ad476ec549e5c..b4c524a869d42b2230682245fb7aa476432c610d 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_restore_global.vhd
@@ -57,17 +57,13 @@ entity dp_bsn_restore_global is
);
end dp_bsn_restore_global;
-
architecture str of dp_bsn_restore_global is
-
signal blk_sync : std_logic;
signal bsn_at_sync : std_logic_vector(g_bsn_w - 1 downto 0);
signal nxt_bsn_at_sync : std_logic_vector(g_bsn_w - 1 downto 0);
signal bsn_restored : std_logic_vector(g_bsn_w - 1 downto 0);
signal snk_in_restored : t_dp_sosi;
-
begin
-
-- keep BSN at sync
p_clk : process(clk, rst)
begin
@@ -117,5 +113,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
index 2bb5db1000d725081b2a4a91ab5c473cc7782d38..b095b03d52a965135e7aac88a20526843d3bd7a1 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler.vhd
@@ -37,7 +37,6 @@ use work.dp_stream_pkg.all;
-- a new scheduled_bsn value.
-- . The bsn scheduler can only handle one scheduled_bsn at a time.
-
entity dp_bsn_scheduler is
generic (
g_bsn_w : natural := 48
@@ -53,14 +52,10 @@ entity dp_bsn_scheduler is
);
end dp_bsn_scheduler;
-
architecture rtl of dp_bsn_scheduler is
-
signal trigger_en : std_logic;
signal nxt_trigger_en : std_logic;
-
begin
-
-- Use the block sync combinatorially, to avoid one cycle latency and have block synchronisation for the trigger_out
trigger_out <= snk_in.eop and trigger_en;
@@ -74,6 +69,4 @@ begin
trigger_en <= nxt_trigger_en;
end if;
end process;
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
index d90b7705c3f717af8648134aba6053cff7b04cb1..36d2d553ae37566374c310a39e4f1f0c651429fa 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_scheduler_reg.vhd
@@ -57,9 +57,7 @@ entity dp_bsn_scheduler_reg is
);
end dp_bsn_scheduler_reg;
-
architecture rtl of dp_bsn_scheduler_reg is
-
constant c_bsn_w : natural := st_current_bsn'length;
-- Define the actual size of the MM slave register
@@ -74,9 +72,7 @@ architecture rtl of dp_bsn_scheduler_reg is
signal mm_current_bsn_hi : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
signal mm_scheduled_bsn : std_logic_vector(c_longword_w - 1 downto 0) := (others => '0');
signal mm_scheduled_bsn_wr : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -165,7 +161,6 @@ begin
end generate; -- no_cross
gen_cross : if g_cross_clock_domain = true generate
-
-- write occurs with sufficient margin before it is used, still use common_reg_cross_domain nonetheless
u_init_bsn : entity common_lib.common_reg_cross_domain
port map (
@@ -193,7 +188,6 @@ begin
out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
out_new => open
);
-
end generate; -- gen_cross
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
index 5dc319ffda8c3452b06a56a5bd4ce20b6f56e065..b1909332630be2e4e9bc92977b5009de29141226 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source.vhd
@@ -61,9 +61,7 @@ entity dp_bsn_source is
);
end dp_bsn_source;
-
architecture rtl of dp_bsn_source is
-
constant c_block_size_cnt_w : natural := ceil_log2(g_block_size);
constant c_block_cnt_zero : std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
@@ -84,9 +82,7 @@ architecture rtl of dp_bsn_source is
signal nxt_dp_on_status : std_logic;
signal i_dp_on_status : std_logic;
-
begin
-
src_out <= i_src_out;
dp_on_status <= i_dp_on_status;
@@ -154,11 +150,9 @@ begin
when others => -- s_init
nxt_state <= s_dp_off;
-
end case;
end process;
-
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -177,7 +171,4 @@ begin
i_dp_on_status <= nxt_dp_on_status;
end if;
end process;
-
end rtl;
-
-
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
index 4e0beb0889ab6cca1f647f00da2d6a7ed78308cd..e6310abb8fd4fe3e288e0643536d7321e766a073 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg.vhd
@@ -69,9 +69,7 @@ entity dp_bsn_source_reg is
);
end dp_bsn_source_reg;
-
architecture rtl of dp_bsn_source_reg is
-
constant c_bsn_w : natural := st_init_bsn'length;
-- Define the actual size of the MM slave register
@@ -96,9 +94,7 @@ architecture rtl of dp_bsn_source_reg is
signal mm_current_bsn_hi : std_logic_vector(c_word_w - 1 downto 0) := (others => '0');
-- Registers in st_clk domain
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -279,7 +275,6 @@ begin
out_dat => mm_current_bsn(c_bsn_w - 1 downto 0),
out_new => open
);
-
end generate; -- gen_cross
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
index 872ffa66a52c678d6e052d02588b768dab8c6906..71eab87eda14396b01034520b7417afaf2385af0 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_reg_v2.vhd
@@ -71,9 +71,7 @@ entity dp_bsn_source_reg_v2 is
);
end dp_bsn_source_reg_v2;
-
architecture rtl of dp_bsn_source_reg_v2 is
-
constant c_bsn_w : natural := st_bsn_init'length;
constant c_bsn_time_offset_w : natural := st_bsn_time_offset'length;
@@ -102,9 +100,7 @@ architecture rtl of dp_bsn_source_reg_v2 is
signal mm_bsn_time_offset_wr : std_logic;
-- Registers in st_clk domain
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -317,7 +313,6 @@ begin
out_dat => st_bsn_time_offset,
out_new => open
);
-
end generate; -- gen_cross
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
index c6fb19795c6403ccc22b5fcde34a7fd23ca30c94..1d2ebf0fbbdcdbe4107083f2e8c8dbfafd8c45a2 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_source_v2.vhd
@@ -87,9 +87,7 @@ entity dp_bsn_source_v2 is
);
end dp_bsn_source_v2;
-
architecture rtl of dp_bsn_source_v2 is
-
constant c_block_size_cnt_w : natural := ceil_log2(g_block_size);
constant c_block_cnt_zero : std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
@@ -120,9 +118,7 @@ architecture rtl of dp_bsn_source_v2 is
signal sync_size_cnt : std_logic_vector(c_word_w - 1 downto 0);
signal nxt_sync : std_logic;
signal sync : std_logic;
-
begin
-
src_out <= i_src_out;
dp_on_status <= i_src_out.valid;
bs_restart <= i_bs_restart;
@@ -266,5 +262,4 @@ begin
bsn_time_offset_cnt <= nxt_bsn_time_offset_cnt;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
index b826cc3eb1ddae340f47b8979e439461e89838e7..f92809dc5488820c280468926a5ee741233aee97 100644
--- a/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
@@ -147,9 +147,7 @@ entity dp_bsn_sync_scheduler is
);
end dp_bsn_sync_scheduler;
-
architecture rtl of dp_bsn_sync_scheduler is
-
type t_reg is record
enable_init : std_logic;
enable : std_logic;
@@ -181,9 +179,7 @@ architecture rtl of dp_bsn_sync_scheduler is
signal output_start_interval_reg : std_logic := '0';
signal output_sync : std_logic;
signal output_sosi : t_dp_sosi;
-
begin
-
assert g_block_size >= 2 report "g_block_size must be >= 2." severity FAILURE;
-- Capture monitoring info
@@ -424,7 +420,6 @@ begin
output_start_interval_reg <= output_start_interval when rising_edge(clk);
-
-----------------------------------------------------------------------------
-- Pipeline output to avoid timing closure problems due to use of output_enable
-----------------------------------------------------------------------------
@@ -446,12 +441,10 @@ begin
out_start_interval <= output_start_interval_reg;
out_enable <= r.output_enable;
end generate;
+
no_pipe_out_start : if g_pipeline = 0 generate
out_start <= output_start;
out_start_interval <= output_start_interval;
out_enable <= output_enable;
end generate;
-
end rtl;
-
-
diff --git a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
index fd3d15755d758257e66fa78615b4917df40e21f4..0326cf21388a40649729228785f7f2148441ed95 100644
--- a/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_calculate_crc.vhd
@@ -36,7 +36,6 @@ use easics_lib.PCK_CRC28_D28.all;
use easics_lib.PCK_CRC32_D32.all;
use easics_lib.PCK_CRC32_D64.all;
-
entity dp_calculate_crc is
generic (
g_data_w : natural := 32;
@@ -51,9 +50,7 @@ entity dp_calculate_crc is
);
end dp_calculate_crc;
-
architecture rtl of dp_calculate_crc is
-
constant c_crc_init : std_logic_vector(g_crc_w - 1 downto 0) := (others => '1');
function func_next_crc(data, crc : std_logic_vector) return std_logic_vector is
@@ -75,9 +72,7 @@ architecture rtl of dp_calculate_crc is
signal nxt_calc_crc : std_logic_vector(g_crc_w - 1 downto 0);
signal i_blk_crc : std_logic_vector(g_crc_w - 1 downto 0);
signal nxt_blk_crc : std_logic_vector(g_crc_w - 1 downto 0);
-
begin
-
data <= snk_in.data(g_data_w - 1 downto 0);
blk_crc <= i_blk_crc;
@@ -112,5 +107,4 @@ begin
nxt_blk_crc <= v_crc;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_complex_add.vhd b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
index ab564fbffec138ac05ef38de3bc22d4f5f8ef9dc..046cd7f80aff6a37fff1dbfddd8e936d75e57bde 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_add.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_add.vhd
@@ -32,7 +32,6 @@ use dp_lib.dp_stream_pkg.all;
-- . Provide a complex adder tree with streaming array I/O types
-- Description:
-
entity dp_complex_add is
generic (
g_technology : natural := c_tech_select_default;
@@ -50,7 +49,6 @@ entity dp_complex_add is
end dp_complex_add;
architecture str of dp_complex_add is
-
constant c_pipeline : natural := 1;
constant c_pipeline_adder_tree : natural := c_pipeline * ceil_log2(g_nof_inputs);
@@ -64,9 +62,7 @@ architecture str of dp_complex_add is
signal common_adder_tree_re_sum : std_logic_vector(c_common_adder_tree_sum_w - 1 downto 0);
signal common_adder_tree_im_sum : std_logic_vector(c_common_adder_tree_sum_w - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Complex Adder Trees
-----------------------------------------------------------------------------
@@ -132,5 +128,4 @@ begin
-- ST source
src_out => snk_in_pipe
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
index 38abb50d56b9106fa0ed6434f4b3aeb1c89df2aa..b41f0cfdf0a6008a676933865c476b5c2efb8e5e 100644
--- a/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
+++ b/libraries/base/dp/src/vhdl/dp_complex_mult.vhd
@@ -55,14 +55,11 @@ entity dp_complex_mult is
end dp_complex_mult;
architecture str of dp_complex_mult is
-
constant c_pipeline : natural := 3; -- Delay introduces by IP multiplier used
signal common_complex_mult_src_out_arr : t_dp_sosi_arr(g_nof_multipliers - 1 downto 0);
signal dp_pipeline_src_out_arr : t_dp_sosi_arr(g_nof_multipliers - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Complex Multipliers
-----------------------------------------------------------------------------
@@ -109,5 +106,4 @@ begin
in_dat => snk_in_2arr_2(0)(0).sync,
out_dat => src_out_arr(0).sync
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
index 697fb8fba2c80305a11a99ba38bfafa70aad1390..2fafe0a210809bd5849bd512b51dc11ff4a022de 100644
--- a/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_components_pkg.vhd
@@ -29,7 +29,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package dp_components_pkg is
-
constant c_dp_clk_MHz : natural := 200;
constant c_dp_sync_timeout : natural := c_dp_clk_MHz * 10**6 + c_dp_clk_MHz * 10**5; -- 10% margin for nominal 1 s
@@ -42,10 +41,7 @@ package dp_components_pkg is
constant c_dp_strobe_total_count_reg_nof_counts_max : natural := 2**c_dp_strobe_total_count_reg_adr_w / 2 - 1; -- = 15
constant c_dp_strobe_total_count_reg_clear_adr : natural := c_dp_strobe_total_count_reg_nof_counts_max * 2; -- after counters in REGMAP
constant c_dp_strobe_total_count_reg_flush_adr : natural := c_dp_strobe_total_count_reg_nof_counts_max * 2 + 1;
-
end dp_components_pkg;
-
package body dp_components_pkg is
end dp_components_pkg;
-
diff --git a/libraries/base/dp/src/vhdl/dp_concat.vhd b/libraries/base/dp/src/vhdl/dp_concat.vhd
index 39714a61016abe75c08e50a77df956e8a902f9b5..e2d6a58f0de31b72bf1c5cebac263981e076a05b 100644
--- a/libraries/base/dp/src/vhdl/dp_concat.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat.vhd
@@ -66,7 +66,6 @@ use work.dp_stream_pkg.all;
-- 10 made tb_dp_concat self checking for data for c_nof_symbols_per_data > 1
-- 11 iterate these steps until the dp_concat works OK
-
entity dp_concat is
generic (
g_data_w : natural := 16; -- >= 1
@@ -84,9 +83,7 @@ entity dp_concat is
);
end dp_concat;
-
architecture rtl of dp_concat is
-
constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w; -- nof symbols per data
constant c_empty_w : natural := ceil_log2(c_nof_symbols_per_data);
constant c_bsn_w : natural := c_dp_stream_bsn_w;
@@ -124,9 +121,7 @@ architecture rtl of dp_concat is
signal i_src_out : t_dp_sosi;
signal nxt_src_out : t_dp_sosi;
-
begin
-
assert (g_data_w mod g_symbol_w) = 0 report "dp_concat : g_data_w/g_symbol_w must be an integer" severity FAILURE;
snk_out_arr <= i_snk_out_arr;
@@ -334,5 +329,4 @@ begin
flush_arr(0).xon <= src_in.xon;
flush_arr(1).xon <= src_in.xon;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
index f896d428f975a8a40e9c07b630537585c097c7ea..c115e41e883e85637f1ea7bc9eac1a4fbb1e4d4d 100644
--- a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
@@ -35,7 +35,6 @@
-- g_symbol_w = g_data_w if the empty field is always 0, so the number of bits in
-- the header and data are an integer number of g_data_w.
-
library IEEE, common_lib, technology_lib, mm_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -74,9 +73,7 @@ entity dp_concat_field_blk is
);
end dp_concat_field_blk;
-
architecture str of dp_concat_field_blk is
-
constant c_dp_field_blk_snk_data_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr , "RW"));
constant c_dp_field_blk_src_data_w : natural := g_data_w;
@@ -94,16 +91,13 @@ architecture str of dp_concat_field_blk is
signal reg_hdr_dat_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal reg_hdr_dat_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
assert c_dp_field_blk_snk_data_w <= c_dp_stream_data_w report "Number of header bits must fit in t_dp_sosi data field." severity FAILURE;
---------------------------------------------------------------------------------------
-- Create header block & concatenate header to offload stream.
---------------------------------------------------------------------------------------
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
-
p_wire_valid : process(snk_in_arr, hdr_fields_in_arr)
begin
for i in 0 to g_nof_streams - 1 loop
@@ -155,12 +149,10 @@ begin
);
dp_field_blk_src_in_arr(i) <= dp_concat_snk_out_2arr(i)(1);
-
end generate;
-- Prepend the header block to the input block
gen_dp_concat : for i in 0 to g_nof_streams - 1 generate
-
dp_concat_snk_in_2arr(i)(0) <= snk_in_arr(i);
dp_concat_snk_in_2arr(i)(1) <= dp_field_blk_src_out_arr(i);
@@ -195,5 +187,4 @@ begin
mosi_arr => reg_hdr_dat_mosi_arr,
miso_arr => reg_hdr_dat_miso_arr
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_counter.vhd b/libraries/base/dp/src/vhdl/dp_counter.vhd
index e84b4ee2a8884891d316e99b93794f8695eb56ca..9748348ee2a86f2031e137f3ef2834fb75fdf7eb 100644
--- a/libraries/base/dp/src/vhdl/dp_counter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter.vhd
@@ -92,9 +92,7 @@ entity dp_counter is
);
end dp_counter;
-
architecture wrap of dp_counter is
-
-- force downto range for unconstraint g_range generics
constant c_range_len : natural := g_range_start'length; -- g_nof_counters must be <= c_range_len
constant c_range_start : t_nat_natural_arr(c_range_len - 1 downto 0) := g_range_start;
@@ -105,9 +103,7 @@ architecture wrap of dp_counter is
constant c_use_dp_pipeline_ready : boolean := (g_pipeline_src_in > 0);
signal dp_counter_func_src_out_arr : t_dp_sosi_arr(g_nof_counters - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- dp_counter_func
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func.vhd b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
index 9f074ba9feedad8875225eb2a8604bf3eb95f021..89431450ddc9d374bc5029dfa76a666ae1b79374 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func.vhd
@@ -61,9 +61,7 @@ entity dp_counter_func is
);
end dp_counter_func;
-
architecture str of dp_counter_func is
-
-- force downto range for unconstraint g_range generics
constant c_range_len : natural := g_range_start'length; -- g_nof_counters must be <= c_range_len
constant c_range_start : t_nat_natural_arr(c_range_len - 1 downto 0) := g_range_start;
@@ -79,14 +77,11 @@ architecture str of dp_counter_func is
signal count_max_arr : std_logic_vector(g_nof_counters - 1 downto 0);
type t_count_arr is array(g_nof_counters - 1 downto 0) of std_logic_vector(c_max_count_w - 1 downto 0);
signal count_arr : t_count_arr;
-
begin
-
--------------------------------------------------------------------------------
-- Counter control inputs
-------------------------------------------------------------------------------
gen_dp_counter_func_single_input : for i in 0 to g_nof_counters - 1 generate
-
gen_c0 : if i = 0 generate
count_en_arr(i) <= count_en;
check_max_arr(i) <= count_en;
diff --git a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
index b258fec13123272b5d2286402e54f987f762436b..01c3d94c4a083a11f3794596d02ae05a34bf6f91 100644
--- a/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
+++ b/libraries/base/dp/src/vhdl/dp_counter_func_single.vhd
@@ -55,9 +55,7 @@ entity dp_counter_func_single is -- FIXME move this to common
);
end dp_counter_func_single;
-
architecture rtl of dp_counter_func_single is
-
-- The user defines the counters like a Python range(start,stop,step) in which the stop value
-- is never actually reached. Calculate the actual maximum values here.
-- . Example:
@@ -80,9 +78,7 @@ architecture rtl of dp_counter_func_single is
end record;
signal r, nxt_r : t_reg;
-
begin
-
--------------------------------------------------------------------------------
-- Combinational logic
--------------------------------------------------------------------------------
@@ -147,6 +143,4 @@ begin
count_init <= nxt_r.count_init;
count_min <= nxt_r.count_min;
count_max <= nxt_r.count_max;
-
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
index 8418f9578d8e96674ad855f5aa096ec8f5fc68fe..e652bad0f33602eaf96897dd7ae3742d9a380e17 100644
--- a/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave.vhd
@@ -59,9 +59,7 @@ entity dp_deinterleave is
);
end dp_deinterleave;
-
architecture wrap of dp_deinterleave is
-
constant c_complex_w : natural := g_dat_w / 2;
signal common_deinterleave_in_dat : std_logic_vector(g_dat_w - 1 downto 0);
@@ -71,9 +69,7 @@ architecture wrap of dp_deinterleave is
signal common_deinterleave_src_out_arr : t_dp_sosi_arr(g_nof_out - 1 downto 0);
signal dp_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_out - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- DP wrapper around common_deinterleave
-----------------------------------------------------------------------------
diff --git a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
index 5c9bd2ba3dd6fdf35b2777c0ce35125d4165d352..aea3de86d75eeb404cded71d73fb6ba2e9b20b91 100755
--- a/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
+++ b/libraries/base/dp/src/vhdl/dp_deinterleave_one_to_n.vhd
@@ -63,9 +63,7 @@ entity dp_deinterleave_one_to_n is
);
end dp_deinterleave_one_to_n;
-
architecture rtl of dp_deinterleave_one_to_n is
-
-- local state registers
type t_reg is record
cnt : natural range 0 to g_nof_outputs - 1;
@@ -77,9 +75,7 @@ architecture rtl of dp_deinterleave_one_to_n is
signal out_siso_arr : t_dp_siso_arr(g_nof_outputs - 1 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(g_nof_outputs - 1 downto 0);
-
begin
-
p_reg : process(rst, clk)
begin
if rst = '1' then
@@ -167,5 +163,4 @@ begin
src_in_arr => src_in_arr,
src_out_arr => src_out_arr
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_demux.vhd b/libraries/base/dp/src/vhdl/dp_demux.vhd
index 392e745ddcf4d2f4bafd65b9f7f3b20409fb8279..f70721856d148527ca0ca2e041dab4a0107c098d 100644
--- a/libraries/base/dp/src/vhdl/dp_demux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_demux.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use work.dp_stream_pkg.all;
-
-- Purpose:
-- De-multiplex frames from one input stream with one or more channels onto
-- separate output streams.
@@ -82,9 +81,7 @@ entity dp_demux is
);
end dp_demux;
-
architecture rtl of dp_demux is
-
-- The low part of snk_in.channel is used to select the output port and the high part of snk_in.channel used for src_out_arr[].channel
constant c_sel_w : natural := true_log2(g_nof_output);
@@ -101,9 +98,7 @@ architecture rtl of dp_demux is
signal prev_src_in_arr : t_dp_siso_arr(0 to g_nof_output - 1);
signal pend_src_out_arr : t_dp_sosi_arr(0 to g_nof_output - 1);
-
begin
-
-- Collapse to wires
gen_one : if g_nof_output = 1 generate
snk_out <= src_in_arr(0);
@@ -139,7 +134,6 @@ begin
-- Use external MM control input to select the output
gen_mode_2 : if g_mode = 2 generate
-
no_pkt_ctrl: if g_sel_ctrl_pkt = false generate
-- Select new output immediately (registered: one cycle after sel_ctrl change)
p_clk : process(rst, clk)
@@ -198,12 +192,10 @@ begin
siso => adapt_siso, -- We're using the adapted sink_in with RL=0
pkt_det => pkt_det
);
-
end generate;
end generate;
-
------------------------------------------------------------------------------
-- g_combined=TRUE : All outputs must be ready
------------------------------------------------------------------------------
@@ -236,7 +228,6 @@ begin
end process;
end generate;
-
------------------------------------------------------------------------------
-- g_combined=FALSE : Only the output for the current channel needs to be ready
------------------------------------------------------------------------------
@@ -307,5 +298,4 @@ begin
);
end generate;
end generate;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_distribute.vhd b/libraries/base/dp/src/vhdl/dp_distribute.vhd
index 23a5d39635c5ab6cd21c137b995cbda49018861e..4165fd637055cd2ac3a3fb7b73ad9388147200f9 100644
--- a/libraries/base/dp/src/vhdl/dp_distribute.vhd
+++ b/libraries/base/dp/src/vhdl/dp_distribute.vhd
@@ -122,9 +122,7 @@ entity dp_distribute is
);
end dp_distribute;
-
architecture str of dp_distribute is
-
constant c_demux_mode : natural := sel_a_b(g_tx, 1, 0);
constant c_demux_remove_channel_lo : boolean := not g_tx;
@@ -150,9 +148,7 @@ architecture str of dp_distribute is
signal mux_sosi_2arr : t_mux_sosi_2arr(0 to g_nof_output - 1);
signal tx_siso_arr : t_dp_siso_arr(0 to g_nof_output - 1); -- ST at output of mux, to src_* for ST output after optional encoding
signal tx_sosi_arr : t_dp_sosi_arr(0 to g_nof_output - 1);
-
begin
-
no_fifo : if g_use_fifo = false generate
snk_out_arr <= in_siso_arr;
in_sosi_arr <= snk_in_arr;
@@ -297,5 +293,4 @@ begin
);
end generate;
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
index 86fed113e909bf8633dae51cf9c4917126e25af3..33b96ad56573de75c40d0db3be6ade34afc6d8a7 100644
--- a/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_dummy_source.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -49,15 +48,11 @@ entity dp_dummy_source is
);
end dp_dummy_source;
-
architecture rtl of dp_dummy_source is
-
constant c_dp_sosi_dummy : t_dp_sosi := ('0', g_dummy_bsn, g_dummy_data, g_dummy_re, g_dummy_im, '0', '0', '0', g_dummy_empty, g_dummy_channel, g_dummy_err);
signal block_sosi : t_dp_sosi;
-
begin
-
src_out.valid <= block_sosi.valid;
src_out.sop <= block_sosi.sop;
src_out.eop <= block_sosi.eop;
@@ -84,6 +79,4 @@ begin
en => '1'
);
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_eop_extend.vhd b/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
index 512c340bd8c9788cdca9aee7c4b83b94e7625826..c32b6480ea4253445887590078cb47b52bc63fbd 100644
--- a/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
+++ b/libraries/base/dp/src/vhdl/dp_eop_extend.vhd
@@ -41,13 +41,9 @@ entity dp_eop_extend is
);
end dp_eop_extend;
-
architecture rtl of dp_eop_extend is
-
signal extend : std_logic;
-
begin
-
u_extend : entity common_lib.common_switch
port map (
rst => rst,
@@ -58,5 +54,4 @@ begin
);
eop_extend <= (in_eop or extend) and not in_sop;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_example_dut.vhd b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
index 03efd8b3a093a048ed4d1fcd7b940e33a630be75..5492efb3861b530acbbba5423b04ea2eace9526c 100644
--- a/libraries/base/dp/src/vhdl/dp_example_dut.vhd
+++ b/libraries/base/dp/src/vhdl/dp_example_dut.vhd
@@ -180,9 +180,7 @@ entity dp_example_dut is
);
end dp_example_dut;
-
architecture rtl of dp_example_dut is
-
type t_reg is record
src_out : t_dp_sosi; -- sosi output
hold_out : t_dp_sosi; -- hold snk_in.sync/sop/eop until end of section and then hold valid src_out until src_in.ready
@@ -191,9 +189,7 @@ architecture rtl of dp_example_dut is
signal r_snk_out : t_dp_siso := c_dp_siso_rdy;
signal r : t_reg;
signal nxt_r : t_reg;
-
begin
-
p_func : process(rst, r, snk_in, src_in)
variable v : t_reg;
begin
@@ -289,11 +285,9 @@ begin
r_snk_out <= c_dp_siso_rdy;
-- < force r_snk_out.ready='0' based on nxt_r if function needs to apply backpressure >
-
end process;
-- combined local and remote src_in flow control
snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready; -- if there is pending output then the src_in ready determines the flow control
snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
index 54970559600787cb3fd891da509f5787b6140a55..abab9714879e983e963cad92c815c9542e56e933 100644
--- a/libraries/base/dp/src/vhdl/dp_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
@@ -128,7 +128,6 @@ entity dp_field_blk is
end dp_field_blk;
architecture str of dp_field_blk is
-
-- CONSTANT c_ovr_field_arr : t_common_field_arr(g_field_arr'RANGE) := field_ovr_arr(g_field_arr, g_field_sel);
-- Mode: fields to data block (c_field_to_block=True) or data block to fields (c_field_to_block=False)
@@ -150,9 +149,7 @@ architecture str of dp_field_blk is
signal dp_repack_data_src_out : t_dp_sosi;
signal dp_repack_data_src_in : t_dp_siso;
-
begin
-
---------------------------------------------------------------------------------------
-- dp_repack_data in source mode: single-cycle snk_in.data to multi-cycle DP data block
---------------------------------------------------------------------------------------
@@ -255,5 +252,4 @@ begin
--
-- slv_out => field_override_arr
-- );
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
index 91105a6c8c6f2916346ed1a9ce2e2466a0401e28..b611fd279702d92d701adc16f58cdb88faec7984 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core.vhd
@@ -89,9 +89,7 @@ entity dp_fifo_core is
);
end dp_fifo_core;
-
architecture str of dp_fifo_core is
-
constant c_use_data : boolean := true;
constant c_ctrl_w : natural := 2; -- sop and eop
@@ -129,9 +127,7 @@ architecture str of dp_fifo_core is
signal rd_siso : t_dp_siso;
signal rd_sosi : t_dp_sosi := c_dp_sosi_rst; -- initialize default values for unused sosi fields
-
begin
-
-- Output monitor FIFO filling
wr_ful <= fifo_wr_ful;
wr_usedw <= fifo_wr_usedw;
@@ -262,5 +258,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
index 1ec8ea0443cb5ba97edbc3c268bd6c915c40784f..b3a020284e31c610dbf1859094006f769ec39299 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_core_arr.vhd
@@ -98,9 +98,7 @@ entity dp_fifo_core_arr is
);
end dp_fifo_core_arr;
-
architecture str of dp_fifo_core_arr is
-
constant c_use_data : boolean := true;
constant c_total_data_w : natural := g_nof_streams * g_data_w;
constant c_ctrl_w : natural := 2; -- sop and eop
@@ -146,9 +144,7 @@ architecture str of dp_fifo_core_arr is
signal in_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
signal out_aux_sosi : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
-- Output monitor FIFO filling
wr_ful <= fifo_wr_ful;
wr_usedw <= fifo_wr_usedw;
@@ -175,6 +171,7 @@ begin
wr_data_complex_arr(I) <= snk_in_arr(I).im(c_complex_w - 1 downto 0) & snk_in_arr(I).re(c_complex_w - 1 downto 0);
wr_data((I + 1) * g_data_w - 1 downto I * g_data_w) <= snk_in_arr(I).data(g_data_w - 1 downto 0) when g_use_complex = false else RESIZE_UVEC(wr_data_complex_arr(I), g_data_w);
end generate;
+
-- fifo wr wires
fifo_wr_req <= snk_in_arr(0).valid;
fifo_wr_dat <= func_slv_concat(c_use_data, g_use_bsn, g_use_empty, g_use_channel, g_use_error, g_use_sync, g_use_ctrl, g_use_aux,
@@ -307,5 +304,4 @@ begin
src_in => src_in_arr(0),
src_out => out_aux_sosi
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
index 41adce2ef407f8e6d29cc80a102c7c853b76a97e..3ec0c419a8368a0b4a1730d264765f4a3405d620 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc.vhd
@@ -69,10 +69,8 @@ entity dp_fifo_dc is
);
end dp_fifo_dc;
-
architecture str of dp_fifo_dc is
begin
-
u_dp_fifo_core : entity work.dp_fifo_core
generic map (
g_technology => g_technology,
@@ -112,5 +110,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
index 4ce5463f84d9a77229154abc2e583e17278305ae..5bc9dffb7f286cb79db7b3d6c6994c6cd236657c 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_arr.vhd
@@ -76,10 +76,8 @@ entity dp_fifo_dc_arr is
);
end dp_fifo_dc_arr;
-
architecture str of dp_fifo_dc_arr is
begin
-
u_dp_fifo_core_arr : entity work.dp_fifo_core_arr
generic map (
g_technology => g_technology,
@@ -124,5 +122,4 @@ begin
src_out_arr => src_out_arr,
out_aux => out_aux
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
index 3e3fd2fc20bc4ce1c0869592d523006e07d92900..2162fd4be1fbdf97b097a5e316bee168eca6e6cd 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_dc_mixed_widths.vhd
@@ -137,9 +137,7 @@ entity dp_fifo_dc_mixed_widths is
);
end dp_fifo_dc_mixed_widths;
-
architecture str of dp_fifo_dc_mixed_widths is
-
constant c_wr_wide : boolean := sel_a_b(g_wr_data_w > g_rd_data_w, true, false);
constant c_nof_narrow : natural := largest(g_wr_data_w / g_rd_data_w, g_rd_data_w / g_wr_data_w);
constant c_nof_narrow_wr : natural := sel_a_b(c_wr_wide, c_nof_narrow, 1);
@@ -160,7 +158,6 @@ architecture str of dp_fifo_dc_mixed_widths is
constant c_fifo_wr_dat_w : natural := sel_a_b(c_wr_wide, c_fifo_wide_data_w, c_fifo_narrow_data_w);
constant c_fifo_rd_dat_w : natural := sel_a_b(c_wr_wide, c_fifo_narrow_data_w, c_fifo_wide_data_w);
-
signal arst : std_logic;
signal i_wr_usedw : std_logic_vector(wr_usedw'range);
@@ -188,9 +185,7 @@ architecture str of dp_fifo_dc_mixed_widths is
signal i_snk_out : t_dp_siso := c_dp_siso_rst;
signal nxt_snk_out : t_dp_siso := c_dp_siso_rst;
-
begin
-
-- Use i_snk_out with defaults to force unused snk_out bits and fields to '0'
snk_out <= i_snk_out;
@@ -294,7 +289,6 @@ begin
-- FIFO write multiple parallel --> read one serial
gen_wr_wide : if c_wr_wide = true generate
-
gen_ctrl : if g_use_ctrl = true generate
-- Write the wide SOSI
p_fifo_wr_dat : process(snk_in)
@@ -314,6 +308,7 @@ begin
end if;
end loop;
end process;
+
-- Read the narrow SOSI
rd_sosi.data <= RESIZE_DP_DATA(fifo_rd_dat(c_fifo_narrow_data_w - 1 downto 2)); -- c_ctrl_w = 2
rd_sosi.valid <= fifo_rd_val and not rd_gap_val;
@@ -342,7 +337,6 @@ begin
end process;
rd_gap_val <= rd_eop_hld and not fifo_rd_dat(1); -- valid during gap between this frame eop and next frame sop
-
end generate;
no_ctrl : if g_use_ctrl = false generate
@@ -356,6 +350,7 @@ begin
fifo_wr_dat((I + 1) * c_narrow_data_w - 1 downto I * c_narrow_data_w) <= snk_in.data((vB + 1) * c_narrow_data_w - 1 downto vB * c_narrow_data_w);
end loop;
end process;
+
-- Read the narrow SOSI
rd_sosi.data <= RESIZE_DP_DATA(fifo_rd_dat(c_narrow_data_w - 1 downto 0));
rd_sosi.valid <= fifo_rd_val;
@@ -365,7 +360,6 @@ begin
-- FIFO write one serial --> read multiple parallel
gen_rd_wide : if c_wr_wide = false generate
-
gen_ctrl : if g_use_ctrl = true generate
-- Write the narrow SOSI
fifo_wr_dat <= snk_in.data(c_narrow_data_w - 1 downto 0) & snk_in.sop & snk_in.eop;
@@ -447,10 +441,8 @@ begin
rd_sosi <= v_sosi;
end process;
end generate;
-
end generate; -- gen_rd_wide
-
-- Support show ahead FIFO with ready latency = 0 at read output
u_rl : entity work.dp_latency_adapter
generic map (
@@ -467,7 +459,5 @@ begin
src_in => src_in,
src_out => src_out
);
-
end generate; -- gen_mixed
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
index 20d57efaa17f62e4b25e21f115de154495c29ca2..5ba44fca042bd7a1f6e631bf2f9108469fc3c4e0 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill.vhd
@@ -75,10 +75,8 @@ entity dp_fifo_fill is
);
end dp_fifo_fill;
-
architecture str of dp_fifo_fill is
begin
-
u_dp_fifo_fill_sc : entity work.dp_fifo_fill_sc
generic map (
g_technology => g_technology,
@@ -120,5 +118,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
index 1b296951d84780d3d9324a6a95a0629f2d38d908..f7c848b155e35b766066af8650195b02bf80287c 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_core.vhd
@@ -108,9 +108,7 @@ entity dp_fifo_fill_core is
);
end dp_fifo_fill_core;
-
architecture rtl of dp_fifo_fill_core is
-
constant c_fifo_rl : natural := sel_a_b(g_fifo_fill = 0, 1, g_fifo_rl);
constant c_fifo_fill_margin : natural := g_fifo_af_margin + 2; -- add +2 extra margin, with tb_dp_fifo_fill it follows that +1 is also enough to avoid almost full when fifo is operating near g_fifo_fill level
constant c_fifo_size : natural := largest(g_fifo_size, g_fifo_fill + c_fifo_fill_margin);
@@ -145,9 +143,7 @@ architecture rtl of dp_fifo_fill_core is
-- Signals for g_fifo_rl=1
signal hold_src_in : t_dp_siso;
signal pend_src_out : t_dp_sosi;
-
begin
-
-- Output monitor FIFO filling
wr_usedw <= wr_fifo_usedw;
rd_usedw <= rd_fifo_usedw;
@@ -245,7 +241,6 @@ begin
end generate; -- no_fill
gen_fill : if g_fifo_fill > 0 generate
-
src_out <= i_src_out;
p_rd_clk: process(rd_clk, rd_rst)
@@ -405,6 +400,5 @@ begin
hold_src_in.xon <= src_in.xon;
end process;
end generate; -- gen_rl_1
-
end generate; -- gen_fill
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
index d5099ebc8fd59793d8adb228ba23a509b5ebb019..e766edd8f673e76a7ca4f1af85467fc55e8ce88b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_dc.vhd
@@ -73,10 +73,8 @@ entity dp_fifo_fill_dc is
);
end dp_fifo_fill_dc;
-
architecture str of dp_fifo_fill_dc is
begin
-
u_dp_fifo_fill_core : entity work.dp_fifo_fill_core
generic map (
g_technology => g_technology,
@@ -119,5 +117,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
index 3f2abfd71def8826205ce01c75174837bd53f458..c7b793d0b5d61acaf586ec16a5808f174d31aae3 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop.vhd
@@ -106,7 +106,6 @@ entity dp_fifo_fill_eop is
end dp_fifo_fill_eop;
architecture rtl of dp_fifo_fill_eop is
-
constant c_fifo_rl : natural := sel_a_b(g_fifo_fill = 0, 1, g_fifo_rl);
constant c_fifo_fill_margin : natural := g_fifo_af_margin + 2; -- add +2 extra margin, with tb_dp_fifo_fill it follows that +1 is also enough to avoid almost full when fifo is operating near g_fifo_fill level
constant c_fifo_size : natural := largest(g_fifo_size, g_fifo_fill + c_fifo_fill_margin);
@@ -156,9 +155,7 @@ architecture rtl of dp_fifo_fill_eop is
-- Signals for g_fifo_rl=1
signal hold_src_in : t_dp_siso;
signal pend_src_out : t_dp_sosi;
-
begin
-
-- Output monitor FIFO filling
wr_usedw <= wr_fifo_usedw;
rd_usedw <= rd_fifo_usedw;
@@ -302,14 +299,12 @@ begin
end if;
end process;
-
no_fill : if g_fifo_fill = 0 generate
rd_siso <= src_in; -- SISO
src_out <= rd_sosi; -- SOSI
end generate; -- no_fill
gen_fill : if g_fifo_fill > 0 generate
-
src_out <= i_src_out;
p_rd_clk: process(rd_clk, rd_rst)
@@ -353,7 +348,6 @@ begin
rd_siso <= hold_src_in;
end generate;
-
p_state : process(state, src_in, xon_reg, pend_src_out, rd_fifo_usedw, rd_fill_ctrl, rd_eop_cnt, eop_cnt, rd_eop_new)
begin
nxt_state <= state;
@@ -415,6 +409,5 @@ begin
-- Pass on frame level flow control
hold_src_in.xon <= src_in.xon;
end process;
-
end generate; -- gen_fill
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
index 7b6567b8709798152c42be32d31992e9263aa124..f7d22ea5bd6053f27f8290e42c3681052db1c360 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_eop_sc.vhd
@@ -75,7 +75,6 @@ end dp_fifo_fill_eop_sc;
architecture wrap of dp_fifo_fill_eop_sc is
begin
-
u_dp_fifo_fill_eop : entity work.dp_fifo_fill_eop
generic map (
g_technology => g_technology,
@@ -120,5 +119,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end wrap;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
index 0dd0ef1ce93a04f01c0fb0ff32e940a84b470c95..d5dabeee58c1845758e978fef65d98da8efc2b78 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_reg.vhd
@@ -49,7 +49,6 @@
-- | max_fifo_used_words stream x |
-- |-----------------------------------------------------------------------|
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -78,9 +77,7 @@ entity dp_fifo_fill_reg is
);
end dp_fifo_fill_reg;
-
architecture str of dp_fifo_fill_reg is
-
constant c_reg_max_used_words_offset : natural := 2;
constant c_nof_regs_per_stream : natural := 4; -- Must always be a power of 2 in order to meet the python register definition.
@@ -96,9 +93,7 @@ architecture str of dp_fifo_fill_reg is
signal reg_wr_arr : std_logic_vector(g_nof_streams * c_nof_regs_per_stream - 1 downto 0) := (others => '0');
signal reg_rd_arr : std_logic_vector(g_nof_streams * c_nof_regs_per_stream - 1 downto 0) := (others => '0');
signal peak_used_w : std_logic_vector(g_nof_streams * c_word_w - 1 downto 0) := (others => '0');
-
begin
-
gen_in_arr_reg : for I in 0 to g_nof_streams - 1 generate
in_arr_reg((c_nof_regs_per_stream * I + 1) * c_word_w - 1 downto c_nof_regs_per_stream * I * c_word_w) <= used_w((I + 1) * c_word_w - 1 downto I * c_word_w);
in_arr_reg((c_nof_regs_per_stream * I + 2) * c_word_w - 31 downto (c_nof_regs_per_stream * I + 1) * c_word_w) <= wr_ful(I) & rd_emp(I);
@@ -150,4 +145,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
index 7c9972b08556ab938d44f231283243ac1f815270..2fc428f43218ee08a63c43c492cb3959b532feac 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_fill_sc.vhd
@@ -74,10 +74,8 @@ entity dp_fifo_fill_sc is
);
end dp_fifo_fill_sc;
-
architecture str of dp_fifo_fill_sc is
begin
-
u_dp_fifo_fill_core : entity work.dp_fifo_fill_core
generic map (
g_technology => g_technology,
@@ -121,5 +119,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
index ecc96675a1c6b43ca6a9caea3d59241be97b774f..0ee926636df22b24bad3747be5df24c262dbfafe 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm.vhd
@@ -45,7 +45,6 @@ use work.dp_stream_pkg.all;
-- hence is operates entirely in the MM clock domain.
-- . The ST sop, eop, empty, channel and error fields are not supported.
-
entity dp_fifo_from_mm is
generic (
g_fifo_size : natural := 512;
@@ -66,16 +65,12 @@ entity dp_fifo_from_mm is
);
end dp_fifo_from_mm;
-
architecture str of dp_fifo_from_mm is
-
constant c_fifo_almost_full : natural := g_fifo_size - g_fifo_af_margin; -- FIFO almost full level, usedw will always be <= c_fifo_almost_full
constant c_usedw_w : natural := ceil_log2(g_fifo_size);
signal availw : std_logic_vector(c_usedw_w - 1 downto 0); -- no need to use ceil_log2(g_fifo_size+1), because availw = g_fifo_size - g_fifo_af_margin < g_fifo_size when the FIFO is empty
-
begin
-
assert g_fifo_af_margin /= 0 report "dp_fifo_from_mm.vhd : the g_fifo_af_margin must be > 0" severity FAILURE;
-- Combinatorial logic
@@ -87,5 +82,4 @@ begin
src_out.valid <= mm_wr;
src_out.data <= RESIZE_DP_DATA(mm_wrdata); -- Unsigned resize to ST data width
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
index c9cc0fa6333bc60ea0b7e384fe9644fd8d7e4f6d..56aa6909193970fe9fe24cbfadce3f3725cf3f49 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_from_mm_reg.vhd
@@ -40,17 +40,13 @@ entity dp_fifo_from_mm_reg is
);
end dp_fifo_from_mm_reg;
-
architecture rtl of dp_fifo_from_mm_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(2),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
nof_dat => 2,
init_sl => '0');
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -76,6 +72,4 @@ begin
end if;
end if;
end process;
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
index 16d0f00cdccd1048a506342d99675edd00c5d83d..05cdd07ee2c625ba31234ac61505d6e6fa31d82c 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_info.vhd
@@ -109,7 +109,6 @@ entity dp_fifo_info is
end dp_fifo_info;
architecture str of dp_fifo_info is
-
constant c_fifo_sop_dat_w : natural := func_slv_concat_w(g_use_sync, g_use_bsn, g_use_channel, 1, g_bsn_w, g_channel_w); -- concat sop info via FIFO
constant c_fifo_eop_dat_w : natural := func_slv_concat_w(g_use_empty, g_use_error, g_empty_w, g_error_w); -- concat eop info via FIFO
constant c_fifo_info_dat_w : natural := c_fifo_sop_dat_w + c_fifo_eop_dat_w;
@@ -142,9 +141,7 @@ architecture str of dp_fifo_info is
signal fifo_eop_rd_val : std_logic;
signal fifo_eop_rd_req : std_logic;
signal fifo_eop_rd_emp : std_logic;
-
begin
-
no_info : if c_fifo_info_dat_w = 0 generate
data_snk_out <= src_in;
src_out <= data_snk_in;
@@ -252,5 +249,4 @@ begin
dp_pipeline_data_src_in <= src_in;
src_out <= func_dp_stream_combine_info_and_data(info_src_out, dp_pipeline_data_src_out);
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
index 85c6969c7b527396d9b0bbcec2d8b9d99c901f17..fd0011ecacc88e7089e2ce55e3ffb927ba922d59 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor.vhd
@@ -55,9 +55,7 @@ entity dp_fifo_monitor is
);
end dp_fifo_monitor;
-
architecture str of dp_fifo_monitor is
-
constant c_field_arr : t_common_field_arr(4 downto 0) := ( (field_name_pad("rd_usedw"), "RO", 32, field_default(0) ),
(field_name_pad("wr_usedw"), "RO", 32, field_default(0) ),
(field_name_pad("rd_empty"), "RO", 1, field_default(0) ),
@@ -66,9 +64,7 @@ architecture str of dp_fifo_monitor is
signal mm_fields_in : std_logic_vector(field_slv_in_len(c_field_arr) - 1 downto 0);
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
-
begin
-
mm_fields_in(field_hi(c_field_arr, "rd_usedw") downto field_lo(c_field_arr, "rd_usedw")) <= rd_usedw_32b;
mm_fields_in(field_hi(c_field_arr, "wr_usedw") downto field_lo(c_field_arr, "wr_usedw")) <= wr_usedw_32b;
mm_fields_in(field_hi(c_field_arr, "rd_empty") downto field_lo(c_field_arr, "rd_empty")) <= slv(rd_emp);
@@ -96,6 +92,4 @@ begin
);
rd_fill_32b <= mm_fields_out(field_hi(c_field_arr, "rd_fill") downto field_lo(c_field_arr, "rd_fill"));
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
index 8b6ceee5e205ae31970665d00a30f8b7d60aa475..4ec10842d177934e3c4ed29051f3fb59d074c03a 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_monitor_arr.vhd
@@ -57,16 +57,12 @@ entity dp_fifo_monitor_arr is
);
end dp_fifo_monitor_arr;
-
architecture str of dp_fifo_monitor_arr is
-
constant c_nof_regs : natural := 5;
signal reg_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -100,4 +96,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
index 52ef061d74bf21eea1e5e47a1775913740c3903f..1ff22a1a71f019ff5204f1c73543dc5581a91022 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_sc.vhd
@@ -68,10 +68,8 @@ entity dp_fifo_sc is
);
end dp_fifo_sc;
-
architecture str of dp_fifo_sc is
begin
-
u_dp_fifo_core : entity work.dp_fifo_core
generic map (
g_technology => g_technology,
@@ -113,5 +111,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
index 7340848573fdd715fce4bc84dcf71dbd47a891d6..2c5adb850c1178c2c5db189113b50c86a1495f9b 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm.vhd
@@ -44,7 +44,6 @@ use work.dp_stream_pkg.all;
-- is operates entirely in the MM clock domain.
-- . The ST sop, eop, empty, channel and error fields are not supported.
-
entity dp_fifo_to_mm is
generic (
g_fifo_size : natural := 512;
@@ -65,11 +64,8 @@ entity dp_fifo_to_mm is
);
end dp_fifo_to_mm;
-
architecture str of dp_fifo_to_mm is
-
begin
-
-- Wires
mm_usedw <= RESIZE_UVEC(usedw, g_mm_word_w);
@@ -79,5 +75,4 @@ begin
snk_out.ready <= mm_rd; -- Combinatorial, because FIFO RL=1 already fits MM read latency=1
mm_rddata <= RESIZE_UVEC(snk_in.data, g_mm_word_w);
mm_rdval <= snk_in.valid;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
index 8f1c2af2fe6a9fa14ff42b2234d70467b3e17f9c..364603eeaef910666ddf261ddd658e02ba435483 100644
--- a/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_fifo_to_mm_reg.vhd
@@ -40,17 +40,13 @@ entity dp_fifo_to_mm_reg is
);
end dp_fifo_to_mm_reg;
-
architecture rtl of dp_fifo_to_mm_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
nof_dat => 1,
init_sl => '0');
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -74,6 +70,4 @@ begin
end if;
end if;
end process;
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_flush.vhd b/libraries/base/dp/src/vhdl/dp_flush.vhd
index 56e1cd282cfc096b686f25fbf7638c02210f1f7f..c800903a5ba46b3b4726c03b18eda17e58a71d6b 100644
--- a/libraries/base/dp/src/vhdl/dp_flush.vhd
+++ b/libraries/base/dp/src/vhdl/dp_flush.vhd
@@ -61,7 +61,6 @@ use work.dp_stream_pkg.all;
-- number is ignored and any sop will affect framed xon or xoff. Use the
-- actual needed width for g_framed_channel_w to ease timing closure.
-
entity dp_flush is
generic (
g_ready_latency : natural := 1; -- >= 0
@@ -85,9 +84,7 @@ entity dp_flush is
);
end dp_flush;
-
architecture rtl of dp_flush is
-
signal flush_dly : std_logic_vector(0 to g_ready_latency); -- use 0 TO high for delay lines, rather than high DOWNTO 0
signal snk_flush : std_logic;
signal snk_flush_hi : std_logic;
@@ -95,9 +92,7 @@ architecture rtl of dp_flush is
signal src_en : std_logic;
signal src_en_hi : std_logic;
signal src_en_lo : std_logic;
-
begin
-
-- Combine MM control flush_en and streaming control src_in.xon
flush_dly(0) <= flush_en or not src_in.xon; -- use flush_dly(0) combinatorially, so that flush_dly supports all g_ready_latency >= 0
p_clk : process(rst, clk)
@@ -209,6 +204,4 @@ begin
switch_low => snk_flush_lo,
out_level => snk_flush
);
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_folder.vhd b/libraries/base/dp/src/vhdl/dp_folder.vhd
index 1e0a142afcbc537809f7576f6b448258f15785d2..7b49530966b8140e84a36a88e751ae7407d0283f 100644
--- a/libraries/base/dp/src/vhdl/dp_folder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_folder.vhd
@@ -68,7 +68,6 @@ entity dp_folder is
end dp_folder;
architecture str of dp_folder is
-
component dp_folder is
generic (
g_nof_inputs : natural;
@@ -99,9 +98,7 @@ architecture str of dp_folder is
signal dp_block_gen_snk_in_arr : t_dp_sosi_arr(sel_a_b(g_nof_folds >= 0, ceil_div(g_nof_inputs, ceil_pow2(g_nof_folds)), 1) - 1 downto 0);
signal dp_block_gen_src_out_arr : t_dp_sosi_arr(sel_a_b(g_nof_folds >= 0, ceil_div(g_nof_inputs, ceil_pow2(g_nof_folds)), 1) - 1 downto 0);
-
begin
-
gen_arch: if g_nof_folds /= 0 generate
-----------------------------------------------------------------------------
-- Wire input array to mux_snk_in_arr to make sure we have an even number
@@ -180,7 +177,6 @@ begin
);
src_out_arr <= dp_folder_src_out_arr;
-
end generate;
-----------------------------------------------------------------------------
@@ -253,4 +249,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
index 43f175cd0c58e1242b74ef904a13fd5970565e5e..7de5defbcacb7bec071fa47c44267f6e4aae3637 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_parallel.vhd
@@ -99,18 +99,14 @@ entity dp_force_data_parallel is
);
end dp_force_data_parallel;
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.dp_stream_pkg.all;
architecture str of dp_force_data_parallel is
-
signal data_in : t_dp_sosi;
signal data_out : t_dp_sosi;
-
begin
-
p_comb : process(snk_in, force_en, force_data, force_re, force_im, data_out)
begin
data_in <= snk_in;
diff --git a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
index c42bffb0ee0bfb095c4fca5802abff5f60521d91..85b4568abdd09dc6f0c369f4d25f6d78c44c0f82 100644
--- a/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/dp_force_data_serial.vhd
@@ -107,9 +107,7 @@ entity dp_force_data_serial is
);
end dp_force_data_serial;
-
architecture str of dp_force_data_serial is
-
constant c_cnt_w : natural := ceil_log2(g_index_period);
signal cnt_clr : std_logic;
@@ -118,9 +116,7 @@ architecture str of dp_force_data_serial is
signal data_in : t_dp_sosi;
signal force_zero : std_logic;
-
begin
-
cnt_clr <= snk_in.sop when g_index_sample_block_n = true else snk_in.sync;
cnt_en <= snk_in.valid when g_index_sample_block_n = true else snk_in.sop;
@@ -178,5 +174,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame.vhd b/libraries/base/dp/src/vhdl/dp_frame.vhd
index 27cc63b903c486eaaa1a40d08487d570f483a848..c60355be35a771512e0c64b922e20d5eecd30133 100644
--- a/libraries/base/dp/src/vhdl/dp_frame.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use work.dp_packetizing_pkg.all;
-
-- Reuse from LOFAR rad_frame.vhd and rad_frame(rtl).vhd
-- Purpose:
@@ -82,9 +81,7 @@ entity dp_frame is
);
end dp_frame;
-
architecture rtl of dp_frame is
-
-- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
constant c_input_reg : boolean := false;
@@ -114,9 +111,7 @@ architecture rtl of dp_frame is
signal nxt_out_val : std_logic;
signal nxt_out_sof : std_logic;
signal nxt_out_eof : std_logic;
-
begin
-
out_dat <= i_out_dat;
gen_input_reg : if c_input_reg = true generate
@@ -139,6 +134,7 @@ begin
end if;
end process;
end generate;
+
no_input_reg : if c_input_reg = false generate
in_fsn_reg <= in_fsn;
in_dat_reg <= in_dat;
@@ -148,7 +144,6 @@ begin
in_err_reg <= in_err;
end generate;
-
p_clk: process(clk, rst)
begin
if rst = '1' then
@@ -201,5 +196,4 @@ begin
nxt_out_val <= '1';
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
index 70a5a265d86dbffe236abd8d68c9369013972119..96e79e56f23fbc49a20294ae0568b61637825b17 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_busy.vhd
@@ -43,13 +43,9 @@ entity dp_frame_busy is
);
end dp_frame_busy;
-
architecture str of dp_frame_busy is
-
signal busy : std_logic;
-
begin
-
u_common_switch : entity common_lib.common_switch
generic map (
g_rst_level => '0', -- Defines the output level at reset.
@@ -77,5 +73,4 @@ begin
in_dat => busy,
out_dat => snk_in_busy
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd b/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
index 066cc3ec5068f2f51e80c30d3a1bd33e266c51e9..8b2e689ec4b6465c2b48bc0507f420d92bca15e4 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_busy_arr.vhd
@@ -40,10 +40,8 @@ entity dp_frame_busy_arr is
);
end dp_frame_busy_arr;
-
architecture str of dp_frame_busy_arr is
begin
-
gen_nof_inputs : for I in 0 to g_nof_inputs - 1 generate
u_dp_frame_busy : entity work.dp_frame_busy
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
index f4d5cc2b5c549c899aebef681253b5392c9212d0..76ab9717de7b403a02aea8eb7c09b693429c5ea9 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_fsn.vhd
@@ -91,9 +91,7 @@ entity dp_frame_fsn is
);
end dp_frame_fsn;
-
architecture rtl of dp_frame_fsn is
-
type state_type is (s_idle, s_data, s_flush);
-- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
@@ -132,9 +130,7 @@ architecture rtl of dp_frame_fsn is
signal i_out_eof : std_logic;
signal nxt_out_eof : std_logic;
signal nxt_out_err : std_logic;
-
begin
-
out_eof <= i_out_eof;
-- Frame sequence number is composed of fsync and fsn
@@ -154,6 +150,7 @@ begin
end if;
end process;
end generate;
+
no_input_reg : if c_input_reg = false generate
in_sync_reg <= in_sync;
in_val_reg <= in_val;
@@ -252,5 +249,4 @@ begin
end if;
end case;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
index 512e5f8c7f601ba072240556d531bbf68eaf01d3..0a1b077acf385964ac688ecc358b7dcaff1186cc 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rd.vhd
@@ -60,7 +60,6 @@ use IEEE.std_logic_1164.all;
-- . The output throttle after the eof to avoid a new sof to follow the
-- previous eof too soon may not be needed (then use g_throttle_eof=FALSE).
-
entity dp_frame_rd is
generic (
g_dat_w : positive := 16;
@@ -105,9 +104,7 @@ entity dp_frame_rd is
);
end dp_frame_rd;
-
architecture rtl of dp_frame_rd is
-
type t_state_enum is (s_idle, s_sof, s_eof, s_err);
constant c_throttle_cnt_max : natural := g_throttle_den + g_throttle_num;
@@ -142,9 +139,7 @@ architecture rtl of dp_frame_rd is
signal nxt_out_val : std_logic;
signal nxt_out_sof : std_logic;
signal nxt_out_eof : std_logic;
-
begin
-
frm_busy <= i_frm_busy;
frm_err <= i_frm_err;
@@ -314,5 +309,4 @@ begin
end if;
end case;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
index ea3baac904d8d996d013885a6b3f4f0e389665c5..41dbe3e5e8d7d9a21f5067063ecf6e4b986e1e5b 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_remove.vhd
@@ -52,9 +52,7 @@ entity dp_frame_remove is
);
end dp_frame_remove;
-
architecture str of dp_frame_remove is
-
constant c_tail_nof_symbols : natural := (g_tail_nof_words * g_symbol_w) / g_symbol_w;
signal hdr_rem_siso : t_dp_siso;
@@ -62,11 +60,8 @@ architecture str of dp_frame_remove is
signal snk_out_rl_1 : t_dp_siso;
signal snk_in_rl_1 : t_dp_sosi;
-
begin
-
no_bypass : if g_internal_bypass = false generate
-
u_dp_latency_adpapter: entity work.dp_latency_adapter
generic map (
g_in_latency => g_snk_latency,
@@ -122,7 +117,6 @@ begin
src_in => src_in,
src_out => src_out
);
-
end generate;
gen_bypass : if g_internal_bypass = true generate
diff --git a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
index f730ceecbe46b67d57e9b3c11a12b7f3f246a74b..7bda823b126ca1c283b9e3f0855b50426fbcf909 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_repack.vhd
@@ -25,7 +25,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity dp_frame_repack is
generic (
g_in_dat_w : natural;
@@ -47,9 +46,7 @@ entity dp_frame_repack is
);
end dp_frame_repack;
-
architecture str of dp_frame_repack is
-
signal pack_fsn : std_logic_vector(in_dat'range);
signal pack_dat : std_logic_vector(in_dat'range);
signal pack_val : std_logic;
@@ -62,9 +59,7 @@ architecture str of dp_frame_repack is
signal repack_val : std_logic;
signal repack_sof : std_logic;
signal repack_eof : std_logic;
-
begin
-
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
-- typically g_out_dat_w=g_in_dat_w
diff --git a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
index 6b03e09732dd941dfef2d11b6988a1580d649ff1..6a5304e97b99986ec0aa59e0d2326aacebfceae3 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_rx.vhd
@@ -97,9 +97,7 @@ entity dp_frame_rx is
);
end dp_frame_rx;
-
architecture rtl of dp_frame_rx is
-
-- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
constant c_input_reg : boolean := false;
@@ -156,9 +154,7 @@ architecture rtl of dp_frame_rx is
end if;
end if;
end proc_handle_rx_timeout;
-
begin
-
gen_input_reg : if c_input_reg = true generate
p_reg : process (clk, rst)
begin
@@ -171,6 +167,7 @@ begin
end if;
end process;
end generate;
+
no_input_reg : if c_input_reg = false generate
in_val_reg <= in_val;
in_dat_reg <= in_dat;
@@ -316,5 +313,4 @@ begin
nxt_state <= v_nxt_state;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
index 9488c327fb4630db8d483e3f412e2ca805f1edc3..6d587242c714b91955a5a045c0c90bd96e81b6fc 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_scheduler.vhd
@@ -72,9 +72,7 @@ entity dp_frame_scheduler is
);
end dp_frame_scheduler;
-
architecture rtl of dp_frame_scheduler is
-
-- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
constant c_input_reg : boolean := false;
@@ -117,9 +115,7 @@ architecture rtl of dp_frame_scheduler is
signal nxt_out_val : std_logic;
signal nxt_out_sof : std_logic;
signal nxt_out_eof : std_logic;
-
begin
-
gen_input_reg : if c_input_reg = true generate
p_reg : process (clk, rst)
begin
@@ -138,6 +134,7 @@ begin
end if;
end process;
end generate;
+
no_input_reg : if c_input_reg = false generate
p_in_reg : process(in_dat, in_val, in_sof, in_eof)
begin
@@ -264,5 +261,4 @@ begin
end if;
end case;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_status.vhd b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
index f8562ab9142b05cd8af8de1013fe35128dbb776c..abff3ccbce1c083e43e0999622f2285906f6e407 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_status.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_status.vhd
@@ -29,7 +29,6 @@
-- The status output is aggregate input discarded & frame sync & aggregate brc & count nof rx frames. The
-- status applies to the interval before the previous sync interval, due to the data processing latency.
-
library IEEE,common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -58,7 +57,6 @@ entity dp_frame_status is
end dp_frame_status;
architecture rtl of dp_frame_status is
-
signal i_status : std_logic_vector(status'range);
signal debug_status : std_logic_vector(status'range);
signal debug_dis : std_logic;
@@ -86,9 +84,7 @@ architecture rtl of dp_frame_status is
signal nxt_cnt : std_logic_vector(cnt'range);
signal cnt_hld : std_logic_vector(cnt'range);
signal nxt_cnt_hld : std_logic_vector(cnt'range);
-
begin
-
status <= i_status;
i_status <= hton(RESIZE_UVEC(dis_hld & fsync_hld & brc_hld & cnt_hld, g_status_w), c_word_sz);
-- synthesis translate_off
@@ -168,5 +164,4 @@ begin
nxt_cnt <= std_logic_vector(unsigned(cnt) + 1);
end if;
end process;
-
end architecture;
diff --git a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
index a16930526b42199483c35988b2e9144501da59c4..01dbbf256a3037d038122e4ba592fdce060154ab 100644
--- a/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_frame_tx.vhd
@@ -83,9 +83,7 @@ entity dp_frame_tx is
);
end dp_frame_tx;
-
architecture rtl of dp_frame_tx is
-
-- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
constant c_input_reg : boolean := false;
@@ -118,9 +116,7 @@ architecture rtl of dp_frame_tx is
signal nxt_out_val : std_logic;
signal nxt_out_sof : std_logic;
signal nxt_out_eof : std_logic;
-
begin
-
gen_input_reg : if c_input_reg = true generate
p_reg : process (clk, rst)
begin
@@ -137,6 +133,7 @@ begin
end if;
end process;
end generate;
+
no_input_reg : if c_input_reg = false generate
in_dat_reg <= in_dat;
in_val_reg <= in_val;
@@ -219,5 +216,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_gap.vhd b/libraries/base/dp/src/vhdl/dp_gap.vhd
index 0c5e71520fc8ba1f40744d148d106e8eda1decab..9f487ec1c7bec965e72ac55474c6c4f6720bea57 100644
--- a/libraries/base/dp/src/vhdl/dp_gap.vhd
+++ b/libraries/base/dp/src/vhdl/dp_gap.vhd
@@ -58,7 +58,6 @@ entity dp_gap is
end dp_gap;
architecture rtl of dp_gap is
-
constant c_dat_len_w : natural := ceil_log2(g_dat_len);
constant c_gap_len_w : natural := ceil_log2(largest(g_gap_len, 1));
@@ -72,13 +71,10 @@ architecture rtl of dp_gap is
signal gap_cnt : std_logic_vector(c_gap_len_w - 1 downto 0);
signal nxt_gap_cnt : std_logic_vector(c_gap_len_w - 1 downto 0);
-
begin
-
src_out <= snk_in;
gen_rtl : if g_gap_len > 0 generate
-
p_clk : process(clk, rst)
begin
if rst = '1' then
@@ -140,7 +136,6 @@ begin
nxt_state <= s_wait_for_val;
nxt_clk_cnt <= (others => '0');
end if;
-
end case;
end process;
@@ -149,6 +144,4 @@ begin
no_rtl : if g_gap_len = 0 generate -- bypass
snk_out <= src_in;
end generate;
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
index 2b8996552a5a8f8a472525359cf5ca4ccfc5e973..4de916688351f6f59cc3429bbab94ce4432705dd 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_insert.vhd
@@ -57,18 +57,14 @@ entity dp_hdr_insert is
);
end dp_hdr_insert;
-
architecture str of dp_hdr_insert is
-
signal hdr_siso : t_dp_siso;
signal hdr_sosi : t_dp_sosi;
-- element (0) becomes the head, element (1) becomes the tail
signal concat_siso_arr : t_dp_siso_arr(0 to 1);
signal concat_sosi_arr : t_dp_sosi_arr(0 to 1);
-
begin
-
no_bypass: if g_internal_bypass = false generate
u_dp_ram_from_mm : entity work.mms_dp_ram_from_mm
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
index dec86251eac8742e209284c6b3f343bf024a733c..c924c29515f109ca45763b7073f08a7e6e3641e1 100644
--- a/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hdr_remove.vhd
@@ -49,17 +49,13 @@ entity dp_hdr_remove is
);
end dp_hdr_remove;
-
architecture str of dp_hdr_remove is
-
constant c_nof_symbols : natural := (g_data_w * g_hdr_nof_words) / g_symbol_w;
-- element (0) gets the head, element (1) gets the tail
signal split_siso_arr : t_dp_siso_arr(0 to 1);
signal split_sosi_arr : t_dp_sosi_arr(0 to 1);
-
begin
-
u_dp_ram_to_mm : entity work.dp_ram_to_mm
generic map (
g_ram_rd_nof_words => g_hdr_nof_words * (g_data_w / c_word_w),
@@ -98,5 +94,4 @@ begin
src_in_arr => split_siso_arr,
src_out_arr => split_sosi_arr
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
index 20e2217497bd7be4c953f2bfa6e7529abbb4e78e..18f45d4172772ae7d951e0ba97e3e48587ac4d40 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_ctrl.vhd
@@ -47,14 +47,10 @@ entity dp_hold_ctrl is
);
end dp_hold_ctrl;
-
architecture rtl of dp_hold_ctrl is
-
signal hi_ctrl : std_logic;
signal lo_ctrl : std_logic;
-
begin
-
hi_ctrl <= in_ctrl and not ready; -- capture
lo_ctrl <= not in_ctrl and ready; -- release
@@ -66,5 +62,4 @@ begin
switch_low => lo_ctrl,
out_level => hld_ctrl
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_hold_data.vhd b/libraries/base/dp/src/vhdl/dp_hold_data.vhd
index 98eeac0af000ea28b1c1c433d7ad0a974da5cd9c..73323f54a670ad0964049c4abab32b1f73d155fe 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_data.vhd
@@ -45,14 +45,10 @@ entity dp_hold_data is
);
end dp_hold_data;
-
architecture rtl of dp_hold_data is
-
signal i_hld_data : std_logic_vector(hld_data'range);
signal nxt_hld_data : std_logic_vector(hld_data'range);
-
begin
-
hld_data <= i_hld_data;
nxt_hld_data <= in_data when in_en = '1' else i_hld_data;
@@ -65,5 +61,4 @@ begin
i_hld_data <= nxt_hld_data;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_hold_input.vhd b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
index 14ec716ede740bb5e1a9aab8112fb8695168c63e..f5e5dd457290a39832a7dcdf3dffa7825be25b59 100644
--- a/libraries/base/dp/src/vhdl/dp_hold_input.vhd
+++ b/libraries/base/dp/src/vhdl/dp_hold_input.vhd
@@ -69,14 +69,10 @@ entity dp_hold_input is
);
end dp_hold_input;
-
architecture rtl of dp_hold_input is
-
signal i_pend_src_out : t_dp_sosi;
signal hold_in : t_dp_sosi; -- uses only the SOSI ctrl fields
-
begin
-
pend_src_out <= i_pend_src_out;
-- SISO:
@@ -153,5 +149,4 @@ begin
next_src_out.sop <= i_pend_src_out.sop and src_in.ready;
next_src_out.eop <= i_pend_src_out.eop and src_in.ready;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
index 752ddb09a9a58d660276a5614e4d509aea4b4117..5335ee16ed78480f4a624009dcb6de60297a4bb6 100755
--- a/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
+++ b/libraries/base/dp/src/vhdl/dp_interleave_n_to_one.vhd
@@ -81,9 +81,7 @@ entity dp_interleave_n_to_one is
);
end dp_interleave_n_to_one;
-
architecture rtl of dp_interleave_n_to_one is
-
-- local state registers
type t_reg is record
ready : std_logic;
@@ -99,9 +97,7 @@ architecture rtl of dp_interleave_n_to_one is
signal snk_out : t_dp_siso;
signal out_siso : t_dp_siso;
signal out_sosi : t_dp_sosi;
-
begin
-
p_reg : process(rst, clk)
begin
if rst = '1' then
@@ -206,5 +202,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
index c1f762e52ffcfdcdbe99b2f7b4f5a96391bb2f22..237ba315c23b67c8082df66a5a01bf0b5e270a41 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_adapter.vhd
@@ -67,9 +67,7 @@ entity dp_latency_adapter is
);
end dp_latency_adapter;
-
architecture rtl of dp_latency_adapter is
-
-- The difference between the input ready latency and the output ready latency
constant c_diff_latency : integer := g_out_latency - g_in_latency;
@@ -93,9 +91,7 @@ architecture rtl of dp_latency_adapter is
signal ff_sosi : t_dp_sosi; -- SOSI
signal i_snk_out : t_dp_siso := c_dp_siso_rdy;
-
begin
-
-- Use i_snk_out with defaults to force unused snk_out bits and fields to '0'
snk_out <= i_snk_out;
@@ -104,7 +100,6 @@ begin
src_out <= snk_in; -- SOSI
end generate gen_wires;
-
no_fifo : if c_diff_latency > 0 generate -- g_out_latency > g_in_latency
-- Go from g_in_latency to required larger g_out_latency
u_latency : entity work.dp_latency_increase
@@ -124,7 +119,6 @@ begin
);
end generate no_fifo;
-
gen_fifo : if c_diff_latency < 0 generate -- g_out_latency < g_in_latency
-- Register [0] contains the FIFO output with zero ready latency
ff_sosi <= fifo_reg(0);
@@ -256,5 +250,4 @@ begin
src_out => src_out
);
end generate gen_fifo;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
index dafab5c55e27fe2f98c3a27a8db4f23b5b8296c0..77c10e03b932bb464eae94ee8ad2a69cc47d5968 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_fifo.vhd
@@ -60,25 +60,20 @@ entity dp_latency_fifo is
);
end dp_latency_fifo;
-
architecture rtl of dp_latency_fifo is
-
constant c_adapter_input_rl : natural := g_input_rl + g_fifo_size;
constant c_adapter_output_rl : natural := g_output_rl;
signal i_snk_out : t_dp_siso;
signal fifo_snk_out : t_dp_siso;
signal i_usedw : std_logic_vector(usedw'range);
-
begin
-
gen_bypass : if g_bypass = true generate
snk_out <= src_in;
src_out <= snk_in;
end generate;
no_bypass : if g_bypass = false generate
-
snk_out <= i_snk_out;
usedw <= i_usedw;
diff --git a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
index 60f10f3d207c5d30710321856c40038586d1d831..4ac0f424655f72c0f6114bed98c449bfec17a798 100644
--- a/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
+++ b/libraries/base/dp/src/vhdl/dp_latency_increase.vhd
@@ -60,18 +60,14 @@ entity dp_latency_increase is
);
end dp_latency_increase;
-
architecture rtl of dp_latency_increase is
-
constant c_out_latency : natural := g_in_latency + g_incr_latency;
signal reg_ready : std_logic_vector(c_out_latency downto 0);
signal reg_val : std_logic;
signal i_snk_out : t_dp_siso := c_dp_siso_rdy;
-
begin
-
-- Use i_snk_out with defaults to force unused snk_out bits and fields to '0'
snk_out <= i_snk_out;
@@ -84,6 +80,7 @@ begin
gen_latency : if g_incr_latency > 0 generate
-- SISO
reg_ready(0) <= src_in.ready; -- use reg_ready(0) to combinatorially store src_in.ready
+
p_clk : process(rst, clk)
begin
if rst = '1' then
@@ -100,6 +97,7 @@ begin
gen_out : if g_in_latency /= 0 generate
src_out <= snk_in;
end generate;
+
gen_zero_out : if g_in_latency = 0 generate
reg_val <= reg_ready(c_out_latency);
@@ -113,5 +111,4 @@ begin
end process;
end generate;
end generate gen_latency;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_loopback.vhd b/libraries/base/dp/src/vhdl/dp_loopback.vhd
index 55a943631616035fd15c4641c194da56a4551941..c28f0223b38c2075e710c0decdd323ac3b4d3bc6 100644
--- a/libraries/base/dp/src/vhdl/dp_loopback.vhd
+++ b/libraries/base/dp/src/vhdl/dp_loopback.vhd
@@ -99,9 +99,7 @@ end dp_loopback;
-- 3) When both demuxes indicate they're done (sel_stat outputs), u_dp_mux_1
-- selects its new input (0) to complete the loopback.
-
architecture str of dp_loopback is
-
constant c_nof_demux_out : natural := 3;
constant c_nof_mux_in : natural := 2;
@@ -125,9 +123,7 @@ architecture str of dp_loopback is
signal mux_0_sel_ctrl : natural range 0 to c_nof_mux_in - 1 := 0;
signal mux_1_sel_ctrl : natural range 0 to c_nof_mux_in - 1 := 1;
-
begin
-
-- The interconnections as shown in the above structure:
mux_0_sosi_arr(0) <= demux_0_sosi_arr(0);
demux_0_siso_arr(0) <= mux_0_siso_arr(0);
@@ -223,6 +219,4 @@ begin
sel_ctrl => mux_1_sel_ctrl
);
-
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_mon.vhd b/libraries/base/dp/src/vhdl/dp_mon.vhd
index 69b0e55d70f586ddc9df1e558e223f2581ba08fe..e1d72e765470b99f38d81a638c15b4030bac8aaa 100644
--- a/libraries/base/dp/src/vhdl/dp_mon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mon.vhd
@@ -50,13 +50,9 @@ entity dp_mon is
);
end dp_mon;
-
architecture rtl of dp_mon is
-
signal snk_accept : std_logic;
-
begin
-
snk_out <= src_in;
src_out <= snk_in;
@@ -75,6 +71,4 @@ begin
cnt_en => snk_accept,
count => word_cnt
);
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_mux.vhd b/libraries/base/dp/src/vhdl/dp_mux.vhd
index ce42b95054d20c31c47c392d377bdcdaf4f67dc4..9e15141bf0d0e2ed1434f088636abf7a57a8c1ce 100644
--- a/libraries/base/dp/src/vhdl/dp_mux.vhd
+++ b/libraries/base/dp/src/vhdl/dp_mux.vhd
@@ -124,9 +124,7 @@ entity dp_mux is
);
end dp_mux;
-
architecture rtl of dp_mux is
-
-- Convert unconstrained range (that starts at INTEGER'LEFT) to 0 TO g_nof_input-1 range
constant c_fifo_fill : t_natural_arr(0 to g_nof_input - 1) := g_fifo_fill;
constant c_fifo_size : t_natural_arr(0 to g_nof_input - 1) := g_fifo_size;
@@ -169,9 +167,7 @@ architecture rtl of dp_mux is
signal nxt_src_out_hi : t_dp_sosi;
signal channel_lo : std_logic_vector(c_sel_w - 1 downto 0);
signal nxt_channel_lo : std_logic_vector(c_sel_w - 1 downto 0);
-
begin
-
snk_out_arr <= i_snk_out_arr;
-- Monitor sink valid input and sink ready output
@@ -244,6 +240,7 @@ begin
src_out => rd_sosi_arr(I)
);
end generate;
+
no_fifo : if g_use_fifo = false generate
i_snk_out_arr <= rd_siso_arr;
rd_sosi_arr <= snk_in_arr;
@@ -339,7 +336,6 @@ begin
end process;
end generate;
-
gen_framed : if g_mode = 0 or g_mode = 1 or g_mode = 3 generate
p_hold_src_in_arr : process(rd_siso_arr, pend_src_out_arr, in_sel, src_in)
begin
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
index 42206bf7ba12d9105eb4942e21af55d9fcb94cff..374201d300f1a3efa12bd2673c87a690242d40b7 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx.vhd
@@ -39,7 +39,6 @@
-- g_symbol_w defines the symbol width of the data and is used to
-- control the snk_out_arr empty field.
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -78,9 +77,7 @@ entity dp_offload_rx is
);
end dp_offload_rx;
-
architecture str of dp_offload_rx is
-
constant c_symbol_w : natural := sel_a_b(g_symbol_w = 0, g_data_w, g_symbol_w);
constant c_nof_symbols_per_data : natural := g_data_w / c_symbol_w;
constant c_nof_header_symbols : natural := field_slv_len(g_hdr_field_arr) / c_symbol_w;
@@ -106,9 +103,7 @@ architecture str of dp_offload_rx is
constant c_dp_field_blk_snk_data_w : natural := g_data_w;
constant c_dp_field_blk_src_data_w : natural := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"));
-
begin
-
---------------------------------------------------------------------------------------
-- Remove header
---------------------------------------------------------------------------------------
@@ -172,7 +167,6 @@ begin
dp_field_blk_slv_out(i)(c_dp_field_blk_src_data_w - 1 downto 0) <= dp_field_blk_src_out_arr(i).data(c_dp_field_blk_src_data_w - 1 downto 0);
dp_field_blk_slv_out_val(i) <= dp_field_blk_src_out_arr(i).valid;
-
end generate;
---------------------------------------------------------------------------------------
@@ -222,6 +216,7 @@ begin
gen_hdr_fields_out_arr : for i in 0 to g_nof_streams - 1 generate
hdr_fields_out_arr(i) <= reg_dp_field_blk_slv_out(i) when dp_tail_remove_src_out_arr(i).sop = '1' else (others => '0');
end generate;
+
-- Put the fields that can be valid during entire packet on the entity combinatorially (e.g. all sosi slv fields)
hdr_fields_raw_arr <= reg_dp_field_blk_slv_out;
@@ -239,5 +234,4 @@ begin
mosi_arr => reg_hdr_dat_mosi_arr,
miso_arr => reg_hdr_dat_miso_arr
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
index 4e55f098cd8797e7a806ade3e3de12e81d116932..fe450e22c104ff81613d9c0de21b3d25672d2217 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
@@ -54,9 +54,7 @@ entity dp_offload_rx_filter is
);
end dp_offload_rx_filter;
-
architecture str of dp_offload_rx_filter is
-
constant c_header_w : natural := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"));
constant c_nof_words: natural := c_header_w / g_data_w;
@@ -74,9 +72,7 @@ architecture str of dp_offload_rx_filter is
end record;
signal r, rin : reg_type;
-
begin
-
snk_out_arr <= src_in_arr;
gen_bypass : if g_bypass = true generate
@@ -109,7 +105,6 @@ begin
if g_udp_dst_port_ena = true and not(hdr_fields_out_arr(i)(udp_dst_port_range) = hdr_fields_in_arr(i)(udp_dst_port_range) ) then
v.valid(i) := '0';
end if;
-
end if;
end loop check;
@@ -119,10 +114,8 @@ begin
end if;
rin <= v;
-
end process;
-
process(r)
begin
src_out_arr <= r.src_out_arr;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
index 4a1a1bbd76b90a378d18c69ab57088324f47ab73..d091171e52e44be574bade197cb2ce51d162e2b2 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
@@ -57,9 +57,7 @@ entity dp_offload_rx_filter_mm is
);
end dp_offload_rx_filter_mm;
-
architecture str of dp_offload_rx_filter_mm is
-
constant c_header_w : natural := field_slv_in_len(field_arr_set_mode(g_hdr_field_arr , "RO"));
constant c_nof_words: natural := c_header_w / g_data_w;
@@ -106,9 +104,7 @@ architecture str of dp_offload_rx_filter_mm is
end record;
signal r, rin : reg_type;
-
begin
-
snk_out_arr <= src_in_arr;
gen_bypass : if g_bypass = true generate
@@ -116,7 +112,6 @@ begin
end generate;
no_bypass : if g_bypass = false generate
-
p_comb : process(hdr_fields_to_check_arr, snk_in_arr, r, dp_rst)
variable v : reg_type;
begin
@@ -142,7 +137,6 @@ begin
if udp_dst_port_ena(i) = true and not(hdr_fields_to_check_arr(i)(udp_dst_port_range) = mm_fields_slv_out_arr(i)(udp_dst_port_range) ) then
v.valid(i) := '0';
end if;
-
end if;
end loop check;
@@ -152,10 +146,8 @@ begin
end if;
rin <= v;
-
end process;
-
process(r)
begin
src_out_arr <= r.src_out_arr;
@@ -173,7 +165,6 @@ begin
end if;
end process;
-
-------------------------------------------
-- mm_fields for MM access to each field --
-------------------------------------------
@@ -190,7 +181,6 @@ begin
);
gen_mm_fields : for i in 0 to g_nof_streams - 1 generate
-
u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => 2,
@@ -203,7 +193,6 @@ begin
miso_arr => common_miso_arr
);
-
eth_dst_mac_ena(i) <= is_true(reg_ena_sig(i)(0));
ip_dst_addr_ena(i) <= is_true(reg_ena_sig(i)(32));
ip_total_length_ena(i) <= is_true(reg_ena_sig(i)(64));
@@ -213,7 +202,6 @@ begin
generic map(
g_reg => c_ena_reg
)
-
port map(
-- Clocks and reset
mm_rst => mm_rst, -- reset synchronous with mm_clk
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
index d9ac55a4e77620d85d8306e33d43e343fea913aa..cbe97b4e0fe8285b53674c2a8d6ce65844a04c4c 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_legacy.vhd
@@ -53,9 +53,7 @@ entity dp_offload_rx_legacy is
);
end dp_offload_rx_legacy;
-
architecture str of dp_offload_rx_legacy is
-
constant c_hdr_remove_ram_addr_w : natural := ceil_log2( g_hdr_nof_words * (g_data_w / c_word_w) );
signal rx_pkt_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
@@ -63,9 +61,7 @@ architecture str of dp_offload_rx_legacy is
signal ram_hdr_remove_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal ram_hdr_remove_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
u_common_mem_mux_hdr_ram : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -79,7 +75,6 @@ begin
);
gen_nof_streams: for i in 0 to g_nof_streams - 1 generate
-
---------------------------------------------------------------------------------------
-- RX: Unframe: remove header (and CRC if phy link is used) from DP packets
---------------------------------------------------------------------------------------
@@ -125,7 +120,6 @@ begin
src_in => dp_siso_arr(i),
src_out => dp_sosi_arr(i)
);
-
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
index 791f83d7e5ef3d261c77b3054c63104a0c338c3c..e88d96a678f6c1bb1baa800c0e18d7eba17b0c01 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx.vhd
@@ -82,9 +82,7 @@ entity dp_offload_tx is
);
end dp_offload_tx;
-
architecture str of dp_offload_tx is
-
constant c_dp_split_val_latency : natural := 1;
constant c_dp_packet_merge_val_latency : natural := 2;
constant c_nof_header_words : natural := field_nof_words(g_hdr_field_arr, g_data_w);
@@ -126,9 +124,7 @@ architecture str of dp_offload_tx is
signal reg_hdr_dat_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal reg_hdr_dat_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
---------------------------------------------------------------------------------------
-- Wire inputs to dp_split inputs
---------------------------------------------------------------------------------------
@@ -142,6 +138,7 @@ begin
end loop;
end process;
end generate;
+
gen_wires_data : if g_use_complex = false generate
dp_split_snk_in_arr <= snk_in_arr;
end generate;
@@ -156,7 +153,6 @@ begin
-- Split nof_words_per_block (forward only the first nof_words_per_block of each block)
---------------------------------------------------------------------------------------
gen_dp_split : for i in 0 to g_nof_streams - 1 generate
-
snk_out_arr(i).ready <= dp_split_snk_out_arr(i).ready;
snk_out_arr(i).xon <= src_in_arr(i).xon; -- Pass on XON from source side
@@ -178,7 +174,6 @@ begin
);
dp_split_src_in_2arr(i)(0) <= c_dp_siso_rdy; -- Always ready to throw away the tail
-
end generate;
-- Introduce the same delay (as dp_plit) on the corresponding header fields
@@ -296,7 +291,6 @@ begin
-- Create header block & concatenate header to offload stream.
---------------------------------------------------------------------------------------
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
-
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
generic map (
@@ -355,5 +349,4 @@ begin
mosi_arr => reg_hdr_dat_mosi_arr,
miso_arr => reg_hdr_dat_miso_arr
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
index b11bcefca2ad049fe42dcdea1ebf9c1524f953c0..b3101b542d49ef12cdf05b2c8b84defdf25134d4 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_legacy.vhd
@@ -72,9 +72,7 @@ entity dp_offload_tx_legacy is
);
end dp_offload_tx_legacy;
-
architecture str of dp_offload_tx_legacy is
-
constant c_fifo_margin : natural := 10;
constant c_dp_pkt_overhead_nof_words : natural := 4 + 1;
@@ -113,9 +111,7 @@ architecture str of dp_offload_tx_legacy is
signal reg_hdr_insert_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal ram_hdr_insert_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
u_common_mem_mux_hdr_reg : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -137,7 +133,6 @@ begin
);
gen_nof_streams0: for i in 0 to g_nof_streams - 1 generate
-
---------------------------------------------------------------------------------------
-- Select complex input if required
---------------------------------------------------------------------------------------
@@ -371,5 +366,4 @@ begin
end generate;
end generate;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
index fb1bdffd29839a7c621c4c3b1aa15154f3a77a33..e95ac25810282d2f48184619c5af08280dfee4f5 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_len_calc.vhd
@@ -56,9 +56,7 @@ entity dp_offload_tx_len_calc is
);
end dp_offload_tx_len_calc;
-
architecture str of dp_offload_tx_len_calc is
-
constant c_eth_header_len : natural := 14;
constant c_ip_header_len : natural := 20;
constant c_udp_header_len : natural := 8;
@@ -79,9 +77,7 @@ architecture str of dp_offload_tx_len_calc is
signal ip_adder_in : std_logic_vector(2 * c_adder_in_w - 1 downto 0);
signal ip_adder_out : std_logic_vector(c_adder_in_w + 1 - 1 downto 0);
-
begin
-
---------------------------------------------------------------------------------------
-- Calculate number of payload words
---------------------------------------------------------------------------------------
@@ -152,5 +148,4 @@ begin
);
ip_total_length <= ip_adder_out(c_adder_in_w - 1 downto 0);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
index f8a4288fe51bd1ba699ce8ca6d2e66cb3a7a770f..9382254dc534548c4d079d4396cc91143c303f55 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_tx_v3.vhd
@@ -39,7 +39,6 @@
-- g_symbol_w = g_data_w if the empty field is always 0, so the number of
-- bits in the header and data are an integer number of g_data_w.
-
library IEEE, common_lib, technology_lib, mm_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -79,9 +78,7 @@ entity dp_offload_tx_v3 is
);
end dp_offload_tx_v3;
-
architecture str of dp_offload_tx_v3 is
-
constant c_dp_field_blk_snk_data_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr , "RW"));
constant c_dp_field_blk_src_data_w : natural := g_data_w;
@@ -102,10 +99,7 @@ architecture str of dp_offload_tx_v3 is
signal mm_fields_slv_out_arr : t_slv_1024_arr(g_nof_streams - 1 downto 0);
signal field_override_arr : std_logic_vector(g_hdr_field_arr'range) := g_hdr_field_sel; -- 1 override bit per field
-
-
begin
-
assert c_dp_field_blk_snk_data_w <= c_dp_stream_data_w report "Number of header bits must fit in t_dp_sosi data field." severity FAILURE;
---------------------------------------------------------------------------------------
-- Create header block & concatenate header to offload stream.
@@ -129,7 +123,6 @@ begin
end process;
gen_dp_field_blk : for i in 0 to g_nof_streams - 1 generate
-
-- Both dp_concat inputs must be ready. One of the inputs toggles ready via dp_field_blk.
snk_out_arr(i).ready <= dp_field_blk_snk_out_arr(i).ready and dp_concat_snk_out_2arr(i)(0).ready;
snk_out_arr(i).xon <= src_in_arr(i).xon;
@@ -174,7 +167,6 @@ begin
slv_out => mm_fields_slv_out_arr(i)(field_slv_len(g_hdr_field_arr) - 1 downto 0)
);
-
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : entity work.dp_field_blk
generic map (
@@ -205,12 +197,10 @@ begin
);
dp_field_blk_src_in_arr(i) <= dp_concat_snk_out_2arr(i)(1);
-
end generate;
-- Prepend the header block to the input block
gen_dp_concat : for i in 0 to g_nof_streams - 1 generate
-
dp_concat_snk_in_2arr(i)(0) <= snk_in_arr(i);
dp_concat_snk_in_2arr(i)(1) <= dp_field_blk_src_out_arr(i);
@@ -245,5 +235,4 @@ begin
mosi_arr => reg_hdr_dat_mosi_arr,
miso_arr => reg_hdr_dat_miso_arr
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
index 026c8f5557aebb60605af16171478905c866a33c..6839ff8a6e9c3ed0002b16aa24b6797b05d973a1 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec.vhd
@@ -75,7 +75,6 @@ use work.dp_packet_pkg.all;
-- . The output SOSI sync is defined such that it can only be active at sop, so
-- not during entire frame or even until the next sop.
-
entity dp_packet_dec is
generic (
g_data_w : natural := 32;
@@ -96,9 +95,7 @@ entity dp_packet_dec is
);
end dp_packet_dec;
-
architecture rtl of dp_packet_dec is
-
constant c_output_reg : boolean := true; -- register dp_shiftreg output to ease timing closure
constant c_channel_len : natural := ceil_div(c_dp_packet_channel_w, g_data_w);
@@ -144,9 +141,7 @@ architecture rtl of dp_packet_dec is
signal new_src_out_inputs : t_dp_sosi_arr(0 to c_shiftreg_len - 1);
signal i_src_out : t_dp_sosi;
-
begin
-
src_out <= i_src_out;
-- Map to slv to ease monitoring in wave window
@@ -285,7 +280,6 @@ begin
hold_src_in.xon <= src_in.xon;
end process;
-
-- Handle output error field and eop
u_src_shift : entity work.dp_shiftreg
generic map (
@@ -337,6 +331,4 @@ begin
end if;
end if;
end process;
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
index c85ee49113c01d78240dc793597fde2dfd217fe1..2fe927abf47a45fb41f062c448edc272edc57107 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_dec_channel_lo.vhd
@@ -54,14 +54,10 @@ entity dp_packet_dec_channel_lo is
);
end dp_packet_dec_channel_lo;
-
architecture rtl of dp_packet_dec_channel_lo is
-
signal channel_lo_hold : std_logic_vector(g_channel_lo - 1 downto 0);
signal nxt_channel_lo_hold : std_logic_vector(g_channel_lo - 1 downto 0);
-
begin
-
assert g_channel_lo + 1 <= g_data_w report "dp_packet_dec_channel_lo : g_channel_lo does not fit in g_data_w" severity FAILURE;
-- Pass on the flow control
@@ -96,5 +92,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
index 8f9aead04435f94b7693881f2b1cd7aca119a732..08011772520ca371f8a98548e918e3421cd0749a 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_detect.vhd
@@ -38,7 +38,6 @@ use work.dp_stream_pkg.all;
-- _________________________
-- pkt_det ______| |____
-
entity dp_packet_detect is
generic (
g_latency : natural := 1
@@ -56,7 +55,6 @@ entity dp_packet_detect is
end dp_packet_detect;
architecture str of dp_packet_detect is
-
signal i_pkt_det : std_logic;
signal prev_pkt_det : std_logic;
signal prev_eop : std_logic;
@@ -64,9 +62,7 @@ architecture str of dp_packet_detect is
-- For RL=0, these signals are only asserted when src_in.ready='1'.
signal sop : std_logic;
signal eop : std_logic;
-
begin
-
gen_rl_0: if g_latency = 0 generate
sop <= sosi.sop and siso.ready;
eop <= sosi.eop and siso.ready;
@@ -100,5 +96,4 @@ begin
prev_pkt_det <= i_pkt_det;
end if;
end process;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
index 75ec661c0bde22b337d021fbf16872cdc4fe2e3c..489bdc80ecd39d220969de42577ec54e6c80d6ab 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc.vhd
@@ -89,9 +89,7 @@ entity dp_packet_enc is
);
end dp_packet_enc;
-
architecture rtl of dp_packet_enc is
-
constant c_channel_len : natural := ceil_div(c_dp_packet_channel_w, g_data_w);
constant c_bsn_len : natural := ceil_div(c_dp_packet_bsn_w, g_data_w);
constant c_error_len : natural := ceil_div(c_dp_packet_error_w, g_data_w);
@@ -125,9 +123,7 @@ architecture rtl of dp_packet_enc is
signal nxt_src_out : t_dp_sosi;
signal i_snk_out : t_dp_siso;
-
begin
-
src_out <= i_src_out;
snk_out <= i_snk_out;
@@ -260,5 +256,4 @@ begin
i_snk_out.xon <= src_in.xon;
hold_src_in.xon <= src_in.xon;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
index 9d3955d30e8011da49044f8ded4fa71b62d5fe9b..9ce09443d742a8d82c09aa0a9806371148a39306 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_enc_channel_lo.vhd
@@ -63,10 +63,8 @@ entity dp_packet_enc_channel_lo is
);
end dp_packet_enc_channel_lo;
-
architecture rtl of dp_packet_enc_channel_lo is
begin
-
assert g_channel_lo + 1 <= g_data_w report "dp_packet_enc_channel_lo : g_channel_lo does not fit in g_data_w" severity FAILURE;
-- Pass on the flow control
@@ -82,5 +80,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
index 551460047fcdcb08626100979c5788b8a1b0ff11..78269fecf91b5630c8e666924ea27304019fed4c 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
@@ -205,9 +205,7 @@ entity dp_packet_merge is
);
end dp_packet_merge;
-
architecture rtl of dp_packet_merge is
-
type t_reg is record
nof_pkt : natural range 0 to g_nof_pkt + 1;
pkt_cnt : natural range 0 to g_nof_pkt + 1;
@@ -227,9 +225,7 @@ architecture rtl of dp_packet_merge is
signal dp_latency_adapter_snk_in : t_dp_sosi;
signal dp_latency_adapter_src_in : t_dp_siso;
signal dp_latency_adapter_src_out : t_dp_sosi;
-
begin
-
-- Map t_reg outputs to entity outputs
nof_pkt_out <= TO_UVEC(r.nof_pkt, ceil_log2(g_nof_pkt + 1));
@@ -264,7 +260,6 @@ begin
src_out <= dp_latency_adapter_src_out;
end generate;
-
-- p_reg
r <= nxt_r when rising_edge(clk);
@@ -398,5 +393,4 @@ begin
nxt_r <= v;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
index b9e33be549d951c16f6b71a2b034335b9431a504..76c65b3a90f6e54de9e7edd5d6a88f58d74c8f24 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_pkg.vhd
@@ -23,9 +23,7 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
package dp_packet_pkg is
-
------------------------------------------------------------------------------
-- DP Packet definition:
--
@@ -55,12 +53,9 @@ package dp_packet_pkg is
-- Determine the length in nof data words to fit the DP packet overhead fields
function func_dp_packet_overhead_len(c_data_w : natural) return natural;
-
end dp_packet_pkg;
-
package body dp_packet_pkg is
-
function func_dp_packet_overhead_len(c_data_w : natural) return natural is
begin
-- Calculate the total DP PACKET overhead length of header (channel and bsn words) + lenght of tail (error words).
@@ -70,4 +65,3 @@ package body dp_packet_pkg is
end;
end dp_packet_pkg;
-
diff --git a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
index 251466d022258639f81abb42ae53008011833e0f..1fe7ebd08f82c15f48ac1e5622692e84b2afd121 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_unmerge.vhd
@@ -31,7 +31,6 @@
-- _ _ _ _ _ _
-- src_out.eop _____________|0|_______|1|_______|2|_______|0|_______|1|_______|2|___
-
library IEEE,common_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -55,13 +54,9 @@ entity dp_packet_unmerge is
);
end dp_packet_unmerge;
-
architecture rtl of dp_packet_unmerge is
-
begin
-
-- Temporary void component that assigns output = input
snk_out <= src_in;
src_out <= snk_in;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
index ca365bcda527778078cac94f58640d531679e365..cbc94af7224cb6c9b209aee2dfd9ec18a17a88c9 100644
--- a/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packetizing_pkg.vhd
@@ -54,7 +54,6 @@ use easics_lib.PCK_CRC32_D64.all;
use easics_lib.PCK_CRC32_D72.all;
package dp_packetizing_pkg is
-
--<types>--
--<functions>--
@@ -78,12 +77,9 @@ package dp_packetizing_pkg is
constant c_dp_mode_buf : std_logic_vector(c_dp_mode_w - 1 downto 0) := "00";
constant c_dp_mode_stream : std_logic_vector(c_dp_mode_w - 1 downto 0) := "11";
constant c_dp_mode_combine : std_logic_vector(c_dp_mode_w - 1 downto 0) := "10";
-
end dp_packetizing_pkg;
-
package body dp_packetizing_pkg is
-
--<functions>--
------------------------------------------------------------------------------
@@ -100,6 +96,7 @@ package body dp_packetizing_pkg is
when 20 => nxt_crc := nextRAD_CRC20_D20(RESIZE_UVEC(dat, 20), crc);
when others => report "DP data width not supported in easics_lib RAD for LOFAR" severity FAILURE;
end case;
+
else
-- CRC-16
if c_dp_crc_w = 16 then
@@ -143,4 +140,3 @@ package body dp_packetizing_pkg is
end func_dp_next_crc;
end dp_packetizing_pkg;
-
diff --git a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
index a0c31ed3d780d1418a1976143c72efbe977e3acd..7a0fe1975a1eb11518ad87dcc0650ae48120c3cc 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_insert.vhd
@@ -40,7 +40,6 @@ use work.dp_stream_pkg.all;
-- . This dp_pad_insert now can only insert 1 word at the head, this could be
-- extended to allow also g_nof_padding > g_data_w/g_symbol_w
-
entity dp_pad_insert is
generic (
g_data_w : natural := 64;
@@ -60,9 +59,7 @@ entity dp_pad_insert is
);
end dp_pad_insert;
-
architecture str of dp_pad_insert is
-
constant c_symbols_per_beat : natural := g_data_w / g_symbol_w;
constant c_pad_empty : natural := c_symbols_per_beat - g_nof_padding;
@@ -81,11 +78,8 @@ architecture str of dp_pad_insert is
-- element (0) becomes the head, element (1) becomes the tail
signal concat_siso_arr : t_dp_siso_arr(0 to 1);
signal concat_sosi_arr : t_dp_sosi_arr(0 to 1);
-
begin
-
no_bypass : if g_internal_bypass = false generate
-
-- Create the padding input word, while preserving the sync and BSN from the snk_in
p_clk : process(rst, clk)
begin
@@ -145,7 +139,6 @@ begin
src_in => src_in,
src_out => src_out
);
-
end generate;
gen_bypass : if g_internal_bypass = true generate
diff --git a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
index 09c049737da154bd0c649b5e7fd9909e243bc396..134fc740effe0bb5ddbd1251b300d03b4ed8e30b 100644
--- a/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pad_remove.vhd
@@ -33,7 +33,6 @@ use work.dp_stream_pkg.all;
-- . Ready latency (RL) = 1
-- . Reverse operation is dp_pad_insert
-
entity dp_pad_remove is
generic (
g_data_w : natural := 64;
@@ -53,15 +52,11 @@ entity dp_pad_remove is
);
end dp_pad_remove;
-
architecture str of dp_pad_remove is
-
-- element (0) gets the head, element (1) gets the tail
signal split_siso_arr : t_dp_siso_arr(0 to 1);
signal split_sosi_arr : t_dp_sosi_arr(0 to 1);
-
begin
-
no_bypass : if g_internal_bypass = false generate
-- Remove the padding octets from the head and output the tail
split_siso_arr(0) <= c_dp_siso_rdy;
diff --git a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
index 2a2eba1ee04259a4cb3e0c5a306a2391fa0ce5c2..a2b024710c6caadc676a06a68937987cc0afd607 100644
--- a/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_paged_sop_eop_reg.vhd
@@ -62,14 +62,10 @@ entity dp_paged_sop_eop_reg is
);
end dp_paged_sop_eop_reg;
-
architecture str of dp_paged_sop_eop_reg is
-
signal snk_in_sync : std_logic_vector(0 downto 0);
signal src_out_sync : std_logic_vector(0 downto 0);
-
begin
-
-- Sosi info at sop
snk_in_sync(0) <= snk_in.sync; -- convert sl to slv
src_out.sync <= src_out_sync(0); -- convert slv to sl
@@ -139,5 +135,4 @@ begin
wr_dat => snk_in.err,
out_dat => src_out.err
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline.vhd b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
index 5a0fcfdae6e30279ffbae2e94a7b97407a9dc764..63f860246cf717d911bbb9282398d93d9ca88a97 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline.vhd
@@ -60,7 +60,6 @@ entity dp_pipeline is
);
end dp_pipeline;
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.dp_stream_pkg.all;
@@ -78,18 +77,14 @@ entity dp_pipeline_one is
);
end dp_pipeline_one;
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.dp_stream_pkg.all;
architecture str of dp_pipeline is
-
signal snk_out_arr : t_dp_siso_arr(0 to g_pipeline);
signal snk_in_arr : t_dp_sosi_arr(0 to g_pipeline);
-
begin
-
-- Input at index 0
snk_out <= snk_out_arr(0);
snk_in_arr(0) <= snk_in;
@@ -114,18 +109,14 @@ begin
end str;
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use work.dp_stream_pkg.all;
architecture str of dp_pipeline_one is
-
signal nxt_src_out : t_dp_sosi;
signal i_src_out : t_dp_sosi;
-
begin
-
src_out <= i_src_out;
-- Pipeline register
@@ -152,5 +143,4 @@ begin
pend_src_out => OPEN,
src_out_reg => i_src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
index 91d70de3fe7ffef7e5811c7f31dda1168d63d7ec..57e45e045e4a8c287749f8c4c494ea63e4bda484 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_arr.vhd
@@ -46,11 +46,8 @@ entity dp_pipeline_arr is
);
end dp_pipeline_arr;
-
architecture str of dp_pipeline_arr is
-
begin
-
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
u_p : entity work.dp_pipeline
generic map (
diff --git a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
index d9115898762efd39b495c75a528e153a86b017d4..b4dcc11aac1b11163a0422c6ac6a81bfc92136ac 100644
--- a/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_pipeline_ready.vhd
@@ -55,14 +55,10 @@ entity dp_pipeline_ready is
);
end dp_pipeline_ready;
-
architecture str of dp_pipeline_ready is
-
signal internal_siso : t_dp_siso;
signal internal_sosi : t_dp_sosi;
-
begin
-
gen_out_incr_rl : if g_out_latency > g_in_latency generate
-- Register siso by incrementing the input RL first
u_incr : entity work.dp_latency_increase
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
index 739b1db04aa5bd0cd13bb5ff252b82db1684cca5..bc4a05d652f25deedd986c36e7eebce07dd26b32 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm.vhd
@@ -53,7 +53,6 @@ entity dp_ram_from_mm is
end dp_ram_from_mm;
architecture rtl of dp_ram_from_mm is
-
constant c_mm_ram_wr : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_ram_wr_nof_words),
dat_w => c_word_w,
@@ -81,9 +80,7 @@ architecture rtl of dp_ram_from_mm is
signal rd_data : std_logic_vector(c_mm_ram_rd.dat_w - 1 downto 0);
signal rd_addr : std_logic_vector(c_mm_ram_rd.adr_w - 1 downto 0);
signal nxt_rd_addr : std_logic_vector(c_mm_ram_rd.adr_w - 1 downto 0);
-
begin
-
p_src_out : process(src_out_ctrl_val, rd_data)
begin
src_out <= src_out_ctrl_val;
@@ -137,10 +134,8 @@ begin
when others =>
nxt_state <= s_init;
end case;
-
end process;
-
p_clk : process(st_rst, st_clk)
begin
if st_rst = '1' then
@@ -176,6 +171,4 @@ begin
rd_dat => rd_data,
rd_val => open
);
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
index c783a7a8e1a8baa365e176ef663231243013104f..25446267eae777e47c8216628519119729ec59e3 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_from_mm_reg.vhd
@@ -41,9 +41,7 @@ entity dp_ram_from_mm_reg is
);
end dp_ram_from_mm_reg;
-
architecture rtl of dp_ram_from_mm_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(1),
dat_w => c_word_w,
@@ -51,9 +49,7 @@ architecture rtl of dp_ram_from_mm_reg is
init_sl => '0');
signal mm_dp_on : std_logic;
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -81,6 +77,4 @@ begin
din => mm_dp_on,
dout => dp_on
);
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
index c2203adebfc85b87f2e48367503d5aa028ae0c60..eab525722aa4aa3411ced649b62f02f23d4390ae 100644
--- a/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ram_to_mm.vhd
@@ -49,7 +49,6 @@ entity dp_ram_to_mm is
end dp_ram_to_mm;
architecture rtl of dp_ram_to_mm is
-
constant c_mm_ram_rd : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_ram_rd_nof_words),
dat_w => c_word_w,
@@ -75,9 +74,7 @@ architecture rtl of dp_ram_to_mm is
signal wr_data : std_logic_vector(c_mm_ram_wr.dat_w - 1 downto 0);
signal wr_addr : std_logic_vector(c_mm_ram_wr.adr_w - 1 downto 0);
signal nxt_wr_addr : std_logic_vector(c_mm_ram_wr.adr_w - 1 downto 0);
-
begin
-
p_state : process(state, wr_addr, snk_in, wr_data)
begin
nxt_state <= state;
@@ -115,10 +112,8 @@ begin
when others =>
nxt_state <= s_init;
end case;
-
end process;
-
p_clk : process(st_rst, st_clk)
begin
if st_rst = '1' then
@@ -154,6 +149,4 @@ begin
rd_dat => sla_out.rddata(c_mm_ram_rd.dat_w - 1 downto 0),
rd_val => sla_out.rdval
);
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_ready.vhd b/libraries/base/dp/src/vhdl/dp_ready.vhd
index 9e3bdb3aa83e952f982acc69ccfddf7ad24ab3ef..f1f8532c37cc45f6c750c6937012ad9fdff2068f 100644
--- a/libraries/base/dp/src/vhdl/dp_ready.vhd
+++ b/libraries/base/dp/src/vhdl/dp_ready.vhd
@@ -47,14 +47,10 @@ entity dp_ready is
);
end dp_ready;
-
architecture rtl of dp_ready is
-
signal reg_ready : std_logic_vector(g_ready_latency downto 0);
signal reg_val : std_logic;
-
begin
-
gen_latency : if g_ready_latency > 0 generate
reg_ready(0) <= src_in.ready; -- use reg_ready(0) to combinatorially store src_in.ready
@@ -82,6 +78,4 @@ begin
src_out.sop <= snk_in.sop and reg_val;
src_out.eop <= snk_in.eop and reg_val;
end process;
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
index 60a4f0f862d3886edd14c6b1bc3834e47e8c462e..d0f65d7299734d6a4c435283a0e453714cb7a57e 100644
--- a/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reinterleave.vhd
@@ -74,9 +74,7 @@ entity dp_reinterleave is
);
end dp_reinterleave;
-
architecture wrap of dp_reinterleave is
-
constant c_complex_w : natural := g_dat_w / 2;
signal common_reinterleave_in_dat : std_logic_vector(g_nof_in * g_dat_w - 1 downto 0);
@@ -86,9 +84,7 @@ architecture wrap of dp_reinterleave is
signal common_reinterleave_src_out_arr : t_dp_sosi_arr(g_nof_out - 1 downto 0);
signal dp_block_gen_src_out_arr : t_dp_sosi_arr(g_nof_out - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Map input sosi_arr to SLV
-----------------------------------------------------------------------------
diff --git a/libraries/base/dp/src/vhdl/dp_repack.vhd b/libraries/base/dp/src/vhdl/dp_repack.vhd
index 80ff6b55ca31d117d8e87239898858ba317f251d..ebc3dd4c1b829e0f05476741b0623d7f483619e9 100644
--- a/libraries/base/dp/src/vhdl/dp_repack.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack.vhd
@@ -63,9 +63,7 @@ entity dp_repack is
);
end dp_repack;
-
architecture rtl of dp_repack is
-
constant c_buf_dat_w : natural := g_in_dat_w * g_in_nof_words;
signal in_dat_vec : std_logic_vector(c_buf_dat_w - 1 downto 0);
@@ -95,9 +93,7 @@ architecture rtl of dp_repack is
signal nxt_buf_eof : std_logic;
signal nxt_out_sof : std_logic;
signal nxt_sof_sync : std_logic;
-
begin
-
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack at the other end,
-- typically g_out_dat_w=g_in_dat_w
@@ -178,7 +174,6 @@ begin
-- Right shift in_dat into in_dat_vec at each in_dat cycle, results in MS to LS word concatenation
nxt_in_dat_vec <= in_dat_vec(in_dat_vec'high - in_dat'length downto 0) & in_dat;
end if;
-
end if;
end process;
@@ -242,5 +237,4 @@ begin
end if;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_repack_data.vhd b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
index 24eb8308cf03b3014fcb53dfd3e7a266848455e0..fbc1849f6a79eb003fcbabc5ed3a4a8e6db5a95a 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_data.vhd
@@ -199,9 +199,7 @@ entity dp_repack_in is
);
end dp_repack_in;
-
architecture rtl of dp_repack_in is
-
constant c_in_buf_dat_w : natural := g_in_dat_w * g_in_nof_words;
constant c_bit_cnt_max : natural := c_in_buf_dat_w;
constant c_in_empty_lo : natural := true_log2(g_in_symbol_w);
@@ -233,9 +231,7 @@ architecture rtl of dp_repack_in is
signal dbg_in_nof_words : natural := g_in_nof_words;
signal dbg_in_symbol_w : natural := g_in_symbol_w;
signal dbc_in_buf_dat_w : natural := c_in_buf_dat_w;
-
begin
-
snk_in_data <= snk_in.data(g_in_dat_w - 1 downto 0);
src_out <= i_src_out;
@@ -248,7 +244,6 @@ begin
end generate;
no_bypass : if g_bypass = false generate
-
p_comb : process(rst, r, snk_in, data_vec, src_in)
variable v : t_reg;
begin
@@ -386,13 +381,10 @@ begin
-- combined local and remote src_in flow control
snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready; -- if there is pending output then the src_in ready determines the flow control
snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
-
end generate;
end rtl;
-
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -420,7 +412,6 @@ entity dp_repack_out is
end dp_repack_out;
architecture rtl of dp_repack_out is
-
constant c_out_buf_dat_w : natural := g_out_dat_w * g_out_nof_words;
constant c_out_buf_dat_lo : natural := sel_a_b(c_out_buf_dat_w > g_in_buf_dat_w, c_out_buf_dat_w - g_in_buf_dat_w, 0); -- pack into subsection with 0 or more padding bits
constant c_snk_in_dat_lo : natural := sel_a_b(c_out_buf_dat_w < g_in_buf_dat_w, g_in_buf_dat_w - c_out_buf_dat_w, 0); -- unpack from subsection that has 0 or more padding bits
@@ -457,9 +448,7 @@ architecture rtl of dp_repack_out is
signal dbc_out_buf_dat_w : natural := c_out_buf_dat_w;
signal dbc_out_buf_dat_lo : natural := c_out_buf_dat_lo;
signal dbc_snk_in_dat_lo : natural := c_snk_in_dat_lo;
-
begin
-
src_out <= i_src_out;
src_out_data <= i_src_out.data(g_out_dat_w - 1 downto 0);
@@ -481,7 +470,6 @@ begin
end generate;
no_bypass : if g_bypass = false generate
-
p_comb : process(rst, snk_in, r, data_vec, src_in)
variable v : t_reg;
begin
@@ -633,13 +621,10 @@ begin
-- combined local and remote src_in flow control
snk_out.ready <= r_snk_out.ready when nxt_r.hold_out.valid = '0' else src_in.ready; -- if there is pending output then the src_in ready determines the flow control
snk_out.xon <= src_in.xon; -- just pass on the xon/off frame flow control
-
end generate;
end rtl;
-
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -671,9 +656,7 @@ entity dp_repack_data is
);
end dp_repack_data;
-
architecture str of dp_repack_data is
-
constant c_in_buf_dat_w : natural := g_in_dat_w * g_in_nof_words;
signal snk_in_data : std_logic_vector(g_in_dat_w - 1 downto 0);
@@ -689,9 +672,7 @@ architecture str of dp_repack_data is
signal snk_out_ready_reg : std_logic_vector(0 to c_dp_stream_rl);
signal pack_ready_reg : std_logic_vector(0 to c_dp_stream_rl);
-
begin
-
gen_dp_pipeline_ready: if g_pipeline_ready = true generate
u_dp_pipeline_ready : entity dp_lib.dp_pipeline_ready
port map (
@@ -773,5 +754,4 @@ begin
-- Simulation only: internal stream RL verification
proc_dp_siso_alert(clk, i_snk_in, i_snk_out, snk_out_ready_reg);
proc_dp_siso_alert(clk, pack_sosi, pack_siso, pack_ready_reg);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
index bbf5cac26cfeaed221a9bfece2ee12c821bb6162..5149b5f2aa0e10f745d397dc9562715acf3a1058 100644
--- a/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
+++ b/libraries/base/dp/src/vhdl/dp_repack_legacy.vhd
@@ -63,9 +63,7 @@ entity dp_repack_legacy is
);
end dp_repack_legacy;
-
architecture rtl of dp_repack_legacy is
-
constant c_buf_dat_w : natural := g_in_dat_w * g_in_nof_words;
signal in_dat_vec : std_logic_vector(c_buf_dat_w - 1 downto 0);
@@ -95,9 +93,7 @@ architecture rtl of dp_repack_legacy is
signal nxt_buf_eof : std_logic;
signal nxt_out_sof : std_logic;
signal nxt_sof_sync : std_logic;
-
begin
-
no_pack : if g_in_nof_words = g_out_nof_words generate
out_dat <= RESIZE_UVEC(in_dat, out_dat'length); -- any extra bits will get stripped again by dp_repack_legacy at the other end,
-- typically g_out_dat_w=g_in_dat_w
@@ -178,7 +174,6 @@ begin
-- Right shift in_dat into in_dat_vec at each in_dat cycle, results in MS to LS word concatenation
nxt_in_dat_vec <= in_dat_vec(in_dat_vec'high - in_dat'length downto 0) & in_dat;
end if;
-
end if;
end process;
@@ -242,5 +237,4 @@ begin
end if;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_requantize.vhd b/libraries/base/dp/src/vhdl/dp_requantize.vhd
index 1c5547523aabb2dddc80eabe3c130468bccaacaf..c063da2ad8305ae55fb422bd0f9299401e8a9d26 100644
--- a/libraries/base/dp/src/vhdl/dp_requantize.vhd
+++ b/libraries/base/dp/src/vhdl/dp_requantize.vhd
@@ -63,9 +63,7 @@ entity dp_requantize is
);
end dp_requantize;
-
architecture str of dp_requantize is
-
constant c_pipeline : natural := g_pipeline_remove_lsb + g_pipeline_remove_msb;
signal snk_in_piped : t_dp_sosi;
@@ -75,9 +73,7 @@ architecture str of dp_requantize is
signal quantized_im : std_logic_vector(g_out_dat_w - 1 downto 0);
signal out_ovr_re : std_logic;
signal out_ovr_im : std_logic;
-
begin
-
assert g_gain_w = 0 report "dp_requantize: must use g_gain_w = 0, because gain is now supported via negative g_lsb_w." severity FAILURE;
---------------------------------------------------------------
@@ -155,7 +151,6 @@ begin
out_ovr <= out_ovr_re or out_ovr_im;
end generate;
-
--------------------------------------------------------------
-- Pipeline to align the other sosi fields
--------------------------------------------------------------
@@ -186,5 +181,4 @@ begin
src_out.im <= RESIZE_DP_DSP_DATA(quantized_im);
end if;
end process;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
index 2c9a6f805698148484a275467755a387d1a39258..7e76bc93ba2fda5f3dbb0ee1e46025cd77b1f1a0 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data.vhd
@@ -64,9 +64,7 @@ entity dp_reverse_n_data is
);
end dp_reverse_n_data;
-
architecture str of dp_reverse_n_data is
-
constant c_pipeline_total : natural := g_pipeline_demux_in + g_pipeline_demux_out +
g_reverse_len - 1 +
g_pipeline_mux_in + g_pipeline_mux_out;
@@ -78,9 +76,7 @@ architecture str of dp_reverse_n_data is
signal reversed_val : std_logic;
signal snk_in_delayed : t_dp_sosi;
-
begin
-
p_in_data : process(snk_in)
begin
if g_use_complex = false then
@@ -139,5 +135,4 @@ begin
src_out.re <= RESIZE_DP_DSP_DATA(reversed_data(c_complex_w - 1 downto 0));
end if;
end process;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
index 50335742ea77b30a63e00b20f6bfb483adb75115..77741d7694fc2fd2e24368c07c94994743ee86ab 100644
--- a/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/src/vhdl/dp_reverse_n_data_fc.vhd
@@ -60,16 +60,12 @@ entity dp_reverse_n_data_fc is
);
end dp_reverse_n_data_fc;
-
architecture str of dp_reverse_n_data_fc is
-
signal demux_siso_arr : t_dp_siso_arr(g_reverse_len - 1 downto 0);
signal demux_sosi_arr : t_dp_sosi_arr(g_reverse_len - 1 downto 0);
signal reverse_siso_arr : t_dp_siso_arr(g_reverse_len - 1 downto 0);
signal reverse_sosi_arr : t_dp_sosi_arr(g_reverse_len - 1 downto 0);
-
begin
-
u_demux_one_to_n : entity work.dp_deinterleave_one_to_n
generic map (
g_pipeline => g_pipeline_in,
@@ -104,5 +100,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
index d492b2fb9feb8152bb3a85bb351fd6c2a4475937..db1c3512342323fb01cfcf219686b085bd84b435 100644
--- a/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/dp_rsn_source.vhd
@@ -89,9 +89,7 @@ entity dp_rsn_source is
);
end dp_rsn_source;
-
architecture rtl of dp_rsn_source is
-
constant c_bs_block_size_cnt_w : natural := ceil_log2(g_bs_block_size) + 1; -- +1 because value 2**n requires n + 1 bits
constant c_rs_block_size_cnt_w : natural := ceil_log2(g_rs_block_size) + 1; -- +1 because value 2**n requires n + 1 bits
constant c_rsn_product_w : natural := g_bsn_w + c_bs_block_size_cnt_w;
@@ -119,9 +117,7 @@ architecture rtl of dp_rsn_source is
signal nxt_rs_restart : std_logic;
signal i_rs_new_interval : std_logic;
signal reg_rs_new_interval : std_logic;
-
begin
-
rs_sosi <= i_rs_sosi;
rs_restart <= i_rs_restart;
rs_new_interval <= i_rs_new_interval;
@@ -248,5 +244,4 @@ begin
reg_rs_new_interval <= i_rs_new_interval;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_selector.vhd b/libraries/base/dp/src/vhdl/dp_selector.vhd
index 045ffea4280497ef6ba09340c8c4be191108b1cc..79aea5699354607b65eb042ed3d080162e1b5ec9 100644
--- a/libraries/base/dp/src/vhdl/dp_selector.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector.vhd
@@ -27,7 +27,6 @@
-- . See dp_selector_arr.vhd for more detail.
-------------------------------------------------------------------------------
-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -59,9 +58,7 @@ entity dp_selector is
end dp_selector;
architecture str of dp_selector is
-
begin
-
u_dp_selector_arr : entity work.dp_selector_arr
generic map (
g_nof_arr => 1,
@@ -82,5 +79,4 @@ begin
selector_en => selector_en
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
index 82c747c2008dcecac377c980ddccf50ab00a6b3f..33b96c99a3e941fe4b52cf4eabaf4abe82f1abfc 100644
--- a/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
+++ b/libraries/base/dp/src/vhdl/dp_selector_arr.vhd
@@ -30,7 +30,6 @@
-- The select register is synchronised with the sync signal in ref_sosi_arr.
-------------------------------------------------------------------------------
-
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -71,9 +70,7 @@ architecture str of dp_selector_arr is
signal pipelined_pipe_sosi_arr : t_dp_sosi_arr(g_nof_arr - 1 downto 0);
signal select_sosi_arr : t_dp_sosi_arr(g_nof_arr - 1 downto 0);
-
begin
-
selector_en <= reg_selector_en(0);
u_mms_common_reg : entity common_lib.mms_common_reg
@@ -93,7 +90,6 @@ begin
out_reg => reg_selector_en
);
-
n_en <= not reg_selector_en(0);
u_common_switch : entity common_lib.common_switch
@@ -106,7 +102,6 @@ begin
out_level => switch_select
);
-
u_pipeline_arr : entity work.dp_pipeline_arr
generic map (
g_nof_streams => g_nof_arr,
@@ -119,7 +114,6 @@ begin
src_out_arr => pipelined_pipe_sosi_arr
);
-
select_sosi_arr <= pipelined_pipe_sosi_arr when switch_select = '1' else ref_sosi_arr;
u_pipeline_arr_out : entity work.dp_pipeline_arr
@@ -133,5 +127,4 @@ begin
snk_in_arr => select_sosi_arr,
src_out_arr => out_sosi_arr
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_shiftram.vhd b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
index bbb1631e139275eae2f6188dae40ef8436617542..f63fd0c4d9a8830d8340939a3e4f26ada9a05ab9 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftram.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftram.vhd
@@ -57,9 +57,7 @@ entity dp_shiftram is
);
end dp_shiftram;
-
architecture str of dp_shiftram is
-
constant c_shift_w : natural := ceil_log2(g_nof_words);
type t_common_shiftram_shift_arr is array(g_nof_streams - 1 downto 0) of std_logic_vector(c_shift_w - 1 downto 0);
@@ -72,9 +70,7 @@ architecture str of dp_shiftram is
type t_mm_fields_out_arr is array(g_nof_streams - 1 downto 0) of std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
signal mm_fields_out_arr : t_mm_fields_out_arr;
-
begin
-
-----------------------------------------------------------------------------
-- common_shiftram
-----------------------------------------------------------------------------
@@ -115,7 +111,6 @@ begin
);
gen_stream : for i in 0 to g_nof_streams - 1 generate
-
u_mm_fields: entity mm_lib.mm_fields
generic map(
g_field_arr => c_field_arr
@@ -132,6 +127,7 @@ begin
slv_out => mm_fields_out_arr(i)
);
+
gen_no_sync : if g_use_sync_in = false generate
common_shiftram_shift_in_arr(i) <= mm_fields_out_arr(i)(field_hi(c_field_arr, "shift") downto field_lo(c_field_arr, "shift"));
end generate;
@@ -148,7 +144,6 @@ begin
end if;
end process;
end generate;
-
end generate;
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
index 5d65ca25fad47c40ce852108c7f7850e5cb01480..0a6c63afa81d0216065f4c21d79df4095509133b 100644
--- a/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_shiftreg.vhd
@@ -70,9 +70,7 @@ entity dp_shiftreg is
);
end dp_shiftreg;
-
architecture rtl of dp_shiftreg is
-
constant c_high : natural := g_nof_words - 1; -- shift stream data from 0 to g_nof_words-1
signal prev_src_in : t_dp_siso;
@@ -86,9 +84,7 @@ architecture rtl of dp_shiftreg is
signal nxt_shiftreg : t_dp_sosi_arr(0 to c_high);
signal shiftreg_out : t_dp_sosi;
-
begin
-
cur_shiftreg_inputs <= i_cur_shiftreg_inputs;
-- Pass on frame level flow control
@@ -115,6 +111,7 @@ begin
no_flush_eop : if g_flush_eop = false generate
flush <= '0';
end generate;
+
gen_flush_eop : if g_flush_eop = true generate
p_eop : process(prev_src_in, shiftreg)
variable v_eop : std_logic := '0';
diff --git a/libraries/base/dp/src/vhdl/dp_split.vhd b/libraries/base/dp/src/vhdl/dp_split.vhd
index fff84c9cd854871ba2d6ce932a3c8c93aea67758..19ac1fb2b5140c73dc0ba9b4000292b702788c65 100644
--- a/libraries/base/dp/src/vhdl/dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split.vhd
@@ -72,7 +72,6 @@ use work.dp_stream_pkg.all;
-- restart -f, then run x ns to just before the when the error occurs and
-- then single step until the error occurs.
-
entity dp_split is
generic (
g_data_w : natural := 16; -- >= 1
@@ -101,9 +100,7 @@ entity dp_split is
);
end dp_split;
-
architecture rtl of dp_split is
-
constant c_nof_symbols_per_data : natural := g_data_w / g_symbol_w; -- nof symbols per data
constant c_empty_w : natural := ceil_log2(c_nof_symbols_per_data);
@@ -147,9 +144,7 @@ architecture rtl of dp_split is
signal nxt_input_empty_reg : std_logic_vector(c_empty_w - 1 downto 0);
signal nof_remain_reg : std_logic_vector(c_empty_w - 1 downto 0);
signal nxt_nof_remain_reg : std_logic_vector(c_empty_w - 1 downto 0);
-
begin
-
assert (g_data_w mod g_symbol_w) = 0 report "dp_split : g_data_w/g_symbol_w must be an integer" severity FAILURE;
snk_out <= i_snk_out;
@@ -221,7 +216,6 @@ begin
variable v_cnt : std_logic_vector(c_symbol_cnt_w - 1 downto 0);
variable v_nof_from_this : natural range 0 to c_nof_symbols_per_data;
begin
-
-- SISO default
i_snk_out <= c_dp_siso_rst; -- no input request
hold_src_in <= c_dp_siso_rst; -- no input request
@@ -394,5 +388,4 @@ begin
i_snk_out.xon <= func_dp_stream_arr_and(src_in_arr, "XON");
hold_src_in.xon <= func_dp_stream_arr_and(src_in_arr, "XON");
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_split_reg.vhd b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
index 16c0abe596ac5500c7fe58eadd9713cec49e4a1d..dc7a67f30eac44f750775c73f8a7c851ede10554 100644
--- a/libraries/base/dp/src/vhdl/dp_split_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_split_reg.vhd
@@ -29,7 +29,6 @@
-- | nof_symbols | 0
-- |-----------------------------------------------------------------------|
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -55,9 +54,7 @@ entity dp_split_reg is
);
end dp_split_reg;
-
architecture str of dp_split_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 1,
dat_w => c_word_w,
@@ -65,9 +62,7 @@ architecture str of dp_split_reg is
init_sl => '0');
signal mm_nof_symbols : std_logic_vector(ceil_log2(g_nof_symbols + 1) - 1 downto 0);
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -118,5 +113,4 @@ begin
out_dat => nof_symbols
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
index 9b20a225803e5494e0926ac415225a4089dc5d11..e47aa13cbc082f269f16527fd5c4d6bcc6e09aa2 100644
--- a/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
+++ b/libraries/base/dp/src/vhdl/dp_src_out_timer.vhd
@@ -54,7 +54,6 @@ entity dp_src_out_timer is
end dp_src_out_timer;
architecture rtl of dp_src_out_timer is
-
type t_state is (s_init, s_wait, s_delay, s_ready, s_not_ready);
signal state : t_state;
signal nxt_state : t_state;
@@ -67,9 +66,7 @@ architecture rtl of dp_src_out_timer is
signal prv_snk_out_ready : std_logic;
signal snk_out_ready : std_logic;
signal nxt_snk_out_ready : std_logic;
-
begin
-
snk_out.ready <= snk_out_ready;
snk_out.xon <= '1';
@@ -78,7 +75,6 @@ begin
-----------------------------------------------------------------------------
p_state : process(state, init_valid_delay_ref, cycle_cnt, snk_out_ready, prv_snk_out_ready, snk_in.valid)
begin
-
nxt_state <= state;
nxt_cycle_cnt <= cycle_cnt;
nxt_snk_out_ready <= snk_out_ready;
@@ -134,9 +130,7 @@ begin
nxt_state <= s_wait;
nxt_snk_out_ready <= '0';
nxt_cycle_cnt <= (others => '0');
-
end case;
-
end process;
-----------------------------------------------------------------------------
@@ -156,5 +150,4 @@ begin
cycle_cnt <= nxt_cycle_cnt;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
index e466a0ad0457ab9536a42f72296b20cc5b6873ba..22b5cc127b9cc70e12ff83e8c407b8fe20242199 100644
--- a/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_stream_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package dp_stream_pkg is
-
------------------------------------------------------------------------------
-- General DP stream record defintion
------------------------------------------------------------------------------
@@ -410,9 +409,7 @@ package dp_stream_pkg is
end dp_stream_pkg;
-
package body dp_stream_pkg is
-
-- Check sosi.valid against siso.ready
procedure proc_dp_siso_alert(constant c_ready_latency : in natural;
signal clk : in std_logic;
@@ -427,6 +424,7 @@ package body dp_stream_pkg is
if sosi.valid = '1' and ready_reg(c_ready_latency) = '0' then
report "RL ERROR" severity FAILURE;
end if;
+
ready_reg( 1 to c_ready_latency) <= ready_reg( 0 to c_ready_latency - 1);
end if;
end proc_dp_siso_alert;
@@ -595,7 +593,6 @@ package body dp_stream_pkg is
return RESIZE_DP_CHANNEL(std_logic_vector(unsigned(vec(w - 1 downto 0)) + dec));
end INCR_DP_CHANNEL;
-
function REPLICATE_DP_DATA(seq : std_logic_vector) return std_logic_vector is
constant c_seq_w : natural := seq'length;
constant c_nof_replications : natural := ceil_div(c_dp_stream_data_w, c_seq_w);
@@ -667,7 +664,6 @@ package body dp_stream_pkg is
return siso_arr(0);
end TO_DP_ONE;
-
-- Keep part of head data and combine part of tail data
function func_dp_data_shift_first(head_sosi, tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail : natural) return t_dp_sosi is
variable vN : natural := nof_symbols_per_data;
@@ -684,7 +680,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_first;
-
-- Shift and combine part of previous data and this data,
function func_dp_data_shift(prev_sosi, this_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_this : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_this;
@@ -717,7 +712,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift;
-
-- Shift part of tail data and account for input empty
function func_dp_data_shift_last(tail_sosi : t_dp_sosi; symbol_w, nof_symbols_per_data, nof_symbols_from_tail, input_empty : natural) return t_dp_sosi is
variable vK : natural := nof_symbols_from_tail;
@@ -746,7 +740,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_data_shift_last;
-
-- Determine resulting empty if two streams are concatenated
-- . both empty must use the same nof symbols per data
function func_dp_empty_concat(head_empty, tail_empty : std_logic_vector; nof_symbols_per_data : natural) return std_logic_vector is
@@ -774,7 +767,6 @@ package body dp_stream_pkg is
return TO_UVEC(v_empty, head_empty'length);
end func_dp_empty_split;
-
-- Multiplex the t_dp_sosi_arr based on the valid, assuming that at most one input is active valid.
function func_dp_sosi_arr_mux(dp : t_dp_sosi_arr) return t_dp_sosi is
variable v_sosi : t_dp_sosi := c_dp_sosi_rst;
@@ -788,7 +780,6 @@ package body dp_stream_pkg is
return v_sosi;
end func_dp_sosi_arr_mux;
-
-- Determine the combined logical value of corresponding STD_LOGIC fields in t_dp_*_arr (for all elements or only for the mask[]='1' elements)
function func_dp_stream_arr_and(dp : t_dp_siso_arr; mask : std_logic_vector; str : string) return std_logic is
variable v_vec : std_logic_vector(dp'range) := (others => '1'); -- set default v_vec such that unmasked input have no influence on operation result
@@ -906,7 +897,6 @@ package body dp_stream_pkg is
return func_dp_stream_arr_or(dp, c_mask, str);
end func_dp_stream_arr_or;
-
-- Functions to set or get a STD_LOGIC field as a STD_LOGIC_VECTOR to or from an siso or an sosi array
function func_dp_stream_arr_set(dp : t_dp_siso_arr; slv : std_logic_vector; str : string) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(dp'range) := dp; -- default
@@ -980,7 +970,6 @@ package body dp_stream_pkg is
return v_ctrl;
end func_dp_stream_arr_get;
-
-- Functions to select elements from two siso or two sosi arrays (sel[] = '1' selects a, sel[] = '0' selects b)
function func_dp_stream_arr_select(sel : std_logic_vector; a, b : t_dp_siso) return t_dp_siso_arr is
variable v_dp : t_dp_siso_arr(sel'range);
@@ -1231,7 +1220,6 @@ package body dp_stream_pkg is
return v_dp;
end func_dp_stream_arr_copy_valid_bsn;
-
-- Functions to combinatorially handle channels
function func_dp_stream_channel_set(st_sosi : t_dp_sosi; ch : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
@@ -1262,7 +1250,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_channel_remove;
-
function func_dp_stream_error_set(st_sosi : t_dp_sosi; n : natural) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1270,7 +1257,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_error_set;
-
function func_dp_stream_bsn_set(st_sosi : t_dp_sosi; bsn : std_logic_vector) return t_dp_sosi is
variable v_rec : t_dp_sosi := st_sosi;
begin
@@ -1278,7 +1264,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_bsn_set;
-
function func_dp_stream_combine_info_and_data(info, data : t_dp_sosi) return t_dp_sosi is
variable v_rec : t_dp_sosi := data; -- Sosi data fields
begin
@@ -1291,7 +1276,6 @@ package body dp_stream_pkg is
return v_rec;
end func_dp_stream_combine_info_and_data;
-
function func_dp_stream_slv_to_integer(slv_sosi : t_dp_sosi; w : natural) return t_dp_sosi_integer is
variable v_rec : t_dp_sosi_integer;
begin
@@ -1572,6 +1556,4 @@ package body dp_stream_pkg is
return func_dp_data_match(snk_in_a, snk_in_b, data_w) and func_dp_data_match(snk_in_b, snk_in_c, data_w);
end;
-
end dp_stream_pkg;
-
diff --git a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
index 211fc2020f33d59d862181d60ca49537dcee4019..82eb03aa00a6e8cd9e06eea8c36635d510a6a146 100644
--- a/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
+++ b/libraries/base/dp/src/vhdl/dp_strobe_total_count.vhd
@@ -104,7 +104,6 @@ entity dp_strobe_total_count is
end dp_strobe_total_count;
architecture rtl of dp_strobe_total_count is
-
-- Fixed by REGMAP
constant c_nof_counts_max : natural := c_dp_strobe_total_count_reg_nof_counts_max;
constant c_clear_adr : natural := c_dp_strobe_total_count_reg_clear_adr;
@@ -134,9 +133,7 @@ architecture rtl of dp_strobe_total_count is
signal cnt_en_arr : std_logic_vector(g_nof_counts - 1 downto 0);
signal cnt_arr : t_cnt_arr(g_nof_counts - 1 downto 0);
signal hold_cnt_arr : t_cnt_arr(g_nof_counts - 1 downto 0) := (others => (others => '0'));
-
begin
-
assert g_nof_counts <= c_nof_counts_max report "Too many counters to fit REGMAP." severity FAILURE;
assert g_count_w <= g_mm_w * 2 report "Too wide counter to fit REGMAP." severity FAILURE;
@@ -236,6 +233,7 @@ begin
rd_reg((2 * I + 1) * g_mm_w - 1 downto (2 * I + 0) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I), g_mm_w); -- low part
rd_reg((2 * I + 2) * g_mm_w - 1 downto (2 * I + 1) * g_mm_w) <= (others => '0'); -- high part (not used)
end generate;
+
gen_reg_64b : if g_count_w > g_mm_w generate
rd_reg((2 * I + 1) * g_mm_w - 1 downto (2 * I + 0) * g_mm_w) <= hold_cnt_arr(I)(g_mm_w - 1 downto 0); -- low part
rd_reg((2 * I + 2) * g_mm_w - 1 downto (2 * I + 1) * g_mm_w) <= RESIZE_UVEC(hold_cnt_arr(I)(g_count_w - 1 downto g_mm_w), g_mm_w); -- high part
@@ -265,5 +263,4 @@ begin
in_reg => rd_reg, -- read only
out_reg => open -- no write
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_switch.vhd b/libraries/base/dp/src/vhdl/dp_switch.vhd
index 5ba1d4d7ad98c9ccf73051849bc9d648276f79d0..e11631038321181d17ceb3c567f5fb6f25d21a0b 100644
--- a/libraries/base/dp/src/vhdl/dp_switch.vhd
+++ b/libraries/base/dp/src/vhdl/dp_switch.vhd
@@ -76,9 +76,7 @@ entity dp_switch is
);
end dp_switch;
-
architecture str of dp_switch is
-
constant c_field_arr : t_common_field_arr(0 downto 0) := (0 => ( field_name_pad("input_select"), "RW", ceil_log2(g_nof_inputs), field_default(g_default_enabled) ));
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -90,9 +88,7 @@ architecture str of dp_switch is
signal inverted_snk_in_arr : t_dp_sosi_arr(0 to g_nof_inputs - 1);
signal inverted_snk_out_arr: t_dp_siso_arr(0 to g_nof_inputs - 1);
-
begin
-
------------------------------------------------------------------------------
-- A single MM register contains input to select
------------------------------------------------------------------------------
@@ -180,5 +176,4 @@ begin
src_out => src_out,
src_in => src_in
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
index bdd968f814f927be864fc260d9a095faf45371bd..e17d04d777c8dd8c0464dc8658e8a8d563dc6122 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_checker.vhd
@@ -78,7 +78,6 @@ entity dp_sync_checker is
end dp_sync_checker;
architecture str of dp_sync_checker is
-
constant c_nof_blk_per_sync : natural := g_nof_blk_per_sync - 1;
type reg_type is record
@@ -92,9 +91,7 @@ architecture str of dp_sync_checker is
end record;
signal r, rin : reg_type;
-
begin
-
snk_out <= c_dp_siso_rdy;
p_comb : process(r, dp_rst, snk_in )
@@ -161,7 +158,6 @@ begin
end if;
rin <= v;
-
end process;
p_regs : process(dp_clk)
@@ -174,7 +170,4 @@ begin
src_out <= r.src_out;
nof_early_syncs <= TO_UVEC(r.nof_early_syncs, c_word_w);
nof_late_syncs <= TO_UVEC(r.nof_late_syncs, c_word_w);
-
end str;
-
-
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
index 6cfdc159357a27abea6a2ed840bb2c886dd1262d..d1da545d1af2c068b214a8ac38babc8c2b7865da 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert.vhd
@@ -55,9 +55,7 @@ entity dp_sync_insert is
);
end dp_sync_insert;
-
architecture rtl of dp_sync_insert is
-
type t_reg is record -- local registers
data_cnt : natural range 0 to g_nof_data_per_blk;
blk_cnt : natural range 0 to g_nof_blk_per_sync;
@@ -72,9 +70,7 @@ architecture rtl of dp_sync_insert is
-- Define the local registers in t_reg record
signal r : t_reg;
signal nxt_r : t_reg;
-
begin
-
src_out <= r.src_out;
p_clk : process(rst, clk)
@@ -86,11 +82,9 @@ begin
end if;
end process;
-
p_comb : process(r, snk_in)
variable v : t_reg;
begin
-
v := r;
v.src_out := func_dp_stream_reset_control(v.src_out);
v.snk_in_reg := snk_in;
@@ -130,7 +124,5 @@ begin
end if;
nxt_r <= v;
-
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
index 9532abac3f987bff2421c09389ca580ab92c7abc..d5d54d2a23d6e683fe8936711552399d3e5bec2f 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_insert_v2.vhd
@@ -65,9 +65,7 @@ entity dp_sync_insert_v2 is
);
end dp_sync_insert_v2;
-
architecture rtl of dp_sync_insert_v2 is
-
type t_reg is record -- local registers
blk_cnt : natural range 0 to g_nof_blk_per_sync;
nof_blk_per_sync : natural range 0 to g_nof_blk_per_sync;
@@ -84,9 +82,7 @@ architecture rtl of dp_sync_insert_v2 is
signal nxt_r : t_reg;
signal reg_nof_blk_per_sync : std_logic_vector(c_mm_reg_w - 1 downto 0);
-
begin
-
out_sosi_arr <= r.out_sosi_arr;
p_clk : process(dp_rst, dp_clk)
@@ -123,7 +119,6 @@ begin
nxt_r <= v;
end process;
-
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
generic map (
g_cross_clock_domain => true,
@@ -148,5 +143,4 @@ begin
in_reg => reg_nof_blk_per_sync,
out_reg => reg_nof_blk_per_sync
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
index 4a4dc90eb140ce674711eaa2e02dba09290f3878..60fee25c8b2c1db2cef921d309acde526dcd4587 100644
--- a/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
+++ b/libraries/base/dp/src/vhdl/dp_sync_recover.vhd
@@ -62,9 +62,7 @@ entity dp_sync_recover is
);
end dp_sync_recover;
-
architecture rtl of dp_sync_recover is
-
type t_reg is record -- local registers
bsn_at_sync : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- bsn to store at which to generate a sync pulse.
bsn_before_restart : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0); -- bsn to store at which to restart te bsn counter.
@@ -81,9 +79,7 @@ architecture rtl of dp_sync_recover is
-- Define the local registers in t_reg record
signal r : t_reg;
signal nxt_r : t_reg;
-
begin
-
out_sosi <= nxt_r.out_sosi;
p_clk : process(dp_rst, dp_clk)
@@ -146,5 +142,4 @@ begin
nxt_r <= v;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
index 280865f0a5ae509d143ef6cece62ba6c371ae8a5..d27a5f17436bb879a14cf9b7a40a9b01b9df2dc0 100644
--- a/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
+++ b/libraries/base/dp/src/vhdl/dp_tail_remove.vhd
@@ -54,9 +54,7 @@ entity dp_tail_remove is
);
end dp_tail_remove;
-
architecture str of dp_tail_remove is
-
constant c_output_reg : boolean := true; -- register dp_shiftreg output to ease timing closure
constant c_tail_nof_words : natural := ceil_div(g_nof_symbols * g_symbol_w, g_data_w);
@@ -66,9 +64,7 @@ architecture str of dp_tail_remove is
signal rd_sosi_arr : t_dp_sosi_arr(0 to c_nof_shiftreg_words - 1);
signal wr_sosi_arr : t_dp_sosi_arr(0 to c_nof_shiftreg_words - 1);
-
begin
-
snk_out <= src_in;
u_src_shift : entity work.dp_shiftreg
@@ -109,5 +105,4 @@ begin
wr_sosi_arr <= v_wr_sosi_arr;
end process;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle.vhd b/libraries/base/dp/src/vhdl/dp_throttle.vhd
index fa7dd4d811683f1c11efdd3e9dbaf83806fc995e..0c1ab51619cf7a0d151571c9c38778bfd870ed3f 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.dp_stream_pkg.all;
-
entity dp_throttle is
generic (
g_dc_period : natural := 100; -- provides a resolution of 1% (1/100..100/100)
@@ -46,11 +45,8 @@ entity dp_throttle is
end dp_throttle;
architecture str of dp_throttle is
-
signal dc_out : std_logic;
-
begin
-
gen_throttle_ready : if g_throttle_valid = false generate
-- Simply AND the ready signal with out duty cycle controlled signal to provide a throttle
snk_out.ready <= src_in.ready and dc_out;
@@ -80,7 +76,4 @@ begin
dc_out_en => '1', -- We can also disable the output by writing zero to dc_act_cnt.
dc_out => dc_out
);
-
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
index 10d5e4a7ce484c97916bbc3433fe19a1d81691dd..3d755e41eef38b65af816033f904fbca74f1ee5f 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_reg.vhd
@@ -44,9 +44,7 @@ entity dp_throttle_reg is
);
end dp_throttle_reg;
-
architecture rtl of dp_throttle_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 2,
@@ -55,9 +53,7 @@ architecture rtl of dp_throttle_reg is
init_sl => '0');
signal mm_throttle : std_logic_vector(ceil_log2(g_dc_period + 1) - 1 downto 0);
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -77,7 +73,6 @@ begin
when others => null;
end case;
-
end if;
end if;
end process;
@@ -93,5 +88,4 @@ begin
out_dat => throttle,
out_new => open
);
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
index 2a769f7a58d5b1f350830506f2eb6f8df4cf2d68..f90a6ffc44cab67006d4ca19d8352d519601b763 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_sop.vhd
@@ -44,7 +44,6 @@ entity dp_throttle_sop is
end dp_throttle_sop;
architecture str of dp_throttle_sop is
-
constant c_cnt_w : natural := ceil_log2(g_period);
signal cnt_clr : std_logic := '0';
@@ -54,9 +53,7 @@ architecture str of dp_throttle_sop is
signal switch_high : std_logic;
signal switch_low : std_logic;
signal switch_out : std_logic;
-
begin
-
snk_out.xon <= '1';
u_common_counter : entity common_lib.common_counter
@@ -92,6 +89,4 @@ begin
switch_high <= not cnt_en;
switch_low <= snk_in.eop;
snk_out.ready <= switch_out;
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
index 48ca4a6a11f819c6639c4143199f22e5ef72ef08..dc6307419b85697a32049843aa797a4c6cff1c9c 100644
--- a/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
+++ b/libraries/base/dp/src/vhdl/dp_throttle_xon.vhd
@@ -33,7 +33,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.dp_stream_pkg.all;
-
entity dp_throttle_xon is
generic (
g_restart_at_sync : boolean := false; -- if true restart xon control at each snk_in_sync, else and start at first valid and never restart
@@ -54,7 +53,6 @@ entity dp_throttle_xon is
end dp_throttle_xon;
architecture rtl of dp_throttle_xon is
-
constant c_nof_block_on : natural := g_nof_block_on - 1; -- adjust by -1 to account for that first block already appears at cnt = 0
constant c_nof_valid_on : natural := c_nof_block_on * g_block_size;
@@ -62,9 +60,7 @@ architecture rtl of dp_throttle_xon is
signal nxt_cnt : natural;
signal xon : std_logic;
signal nxt_xon : std_logic;
-
begin
-
snk_out.ready <= src_in.ready; -- pass on ready
snk_out.xon <= src_in.xon and xon; -- control xon
@@ -120,6 +116,4 @@ begin
nxt_xon <= '1';
end if;
end process;
-
end rtl;
-
diff --git a/libraries/base/dp/src/vhdl/dp_unfolder.vhd b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
index 6d6bb3c5bba800a8014e5aace122b23fc00803f5..3df7cc4c185dbc765a534f033d12a27592ae1ab5 100644
--- a/libraries/base/dp/src/vhdl/dp_unfolder.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unfolder.vhd
@@ -57,7 +57,6 @@ entity dp_unfolder is
end dp_unfolder;
architecture str of dp_unfolder is
-
component dp_unfolder is
generic (
g_nof_inputs : natural;
@@ -91,9 +90,7 @@ architecture str of dp_unfolder is
signal dp_block_gen_snk_in_arr : t_dp_sosi_arr(c_nof_outputs - 1 downto 0);
signal dp_block_gen_src_out_arr : t_dp_sosi_arr(c_nof_outputs - 1 downto 0);
-
begin
-
gen_arch: if g_nof_unfolds /= 0 generate
-----------------------------------------------------------------------------
-- Simple 2-output demux logic
@@ -175,7 +172,6 @@ begin
-- g_nof_unfolds=1, so this is the last stage. Wire up the outputs.
-----------------------------------------------------------------------------
gen_src_out_arr: if g_nof_unfolds = 1 generate
-
gen_output_align : if g_output_align = true generate
dp_pipeline_snk_in_arr <= demux_src_out_arr;
@@ -256,7 +252,6 @@ begin
end generate;
end generate;
-
end generate;
-----------------------------------------------------------------------------
@@ -267,4 +262,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/dp_unframe.vhd b/libraries/base/dp/src/vhdl/dp_unframe.vhd
index 1164b21af89e410c48153826aa2170f326bea1a5..2e9d0f5b21e5c852c17edee51b699a5beabc3431 100644
--- a/libraries/base/dp/src/vhdl/dp_unframe.vhd
+++ b/libraries/base/dp/src/vhdl/dp_unframe.vhd
@@ -79,12 +79,9 @@ begin
report "g_fsn_w must be smaller than or equal to g_dat_w"
severity ERROR;
-- synthesis translate_on
-
end dp_unframe;
-
architecture rtl of dp_unframe is
-
-- Use unregistered input to save logic, use registered input to ease achieving timing constrains.
constant c_input_reg : boolean := false;
@@ -125,9 +122,7 @@ architecture rtl of dp_unframe is
signal nxt_out_sof : std_logic;
signal nxt_out_eof : std_logic;
signal nxt_sof_sync : std_logic;
-
begin
-
out_fsn <= i_out_fsn;
out_err <= i_out_err;
out_dat <= i_out_dat;
@@ -148,6 +143,7 @@ begin
end if;
end process;
end generate;
+
no_input_reg : if c_input_reg = false generate
in_dat_reg <= in_dat;
in_val_reg <= in_val;
@@ -241,5 +237,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_validate.vhd b/libraries/base/dp/src/vhdl/dp_validate.vhd
index 7db309c9bfc954b5966acbe9251ee3648ec91216..763676ec420ed4cadc52cefbe14d285f82a5714c 100644
--- a/libraries/base/dp/src/vhdl/dp_validate.vhd
+++ b/libraries/base/dp/src/vhdl/dp_validate.vhd
@@ -51,13 +51,9 @@ entity dp_validate is
);
end dp_validate;
-
architecture rtl of dp_validate is
-
signal valid : std_logic;
-
begin
-
-- SISO ready
snk_out <= src_in;
@@ -90,5 +86,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
index ed719fde5563dc79948ab32aeccaf461eed88818..a12132a9ea42961ed3a9147d985556f51829be0d 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_sp_arr_scope.vhd
@@ -46,7 +46,6 @@
-- and the input sosi array has size g_wideband_factor, so there the wideband
-- data is carried via the sosi array dimension.
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -78,19 +77,16 @@ entity dp_wideband_sp_arr_scope is
);
end dp_wideband_sp_arr_scope;
-
architecture beh of dp_wideband_sp_arr_scope is
-
signal SCLKi : std_logic; -- sampling clk, for simulation only
signal scope_cnt_arr : t_natural_arr(g_nof_streams - 1 downto 0);
signal st_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
sim_only : if g_sim = true generate
use_sclk : if g_use_sclk = true generate
SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
end generate;
+
gen_sclk : if g_use_sclk = false generate
proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
end generate;
@@ -131,5 +127,4 @@ begin
scope_sosi_arr(I) <= func_dp_stream_slv_to_integer(st_sosi_arr(I), g_dat_w);
end generate;
end generate;
-
end beh;
diff --git a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
index ac4ac46a7e977fd3f7f153761761ac2a3b8627e4..fcedf587507c3e5aed27237bcec33f8be5d55e97 100644
--- a/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
+++ b/libraries/base/dp/src/vhdl/dp_wideband_wb_arr_scope.vhd
@@ -39,7 +39,6 @@
-- data is carried by g_wideband_factor concatenated symbols in the data
-- field or in the (re, im) fields.
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -68,19 +67,16 @@ entity dp_wideband_wb_arr_scope is
);
end dp_wideband_wb_arr_scope;
-
architecture beh of dp_wideband_wb_arr_scope is
-
signal SCLKi : std_logic; -- sampling clk, for simulation only
signal sample_cnt : natural range 0 to g_wideband_factor - 1 := 0;
signal st_sosi : t_dp_sosi;
-
begin
-
sim_only : if g_sim = true generate
use_sclk : if g_use_sclk = true generate
SCLKi <= SCLK; -- no worry about the delta cycle delay from SCLK to SCLKi
end generate;
+
gen_sclk : if g_use_sclk = false generate
proc_common_dclk_generate_sclk(g_wideband_factor, DCLK, SCLKi);
end generate;
@@ -104,5 +100,4 @@ begin
-- Map sosi to SLV of actual g_dat_w to allow observation in Wave Window in analogue format
scope_sosi <= func_dp_stream_slv_to_integer(st_sosi, g_dat_w);
end generate;
-
end beh;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff.vhd b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
index c85d77fe4c2f931fb67d15e101418992349653d7..e9768eda7a94e66064fb093c00a703b5de5ef37d 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff.vhd
@@ -114,9 +114,7 @@ entity dp_xonoff is
);
end dp_xonoff;
-
architecture rtl of dp_xonoff is
-
signal frm_busy : std_logic;
signal frm_busy_reg : std_logic;
@@ -125,9 +123,7 @@ architecture rtl of dp_xonoff is
signal i_out_en : std_logic;
signal nxt_out_en : std_logic;
-
begin
-
out_en <= i_out_en;
gen_bypass : if g_bypass = true generate
@@ -188,5 +184,4 @@ begin
out_sosi.eop <= in_sosi.eop and i_out_en;
end process;
end generate;
-
end architecture;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
index c64bf88f1b5889fab35806916f7b9ba6b6d3c249..7690cbfe3f5d12f8cafcec558220b4144ed6d28b 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg.vhd
@@ -57,9 +57,7 @@ entity dp_xonoff_reg is
);
end dp_xonoff_reg;
-
architecture str of dp_xonoff_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 1,
dat_w => c_word_w,
@@ -67,9 +65,7 @@ architecture str of dp_xonoff_reg is
init_sl => g_default_value);
signal mm_xonoff_reg : std_logic_vector(0 downto 0);
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -120,5 +116,4 @@ begin
out_dat => xonoff_reg
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
index 1edae2143b27c7ab629e26cf6fab54a80384e0f9..4fd64c8f6e32acd2b9866efb3fe59b9d78607a17 100644
--- a/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/src/vhdl/dp_xonoff_reg_timeout.vhd
@@ -59,9 +59,7 @@ entity dp_xonoff_reg_timeout is
);
end dp_xonoff_reg_timeout;
-
architecture str of dp_xonoff_reg_timeout is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 1,
dat_w => c_word_w,
@@ -69,17 +67,12 @@ architecture str of dp_xonoff_reg_timeout is
init_sl => g_default_value);
constant c_mm_max_counter : natural := sel_a_b(g_sim, g_mm_timeout * 50, g_mm_timeout * (50 * 10**6)); -- @50MHz
-
signal mm_xonoff_reg : std_logic_vector(0 downto 0);
signal mm_xonoff_reg_out : std_logic_vector(0 downto 0);
signal counter : std_logic_vector(c_word_w - 1 downto 0);
signal cnt_clr : std_logic := '0';
signal cnt_en : std_logic := '1';
-
-
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -128,8 +121,6 @@ begin
end if;
end process;
-
-
u_counter : entity common_lib.common_counter
generic map (
g_latency => 0
@@ -154,5 +145,4 @@ begin
out_dat => xonoff_reg
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
index 5f5977b0649ff3847cfb311db66194006877ecec..20456ab387ba3873e6a87d8843bafd78250ac876 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_align_v2.vhd
@@ -41,7 +41,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mmp_dp_bsn_align_v2 is
generic (
-- for dp_bsn_align_v2
@@ -94,9 +93,7 @@ entity mmp_dp_bsn_align_v2 is
);
end mmp_dp_bsn_align_v2;
-
architecture str of mmp_dp_bsn_align_v2 is
-
-- Use one MM word (bit 0) per input_enable bit, similar as in dp_bsn_align_reg.vhd.
-- TYPE t_c_mem IS RECORD
@@ -116,9 +113,7 @@ architecture str of mmp_dp_bsn_align_v2 is
signal mon_out_sosi_arr : t_dp_sosi_arr(0 downto 0);
signal i_out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal i_mm_sosi : t_dp_sosi;
-
begin
-
-- MM control of BSN aligner
u_reg : entity common_lib.common_reg_r_w_dc
generic map (
@@ -151,7 +146,6 @@ begin
reg_rd((2 * I + 2) * c_word_w - 1 downto (2 * I + 1) * c_word_w) <= stream_replaced_cnt_arr(I);
end generate;
-
-- Use local sync as reference sync input for the BSN monitors
ref_sync <= in_sosi_arr(0).sync;
@@ -252,6 +246,4 @@ begin
-- Output via streaming DP interface, when g_use_mm_output = TRUE.
out_sosi_arr => i_out_sosi_arr
);
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
index 114045c44f35f14c467a03c30bb0569e61195a40..4cab59e25a3a5fb7940625da40cb2af9a33d673f 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler.vhd
@@ -60,7 +60,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mmp_dp_bsn_sync_scheduler is
generic (
g_bsn_w : natural := c_dp_stream_bsn_w;
@@ -88,7 +87,6 @@ entity mmp_dp_bsn_sync_scheduler is
end mmp_dp_bsn_sync_scheduler;
architecture str of mmp_dp_bsn_sync_scheduler is
-
-- TYPE t_c_mem IS RECORD
-- latency : NATURAL; -- read latency
-- adr_w : NATURAL;
@@ -118,9 +116,7 @@ architecture str of mmp_dp_bsn_sync_scheduler is
signal rd_current_input_bsn_64 : std_logic_vector(2 * c_word_w - 1 downto 0);
signal rd_input_bsn_at_sync_64 : std_logic_vector(2 * c_word_w - 1 downto 0);
signal rd_output_sync_bsn_64 : std_logic_vector(2 * c_word_w - 1 downto 0);
-
begin
-
ctrl_start_bsn <= wr_start_bsn_64(g_bsn_w - 1 downto 0);
rd_current_input_bsn_64 <= RESIZE_UVEC(mon_current_input_bsn, 2 * c_word_w);
@@ -219,6 +215,4 @@ begin
out_start_interval => out_start_interval,
out_enable => out_enable
);
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
index 571927de276ca478ffbfbf96e04b9d2e71988a82..85a154fa94cf94049225eab31c7d7e19d21e33c3 100644
--- a/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mmp_dp_bsn_sync_scheduler_arr.vhd
@@ -30,7 +30,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mmp_dp_bsn_sync_scheduler_arr is
generic (
g_nof_streams : positive := 1;
@@ -65,7 +64,6 @@ architecture str of mmp_dp_bsn_sync_scheduler_arr is
signal in_sosi_arr_piped : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
begin
-
-- dp_bsn_sync_scheduler
u_mmp_dp_bsn_sync_scheduler : entity work.mmp_dp_bsn_sync_scheduler
generic map (
@@ -115,5 +113,4 @@ begin
out_sosi_arr(I).sync <= single_src_out.sync;
end loop;
end process;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
index 24912d4a4152a6daac3c41f974d4dcc752eb2f94..336f7e55650bcfe35676e4a5d72bfc1b5140ce16 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_block_select.vhd
@@ -61,9 +61,7 @@ entity mms_dp_block_select is
);
end mms_dp_block_select;
-
architecture str of mms_dp_block_select is
-
constant c_field_arr : t_common_field_arr(1 downto 0) := ( (field_name_pad("index_hi"), "RW", 32, field_default(g_index_hi) ),
(field_name_pad("index_lo"), "RW", 32, field_default(g_index_lo) ));
@@ -71,9 +69,7 @@ architecture str of mms_dp_block_select is
signal index_lo : natural;
signal index_hi : natural;
-
begin
-
-- Use same control for all streams
u_mm_fields: entity mm_lib.mm_fields
generic map(
@@ -119,4 +115,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
index 564443cdaae03cb70bb938fae6ef74b5ba09fdc5..fd265dbd4009b7acff0a4d6d6da2de9065916e45 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_align.vhd
@@ -59,14 +59,10 @@ entity mms_dp_bsn_align is
);
end mms_dp_bsn_align;
-
architecture str of mms_dp_bsn_align is
-
signal en_evt : std_logic;
signal en_arr : std_logic_vector(g_nof_input - 1 downto 0);
-
begin
-
u_align : entity work.dp_bsn_align
generic map(
g_block_size => g_block_size,
@@ -111,6 +107,4 @@ begin
out_en_evt => en_evt,
out_en_arr => en_arr
);
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
index a9f4549ae4b31875efc8cbd8d73b3f3e3bed33cd..645f43333ff9b7cb54ce3df380b8ba1a0f318484 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor.vhd
@@ -57,9 +57,7 @@ entity mms_dp_bsn_monitor is
);
end mms_dp_bsn_monitor;
-
architecture str of mms_dp_bsn_monitor is
-
constant c_reg_adr_w : natural := ceil_log2(9);
signal mon_evt_arr : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -81,9 +79,7 @@ architecture str of mms_dp_bsn_monitor is
signal reg_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -97,7 +93,6 @@ begin
);
gen_stream : for i in 0 to g_nof_streams - 1 generate
-
u_reg : entity work.dp_bsn_monitor_reg
generic map (
g_cross_clock_domain => g_cross_clock_domain
@@ -162,8 +157,6 @@ begin
mon_bsn_first => mon_bsn_first_arr(i),
mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt_arr(i)
);
-
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
index d99687e5078098791c55ca8c2742ee7cad549dda..5ba8560094d70960cc11046750eb30bdc7120eeb 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_monitor_v2.vhd
@@ -59,9 +59,7 @@ entity mms_dp_bsn_monitor_v2 is
);
end mms_dp_bsn_monitor_v2;
-
architecture str of mms_dp_bsn_monitor_v2 is
-
constant c_reg_adr_w : natural := c_dp_bsn_monitor_v2_reg_adr_w;
signal mon_evt_arr : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -83,9 +81,7 @@ architecture str of mms_dp_bsn_monitor_v2 is
signal reg_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -99,7 +95,6 @@ begin
);
gen_stream : for i in 0 to g_nof_streams - 1 generate
-
u_reg : entity work.dp_bsn_monitor_reg_v2
generic map (
g_cross_clock_domain => g_cross_clock_domain
@@ -159,8 +154,6 @@ begin
mon_nof_valid => mon_nof_valid_arr(i),
mon_latency => mon_latency_arr(i)
);
-
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
index 5a78c9c27b04c28610da10c60991de72d33b9a35..bf03acd736f054fe9f9bdb4dd0f619088f8036d7 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_scheduler.vhd
@@ -51,13 +51,9 @@ entity mms_dp_bsn_scheduler is
);
end mms_dp_bsn_scheduler;
-
architecture str of mms_dp_bsn_scheduler is
-
signal scheduled_bsn : std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
-
begin
-
u_mm_reg : entity work.dp_bsn_scheduler_reg
generic map (
g_cross_clock_domain => g_cross_clock_domain
@@ -91,6 +87,4 @@ begin
snk_in => snk_in,
trigger_out => trigger_out
);
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
index 7cbfb893d107f8f89ba2df3a44d8d2d90acd7fcb..9b7f13a519d752601ba4c88ebfd145c76e89d837 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source.vhd
@@ -28,7 +28,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mms_dp_bsn_source is
generic (
g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
@@ -53,9 +52,7 @@ entity mms_dp_bsn_source is
);
end mms_dp_bsn_source;
-
architecture str of mms_dp_bsn_source is
-
signal dp_on : std_logic;
signal dp_on_pps : std_logic;
signal nof_block_per_sync : std_logic_vector(c_word_w - 1 downto 0);
@@ -66,9 +63,7 @@ architecture str of mms_dp_bsn_source is
signal dp_on_status : std_logic;
signal capture_bsn : std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
-
begin
-
bs_sosi <= i_bs_sosi;
u_mm_reg : entity work.dp_bsn_source_reg
@@ -119,6 +114,4 @@ begin
--capture_bsn <= i_bs_sosi.bsn; -- capture current BSN
--capture_bsn <= i_bs_sosi.bsn WHEN rising_edge(dp_clk) AND dp_pps='1'; -- capture BSN at external PPS
capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1'; -- capture BSN at internal sync
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
index 8aab344a1dc2b515bc487057c2cf48602a64aabd..92388ecf1eaa14e91dc3a24c27d05dd1c1913648 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_bsn_source_v2.vhd
@@ -28,7 +28,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mms_dp_bsn_source_v2 is
generic (
g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
@@ -58,9 +57,7 @@ entity mms_dp_bsn_source_v2 is
);
end mms_dp_bsn_source_v2;
-
architecture str of mms_dp_bsn_source_v2 is
-
signal dp_on : std_logic;
signal dp_on_pps : std_logic;
signal nof_clk_per_sync : std_logic_vector(c_word_w - 1 downto 0);
@@ -72,9 +69,7 @@ architecture str of mms_dp_bsn_source_v2 is
signal dp_on_status : std_logic;
signal capture_bsn : std_logic_vector(g_bsn_w - 1 downto 0) := (others => '0');
-
begin
-
bs_sosi <= i_bs_sosi;
bs_nof_clk_per_sync <= nof_clk_per_sync;
@@ -128,6 +123,4 @@ begin
);
capture_bsn <= i_bs_sosi.bsn when rising_edge(dp_clk) and i_bs_sosi.sync = '1'; -- capture BSN at internal sync
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
index a038a376b69b1f53f858fa38e575f95e033c6928..4cc0b97ba5c903ee48d33521efb305e9d000fda2 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_fill.vhd
@@ -80,17 +80,13 @@ entity mms_dp_fifo_fill is
);
end mms_dp_fifo_fill;
-
architecture str of mms_dp_fifo_fill is
-
constant c_usedw_w : natural := ceil_log2(largest(g_fifo_size, g_fifo_fill + g_fifo_af_margin + 2));
signal fifo_usedw_reg : std_logic_vector(g_nof_streams * c_word_w - 1 downto 0) := (others => '0');
signal wr_ful_reg : std_logic_vector(g_nof_streams - 1 downto 0);
signal rd_emp_reg : std_logic_vector(g_nof_streams - 1 downto 0);
-
begin
-
gen_fifos : for I in 0 to g_nof_streams - 1 generate
dp_fifo_sc : entity work.dp_fifo_fill
generic map (
@@ -148,5 +144,4 @@ begin
rd_emp => rd_emp_reg,
wr_ful => wr_ful_reg
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
index 45027c7c90be062f8a404aba02dede1f09b99bbc..8298bcacd57667b2e9c8f5eabcc68edbe367e7bb 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_from_mm.vhd
@@ -47,16 +47,12 @@ entity mms_dp_fifo_from_mm is
);
end mms_dp_fifo_from_mm;
-
architecture str of mms_dp_fifo_from_mm is
-
signal mm_wr_usedw : std_logic_vector(c_word_w - 1 downto 0);
signal mm_wr_availw : std_logic_vector(c_word_w - 1 downto 0);
signal mm_wr_data : std_logic_vector(c_word_w - 1 downto 0);
signal mm_wr : std_logic;
-
begin
-
u_dp_fifo_from_mm : entity dp_lib.dp_fifo_from_mm
generic map(
g_fifo_size => g_wr_fifo_depth
@@ -88,6 +84,4 @@ begin
mm_wr_data <= data_mosi.wrdata(c_word_w - 1 downto 0);
mm_wr <= data_mosi.wr;
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
index 7d5c3baf6a1ce7c4d51043018f9c315e0d0e6247..982363aafe4d003065908446d703ce473d85c329 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_fifo_to_mm.vhd
@@ -49,16 +49,12 @@ entity mms_dp_fifo_to_mm is
);
end mms_dp_fifo_to_mm;
-
architecture str of mms_dp_fifo_to_mm is
-
signal mm_rd_usedw : std_logic_vector(c_word_w - 1 downto 0);
signal mm_rd_data : std_logic_vector(c_word_w - 1 downto 0);
signal mm_rd_val : std_logic;
signal mm_rd : std_logic;
-
begin
-
u_dp_fifo_to_mm : entity dp_lib.dp_fifo_to_mm
generic map(
g_fifo_size => g_rd_fifo_depth
@@ -91,6 +87,4 @@ begin
data_miso.rddata(c_word_w - 1 downto 0) <= mm_rd_data;
data_miso.rdval <= mm_rd_val;
mm_rd <= data_mosi.rd;
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
index 271f59d2e71e8181d8c1798c460ca524b6b2ffe2..78ef7e85f096233c9e3db7bf78bfa5ab55ca2fad 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel.vhd
@@ -38,7 +38,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mms_dp_force_data_parallel is
generic (
g_dat_w : natural := 32; -- must be <= 32 to fit INTEGER range
@@ -74,7 +73,6 @@ entity mms_dp_force_data_parallel is
end mms_dp_force_data_parallel;
architecture str of mms_dp_force_data_parallel is
-
-- TYPE t_c_mem IS RECORD
-- latency : NATURAL; -- read latency
-- adr_w : NATURAL;
@@ -92,9 +90,7 @@ architecture str of mms_dp_force_data_parallel is
signal force_data : integer := 0; -- used for sosi.data
signal force_re : integer := 0; -- used for sosi.re
signal force_im : integer := 0; -- used for sosi.im
-
begin
-
-- wires
force_en <= reg_force_data_wr(0);
reg_force_data_rd(0) <= reg_force_data_wr(0); -- other bits are not used and will read '0'
@@ -162,4 +158,3 @@ begin
src_out => src_out
);
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
index 04a13556ca56353bb4a2c791ec6ab7a5a8aee49c..405a23ba8e716ff027a88e514b2db030e8adfbbe 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_parallel_arr.vhd
@@ -39,7 +39,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mms_dp_force_data_parallel_arr is
generic (
g_nof_streams : natural := 1;
@@ -75,16 +74,12 @@ entity mms_dp_force_data_parallel_arr is
);
end mms_dp_force_data_parallel_arr;
-
architecture str of mms_dp_force_data_parallel_arr is
-
constant c_mm_reg_adr_w : natural := 2; -- = ceil_log2(c_mm_reg.adr_w), copied from mms_dp_force_data_parallel.vhd
signal reg_force_data_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0) := (others => c_mem_mosi_rst);
signal reg_force_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
u_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -131,4 +126,3 @@ begin
);
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
index 3f19c86b9041fe36b52a04216439f7617de9b8f4..63de286f7c454f9e294ebe2725b020774714f619 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial.vhd
@@ -42,7 +42,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mms_dp_force_data_serial is
generic (
g_dat_w : natural := 32; -- number of bits per force data value, must be <= 32 to fit INTEGER range
@@ -68,7 +67,6 @@ entity mms_dp_force_data_serial is
end mms_dp_force_data_serial;
architecture str of mms_dp_force_data_serial is
-
constant c_index_w : natural := ceil_log2(g_index_period);
-- TYPE t_c_mem IS RECORD
@@ -91,9 +89,7 @@ architecture str of mms_dp_force_data_serial is
signal force_data : integer := 0; -- used for sosi.data
signal force_re : integer := 0; -- used for sosi.re
signal force_im : integer := 0; -- used for sosi.im
-
begin
-
-- write wires
force_en <= reg_force_data_wr(0);
force_value <= reg_force_data_wr(1);
@@ -169,6 +165,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
index a999fcdc8da39ecc7f581447e8303b8cd7d53711..38e1ad0980603a0032a483758b2b3676546ad9ff 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_force_data_serial_arr.vhd
@@ -39,7 +39,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mms_dp_force_data_serial_arr is
generic (
g_nof_streams : natural := 1; -- number of parallel streams
@@ -65,16 +64,12 @@ entity mms_dp_force_data_serial_arr is
);
end mms_dp_force_data_serial_arr;
-
architecture str of mms_dp_force_data_serial_arr is
-
constant c_mm_reg_adr_w : natural := 3; -- = ceil_log2(c_mm_reg.adr_w), copied from mms_dp_force_data_serial.vhd
signal reg_force_data_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0) := (others => c_mem_mosi_rst);
signal reg_force_data_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
begin
-
u_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -112,4 +107,3 @@ begin
);
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
index fe0950141c0fdd71333382efe6de8f96c3b2eab3..cfb48e893704fbe95f331b1cce09c3fc5acb5530 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain.vhd
@@ -33,7 +33,6 @@ use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity mms_dp_gain is
generic (
g_technology : natural := c_tech_select_default;
@@ -78,12 +77,9 @@ entity mms_dp_gain is
);
end mms_dp_gain;
-
architecture str of mms_dp_gain is
-
signal in_sosi_arr : t_dp_sosi_arr(0 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(0 downto 0);
-
begin
-- wires
in_sosi_arr(0) <= in_sosi;
@@ -131,6 +127,4 @@ begin
in_sosi_arr => in_sosi_arr,
out_sosi_arr => out_sosi_arr
);
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
index f338e6da0077c06147505c92abba994ff11b071a..f6915b5ef663b0b58dff63f1d6d0013cbc16f0e6 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
@@ -58,7 +58,6 @@ use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity mms_dp_gain_arr is
generic (
g_technology : natural := c_tech_select_default;
@@ -104,9 +103,7 @@ entity mms_dp_gain_arr is
);
end mms_dp_gain_arr;
-
architecture str of mms_dp_gain_arr is
-
constant c_real_multiply : boolean := g_complex_data = false and g_complex_gain = false;
constant c_real_multiply_latency : natural := g_pipeline_real_mult_input + g_pipeline_real_mult_product + g_pipeline_real_mult_output;
@@ -131,9 +128,7 @@ architecture str of mms_dp_gain_arr is
signal mult_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal pipelined_in_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
reg_gain_re <= i_reg_gain_re;
reg_gain_im <= i_reg_gain_im;
@@ -235,6 +230,7 @@ begin
out_reg => i_reg_gain_im -- readback via ST clock domain
);
end generate gen_complex_gain;
+
-- ELSE: if g_complex_gain=FALSE then use default i_reg_gain_im, which is then typically g_gain_init_im=0 for all streams.
gen_nof_streams : for I in 0 to g_nof_streams - 1 generate
@@ -285,6 +281,4 @@ begin
end generate gen_nof_streams;
end generate gen_complex_multiply;
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
index 3992244b9a525f54c8df1051f54c8614560ef05f..f84253d771ccd9b74043b71ac88abce1dda33a1f 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial.vhd
@@ -33,7 +33,6 @@ use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity mms_dp_gain_serial is
generic (
g_technology : natural := c_tech_select_default;
@@ -76,12 +75,9 @@ entity mms_dp_gain_serial is
);
end mms_dp_gain_serial;
-
architecture str of mms_dp_gain_serial is
-
signal in_sosi_arr : t_dp_sosi_arr(0 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(0 downto 0);
-
begin
-- wires
in_sosi_arr(0) <= in_sosi;
@@ -128,6 +124,4 @@ begin
in_sosi_arr => in_sosi_arr,
out_sosi_arr => out_sosi_arr
);
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
index c3fc8bfb182a659a664d6c08358b94ae239d9c83..e81bb5a6d051448e101a2ab40e71e463b3244cc2 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_gain_serial_arr.vhd
@@ -92,7 +92,6 @@ entity mms_dp_gain_serial_arr is
end mms_dp_gain_serial_arr;
architecture str of mms_dp_gain_serial_arr is
-
constant c_real_multiply : boolean := g_complex_data = false and g_complex_gain = false;
constant c_conjugate : boolean := false;
@@ -142,9 +141,7 @@ architecture str of mms_dp_gain_serial_arr is
signal out_dat_re_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
signal out_dat_im_arr : t_slv_out_dat_arr(g_nof_streams - 1 downto 0);
signal out_val_arr : std_logic_vector(g_nof_streams - 1 downto 0);
-
begin
-
-- pipeline in_sosi_arr to align it with gains_rd_data_arr
u_pipeline_arr : entity work.dp_pipeline_arr
generic map (
@@ -307,7 +304,5 @@ begin
out_sosi_arr(I).bsn <= in_sosi_arr_pipe_ctrl(I).bsn;
end process;
end generate gen_complex_multiply;
-
end generate gen_nof_streams;
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
index d498b85797ebd4e3941278d57c016f554e4898fa..5191eef130c0cbf7c8b564763723026555d413da 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_packet_merge.vhd
@@ -57,9 +57,7 @@ entity mms_dp_packet_merge is
);
end mms_dp_packet_merge;
-
architecture str of mms_dp_packet_merge is
-
constant c_field_arr : t_common_field_arr(0 downto 0) := (0 => ( field_name_pad("nof_pkt"), "RW", ceil_log2(g_nof_pkt + 1), field_default(18) ));
type t_mm_fields_out_arr is array(g_nof_streams - 1 downto 0) of std_logic_vector(field_slv_out_len(c_field_arr) - 1 downto 0);
@@ -70,9 +68,7 @@ architecture str of mms_dp_packet_merge is
signal mm_fields_out_arr : t_mm_fields_out_arr;
signal nof_pkt : t_nof_pkt_arr;
-
begin
-
u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -86,7 +82,6 @@ begin
);
gen_stream : for i in 0 to g_nof_streams - 1 generate
-
u_mm_fields: entity mm_lib.mm_fields
generic map(
g_field_arr => c_field_arr
@@ -119,8 +114,6 @@ begin
src_in => src_in_arr(i),
src_out => src_out_arr(i)
);
-
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
index fa15b23d32e3ce8b9bcd326f8c5c600a61bb089c..47d9371bc9aa81f8bafb3e427e274f85ccaa46eb 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_ram_from_mm.vhd
@@ -47,13 +47,9 @@ entity mms_dp_ram_from_mm is
);
end mms_dp_ram_from_mm;
-
architecture str of mms_dp_ram_from_mm is
-
signal dp_on : std_logic;
-
begin
-
u_dp_ram_from_mm : entity dp_lib.dp_ram_from_mm
generic map(
g_ram_wr_nof_words => g_ram_wr_nof_words,
@@ -92,5 +88,4 @@ begin
dp_on => dp_on
);
-
end str;
diff --git a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
index 75bf826fe24cd8e42d4d166bf87cb060f8624957..37b2b5a73d502da1f556d1c78733a976eae220af 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_scale.vhd
@@ -76,12 +76,10 @@ entity mms_dp_scale is
end mms_dp_scale;
architecture str of mms_dp_scale is
-
constant c_dp_requantize_complex : boolean := g_complex_gain or g_complex_data;
constant c_gain_out_dat_w : natural := g_gain_w + g_in_dat_w - 1; -- -1 to compensate for double sign-bit
signal dp_gain_out_sosi : t_dp_sosi;
-
begin
---------------------------------------------------------------
-- Gain
diff --git a/libraries/base/dp/src/vhdl/mms_dp_split.vhd b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
index a0d091529835903eacc0b25f07702662553ff6c2..ee7ade081fde5e7f57217c5313a7238ff945c635 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_split.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_split.vhd
@@ -56,9 +56,7 @@ entity mms_dp_split is
);
end mms_dp_split;
-
architecture str of mms_dp_split is
-
constant c_reg_adr_w : natural := 1;
signal reg_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
@@ -67,9 +65,7 @@ architecture str of mms_dp_split is
type t_nof_symbols_arr is array(g_nof_streams - 1 downto 0) of std_logic_vector(ceil_log2(g_nof_symbols_max + 1) - 1 downto 0);
signal nof_symbols : t_nof_symbols_arr;
-
begin
-
u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -83,7 +79,6 @@ begin
);
gen_stream : for i in 0 to g_nof_streams - 1 generate
-
out_nof_symbols(i) <= TO_UINT(nof_symbols(i));
u_reg : entity work.dp_split_reg
@@ -121,8 +116,6 @@ begin
src_in_arr => src_in_2arr(i),
src_out_arr => src_out_2arr(i)
);
-
end generate;
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
index 628f50a26aa0c9c4707d427d9c2a74e416abbe03..ad8d312d44271b1ebad5b073a69b28b738348639 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker.vhd
@@ -81,7 +81,6 @@ entity mms_dp_sync_checker is
end mms_dp_sync_checker;
architecture str of mms_dp_sync_checker is
-
-- Define the actual size of the MM slave register
constant c_nof_regs : positive := 2;
constant c_mm_reg : t_c_mem := (latency => 1,
@@ -94,9 +93,7 @@ architecture str of mms_dp_sync_checker is
signal nof_early_syncs : std_logic_vector(c_word_w - 1 downto 0);
signal nof_late_syncs : std_logic_vector(c_word_w - 1 downto 0);
signal reg_rd_arr : std_logic_vector(c_nof_regs - 1 downto 0);
-
begin
-
u_dp_sync_checker : entity work.dp_sync_checker
generic map(
g_nof_blk_per_sync => g_nof_blk_per_sync
@@ -142,7 +139,4 @@ begin
out_reg => OPEN,
out_new => open
);
-
end str;
-
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
index a5f96ef3e16e9812b97d44e3fba94a8938481083..1d6a6bbdefe88010c2d0e35c81db0967b84ede59 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_sync_checker_arr.vhd
@@ -58,17 +58,13 @@ entity mms_dp_sync_checker_arr is
);
end mms_dp_sync_checker_arr;
-
architecture str of mms_dp_sync_checker_arr is
-
constant c_latency : natural := 2;
signal sync_checker_snk_out : t_dp_siso;
signal sync_checker_src_out : t_dp_sosi;
signal pipeline_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
-- Copy flow control from output stream 0 via sync_checker to all input streams, ignore flow control from other output streams
snk_out_arr <= (others => sync_checker_snk_out);
@@ -122,7 +118,4 @@ begin
src_out_arr(i).im <= pipeline_src_out_arr(i).im;
end loop;
end process;
-
end str;
-
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
index 13f6ba742a453a478731f81a5bdfa59d16b5d2a6..8194cddac1c46f57530f88d33649a57edd6a4d1b 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_throttle.vhd
@@ -25,7 +25,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use work.dp_stream_pkg.all;
-
entity mms_dp_throttle is
generic (
g_dc_period : natural := 100;
@@ -49,13 +48,9 @@ entity mms_dp_throttle is
);
end mms_dp_throttle;
-
architecture str of mms_dp_throttle is
-
signal throttle : std_logic_vector(ceil_log2(g_dc_period + 1) - 1 downto 0);
-
begin
-
u_dp_throttle_reg : entity work.dp_throttle_reg
generic map (
g_dc_period => g_dc_period
@@ -91,6 +86,4 @@ begin
throttle => throttle
);
-
end str;
-
diff --git a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
index a12560736e97339000773d02ff30437ecf2899d9..ac9ddc3c2c61bc2adb2aeb61bafddccc6059a8b6 100644
--- a/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
+++ b/libraries/base/dp/src/vhdl/mms_dp_xonoff.vhd
@@ -59,9 +59,7 @@ entity mms_dp_xonoff is
);
end mms_dp_xonoff;
-
architecture str of mms_dp_xonoff is
-
constant c_nof_ctrl_streams : natural := sel_a_b(g_combine_streams, 1, g_nof_streams);
constant c_reg_adr_w : natural := 1;
@@ -71,9 +69,7 @@ architecture str of mms_dp_xonoff is
signal xonoff_reg : std_logic_vector(c_nof_ctrl_streams - 1 downto 0);
signal xonoff_reg_i : std_logic_vector(g_nof_streams - 1 downto 0);
signal src_in_arr_i : t_dp_siso_arr(g_nof_streams - 1 downto 0);
-
begin
-
u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => c_nof_ctrl_streams,
@@ -159,5 +155,3 @@ begin
end generate;
end str;
-
-
diff --git a/libraries/base/dp/tb/vhdl/dp_phy_link.vhd b/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
index e88d9c87c36578c5997962cc64906117101b379a..bf481437ec77e990024c18bfb14bcf12a04f5b5c 100644
--- a/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_phy_link.vhd
@@ -48,11 +48,8 @@ entity dp_phy_link is
);
end dp_phy_link;
-
architecture beh of dp_phy_link is
-
begin
-
out_dat <= transport in_dat after g_latency;
gen_valid : if g_valid_support = true generate
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
index f33e7e29f81c214b00f1cc4beec3dafef50df65c..2df830e9506cd7a143f3bc6129cd843ca2b1edd7 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_arr_recorder.vhd
@@ -62,9 +62,7 @@ entity dp_sosi_arr_recorder is
);
end dp_sosi_arr_recorder;
-
architecture beh of dp_sosi_arr_recorder is
-
constant c_nof_bsn_chars : natural := sel_a_b(g_record_bsn, ceil_div(g_bsn_w, 4), 1);
constant c_nof_data_chars : natural := sel_a_b(g_record_data, ceil_div(g_data_w, 4), 1);
constant c_nof_re_chars : natural := sel_a_b(g_record_re, ceil_div(g_re_w, 4), 1);
@@ -75,9 +73,7 @@ architecture beh of dp_sosi_arr_recorder is
signal record_start : boolean := false;
file record_file : TEXT;
-
begin
-
gen_record_start : if g_wait_for_valid = true generate -- Start recording after valid=1
p_record_start : process(snk_in.valid)
variable v_open_status : file_open_status;
@@ -174,5 +170,4 @@ begin
end if;
end if;
end process;
-
end beh;
diff --git a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
index b337797dae851651c6724777c693b21c6b4fe6dc..4fa5cf10e3490970fbfaea866d6668bc5c5837ea 100644
--- a/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_sosi_recorder.vhd
@@ -78,9 +78,7 @@ entity dp_sosi_recorder is
);
end dp_sosi_recorder;
-
architecture beh of dp_sosi_recorder is
-
constant c_nof_bsn_chars : natural := sel_a_b(g_record_bsn, ceil_div(g_bsn_w, 4), 1);
constant c_nof_data_chars : natural := sel_a_b(g_record_data, ceil_div(g_data_w, 4), 1);
constant c_nof_re_chars : natural := sel_a_b(g_record_re, ceil_div(g_re_w, 4), 1);
@@ -91,9 +89,7 @@ architecture beh of dp_sosi_recorder is
signal record_start : boolean := false;
file record_file : TEXT;
-
begin
-
gen_record_start : if g_wait_for_valid = true generate -- Start recording after valid=1
p_record_start : process(snk_in.valid)
variable v_open_status : file_open_status;
@@ -190,5 +186,4 @@ begin
end if;
end if;
end process;
-
end beh;
diff --git a/libraries/base/dp/tb/vhdl/dp_statistics.vhd b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
index c0e16cf02fb7bd397d4390a19a849c7dc0bc6e41..90c09b5f2448bf0e3d3462be865e6cb8b8766fa3 100644
--- a/libraries/base/dp/tb/vhdl/dp_statistics.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_statistics.vhd
@@ -62,9 +62,7 @@ entity dp_statistics is
);
end dp_statistics;
-
architecture str of dp_statistics is
-
signal packet_count : natural := 0;
signal nxt_packet_count : natural := 0;
@@ -75,9 +73,7 @@ architecture str of dp_statistics is
signal dp_done : std_logic := '0';
signal nxt_dp_done : std_logic;
-
begin
-
-- Make sure tb_end will not cause dp_clk to be stopped before dp_done has
-- been evaluated in p_dp_done_check
tb_end <= dp_done when rising_edge(dp_clk);
@@ -138,5 +134,4 @@ begin
dp_done <= nxt_dp_done;
end if;
end process;
-
end str;
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
index 100854294ca7348c1c0a6157fa94433a34933bcf..2591a2fa72489cc5919f39008c3c547f7a99e185 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_player.vhd
@@ -47,16 +47,12 @@ entity dp_stream_player is
);
end dp_stream_player;
-
architecture beh of dp_stream_player is
-
constant c_nof_chars_per_line : natural := 144;
signal playback_start : boolean := false;
file playback_file : TEXT;
-
begin
-
p_playback_start : process(src_in.xon)
variable v_open_status : file_open_status;
begin
@@ -96,5 +92,4 @@ begin
end if;
end if;
end process;
-
end beh;
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd b/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
index 659ca1a745a0bd480786884341562b218fba7c8c..fe65542bf2fbd85107eb3668b1d835aa1055b805 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_rec_play.vhd
@@ -52,11 +52,8 @@ entity dp_stream_rec_play is
);
end dp_stream_rec_play;
-
architecture str of dp_stream_rec_play is
-
begin
-
gen_pass_through: if g_pass_through = true or g_sim = false generate
snk_out <= src_in;
src_out <= snk_in;
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
index a59de840820dbff363a4ae4af1d3e9ed790b7639..6b507231b2dc1ee37e5e5f5d516b299168c93e7f 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_stimuli.vhd
@@ -40,7 +40,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity dp_stream_stimuli is
generic (
g_instance_nr : natural := 0;
@@ -83,9 +82,7 @@ entity dp_stream_stimuli is
);
end dp_stream_stimuli;
-
architecture str of dp_stream_stimuli is
-
signal random : std_logic_vector(g_random_w - 1 downto 0) := TO_UVEC(g_instance_nr, g_random_w); -- use different initialization to have different random sequences per stream
signal pulse : std_logic;
signal pulse_en : std_logic := '1';
@@ -93,9 +90,7 @@ architecture str of dp_stream_stimuli is
signal stimuli_en : std_logic := '1';
signal src_out_data : std_logic_vector(g_in_dat_w - 1 downto 0);
signal i_src_out : t_dp_sosi;
-
begin
-
src_out <= i_src_out;
------------------------------------------------------------------------------
@@ -200,5 +195,4 @@ begin
-- Map to slv to ease monitoring in wave window
src_out_data <= i_src_out.data(g_in_dat_w - 1 downto 0);
-
end str;
diff --git a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
index 18f1cdcd8726ef559c8933030a96234913f86258..374ccc129dc01a07aa6b38b5c702eddcccabe463 100644
--- a/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
+++ b/libraries/base/dp/tb/vhdl/dp_stream_verify.vhd
@@ -47,7 +47,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity dp_stream_verify is
generic (
g_instance_nr : natural := 0;
@@ -82,9 +81,7 @@ entity dp_stream_verify is
);
end dp_stream_verify;
-
architecture tb of dp_stream_verify is
-
constant c_rl : natural := 1;
constant c_no_dut : boolean := true;
@@ -105,9 +102,7 @@ architecture tb of dp_stream_verify is
signal exp_size : natural;
signal cnt_size : natural;
-
begin
-
snk_out <= i_snk_out;
------------------------------------------------------------------------------
@@ -196,5 +191,4 @@ begin
snk_in_data <= snk_in.data(g_in_dat_w - 1 downto 0);
hold_snk_in_data <= snk_in.data when snk_in.valid = '1';
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
index b26e59d13fadc9bc2557a7d31cb5cfcdc8be5b70..a66fd6e3029ac11a1f05c4d16b57d111bb609fba 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_demux.vhd
@@ -69,9 +69,7 @@ entity tb2_dp_demux is
);
end tb2_dp_demux;
-
architecture tb of tb2_dp_demux is
-
constant c_data_w : natural := 16;
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
@@ -114,9 +112,7 @@ architecture tb of tb2_dp_demux is
signal out_eop : std_logic;
signal hold_out_sop : std_logic;
signal expected_out_data : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -126,7 +122,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse_1);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -139,7 +134,6 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -172,12 +166,10 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
-
-- Verification logistics
verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1'; -- count number of output eop
@@ -195,7 +187,6 @@ begin
out_sop <= out_sosi.sop;
out_eop <= out_sosi.eop;
-
------------------------------------------------------------------------------
-- DUT dp_demux
------------------------------------------------------------------------------
@@ -252,5 +243,4 @@ begin
src_in => out_siso,
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
index 8333435a04fa0d23372973a04a81ff926b65ebdb..de5f5139e019b4afd37b3280ca0e1788e993a306 100644
--- a/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb2_dp_mux.vhd
@@ -58,7 +58,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb2_dp_mux is
generic (
g_in_en : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
@@ -71,9 +70,7 @@ entity tb2_dp_mux is
);
end tb2_dp_mux;
-
architecture tb of tb2_dp_mux is
-
constant c_mode_demux : natural := 0;
constant c_use_channel_lo : boolean := true;
constant c_use_bsn : boolean := true;
@@ -165,9 +162,7 @@ architecture tb of tb2_dp_mux is
signal out_eop : t_ctrl_2arr;
signal hold_out_sop : t_ctrl_2arr;
signal expected_out_data : t_data_2arr;
-
begin
-
tb_end <= vector_and(tb_end_vec);
clk <= (not clk) or tb_end after clk_period / 2;
@@ -179,7 +174,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse_1);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -194,7 +188,6 @@ begin
out_siso_2arr <= (others => (others => out_siso));
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -227,7 +220,6 @@ begin
end generate;
end generate;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -251,7 +243,6 @@ begin
end generate;
end generate;
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -323,7 +314,6 @@ begin
mux_eop <= mux_sosi.eop;
mux_channel <= mux_sosi.channel(c_channel_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- DATA DEMULTIPLEXING
------------------------------------------------------------------------------
@@ -374,5 +364,4 @@ begin
out_eop( I, J) <= out_sosi_2arr(I)(J).eop;
end generate;
end generate;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
index ce92600ab401c13eab7dd864910ee462816be1cc..47b21dc98e8f1775f5560ee234ef8ac435f5a843 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_demux.vhd
@@ -55,9 +55,7 @@ entity tb3_dp_demux is
);
end tb3_dp_demux;
-
architecture tb of tb3_dp_demux is
-
constant c_sel_ctrl_pkt : boolean := true; -- TRUE requires: c_mode_demux = 2 and c_combined_demux = FALSE
constant c_mode_demux : natural := 2;
constant c_use_channel_lo : boolean := false;
@@ -105,9 +103,7 @@ architecture tb of tb3_dp_demux is
signal out_eop : std_logic;
signal hold_out_sop : std_logic;
signal expected_out_data : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -117,7 +113,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse_1);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -130,11 +125,9 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
-
-- Some random stimuli for sel_ctrl
sel_ctrl <= TO_UINT(random_0) mod g_nof_outputs when rising_edge(clk) and unsigned(in_sosi.data(c_data_w - 1 downto 0)) mod 19 = 0 and in_sosi.valid = '1';
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -167,12 +160,10 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
-
-- Verification logistics
verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1'; -- count number of output eop
@@ -190,7 +181,6 @@ begin
out_sop <= out_sosi.sop;
out_eop <= out_sosi.eop;
-
------------------------------------------------------------------------------
-- DUT dp_demux
------------------------------------------------------------------------------
@@ -219,5 +209,4 @@ begin
-- Use same ready stimuli for all outputs to ease verification
out_siso_arr <= (others => out_siso);
out_sosi <= func_dp_sosi_arr_mux(out_sosi_arr);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
index 365c95c0d1823081425f1a66fdd7eb02bf7dc9b4..535656ce91e41885071b00fdc6466233f4bf37f7 100644
--- a/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb3_dp_mux.vhd
@@ -52,9 +52,7 @@ entity tb3_dp_mux is
);
end tb3_dp_mux;
-
architecture tb of tb3_dp_mux is
-
constant c_mode_mux : natural := 2;
constant c_use_channel_lo : boolean := false;
@@ -100,9 +98,7 @@ architecture tb of tb3_dp_mux is
signal out_eop : std_logic;
signal hold_out_sop : std_logic;
signal expected_out_data : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -112,7 +108,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse_1);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -125,11 +120,9 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
-
-- Some random stimuli for sel_ctrl
sel_ctrl <= TO_UINT(random_0) mod g_nof_inputs when rising_edge(clk) and unsigned(in_sosi.data(c_data_w - 1 downto 0)) mod 19 = 0 and in_sosi.valid = '1';
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -170,12 +163,10 @@ begin
-- Use these commented in_sosi_arr to check that indeed all inputs are used by the dp_demux, this will cause errors due to the invalid input at port 2
--in_sosi_arr <= (in_sosi, in_sosi, c_dp_sosi_rst);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
-
-- Verification logistics
verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1'; -- count number of output eop
@@ -193,7 +184,6 @@ begin
out_sop <= out_sosi.sop;
out_eop <= out_sosi.eop;
-
------------------------------------------------------------------------------
-- DUT dp_mux
------------------------------------------------------------------------------
@@ -221,5 +211,4 @@ begin
src_in => out_siso,
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
index 7d3d9319bb381d28894e880d189d9340642b7e59..b8030bfb668188ed5d08feab8ba81c3d93ccd442 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd
@@ -50,7 +50,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_block_from_mm is
generic (
g_data_size : natural := 2;
@@ -60,7 +59,6 @@ entity tb_dp_block_from_mm is
end tb_dp_block_from_mm;
architecture tb of tb_dp_block_from_mm is
-
constant c_nof_blocks : natural := g_step_size / g_data_size;
constant c_ram_data_size : natural := g_nof_data * g_data_size * c_nof_blocks;
constant c_ram_adr_w : natural := ceil_log2(c_ram_data_size);
@@ -103,9 +101,7 @@ architecture tb of tb_dp_block_from_mm is
signal init_done : std_logic := '0';
signal transfer_done : std_logic := '0';
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -273,5 +269,4 @@ begin
rd_dat => ram_rd_dat,
rd_val => ram_rd_val
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
index d6e6335fe56121e7e4b7c42173957f31fb7ef830..0e4fc37681d2d540ac123e6169f513843cc75464 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen.vhd
@@ -35,7 +35,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_block_gen is
generic (
g_use_src_in : boolean := false;
@@ -47,9 +46,7 @@ entity tb_dp_block_gen is
);
end tb_dp_block_gen;
-
architecture tb of tb_dp_block_gen is
-
constant c_rl : natural := 1;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -84,9 +81,7 @@ architecture tb of tb_dp_block_gen is
signal verify_valid : std_logic := '0';
signal verify_sop : std_logic := '0';
signal verify_eop : std_logic := '0';
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -102,7 +97,6 @@ begin
random(random'high) when g_out_ready = e_random else
pulse when g_out_ready = e_pulse;
-
------------------------------------------------------------------------------
-- STIMULI
------------------------------------------------------------------------------
@@ -205,5 +199,4 @@ begin
-- MM control
en => enable
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
index e086efbfa84c117cb43caee8c72c642f6bd77d2b..52b11dd5ce321c0ea9cc66a9cb3fbaa03a870c2b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_gen_valid_arr.vhd
@@ -36,7 +36,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_block_gen_valid_arr is
generic (
g_nof_streams : positive := 1;
@@ -51,9 +50,7 @@ entity tb_dp_block_gen_valid_arr is
);
end tb_dp_block_gen_valid_arr;
-
architecture tb of tb_dp_block_gen_valid_arr is
-
constant c_pulse_period : natural := 5;
constant c_nof_valid_per_sync : natural := g_nof_blk_per_sync * g_nof_data_per_block;
constant c_nof_valid_per_enable : natural := 3 * c_nof_valid_per_sync + 1;
@@ -101,9 +98,7 @@ architecture tb of tb_dp_block_gen_valid_arr is
signal verify_sop : std_logic := '0';
signal verify_eop : std_logic := '0';
signal verify_sync : std_logic := '0';
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -254,6 +249,7 @@ begin
-- verify BSN for the other sop between sync using out_sosi_local
proc_dp_verify_data("BSN", c_local_bsn_max, c_local_bsn_gap, clk, verify_bsn_en, out_sosi_local.sop, out_sosi_local.bsn, prev_out_sosi_local.bsn);
end generate;
+
verify_global_bsn : if g_restore_global_bsn = true generate
-- verify BSN for all sop
proc_dp_verify_data("BSN", clk, verify_bsn_en, out_sosi.sop, out_sosi.bsn, prev_out_sosi.bsn);
@@ -288,5 +284,4 @@ begin
-- MM control
enable => enable
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
index 20a72c57ba3b8ecff038f66eef66c6204c94426b..91d7db77387553a526cad2717875624b73b592fd 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape.vhd
@@ -57,9 +57,7 @@ entity tb_dp_block_reshape is
);
end tb_dp_block_reshape;
-
architecture tb of tb_dp_block_reshape is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -87,9 +85,7 @@ architecture tb of tb_dp_block_reshape is
signal verify_index_arr : t_natural_arr(1 downto 0); -- [1] sop index, [0] valid index
signal pipeline_sosi : t_dp_sosi;
signal pipeline_siso : t_dp_siso := c_dp_siso_rdy;
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -161,7 +157,6 @@ begin
src_index_arr => verify_index_arr -- [1] sop index, [0] valid index
);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -189,5 +184,4 @@ begin
end process;
tb_end <= '0', stimuli_end after (1 + 10 * g_pipeline) * c_clk_period;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
index f2ddb10f0c653835319c5868dfbe4a03c67142b3..d03c07a6ad4d70297f78a745c37894c86b227ce5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_reshape_sync.vhd
@@ -59,9 +59,7 @@ entity tb_dp_block_reshape_sync is
);
end tb_dp_block_reshape_sync;
-
architecture tb of tb_dp_block_reshape_sync is
-
constant c_pipeline : natural := sel_a_b(g_pipeline_src_out + g_pipeline_src_in > 0, 1, 0);
------------------------------------------------------------------------------
@@ -89,9 +87,7 @@ architecture tb of tb_dp_block_reshape_sync is
signal pipeline_dut_siso : t_dp_siso := c_dp_siso_rdy;
signal pipeline_total_sosi : t_dp_sosi;
signal pipeline_total_siso : t_dp_siso := c_dp_siso_rdy;
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -163,7 +159,6 @@ begin
src_in => verify_siso
);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -236,5 +231,4 @@ begin
end process;
tb_end <= '0', stimuli_end after (1 + 10 * c_pipeline) * c_clk_period;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
index 9390dbd1212feb817d782a6b0e8d0c2a4e2c2143..1162980ee84071603c8a4136ccc6a829e737495c 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_select.vhd
@@ -55,9 +55,7 @@ entity tb_dp_block_select is
);
end tb_dp_block_select;
-
architecture tb of tb_dp_block_select is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -82,9 +80,7 @@ architecture tb of tb_dp_block_select is
signal reference_sosi : t_dp_sosi;
signal reference_siso : t_dp_siso := c_dp_siso_rdy;
signal sync_sosi : t_dp_sosi;
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -139,7 +135,6 @@ begin
src_out => verify_sosi
);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -221,5 +216,4 @@ begin
end process;
tb_end <= '0', stimuli_end after (1 + 10 * g_dut_pipeline) * c_clk_period;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
index b3b2baea765aece15de1c716afc2dda6036975fc..9ec17af29ee826356a73a2f2736357718c22de97 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_bsn_at_sync.vhd
@@ -50,9 +50,7 @@ entity tb_dp_block_validate_bsn_at_sync is
);
end tb_dp_block_validate_bsn_at_sync;
-
architecture tb of tb_dp_block_validate_bsn_at_sync is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -91,7 +89,6 @@ architecture tb of tb_dp_block_validate_bsn_at_sync is
signal reg_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_miso : t_mem_miso := c_mem_miso_rst;
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -169,7 +166,6 @@ begin
reg_miso => reg_miso
);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -235,5 +231,4 @@ begin
tb_end <= '1';
wait;
end process;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
index e5c9a0f944dff2c070ffead61404aea72968a52e..d6ba2d4592ef9ae9e0a91591e71bab83ad553479 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_channel.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright 2021
@@ -52,9 +51,7 @@ entity tb_dp_block_validate_channel is
);
end tb_dp_block_validate_channel;
-
architecture tb of tb_dp_block_validate_channel is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -77,7 +74,6 @@ architecture tb of tb_dp_block_validate_channel is
signal reference_sosi : t_dp_sosi;
signal reference_siso : t_dp_siso := c_dp_siso_rdy;
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -128,7 +124,6 @@ begin
remove_channel => TO_UVEC(g_remove_channel, 32)
);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -194,5 +189,4 @@ begin
end process;
tb_end <= '0', stimuli_end after (1 + 10 * c_dut_pipeline) * c_dp_clk_period;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
index 235e95b15b3aad1d6c80ba0ad25827e2eb72ab99..fd24928a064a105a47c92b0df9334a648f853af9 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_err.vhd
@@ -56,9 +56,7 @@ entity tb_dp_block_validate_err is
);
end tb_dp_block_validate_err;
-
architecture tb of tb_dp_block_validate_err is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -100,9 +98,7 @@ architecture tb of tb_dp_block_validate_err is
signal rd_blk_cnt : natural;
signal rd_discarded_cnt : natural;
signal rd_err_cnt_arr : t_natural_arr(g_nof_err_counts - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -176,7 +172,6 @@ begin
reg_miso => reg_miso
);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -277,5 +272,4 @@ begin
tb_end <= '1';
wait;
end process;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
index 5ae417b6fbf4f7eb220593e63d0e81205180b097..2ecc70415eef47ed08d8590555499cf4b2c6cf64 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_block_validate_length.vhd
@@ -47,9 +47,7 @@ entity tb_dp_block_validate_length is
);
end tb_dp_block_validate_length;
-
architecture tb of tb_dp_block_validate_length is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -74,9 +72,7 @@ architecture tb of tb_dp_block_validate_length is
signal reference_cnt : natural;
signal reference_sosi : t_dp_sosi;
signal reference_siso : t_dp_siso := c_dp_siso_rdy;
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -128,7 +124,6 @@ begin
src_out => verify_sosi
);
-
------------------------------------------------------------------------------
-- Verification
------------------------------------------------------------------------------
@@ -198,5 +193,4 @@ begin
end process;
tb_end <= '0', stimuli_end after (1 + 10 * c_dut_pipeline) * c_clk_period;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
index 9f775c733bde5398f6d5c2892e5d19a0b591a5af..5b799b6b68ef81521aa853c858c3d117555e1925 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align.vhd
@@ -32,7 +32,6 @@
-- BSN alignment thanks to verify_dis_arr these cases are also verified
-- automatically.
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -42,7 +41,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_bsn_align is
generic (
g_block_size : natural := 11;
@@ -56,9 +54,7 @@ entity tb_dp_bsn_align is
);
end tb_dp_bsn_align;
-
architecture tb of tb_dp_bsn_align is
-
constant c_rl : natural := 1;
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -145,9 +141,7 @@ architecture tb of tb_dp_bsn_align is
signal bsn_event_ack : std_logic;
signal in_en_event : std_logic := '0'; -- pulse '1' indicates that the input enables in in_en_arr have been updated
signal in_en_arr : std_logic_vector(g_nof_input - 1 downto 0) := (others => '1'); -- default all inputs are enabled
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -155,7 +149,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -407,7 +400,6 @@ begin
proc_dp_verify_value(e_equal, clk, verify_done_arr(I), expected_out_bsn(I), prev_out_bsn(I));
end generate;
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -434,5 +426,4 @@ begin
in_en_evt => in_en_event,
in_en_arr => in_en_arr
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
index 2bf2549ee0f2486c7ade97b5f9b1f6ca66c46e36..c6db289f9ed18f783f7200c0011a250f934233b7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_align_v2.vhd
@@ -81,7 +81,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_bsn_align_v2 is
generic (
-- DUT
@@ -110,9 +109,7 @@ entity tb_dp_bsn_align_v2 is
);
end tb_dp_bsn_align_v2;
-
architecture tb of tb_dp_bsn_align_v2 is
-
constant c_rl : natural := 1;
constant c_data_w : natural := 16;
@@ -263,9 +260,7 @@ architecture tb of tb_dp_bsn_align_v2 is
signal dbg_verify_bsn_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- '1' when bsn in all streams is verified
signal dbg_verify_no_lost_flag_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- '1' when lost data flag = 0 is verified
signal dbg_verify_lost_flag_arr : std_logic_vector(g_nof_streams - 1 downto 0) := (others => '0'); -- '1' when lost data flag = 1 is verified
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -366,7 +361,6 @@ begin
end if;
end process;
-
-- Use tb_state to view tb progress in Wave window
restart_cnt <= restart_cnt_arr(0);
@@ -666,5 +660,4 @@ begin
out_sosi_arr <= nxt_r.out_sosi_arr;
end generate;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
index e4b19609beb81c0a50fa038aa96ca266c1f389e6..2003d4327fcff14a6b85e468cb94ad4f94db4e84 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor.vhd
@@ -36,7 +36,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_bsn_monitor is
generic (
g_in_en : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -44,9 +43,7 @@ entity tb_dp_bsn_monitor is
);
end tb_dp_bsn_monitor;
-
architecture tb of tb_dp_bsn_monitor is
-
constant c_rl : natural := 1;
constant c_data_w : natural := 16;
constant c_data_init : integer := 0;
@@ -112,9 +109,7 @@ architecture tb of tb_dp_bsn_monitor is
signal expected_nof_sop : std_logic_vector(c_word_w - 1 downto 0);
signal expected_nof_err : std_logic_vector(c_word_w - 1 downto 0);
signal expected_nof_valid : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -122,7 +117,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
-
------------------------------------------------------------------------------
-- SOSI DATA GENERATION
------------------------------------------------------------------------------
@@ -273,7 +267,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -297,7 +290,6 @@ begin
in_sop <= in_sosi.sop;
in_eop <= in_sosi.eop;
-
------------------------------------------------------------------------------
-- MONITOR VERIFICATION
------------------------------------------------------------------------------
@@ -307,7 +299,6 @@ begin
proc_dp_verify_value(e_equal, clk, verify_done, expected_nof_err, mon_nof_err);
proc_dp_verify_value(e_equal, clk, verify_done, expected_nof_valid, mon_nof_valid);
-
------------------------------------------------------------------------------
-- DUT dp_bsn_monitor
------------------------------------------------------------------------------
@@ -344,5 +335,4 @@ begin
mon_bsn_first => mon_bsn_first,
mon_bsn_first_cycle_cnt => mon_bsn_first_cycle_cnt
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
index e013906e0ba4fdaf0b4ac2a68751b27eb339325a..8f76b0058e0f43e23babe9cff785b82e7f463c94 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_monitor_v2.vhd
@@ -36,7 +36,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_bsn_monitor_v2 is
generic (
g_in_en : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -44,9 +43,7 @@ entity tb_dp_bsn_monitor_v2 is
);
end tb_dp_bsn_monitor_v2;
-
architecture tb of tb_dp_bsn_monitor_v2 is
-
constant c_rl : natural := 1;
constant c_data_w : natural := 16;
constant c_data_init : integer := 0;
@@ -115,9 +112,7 @@ architecture tb of tb_dp_bsn_monitor_v2 is
signal expected_nof_err : std_logic_vector(c_word_w - 1 downto 0);
signal expected_nof_valid : std_logic_vector(c_word_w - 1 downto 0);
signal expected_latency : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -125,7 +120,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
-
------------------------------------------------------------------------------
-- SOSI DATA GENERATION
------------------------------------------------------------------------------
@@ -272,7 +266,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -296,7 +289,6 @@ begin
in_sop <= in_sosi.sop;
in_eop <= in_sosi.eop;
-
------------------------------------------------------------------------------
-- MONITOR VERIFICATION
------------------------------------------------------------------------------
@@ -307,7 +299,6 @@ begin
proc_dp_verify_value(e_equal, clk, verify_done, expected_nof_valid, mon_nof_valid);
proc_dp_verify_value(e_equal, clk, verify_done, expected_latency, mon_latency);
-
------------------------------------------------------------------------------
-- DUT dp_bsn_monitor_v2
------------------------------------------------------------------------------
@@ -341,5 +332,4 @@ begin
mon_nof_valid => mon_nof_valid,
mon_latency => mon_latency
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
index 1d21b09efd07b84e41acdae13123377150f473bc..77429b4b4f377149a3435a54dc6a1463df928a56 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source.vhd
@@ -38,7 +38,6 @@ entity tb_dp_bsn_source is
end tb_dp_bsn_source;
architecture tb of tb_dp_bsn_source is
-
constant c_clk_period : time := 10 ns;
constant c_block_size : natural := 31;
@@ -71,9 +70,7 @@ architecture tb of tb_dp_bsn_source is
-- Verify
signal verify_sync : std_logic := '1';
signal hold_bs_sop : std_logic;
-
begin
-
-----------------------------------------------------------------------------
-- Stimuli
-----------------------------------------------------------------------------
@@ -142,13 +139,11 @@ begin
proc_common_wait_some_cycles(clk, 1);
pps <= '0';
-
proc_common_wait_some_cycles(clk, 10000);
tb_end <= '1';
wait;
end process;
-
-----------------------------------------------------------------------------
-- Verification
-----------------------------------------------------------------------------
@@ -176,5 +171,4 @@ begin
-- Streaming
src_out => bs_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
index 69c2a55e5be3fc9d565a7d7b07f35b2e64ae2105..d8de93d6138f6fe1a4a6956b3721ea95596ed6c8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_source_v2.vhd
@@ -58,7 +58,6 @@ entity tb_dp_bsn_source_v2 is
end tb_dp_bsn_source_v2;
architecture tb of tb_dp_bsn_source_v2 is
-
-- The nof block per sync interval will be the same after every
-- c_min_nof_pps_interval. The c_gcd is the greatest common divider of
-- g_pps_interval and g_block_size, so g_block_size / c_gcd yields an
@@ -146,9 +145,7 @@ architecture tb of tb_dp_bsn_source_v2 is
signal dbg_nof_blk : natural;
signal dbg_accumulate : natural;
signal dbg_expected_bsn : natural;
-
begin
-
rst <= '1', '0' after c_clk_period * 7;
clk <= (not clk) or tb_end after c_clk_period / 2;
@@ -249,7 +246,6 @@ begin
wait;
end process;
-
-----------------------------------------------------------------------------
-- Verification
-- . Some aspects of bs_sosi are verified multiple times in different ways,
@@ -352,5 +348,4 @@ begin
-- Streaming
src_out => bs_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
index 5165a0f84836575cc5e1f697ef5a1599f5a8f8f7..5a8bde3e8658d01b4f4fe76d577230b2c2f63738 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
@@ -92,7 +92,6 @@ entity tb_dp_bsn_sync_scheduler is
end tb_dp_bsn_sync_scheduler;
architecture tb of tb_dp_bsn_sync_scheduler is
-
constant c_clk_period : time := 10 ns;
constant c_bsn_w : natural := 31;
constant c_dut_latency : natural := 1;
@@ -231,9 +230,7 @@ architecture tb of tb_dp_bsn_sync_scheduler is
proc_common_wait_some_cycles(clk, 1);
ctrl_enable_evt <= '0';
end proc_output_disable;
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -565,7 +562,6 @@ begin
end if;
end process;
-
-----------------------------------------------------------------------------
-- DUT: dp_bsn_sync_scheduler
-----------------------------------------------------------------------------
@@ -597,5 +593,4 @@ begin
out_start_interval => out_start_interval,
out_enable => out_enable
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
index 1db8875e84cf3bca1bb81ffb214a22643ba814d3..9506ca762cb29cc620bc8fca7070245eaa168c8d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_calculate_crc.vhd
@@ -48,9 +48,7 @@ entity tb_dp_calculate_crc is
);
end tb_dp_calculate_crc;
-
architecture tb of tb_dp_calculate_crc is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -74,9 +72,7 @@ architecture tb of tb_dp_calculate_crc is
-- Expected specific value obtained from simulation
signal exp_crc_28 : std_logic_vector(28 - 1 downto 0) := X"ABDE9EB";
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -150,5 +146,4 @@ begin
end process;
tb_end <= '0', stimuli_end after 10 * c_clk_period;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
index d8aeb34095e33f31578688be10f6991de68c8f3f..e4ceabe74ded544ff68ac1da6ed7d0e1ece038e7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat.vhd
@@ -36,9 +36,7 @@ entity tb_dp_concat is
);
end tb_dp_concat;
-
architecture tb of tb_dp_concat is
-
constant c_period : time := 100 ns;
constant c_rl : natural := 1;
@@ -83,9 +81,7 @@ architecture tb of tb_dp_concat is
signal prev_out_data : std_logic_vector(g_data_w - 1 downto 0);
signal expected_data : std_logic_vector(g_data_w - 1 downto 0);
signal hold_out_sop : std_logic;
-
begin
-
-- run 100 us
rst <= '1', '0' after c_period * 7;
@@ -200,5 +196,4 @@ begin
-- Check that the test has ran at all
proc_dp_verify_value(e_at_least, clk, verify_done, expected_data, out_data);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
index a4504c4175f15bca8d42b5c5ce8b2ed192234cf6..aea02918e9685a84717f4ac60a9619278e7919e2 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_concat_field_blk.vhd
@@ -46,7 +46,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_concat_field_blk is
generic (
-- general
@@ -60,9 +59,7 @@ entity tb_dp_concat_field_blk is
);
end tb_dp_concat_field_blk;
-
architecture tb of tb_dp_concat_field_blk is
-
constant c_mm_clk_period : time := 1 ns;
constant c_dp_clk_period : time := 5 ns;
@@ -183,9 +180,7 @@ architecture tb of tb_dp_concat_field_blk is
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
signal verify_snk_in_data : std_logic_vector(g_data_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -230,7 +225,6 @@ begin
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -430,5 +424,4 @@ begin
-- Map to slv to ease monitoring in wave window
stimuli_src_out_data <= stimuli_src_out.data(g_data_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(g_data_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
index 1443301e5acdb569cbddcafc36fa928ff6bc0088..50c0401ffe35f78b823caac59d9754c36cfe1961 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter.vhd
@@ -57,9 +57,7 @@ entity tb_dp_counter is
);
end tb_dp_counter;
-
architecture tb of tb_dp_counter is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -114,10 +112,7 @@ architecture tb of tb_dp_counter is
signal in_en : std_logic := '0';
signal out_ready : std_logic := '0';
-
-
begin
-
------------------------------------------------------------------------------
-- Flow control
------------------------------------------------------------------------------
@@ -220,5 +215,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
index 2e20614d261b5cbf1899d2ddaf0b6dc9aca2ba5f..f9ff61dc0cde12b083755783d457d3e0a4726a7e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_func.vhd
@@ -56,9 +56,7 @@ entity tb_dp_counter_func is
);
end tb_dp_counter_func;
-
architecture tb of tb_dp_counter_func is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -93,9 +91,7 @@ architecture tb of tb_dp_counter_func is
type t_count_arr is array(g_nof_counters - 1 downto 0) of natural;
signal tb_count_arr : t_count_arr := (others => 0);
signal tb_last_count_arr : t_count_arr := (others => 0);
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -239,7 +235,6 @@ architecture tb of tb_dp_counter_func is
end if;
end process;
-
tb_last_count_arr <= tb_count_arr when rising_edge(clk);
gen_tb_count_arr : for i in 0 to g_nof_counters - 1 generate
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
index b78741a4631a1f9f0b1c41ddf11a0932074b7ada..0d79d8e8f69e8bfae23a695169653267af9d8078 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_counter_offset.vhd
@@ -58,9 +58,7 @@ entity tb_dp_counter_offset is
);
end tb_dp_counter_offset;
-
architecture tb of tb_dp_counter_offset is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -117,9 +115,7 @@ architecture tb of tb_dp_counter_offset is
signal out_ready : std_logic := '0';
signal count_offset_in_arr : t_nat_natural_arr(g_nof_counters - 1 downto 0) := (others => 0);
-
begin
-
------------------------------------------------------------------------------
-- Flow control
------------------------------------------------------------------------------
@@ -224,5 +220,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
index db0399479cfbe5d9adba43938d6a8ef60ca1efa0..033d1fe07974c6468c04f7896a1148591d17e9c2 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave.vhd
@@ -45,7 +45,6 @@ entity tb_dp_deinterleave is
end;
architecture tb of tb_dp_deinterleave is
-
type t_dsp_data_arr is array (integer range <>) of std_logic_vector(g_dat_w / 2 - 1 downto 0);
type t_data_arr is array (integer range <>) of std_logic_vector(g_dat_w - 1 downto 0);
type t_val_arr is array (integer range <>) of std_logic;
@@ -83,9 +82,7 @@ architecture tb of tb_dp_deinterleave is
signal out_re_arr : t_dsp_data_arr(g_nof_out - 1 downto 0);
signal out_im_arr : t_dsp_data_arr(g_nof_out - 1 downto 0);
signal out_val_arr : t_val_arr(g_nof_out - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Standard TB clocking, RST and control
-----------------------------------------------------------------------------
@@ -132,7 +129,6 @@ begin
src_out_arr => src_out_arr
);
-
-----------------------------------------------------------------------------
-- Wave window monitor
-----------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
index 2eeac9a7e2acf55e3719c03f1c33c5e1c72cda23..9d28335701b636c9b8b312b85bd018a63ecb8759 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_interleave_to_one.vhd
@@ -65,9 +65,7 @@ entity tb_dp_deinterleave_interleave_to_one is
);
end tb_dp_deinterleave_interleave_to_one;
-
architecture tb of tb_dp_deinterleave_interleave_to_one is
-
constant c_flow_control_verify : t_dp_flow_control_enum := e_active;
constant c_pipeline : natural := 1; -- 0 for combinatorial, > 0 for registers
@@ -135,9 +133,7 @@ architecture tb of tb_dp_deinterleave_interleave_to_one is
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
signal verify_snk_in_data : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -329,5 +325,4 @@ begin
-- Map to slv to ease monitoring in wave window
stimuli_src_out_data <= stimuli_src_out.data(c_data_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(c_data_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
index 0efefa875cddf83c2acc7511b61c5c7dbc57f490..85bdf4243f1a90661baa7591005d9f1f51df3cd9 100755
--- a/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_deinterleave_one_to_n_to_one.vhd
@@ -62,9 +62,7 @@ entity tb_dp_deinterleave_one_to_n_to_one is
);
end tb_dp_deinterleave_one_to_n_to_one;
-
architecture tb of tb_dp_deinterleave_one_to_n_to_one is
-
-- Only verify the sosi data fields when g_pkt_len is an integer multiple of g_nof_streams,
-- the sosi info and control fields are always verified using c_out_pkt_len
constant c_out_pkt_len : natural := ceil_value(g_pkt_len, g_nof_streams);
@@ -127,9 +125,7 @@ architecture tb of tb_dp_deinterleave_one_to_n_to_one is
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
signal verify_snk_in_data : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -176,7 +172,6 @@ begin
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -322,5 +317,4 @@ begin
-- Map to slv to ease monitoring in wave window
stimuli_src_out_data <= stimuli_src_out.data(c_data_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(c_data_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
index bbdf5573bf29ec08b779385174ef16bb56953c40..16b878e5441c78ac0f30b5f18b92ea15c83eb997 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_demux.vhd
@@ -35,9 +35,7 @@ entity tb_dp_demux is
);
end tb_dp_demux;
-
architecture tb of tb_dp_demux is
-
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
@@ -134,9 +132,7 @@ architecture tb of tb_dp_demux is
signal verify_done : std_logic_vector(0 to g_dut_nof_output - 1);
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(5000, c_dp_data_w);
-
begin
-
tb_end <= vector_and(tb_end_vec);
clk <= not clk or tb_end after clk_period / 2;
@@ -196,7 +192,6 @@ begin
proc_dp_verify_value(e_at_least, clk, verify_done(I), exp_data, out_data(I));
end generate;
-
-- map sl, slv to record
p_in : process(in_siso, in_data_vec, in_empty_vec, in_channel_vec, in_val, in_sop, in_eop)
begin
@@ -268,5 +263,4 @@ begin
src_in_arr => demux_siso, -- IN = request from downstream ST sink
src_out_arr => demux_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
index f300446af562eb6823d711b7a863c0ad1e1cdbf5..6fe69179dad03f809521fe4c9c25d49f673c7552 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_distribute.vhd
@@ -71,9 +71,7 @@ entity tb_dp_distribute is
);
end tb_dp_distribute;
-
architecture tb of tb_dp_distribute is
-
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
constant c_frame_len : integer := 10;
@@ -132,9 +130,7 @@ architecture tb of tb_dp_distribute is
signal out_eop : std_logic_vector(0 to g_nof_input - 1);
signal hold_out_sop : std_logic_vector(0 to g_nof_input - 1);
signal expected_out_data : t_data_arr;
-
begin
-
tb_end <= vector_and(tb_end_vec);
clk <= (not clk) or tb_end after clk_period / 2;
@@ -146,7 +142,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse_1);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -162,7 +157,6 @@ begin
out_siso_arr <= (others => out_siso);
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -201,13 +195,11 @@ begin
end process;
end generate;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
gen_verify : for I in 0 to g_nof_input - 1 generate
-
-- Verification logistics
verify_en(I) <= '1' when rising_edge(clk) and out_sosi_arr(I).sop = '1'; -- enable verify after first output sop
count_eop(I) <= count_eop(I) + 1 when rising_edge(clk) and out_sosi_arr(I).eop = '1'; -- count number of output eop
@@ -226,6 +218,7 @@ begin
-- Use at least because there will still be some frames in the FIFO due to the required fill level
proc_dp_verify_value(e_at_least, clk, verify_done(I), expected_out_data(I), prev_out_data(I)); -- Verify that the stimuli have been applied at all
end generate;
+
gen_equal : if g_tx_use_fifo = false and g_tx_use_fifo = false generate
-- Use equal because without FIFOs all frames must come through
proc_dp_verify_value(e_equal, clk, verify_done(I), expected_out_data(I), prev_out_data(I)); -- Verify that the stimuli have been applied at all
@@ -238,10 +231,8 @@ begin
out_val(I) <= out_sosi_arr(I).valid;
out_sop(I) <= out_sosi_arr(I).sop;
out_eop(I) <= out_sosi_arr(I).eop;
-
end generate;
-
------------------------------------------------------------------------------
-- DUT dp_distribute
------------------------------------------------------------------------------
@@ -315,5 +306,4 @@ begin
src_in_arr => out_siso_arr,
src_out_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
index d200c08db47f1dbf32690deb3d28f0fc53fb2bc1..464fd24ca51e27772f1d3b83c3c6d3d085ec2eb5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_dut.vhd
@@ -128,7 +128,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_example_dut is
generic (
-- general
@@ -143,9 +142,7 @@ entity tb_dp_example_dut is
);
end tb_dp_example_dut;
-
architecture tb of tb_dp_example_dut is
-
-- dp_stream_stimuli
constant c_stimuli_pulse_active : natural := 3;
constant c_stimuli_pulse_period : natural := 7;
@@ -192,9 +189,7 @@ architecture tb of tb_dp_example_dut is
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
signal verify_snk_in_data : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -237,7 +232,6 @@ begin
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -334,7 +328,6 @@ begin
dut_src_in <= verify_snk_out;
verify_snk_in <= dut_src_out;
-
------------------------------------------------------------------------------
-- Auxiliary
------------------------------------------------------------------------------
@@ -342,5 +335,4 @@ begin
-- Map to slv to ease monitoring in wave window
stimuli_src_out_data <= stimuli_src_out.data(g_dat_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(g_dat_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
index 296ac0eab6150944df1cb736848bda9594706078..7cf8b884b245a1a100016b9349c80f8aae027225 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_example_no_dut.vhd
@@ -119,7 +119,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_example_no_dut is
generic (
-- general
@@ -134,9 +133,7 @@ entity tb_dp_example_no_dut is
);
end tb_dp_example_no_dut;
-
architecture tb of tb_dp_example_no_dut is
-
constant c_rl : natural := 1;
constant c_no_dut : boolean := true;
@@ -190,9 +187,7 @@ architecture tb of tb_dp_example_no_dut is
signal expected_verify_snk_in : t_dp_sosi;
signal exp_size : natural;
signal cnt_size : natural;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -214,7 +209,6 @@ begin
random_1(random_1'high) when g_flow_control_verify = e_random else
pulse_1 when g_flow_control_verify = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -268,7 +262,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -307,7 +300,6 @@ begin
-- Verify output ready latency
proc_dp_verify_valid(clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -323,14 +315,12 @@ begin
-- DUT function
gen_dut : if c_no_dut = false generate
-
end generate;
-- Connect DUT source output stream to verification
dut_src_in <= verify_snk_out;
verify_snk_in <= dut_src_out;
-
------------------------------------------------------------------------------
-- Auxiliary
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
index aa85d51adbe9c9609f33bbd7d27d876ec3c43728..2c5c009486395e7a4878c2fc6831f797ae1edb3a 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc.vhd
@@ -41,9 +41,7 @@ entity tb_dp_fifo_dc is
);
end tb_dp_fifo_dc;
-
architecture tb of tb_dp_fifo_dc is
-
-- See tb_dp_pkg.vhd for explanation and run time, increase the run time by g_dut_rd_clk_freq/g_dut_wr_clk_freq if g_dut_rd_clk_freq>g_dut_wr_clk_freq
-- DUT
@@ -118,9 +116,7 @@ architecture tb of tb_dp_fifo_dc is
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(19000 / g_dut_wr_clk_freq, c_dp_data_w);
signal usedw : std_logic_vector(ceil_log2(c_dut_fifo_size) - 1 downto 0);
-
begin
-
wr_clk <= not wr_clk or tb_end after g_dut_rd_clk_freq * clk_period / 2;
rd_clk <= not rd_clk or tb_end after g_dut_wr_clk_freq * clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -227,5 +223,4 @@ begin
src_in => out_siso, -- IN = request from downstream ST sink
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
index cfce57389f1da4466b3dde695277e1ed9c62a6fe..5c75f0d420d57874dea2b76072bc5b1309c7d920 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_arr.vhd
@@ -48,9 +48,7 @@ entity tb_dp_fifo_dc_arr is
);
end tb_dp_fifo_dc_arr;
-
architecture tb of tb_dp_fifo_dc_arr is
-
-- See tb_dp_pkg.vhd for explanation and run time, increase the run time by g_dut_rd_clk_freq/g_dut_wr_clk_freq if g_dut_rd_clk_freq>g_dut_wr_clk_freq
-- DUT
@@ -127,9 +125,7 @@ architecture tb of tb_dp_fifo_dc_arr is
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(19000 / g_dut_wr_clk_freq, c_dp_data_w);
signal usedw : std_logic_vector(ceil_log2(c_dut_fifo_size) - 1 downto 0);
-
begin
-
wr_clk <= not wr_clk or tb_end after g_dut_rd_clk_freq * clk_period / 2;
rd_clk <= not rd_clk or tb_end after g_dut_wr_clk_freq * clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -194,6 +190,7 @@ begin
-- map sl, slv to record
in_ready <= in_siso_arr(0).ready; -- SISO
in_aux <= in_sync; -- use sync to test aux data
+
gen_streams : for I in 0 to g_dut_nof_streams - 1 generate
in_sosi_arr(I).data(c_dp_data_w - 1 downto 0) <= in_data; -- SOSI
in_sosi_arr(I).bsn(c_dp_bsn_w - 1 downto 0) <= in_bsn(c_dp_bsn_w - 1 downto 0);
@@ -205,6 +202,7 @@ begin
in_sosi_arr(I).eop <= in_eop;
out_siso_arr(I).ready <= out_ready; -- SISO
end generate;
+
out_data <= out_sosi_arr(0).data(c_dp_data_w - 1 downto 0); -- SOSI
out_bsn(c_dp_bsn_w - 1 downto 0) <= out_sosi_arr(0).bsn(c_dp_bsn_w - 1 downto 0);
out_empty(c_dp_empty_w - 1 downto 0) <= out_sosi_arr(0).empty;
@@ -247,5 +245,4 @@ begin
src_out_arr => out_sosi_arr,
out_aux(0) => out_aux
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
index a3d7ed7ebd1029acd52c4da095fb0dc2eab895f7..58dfd08b6b86182b08636a4040a432cc9bccb9f0 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_dc_mixed_widths.vhd
@@ -42,9 +42,7 @@ entity tb_dp_fifo_dc_mixed_widths is
);
end tb_dp_fifo_dc_mixed_widths;
-
architecture tb of tb_dp_fifo_dc_mixed_widths is
-
constant c_rl : natural := 1;
constant c_wr_fifo_size : natural := 128; -- use same nof words for both n2w FIFO and w2n FIFO, hence the w2n FIFO is bigger
constant c_long_frame_len : natural := c_wr_fifo_size * 5;
@@ -102,9 +100,7 @@ architecture tb of tb_dp_fifo_dc_mixed_widths is
signal expected_about : std_logic_vector(g_narrow_w - 1 downto 0);
signal expected_exact : std_logic_vector(g_narrow_w - 1 downto 0);
-
begin
-
narrow_rst <= '1', '0' after g_narrow_period * 7;
narrow_clk <= not narrow_clk or tb_end after g_narrow_period / 2;
@@ -120,6 +116,7 @@ begin
in_en <= '1';
out_siso.ready <= out_en;
end generate;
+
gen_random_flow : if g_random_flow = true generate
in_en <= random_0(random_0'high);
out_siso.ready <= random_1(random_1'high) and out_en;
@@ -220,7 +217,6 @@ begin
src_out => wide_sosi
);
-
-- Adapt for wide to narrow FIFO input RL=1 in case g_read_rl=0
u_rl : entity work.dp_latency_adapter
generic map (
@@ -238,7 +234,6 @@ begin
src_out => wide_sosi_rl1
);
-
-- Wide to narrow FIFO
u_dut_w2n : entity work.dp_fifo_dc_mixed_widths
generic map (
@@ -276,7 +271,6 @@ begin
proc_dp_verify_valid(g_read_rl, wide_clk, verify_wide_en, wide_siso.ready, prev_wide_ready, wide_sosi.valid);
proc_dp_verify_gap_invalid(wide_clk, wide_sosi.valid, wide_sosi.sop, wide_sosi.eop, wide_gap);
-
-- 2) Verify final narrow data
-- . Note that verify per frame can only verify frames that are longer than 1 data word
@@ -290,6 +284,7 @@ begin
-- . Check that the test has ran at all
proc_dp_verify_value(e_at_least, narrow_clk, verify_done, expected_about, prev_out_data); -- for unframed data we know at least what to expect
+
gen_exact : if g_use_ctrl = true generate
proc_dp_verify_value(e_equal, narrow_clk, verify_done, expected_exact, prev_out_data); -- for framed data we know exactly what to expect
end generate;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
index 2678bf711eaae65fc2c1c7d31272e6dc05f3e924..d6ad771c2a194788d7163a489de69e9fd2f48d52 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill.vhd
@@ -54,9 +54,7 @@ entity tb_dp_fifo_fill is
);
end tb_dp_fifo_fill;
-
architecture tb of tb_dp_fifo_fill is
-
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
@@ -130,9 +128,7 @@ architecture tb of tb_dp_fifo_fill is
signal verify_done : std_logic;
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(15000, c_dp_data_w);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -162,6 +158,7 @@ begin
gen_verify_data : if c_verify_data_en = true generate
proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
end generate;
+
assert c_verify_data_en = true report "proc_dp_verify_data() can not verify the data if it is not continuous" severity WARNING;
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
@@ -238,5 +235,4 @@ begin
src_in => out_siso, -- IN = request from downstream ST sink
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
index b2ce169ff9463cac24202c5c6cb4f4b5c6385302..aeceefb25f8bc843758debbb6a078bbd2bd24980 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_eop.vhd
@@ -62,9 +62,7 @@ entity tb_dp_fifo_fill_eop is
);
end tb_dp_fifo_fill_eop;
-
architecture tb of tb_dp_fifo_fill_eop is
-
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
@@ -147,9 +145,7 @@ architecture tb of tb_dp_fifo_fill_eop is
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(15000, c_dp_data_w);
signal gap_en : std_logic := '0';
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -164,6 +160,7 @@ begin
proc_dp_tx_ctrl(c_tx_offset_sync, c_tx_period_sync, in_data, in_val, in_sync);
proc_dp_tx_ctrl(c_tx_offset_sop, c_tx_period_sop, in_data, in_val, in_sop);
proc_dp_tx_ctrl(c_tx_offset_eop, c_tx_period_eop, in_data, in_val, in_eop);
+
gen_gap: if g_dut_use_gap generate
proc_dp_tx_ctrl(c_tx_offset_gap, c_tx_period_gap, in_data, in_val, gap_en);
end generate;
@@ -191,6 +188,7 @@ begin
-- Stimuli control
proc_dp_count_en(rst, clk, sync, lfsr1, state, verify_done, tb_done, cnt_en);
+
gen_random_ctrl : if g_dut_use_random_ctrl generate
proc_dp_out_ready(rst, clk, sync, lfsr2, out_ready);
end generate;
@@ -201,6 +199,7 @@ begin
gen_verify_data : if c_verify_data_en = true generate
proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
end generate;
+
assert c_verify_data_en = true report "proc_dp_verify_data() can not verify the data if it is not continuous" severity WARNING;
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
@@ -234,7 +233,6 @@ begin
if g_dut_use_rd_fill_32b = true then
rd_fill_32b <= TO_UVEC(g_dut_fifo_size / 5, c_word_w);
end if;
-
end if;
proc_common_wait_until_high(clk, tb_done);
@@ -298,5 +296,4 @@ begin
src_in => out_siso, -- IN = request from downstream ST sink
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
index 4f38f193048082a2cf808208170a7c9d266b6eff..bd1ccdaaa0c07ae157a96cc4a067bcf8cd611fcb 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_fill_sc.vhd
@@ -56,9 +56,7 @@ entity tb_dp_fifo_fill_sc is
);
end tb_dp_fifo_fill_sc;
-
architecture tb of tb_dp_fifo_fill_sc is
-
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
@@ -136,9 +134,7 @@ architecture tb of tb_dp_fifo_fill_sc is
signal tb_done : std_logic;
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(15000, c_dp_data_w);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -168,6 +164,7 @@ begin
gen_verify_data : if c_verify_data_en = true generate
proc_dp_verify_data("out_sosi.data", c_rx_latency, clk, verify_en, out_ready, out_val, out_data, prev_out_data);
end generate;
+
assert c_verify_data_en = true report "proc_dp_verify_data() can not verify the data if it is not continuous" severity WARNING;
proc_dp_verify_valid(c_rx_latency, clk, verify_en, out_ready, prev_out_ready, out_val);
@@ -270,5 +267,4 @@ begin
src_in => out_siso, -- IN = request from downstream ST sink
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
index 2b872e5856867710bff5d065f608140d1350999f..aea359818b59eaab5fd1f1bcd8211b06d3c54fd4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_info.vhd
@@ -58,9 +58,7 @@ entity tb_dp_fifo_info is
);
end tb_dp_fifo_info;
-
architecture tb of tb_dp_fifo_info is
-
constant c_rl : natural := 1; -- fixed
constant c_data_w : natural := 16;
@@ -117,9 +115,7 @@ architecture tb of tb_dp_fifo_info is
signal verify_done_error : std_logic := '0';
signal expected_verify_snk_in : t_dp_sosi;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -141,7 +137,6 @@ begin
random_1(random_1'high) when g_flow_control_verify = e_random else
pulse_1 when g_flow_control_verify = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -280,5 +275,4 @@ begin
-- Verify output ready latency
proc_dp_verify_valid(c_rl, clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out_ready, verify_snk_in.valid);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
index 351fd26ab58f40e66de35e46c5e82c85cd416389..0597d8e0dc06249db6a37dd459e363922ab17a03 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_sc.vhd
@@ -42,9 +42,7 @@ entity tb_dp_fifo_sc is
);
end tb_dp_fifo_sc;
-
architecture tb of tb_dp_fifo_sc is
-
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
@@ -117,9 +115,7 @@ architecture tb of tb_dp_fifo_sc is
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(19000, c_dp_data_w);
signal usedw : std_logic_vector(ceil_log2(g_dut_fifo_size) - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -224,5 +220,4 @@ begin
src_in => out_siso, -- IN = request from downstream ST sink
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
index fa7c604eeed7a033cedcc4a8a82193aec04eb660..141127e58cb195aa67381dc8d13cf96e47d40e12 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_to_mm.vhd
@@ -49,12 +49,10 @@ use work.tb_dp_pkg.all;
-- to run as long as necessary so that wr_availw_is_0='1' and
-- rd_usedw_is_0='1' have occurred.
-
entity tb_dp_fifo_to_mm is
end tb_dp_fifo_to_mm;
architecture tb of tb_dp_fifo_to_mm is
-
constant clk_period : time := 10 ns;
constant c_run_time : natural := 9000;
@@ -105,9 +103,7 @@ architecture tb of tb_dp_fifo_to_mm is
signal prev_mm_rddata : std_logic_vector(c_mm_data_w - 1 downto 0);
signal expected_mm_rddata : std_logic_vector(c_mm_data_w - 1 downto 0) := (others => '0');
-
begin
-
-- as 10
-- run 10 ms
@@ -282,5 +278,4 @@ begin
-- Verify that the read data is incrementing data
mm_rdval <= mm_rd when rising_edge(clk);
proc_common_verify_data(c_rl, clk, verify_en, ready, mm_rdval, mm_rddata, prev_mm_rddata);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
index cbeb6ede60b47508d15f5ccb5e9ff5d05f3f80fe..2c7c60352a14a2f1c1517802ef2d84570db53a80 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_fifo_xonoff.vhd
@@ -95,9 +95,7 @@ entity tb_dp_fifo_xonoff is
);
end tb_dp_fifo_xonoff;
-
architecture tb of tb_dp_fifo_xonoff is
-
constant c_clk_period : time := 5 ns;
constant c_tb_nof_clk_cycles : natural := g_nof_blocks * g_block_size;
@@ -153,9 +151,7 @@ architecture tb of tb_dp_fifo_xonoff is
signal out_fifo_wr_ful : std_logic;
signal out_fifo_usedw : std_logic_vector(ceil_log2(c_out_fifo_size) - 1 downto 0);
signal out_fifo_rd_emp : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -201,6 +197,7 @@ begin
out_en => dp_out_en_arr(I)
);
end generate;
+
no_dp_xonoff : if not g_use_in_xonoff generate
fifo_in_sosi_arr <= bg_sosi_arr;
dp_out_en_arr <= (others => '1');
@@ -283,6 +280,7 @@ begin
out_en => dp_out_en
);
end generate;
+
no_dp_xonoff : if not g_use_out_xonoff generate
fifo_fill_in_sosi <= mux_out_sosi;
mux_out_siso <= fifo_fill_in_siso;
@@ -315,5 +313,4 @@ begin
src_in => out_siso,
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
index 10384668f42e52b69b6d80dbcb252fb47cc2f6d6..bb5e1dce668631c35da92367a168cdf38465c06b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_flush.vhd
@@ -37,7 +37,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_flush is
generic (
g_rl : natural := 0; -- this tb supports ready latency is 0 or 1
@@ -49,9 +48,7 @@ entity tb_dp_flush is
);
end tb_dp_flush;
-
architecture tb of tb_dp_flush is
-
constant c_pulse_active : natural := 1;
constant c_pulse_period : natural := 7;
@@ -108,9 +105,7 @@ architecture tb of tb_dp_flush is
signal reg_mode_flush_en_framed_xoff : std_logic := '0';
signal reg_mode_flush_en : std_logic;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -134,7 +129,6 @@ begin
out_siso.ready <= out_ready when g_rl /= 0 else out_ready and out_sosi.valid; -- request for RL > 0, acknowledge for RL = 0
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -257,7 +251,6 @@ begin
end if;
end process;
-
------------------------------------------------------------------------------
-- DUT : DP_FLUSH
------------------------------------------------------------------------------
@@ -298,5 +291,4 @@ begin
-- Use reg_m is registered m signal to match the register stage in reg_mode_flush_en
reg_m <= m when rising_edge(clk);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
index 591b226ddfcb7efecacc8936cffc9f682b316639..1a752aaa71ad8deac703a7c386a827a560fae434 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_folder.vhd
@@ -37,9 +37,7 @@ use work.tb_dp_pkg.all;
entity tb_dp_folder is
end tb_dp_folder;
-
architecture tb of tb_dp_folder is
-
constant c_nof_inputs : natural := 1;
constant c_nof_unfolds : natural := 1; -- 5 folds = 1->2->4->8->16->32 unfolded streams
constant c_nof_unfolded_streams : natural := c_nof_inputs * pow2(c_nof_unfolds);
@@ -63,9 +61,7 @@ architecture tb of tb_dp_folder is
signal dp_unfolder_snk_in_arr : t_dp_sosi_arr(c_nof_inputs - 1 downto 0);
signal dp_folder_snk_in_arr : t_dp_sosi_arr(c_nof_unfolded_streams - 1 downto 0);
signal dp_folder_src_out_arr : t_dp_sosi_arr(c_nof_inputs - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Clock,reset generation
-----------------------------------------------------------------------------
@@ -124,6 +120,4 @@ begin
snk_in_arr => dp_folder_snk_in_arr,
src_out_arr => dp_folder_src_out_arr
);
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
index 8673515a107bfefd388cb7efaf56639b447ece1f..8b0d02b22bb7ea8f243399277cd8e93dda14e2a5 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_rd.vhd
@@ -27,13 +27,10 @@ use common_lib.common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_frame_rd is
end tb_dp_frame_rd;
-
architecture tb of tb_dp_frame_rd is
-
-- > as 5
-- > run 10 us, at 4335 ns expect Warning: Frame with valid data but no sof.
@@ -141,9 +138,7 @@ architecture tb of tb_dp_frame_rd is
-- gap
for I in 1 to c_gap_length loop wait until rising_edge(clk); end loop;
end proc_frame;
-
begin
-
clk <= not clk after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -258,7 +253,6 @@ begin
out_eof => out_eof
);
-
p_output_stimuli : process
begin
frm_req <= '0';
@@ -294,7 +288,6 @@ begin
end loop;
end process;
-
p_verify : process(clk)
begin
if rising_edge(clk) then
@@ -309,5 +302,4 @@ begin
-- Check that the test has ran at all
proc_dp_verify_value(e_at_least, clk, verify_done, exp_data, out_data);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
index 47bc08630fc35a6a981df27e98862228f50d4a53..3030dbaa28114bd9073add030febfc9be0e991fc 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_frame_scheduler.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use work.dp_stream_pkg.all;
use work.dp_packetizing_pkg.all;
-
entity tb_dp_frame_scheduler is
generic (
g_dut_verify_mux : boolean := true; -- when FALSE verify dp_frame_scheduler else verify dp_mux
@@ -38,7 +37,6 @@ end tb_dp_frame_scheduler;
-- run 12 ms, enough to let mark_in_sof occur at least twice
architecture tb of tb_dp_frame_scheduler is
-
constant c_clk_period : time := 5 ns;
constant c_rst_delay : natural := 4;
constant c_dut_delay : natural := 11;
@@ -203,9 +201,7 @@ architecture tb of tb_dp_frame_scheduler is
end if;
end if;
end proc_cnt;
-
begin
-
------------------------------------------------------------------------------
-- Clock, reset and sync
------------------------------------------------------------------------------
@@ -236,7 +232,6 @@ begin
end if;
end process;
-
------------------------------------------------------------------------------
-- Generate crosslet and beamlet packets, about one per slice
------------------------------------------------------------------------------
@@ -281,7 +276,6 @@ begin
clk);
end process;
-
------------------------------------------------------------------------------
-- DUT : The dp_frame_scheduler
------------------------------------------------------------------------------
@@ -481,5 +475,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd b/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
index c43c39581f2ba70632d4138ae6a14d14decf44c7..45705b5ea188f3ebf05af2bfc14cf766d55a2fb4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_gap.vhd
@@ -31,7 +31,6 @@ entity tb_dp_gap is
end tb_dp_gap;
architecture tb of tb_dp_gap is
-
constant c_clk_period : time := 10 ns;
constant c_dat_w : natural := c_dp_stream_data_w; -- use full SOSI data width to ease viewing in wave window
@@ -54,9 +53,7 @@ architecture tb of tb_dp_gap is
signal prev_ready2 : std_logic_vector(0 downto 0);
signal prev_data1 : std_logic_vector(c_dat_w - 1 downto 0);
signal prev_data2 : std_logic_vector(c_dat_w - 1 downto 0);
-
begin
-
-- Run for 12us
rst <= '1', '0' after c_clk_period * 7;
@@ -151,5 +148,4 @@ begin
src_in => gap_siso,
src_out => gap_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
index 7fff19d325f7396004f6cb9953253070dce4ec68..901fe867b80e92fcc4a8244fcc5a8b6d714009ea 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_hdr_insert_remove.vhd
@@ -42,9 +42,7 @@ entity tb_dp_hdr_insert_remove is
);
end tb_dp_hdr_insert_remove;
-
architecture tb of tb_dp_hdr_insert_remove is
-
-- tb default
constant c_rl : natural := 1;
constant c_pulse_active : natural := 1;
@@ -140,9 +138,7 @@ architecture tb of tb_dp_hdr_insert_remove is
constant c_ram_header_start : std_logic_vector(c_word_w - 1 downto 0) := x"DEADBEEF";
constant c_ram_header_end : std_logic_vector(c_word_w - 1 downto 0) := x"CAFEBABE";
-
begin
-
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * 20;
@@ -167,7 +163,6 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -236,7 +231,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -330,5 +324,4 @@ begin
out_err <= out_sosi.err(in_err'range);
out_sync <= out_sosi.sync;
out_bsn <= out_sosi.bsn(c_bsn_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
index 28a0757a53b3d8a1d1ec4990f9f71f015d4539c7..cb7c1b30aed2a2c3b3e7c93429b7e97b91369b95 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_adapter.vhd
@@ -30,9 +30,7 @@ use work.tb_dp_pkg.all;
entity tb_dp_latency_adapter is
end tb_dp_latency_adapter;
-
architecture tb of tb_dp_latency_adapter is
-
-- See tb_dp_pkg.vhd for explanation and run time
subtype t_dut_range is integer range - 1 to integer'high;
@@ -127,9 +125,7 @@ architecture tb of tb_dp_latency_adapter is
signal verify_done : std_logic;
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(19555, c_dp_data_w);
-
begin
-
-- Use intervals marked by sync to start a new test named by state.
--
-- Under all circumstances the out_data should not mis or duplicate a count
@@ -250,5 +246,4 @@ begin
out_val <= dut_val(c_nof_dut - 1);
out_sop <= dut_sop(c_nof_dut - 1);
out_eop <= dut_eop(c_nof_dut - 1);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
index 7af4073c2a064b4fc2b600759aa844c9d159d062..a0a272ebb63ad809adc286fd1c76455cac57acf7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_latency_fifo.vhd
@@ -49,9 +49,7 @@ entity tb_dp_latency_fifo is
);
end tb_dp_latency_fifo;
-
architecture tb of tb_dp_latency_fifo is
-
constant c_nof_data_per_block : natural := ceil_div(g_nof_symbols_per_block, g_nof_symbols_per_data);
-- tb default
@@ -113,9 +111,7 @@ architecture tb of tb_dp_latency_fifo is
signal out_eop : std_logic;
signal out_gap : std_logic := '1';
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -137,7 +133,6 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -176,7 +171,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -194,7 +188,6 @@ begin
-- . verify that the stimuli have been applied at all
proc_dp_verify_value(e_equal, clk, verify_done, expected_out_data, out_data);
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -233,5 +226,4 @@ begin
out_sop <= out_sosi.sop;
out_eop <= out_sosi.eop;
out_sync <= out_sosi.sync;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
index 951833600660b2ccc0e50734220c5a9e976a27c1..bc34fa7cc535d23e5712b149b74f831293305c4d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_mux.vhd
@@ -42,9 +42,7 @@ entity tb_dp_mux is
);
end tb_dp_mux;
-
architecture tb of tb_dp_mux is
-
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT
@@ -147,9 +145,7 @@ architecture tb of tb_dp_mux is
signal verify_done : std_logic_vector(0 to g_dut_nof_input - 1);
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(1000, c_dp_data_w);
-
begin
-
tb_end <= vector_and(tb_end_vec);
clk <= not clk or tb_end after clk_period / 2;
@@ -211,6 +207,7 @@ begin
gen_verify_empty : if g_dut_use_empty = true generate
proc_dp_verify_other_sosi("empty", INCR_UVEC(out_data(I), c_empty_offset), clk, verify_en, out_empty(I));
end generate;
+
gen_verify_channel : if g_dut_use_in_channel = true generate
out_channel(I)(c_dut_in_channel_w - 1 downto 0) <= mux_channel(c_dut_out_channel_w - 1 downto c_dut_nof_input_w);
proc_dp_verify_other_sosi("channel", INCR_UVEC(out_data(I), c_channel_offset), clk, verify_en, out_channel(I));
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
index 6af75575e4bf1bf5f755089231ad907d7adc86bc..4cca345bbd35100172c94b8936b40d15d0071eff 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
@@ -50,9 +50,7 @@ use work.tb_dp_pkg.all;
entity tb_dp_offload_rx_filter is
end tb_dp_offload_rx_filter;
-
architecture tb of tb_dp_offload_rx_filter is
-
constant c_nof_stream : natural := 1;
constant c_data_w : natural := 64;
@@ -122,9 +120,7 @@ architecture tb of tb_dp_offload_rx_filter is
signal hdr_fields_out_arr: t_slv_1024_arr(c_nof_streams - 1 downto 0);
signal hdr_fields_wrong_arr : t_slv_1024_arr(c_nof_streams - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -146,8 +142,6 @@ begin
hdr_fields_wrong_arr(i)(field_hi(c_hdr_field_arr, "ip_total_length" ) downto field_lo(c_hdr_field_arr, "ip_total_length" )) <= TO_UVEC(c_wrong_length, 16);
end generate;
-
-
p_stimuli : process
begin
proc_common_wait_some_cycles(dp_clk, 10);
@@ -188,10 +182,8 @@ begin
if c_nof_packets + 1 <= counter then
tb_end <= '1';
end if;
-
end process;
-
dut : entity work.dp_offload_rx_filter
generic map(
g_nof_streams => c_nof_streams, -- : POSITIVE;
@@ -216,5 +208,4 @@ begin
hdr_fields_out_arr => hdr_fields_out_arr,
hdr_fields_in_arr => hdr_fields_in_arr
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
index ad3da91825a6e973bb7377548dbd89955c518a07..41811773fe9a84b049f0d11b505e6d614e1f287b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_tx_v3.vhd
@@ -65,7 +65,6 @@ use common_lib.tb_common_mem_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_offload_tx_v3 is
generic (
-- general
@@ -81,9 +80,7 @@ entity tb_dp_offload_tx_v3 is
);
end tb_dp_offload_tx_v3;
-
architecture tb of tb_dp_offload_tx_v3 is
-
constant c_mm_clk_period : time := 1 ns;
constant c_dp_clk_period : time := 5 ns;
@@ -342,9 +339,7 @@ architecture tb of tb_dp_offload_tx_v3 is
signal verify_snk_in : t_dp_sosi;
signal verify_snk_in_data : std_logic_vector(g_data_w - 1 downto 0);
signal prev_verify_snk_in_data : std_logic_vector(g_data_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -391,7 +386,6 @@ begin
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -526,7 +520,6 @@ begin
hdr_fields_out_arr => tx_hdr_fields_out_arr
);
-
p_rd_tx_hdr_words : process
variable v_word : std_logic_vector(c_word_w - 1 downto 0);
begin
@@ -551,7 +544,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- Link
------------------------------------------------------------------------------
@@ -621,7 +613,6 @@ begin
dp_offload_rx_src_in_arr <= (others => c_dp_siso_rdy);
dp_offload_rx_src_in_arr(0) <= verify_snk_out;
-
p_rd_rx_hdr_words : process
variable v_word : std_logic_vector(c_word_w - 1 downto 0);
begin
@@ -691,7 +682,6 @@ begin
end if;
end process;
-
------------------------------------------------------------------------------
-- Auxiliary
------------------------------------------------------------------------------
@@ -699,5 +689,4 @@ begin
-- Map to slv to ease monitoring in wave window
stimuli_src_out_data <= stimuli_src_out.data(g_data_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(g_data_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
index 0a4f1ea66459a868c788417dc935aa1b7f00429b..f0d5e7bde9cc567b2d583ebaf038e3f8adf32b95 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet.vhd
@@ -35,7 +35,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_packet is
generic (
g_data_w : natural := 16;
@@ -46,7 +45,6 @@ entity tb_dp_packet is
end tb_dp_packet;
architecture tb of tb_dp_packet is
-
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
constant c_data_w : integer := sel_a_b(g_data_w < 30, g_data_w, 30); -- used to avoid INTEGER range error for 2**31 and 2**32
@@ -129,9 +127,7 @@ architecture tb of tb_dp_packet is
signal expected_rx_data : std_logic_vector(g_data_w - 1 downto 0);
signal expected_rx_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
signal expected_rx_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -153,7 +149,6 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -206,7 +201,6 @@ begin
wait;
end process;
-
-- Map to slv to ease monitoring in wave window
in_data <= in_sosi.data(in_data'range);
in_val <= in_sosi.valid;
@@ -241,7 +235,6 @@ begin
proc_dp_verify_sync(c_sync_period, c_sync_offset, clk, verify_en, rx_sync, rx_sop, rx_bsn); -- Verify that the output sync occurs when expected
-
------------------------------------------------------------------------------
-- DP SOSI ==> DP PACKET
------------------------------------------------------------------------------
@@ -277,7 +270,6 @@ begin
pkt_eop <= pkt_sosi.eop;
pkt_sync <= pkt_sosi.sync;
-
------------------------------------------------------------------------------
-- DP PACKET ==> DP SOSI
------------------------------------------------------------------------------
@@ -307,5 +299,4 @@ begin
rx_channel <= rx_sosi.channel(rx_channel'range);
rx_sync <= rx_sosi.sync;
rx_bsn <= rx_sosi.bsn(rx_bsn'range);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
index 2c60d0f34f4d88165c32aac96f975f7629ff2d74..6466f7e36b7f408b3d2687d849b74e35654a6358 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packet_merge.vhd
@@ -53,7 +53,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_packet_merge is
generic (
-- general
@@ -73,9 +72,7 @@ entity tb_dp_packet_merge is
);
end tb_dp_packet_merge;
-
architecture tb of tb_dp_packet_merge is
-
constant c_rl : natural := 1;
constant c_pulse_active : natural := 1;
@@ -141,9 +138,7 @@ architecture tb of tb_dp_packet_merge is
signal verify_value_en : std_logic := sel_a_b(g_nof_pkt = 0, '0', '1');
signal expected_verify_snk_in : t_dp_sosi;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -165,7 +160,6 @@ begin
random_1(random_1'high) when g_flow_control_verify = e_random else
pulse_1 when g_flow_control_verify = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -232,7 +226,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -253,8 +246,10 @@ begin
-- Verify that the output is incrementing data, like the input stimuli
proc_dp_verify_data("verify_snk_in.data", c_rl, c_data_max, c_unsigned_1, clk, verify_en_valid, verify_snk_out.ready, verify_snk_in.valid, verify_snk_in.data, prev_verify_snk_in.data);
+
gen_verify_bsn_increment : if g_verify_bsn_err = false generate
proc_dp_verify_data("verify_snk_in.bsn", c_rl, c_unsigned_0, to_unsigned(c_verify_bsn_gap, 32), clk, verify_en_sop, verify_snk_out.ready, verify_snk_in.sop, verify_snk_in.bsn, prev_verify_snk_in.bsn);
+
gen_verify_err : if g_nof_pkt = 1 generate
-- Assume verifying g_nof_pkt = 1 is sufficient. Verifing g_nof_pkt > 1 is more difficult,
-- because the merged output error field is the bitwise OR of the input error fields
@@ -292,7 +287,6 @@ begin
-- Verify output ready latency
proc_dp_verify_valid(clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
-
------------------------------------------------------------------------------
-- DUT dp_packet_merge
------------------------------------------------------------------------------
@@ -319,7 +313,6 @@ begin
src_out => dp_packet_merge_src_out
);
-
------------------------------------------------------------------------------
-- Optional reverse DUT dp_packet_unmerge
------------------------------------------------------------------------------
@@ -351,5 +344,4 @@ begin
-- Map to slv to ease monitoring in wave window
stimuli_data <= stimuli_src_out.data(g_data_w - 1 downto 0);
verify_data <= verify_snk_in.data(g_data_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
index ceb0c22c1d1d28e3c2acf4dc7447018d75544798..7046fe0e483ecbc27af54c2431eedc0d8feb2e42 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_packetizing.vhd
@@ -28,7 +28,6 @@ use work.dp_stream_pkg.all;
use work.dp_packetizing_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_packetizing is
generic (
-- Try different packing
@@ -39,9 +38,7 @@ entity tb_dp_packetizing is
);
end tb_dp_packetizing;
-
architecture tb of tb_dp_packetizing is
-
-- > as 10
-- > run 30 us --> OK
-- > restart -f
@@ -53,7 +50,6 @@ architecture tb of tb_dp_packetizing is
constant c_fsn_w : natural := 8; -- <= g_usr_dat_w
-
------------------------------------------------------------------------------
-- Try different block sizes
@@ -65,7 +61,6 @@ architecture tb of tb_dp_packetizing is
constant c_phy_block_size : natural := c_usr_block_size * g_phy_nof_words / g_usr_nof_words;
-
------------------------------------------------------------------------------
constant c_nof_block_per_sync : natural := 10;
@@ -155,13 +150,10 @@ architecture tb of tb_dp_packetizing is
signal rcv_err : std_logic := '0';
signal prev_rcv_dat : std_logic_vector(g_usr_dat_w - 1 downto 0) := (others => '1'); -- -1 to also verify first sample 0 correctly
-
begin
-
clk <= not clk after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
-
------------------------------------------------------------------------------
-- DATA GENERATION and VERIFICATION
------------------------------------------------------------------------------
@@ -193,7 +185,6 @@ begin
-- Verify the data path output CRC (avoid error message at initialisation)
assert NOW = 0 ps or rcv_err = '0' report "rcv_err = '1' indicating CRC error" severity ERROR;
-
------------------------------------------------------------------------------
-- TRANSMITTER
------------------------------------------------------------------------------
@@ -290,7 +281,6 @@ begin
out_eof => xmt_pace_eof(0)
);
-
------------------------------------------------------------------------------
-- PHY LINK INTERFACE
------------------------------------------------------------------------------
@@ -481,7 +471,6 @@ begin
end generate; -- gen_rcv_throttle
end generate; -- no_valid_support
-
------------------------------------------------------------------------------
-- RECEIVER
------------------------------------------------------------------------------
@@ -532,5 +521,4 @@ begin
out_eof => rcv_eof,
out_err => rcv_err
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
index c4f631b23f8aa0779a30b351067be18881bce32f..f5bfc3ebe3ed4aac611671101f78a9e9cebe7082 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pad_insert_remove.vhd
@@ -47,9 +47,7 @@ entity tb_dp_pad_insert_remove is
);
end tb_dp_pad_insert_remove;
-
architecture tb of tb_dp_pad_insert_remove is
-
-- tb default
constant c_rl : natural := 1;
constant c_pulse_active : natural := 1;
@@ -129,9 +127,7 @@ architecture tb of tb_dp_pad_insert_remove is
signal out_err : std_logic_vector(c_dp_stream_error_w - 1 downto 0);
signal out_gap : std_logic := '1';
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -153,7 +149,6 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -195,7 +190,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -223,7 +217,6 @@ begin
proc_dp_verify_value(e_equal, clk, verify_done, expected_out_channel, prev_out_channel);
proc_dp_verify_value(e_equal, clk, verify_done, expected_out_err, prev_out_err);
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -287,5 +280,4 @@ begin
out_err <= out_sosi.err(in_err'range);
out_sync <= out_sosi.sync;
out_bsn <= out_sosi.bsn(c_bsn_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
index 55baa7e428a24f47228b6c51e430ff38c48a8b06..aec011b91bd00c5ee57c1657d886a3fb050e7e97 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline.vhd
@@ -33,9 +33,7 @@ entity tb_dp_pipeline is
);
end tb_dp_pipeline;
-
architecture tb of tb_dp_pipeline is
-
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT ready latency
@@ -95,9 +93,7 @@ architecture tb of tb_dp_pipeline is
signal verify_done : std_logic;
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(sel_a_b(g_pipeline = 0, 18953, 18952), c_dp_data_w);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -160,5 +156,4 @@ begin
src_in => out_siso, -- IN = request from downstream ST sink
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
index c218fc83601aa74662a7b644864c233b91b907ca..87366a33880b4f7b5a43161f5a3e0912711d917b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pipeline_ready.vhd
@@ -36,7 +36,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_pipeline_ready is
generic (
g_in_en : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
@@ -47,7 +46,6 @@ entity tb_dp_pipeline_ready is
);
end tb_dp_pipeline_ready;
-
architecture tb of tb_dp_pipeline_ready is
constant c_data_w : natural := 16;
constant c_rl : natural := 1;
@@ -94,9 +92,7 @@ architecture tb of tb_dp_pipeline_ready is
signal out_eop : std_logic;
signal hold_out_sop : std_logic;
signal expected_out_data : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -106,7 +102,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse_1);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -119,7 +114,6 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -171,12 +165,10 @@ begin
src_out => adapt_sosi
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
-
-- Verification logistics
verify_en <= '1' when rising_edge(clk) and out_sosi.sop = '1'; -- enable verify after first output sop
count_eop <= count_eop + 1 when rising_edge(clk) and out_sosi.eop = '1' and((g_out_latency > 0) or
@@ -198,7 +190,6 @@ begin
out_sop <= out_sosi.sop;
out_eop <= out_sosi.eop;
-
------------------------------------------------------------------------------
-- DUT dp_pipeline_ready
------------------------------------------------------------------------------
@@ -218,6 +209,4 @@ begin
src_in => out_siso,
src_out => out_sosi
);
-
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
index b52ebc9b105bae41ed196fa9caf775d93cda504a..3cb638a976fa37e0b8803b2ae627751a143a2cde 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_pkg.vhd
@@ -29,9 +29,7 @@ use common_lib.common_str_pkg.all;
use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
-
package tb_dp_pkg is
-
------------------------------------------------------------------------------
-- Purpose:
--
@@ -608,12 +606,9 @@ package tb_dp_pkg is
procedure proc_dp_stream_valid_eop(signal clk : in std_logic;
signal in_valid : in std_logic;
signal in_eop : in std_logic);
-
end tb_dp_pkg;
-
package body tb_dp_pkg is
-
------------------------------------------------------------------------------
-- PROCEDURE: Block data generator with feedforward throttle control
------------------------------------------------------------------------------
@@ -658,6 +653,7 @@ package body tb_dp_pkg is
cnt_dat <= INCR_UVEC(cnt_dat, 1);
wait until rising_edge(clk);
end loop;
+
else
-- throttle cnt_val, so c_throttle_num active cnt_val cycles per c_throttle_den cycles
for I in 0 to c_block_size / c_throttle_num - 1 loop
@@ -687,7 +683,6 @@ package body tb_dp_pkg is
end loop;
end proc_dp_gen_block_data;
-
------------------------------------------------------------------------------
-- PROCEDURE: Block data generator with ready flow control and symbols counter
-- . dependent on in_en and src_in.ready
@@ -858,7 +853,6 @@ package body tb_dp_pkg is
out_eop <= '0';
end proc_dp_stream_ready_latency;
-
------------------------------------------------------------------------------
-- FUNCTION: Initialize the data per symbol
-- . use big endian
@@ -878,7 +872,6 @@ package body tb_dp_pkg is
return v_data;
end func_dp_data_init;
-
------------------------------------------------------------------------------
-- FUNCTION: Increment the data per symbol
-- . use big endian
@@ -900,7 +893,6 @@ package body tb_dp_pkg is
return v_data;
end func_dp_data_incr;
-
------------------------------------------------------------------------------
-- PROCEDURE: Generate counter data with valid
-- . Output counter data dependent on in_en and src_in.ready
@@ -927,7 +919,6 @@ package body tb_dp_pkg is
end if;
end proc_dp_gen_data;
-
------------------------------------------------------------------------------
-- PROCEDURE: Generate counter data with valid
-- . Output counter data dependent on in_en and src_in.ready
@@ -960,7 +951,6 @@ package body tb_dp_pkg is
end if;
end proc_dp_gen_data;
-
------------------------------------------------------------------------------
-- PROCEDURE: Generate a frame with symbols counter
-- . dependent on in_en and src_in.ready
@@ -1010,7 +1000,6 @@ package body tb_dp_pkg is
src_out.eop <= '0';
end proc_dp_gen_frame;
-
------------------------------------------------------------------------------
-- PROCEDURE: Input data counter
------------------------------------------------------------------------------
@@ -1076,7 +1065,6 @@ package body tb_dp_pkg is
out_val <= tx_val(c_ready_latency);
end proc_dp_tx_data;
-
------------------------------------------------------------------------------
-- PROCEDURE: Transmit data control (use for sop, eop)
------------------------------------------------------------------------------
@@ -1094,7 +1082,6 @@ package body tb_dp_pkg is
end if;
end proc_dp_tx_ctrl;
-
------------------------------------------------------------------------------
-- PROCEDURE: Define test sync interval
------------------------------------------------------------------------------
@@ -1107,7 +1094,6 @@ package body tb_dp_pkg is
wait until rising_edge(clk);
end proc_dp_sync_interval;
-
------------------------------------------------------------------------------
-- PROCEDURE: Stimuli for cnt_en
------------------------------------------------------------------------------
@@ -1415,7 +1401,6 @@ package body tb_dp_pkg is
wait;
end proc_dp_count_en;
-
------------------------------------------------------------------------------
-- PROCEDURE: Stimuli for out_ready
------------------------------------------------------------------------------
@@ -1687,7 +1672,6 @@ package body tb_dp_pkg is
wait;
end proc_dp_out_ready;
-
------------------------------------------------------------------------------
-- PROCEDURE: DUT output verify enable
------------------------------------------------------------------------------
@@ -1711,7 +1695,6 @@ package body tb_dp_pkg is
wait;
end proc_dp_verify_en;
-
-- Dynamicly depend on first valid data to make verify_en active
procedure proc_dp_verify_en(constant c_continuous : in boolean;
signal clk : in std_logic;
@@ -1751,7 +1734,6 @@ package body tb_dp_pkg is
proc_common_wait_some_cycles(clk, nof_post_clk);
end proc_dp_verify_run_some_cycles;
-
------------------------------------------------------------------------------
-- PROCEDURE: Verify the expected value
------------------------------------------------------------------------------
@@ -2067,7 +2049,6 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_symbols;
-
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT output data with empty
-- . account for stream empty
@@ -2155,7 +2136,6 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_data_empty;
-
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT output other SOSI data
-- . Suited to verify the empty, error, channel fields assuming that these
@@ -2672,7 +2652,6 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_gap_invalid;
-
------------------------------------------------------------------------------
-- PROCEDURE: Verify the DUT output control (use for sop, eop)
------------------------------------------------------------------------------
@@ -2702,7 +2681,6 @@ package body tb_dp_pkg is
end if;
end proc_dp_verify_ctrl;
-
------------------------------------------------------------------------------
-- PROCEDURE: Wait for stream valid
------------------------------------------------------------------------------
@@ -2715,7 +2693,6 @@ package body tb_dp_pkg is
end loop;
end proc_dp_stream_valid;
-
------------------------------------------------------------------------------
-- PROCEDURE: Wait for stream valid AND sop
------------------------------------------------------------------------------
@@ -2729,7 +2706,6 @@ package body tb_dp_pkg is
end loop;
end proc_dp_stream_valid_sop;
-
------------------------------------------------------------------------------
-- PROCEDURE: Wait for stream valid AND eop
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
index 5e78c8d0c29808794df0d5b714bc77310c8da3cd..da2ad8b364e2d8096b719a92456d7eb26b19e944 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reinterleave.vhd
@@ -48,7 +48,6 @@ entity tb_dp_reinterleave is
end;
architecture rtl of tb_dp_reinterleave is
-
type t_dat_arr is array (integer range <>) of std_logic_vector(g_dat_w - 1 downto 0);
type t_val_arr is array (integer range <>) of std_logic;
@@ -73,9 +72,7 @@ architecture rtl of tb_dp_reinterleave is
signal snk_out_arr : t_dp_siso_arr(g_nof_in - 1 downto 0);
signal src_out_arr : t_dp_sosi_arr(g_nof_out - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Standard TB clocking, RST and control
-----------------------------------------------------------------------------
@@ -135,5 +132,4 @@ begin
snk_in_arr => snk_in_arr,
src_out_arr => src_out_arr
);
-
end rtl;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
index 3e7ba004a12dd4be954c0d26fe734b35e06b52a5..f8137c37ce8e2eac48b0f108c61f2b6651f51a2f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack.vhd
@@ -40,7 +40,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_repack is
generic (
-- general
@@ -57,9 +56,7 @@ entity tb_dp_repack is
);
end tb_dp_repack;
-
architecture tb of tb_dp_repack is
-
constant c_rl : natural := 1;
constant c_pulse_active : natural := g_in_nof_words;
@@ -110,9 +107,7 @@ architecture tb of tb_dp_repack is
signal verify_done : std_logic := '0';
signal expected_verify_snk_in : t_dp_sosi;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -134,7 +129,6 @@ begin
random_1(random_1'high) when g_flow_control_verify = e_random else
pulse_1 when g_flow_control_verify = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -188,7 +182,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -222,7 +215,6 @@ begin
-- Verify output ready latency
proc_dp_verify_valid(clk, verify_en_valid, verify_snk_out.ready, prev_verify_snk_out.ready, verify_snk_in.valid);
-
------------------------------------------------------------------------------
-- Pack
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
index 116b8e6fd56693066a194b9a4f2df9abdbd096b9..1fbc042d83c68b5f5e55817d62faab380e2ca0c7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack_data.vhd
@@ -48,7 +48,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_repack_data is
generic (
-- general
@@ -69,9 +68,7 @@ entity tb_dp_repack_data is
);
end tb_dp_repack_data;
-
architecture tb of tb_dp_repack_data is
-
constant c_no_unpack : boolean := false;
constant c_enable_repack_in : boolean := true;
constant c_enable_repack_out : boolean := true;
@@ -126,9 +123,7 @@ architecture tb of tb_dp_repack_data is
signal unpack_src_in : t_dp_siso;
signal unpack_src_out : t_dp_sosi;
signal unpack_src_out_data : std_logic_vector(g_in_dat_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -171,7 +166,6 @@ begin
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -313,5 +307,4 @@ begin
-- Map to slv to ease monitoring in wave window
stimuli_src_out_data <= stimuli_src_out.data(g_in_dat_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(g_in_dat_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd b/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
index e6d77cdd7b3f22129ddef6831b5a3f978769acc1..062f9d2deeca01986cb62ec00d32c670005a83fe 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_repack_legacy.vhd
@@ -40,7 +40,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_repack_legacy is
generic (
-- general
@@ -64,9 +63,7 @@ entity tb_dp_repack_legacy is
);
end tb_dp_repack_legacy;
-
architecture tb of tb_dp_repack_legacy is
-
-- dp_stream_stimuli
constant c_stimuli_pulse_active : natural := 1;
constant c_stimuli_pulse_period : natural := 2;
@@ -114,9 +111,7 @@ architecture tb of tb_dp_repack_legacy is
signal unpack_src_in : t_dp_siso;
signal unpack_src_out : t_dp_sosi;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -159,7 +154,6 @@ begin
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -303,5 +297,4 @@ begin
-- Map to slv to ease monitoring in wave window
stimuli_src_out_data <= stimuli_src_out.data(g_in_dat_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(g_in_dat_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
index ed94016f85ac6d309aef221faabfd5bd97d6e185..163c4635bf689c8634b5b045fe0a48a7e33d287b 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data.vhd
@@ -59,9 +59,7 @@ entity tb_dp_reverse_n_data is
);
end tb_dp_reverse_n_data;
-
architecture tb of tb_dp_reverse_n_data is
-
constant c_pkt_len : natural := g_reverse_len * 5;
-- dp_stream_stimuli
@@ -113,9 +111,7 @@ architecture tb of tb_dp_reverse_n_data is
signal verify_fc_snk_in : t_dp_sosi;
signal verify_fc_snk_in_data : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -159,7 +155,6 @@ begin
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -316,5 +311,4 @@ begin
verify_snk_in_data <= verify_snk_in.data(c_data_w - 1 downto 0);
verify_fc_snk_in_data <= verify_fc_snk_in.data(c_data_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
index e9b6d64ff701aed7907ea1ed6b581bac7a358d08..5d89c3ab55ca9cb41d1e52e3d28925e3bf6393c4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_reverse_n_data_fc.vhd
@@ -58,9 +58,7 @@ entity tb_dp_reverse_n_data_fc is
);
end tb_dp_reverse_n_data_fc;
-
architecture tb of tb_dp_reverse_n_data_fc is
-
constant c_pkt_len : natural := g_reverse_len * 5;
-- dp_stream_stimuli
@@ -116,9 +114,7 @@ architecture tb of tb_dp_reverse_n_data_fc is
signal verify_snk_out : t_dp_siso := c_dp_siso_rdy;
signal verify_snk_in : t_dp_sosi;
signal verify_snk_in_data : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -165,7 +161,6 @@ begin
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -272,5 +267,4 @@ begin
stimuli_src_out_data <= stimuli_src_out.data(c_data_w - 1 downto 0);
reverse_src_out_data <= reverse_src_out.data(c_data_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(c_data_w - 1 downto 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
index ef9aff6ee3a0f84ab6fc66133d45c902f394689b..2079df76274b23a4f88114270dd0461d2037edb4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_rsn_source.vhd
@@ -46,7 +46,6 @@ entity tb_dp_rsn_source is
end tb_dp_rsn_source;
architecture tb of tb_dp_rsn_source is
-
-- The nof block per sync interval will be the same after every
-- c_min_nof_pps_interval. The c_gcd is the greatest common divider of
-- g_pps_interval and g_bs_block_size, so g_bs_block_size / c_gcd yields an
@@ -147,9 +146,7 @@ architecture tb of tb_dp_rsn_source is
signal dbg_nof_blk : natural;
signal dbg_accumulate : natural;
signal dbg_expected_bsn : natural;
-
begin
-
rst <= '1', '0' after c_clk_period * 7;
clk <= (not clk) or tb_end after c_clk_period / 2;
@@ -248,11 +245,9 @@ begin
end if;
end if;
end if;
-
end if;
end process;
-
-----------------------------------------------------------------------------
-- Stimuli
-----------------------------------------------------------------------------
@@ -316,7 +311,6 @@ begin
wait;
end process;
-
-----------------------------------------------------------------------------
-- Verification
-- . Some aspects of rs_sosi are verified multiple times in different ways,
@@ -440,5 +434,4 @@ begin
rs_restart => rs_restart, -- = rs_sosi.sync for first sync after bs_sosi.valid went high
rs_new_interval => rs_new_interval -- = active during first rs_sosi.sync interval
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
index b2d945c8874c8d9ea894f55be4cd6b661d7a5129..2801b29fc2bebb169ad5c1663573eecf1a7410e4 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_selector_arr.vhd
@@ -59,7 +59,6 @@ entity tb_dp_selector_arr is
end tb_dp_selector_arr;
architecture tb of tb_dp_selector_arr is
-
constant c_nof_streams : natural := 4;
constant c_sync_period : natural := 10;
@@ -89,14 +88,10 @@ architecture tb of tb_dp_selector_arr is
signal mm_mosi_pipe : t_mem_mosi;
signal mm_mosi_ref : t_mem_mosi;
-
begin
-
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -152,7 +147,6 @@ begin
wait;
end process;
-
p_verify : process
begin
proc_common_wait_some_cycles(clk, g_nof_repeat * (g_pkt_gap + g_pkt_len)); -- Wait until end of simulation.
@@ -242,6 +236,4 @@ begin
proc_mem_mm_bus_wr(0, x"1", clk, mm_mosi_pipe); -- select pipe_sosi_arr on dut_pipe
wait;
end process;
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd b/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
index ed63595ab89de36e5b83d0a1f6e765184d2b4a3b..dfa71d0f185870e7a6eaf8b443d30ca53e0aae2e 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_shiftram.vhd
@@ -42,7 +42,6 @@ use common_lib.tb_common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_shiftram is
generic (
-- DUT
@@ -56,9 +55,7 @@ entity tb_dp_shiftram is
);
end tb_dp_shiftram;
-
architecture tb of tb_dp_shiftram is
-
constant dp_clk_period : time := 5 ns;
constant mm_clk_period : time := 20 ns;
@@ -83,9 +80,7 @@ architecture tb of tb_dp_shiftram is
signal out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal state : natural := 0;
-
begin
-
mm_clk <= (not mm_clk) or tb_end after mm_clk_period / 2;
mm_rst <= '1', '0' after mm_clk_period * 7;
@@ -213,6 +208,4 @@ begin
-- Streaming source
src_out_arr => out_sosi_arr
);
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
index 8454ab7834719478211c79bd49daeda15d51e5d4..1d249b0aa1e22a96485c7659d14849f8fa0e2bfb 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_shiftreg.vhd
@@ -30,9 +30,7 @@ use work.tb_dp_pkg.all;
entity tb_dp_shiftreg is
end tb_dp_shiftreg;
-
architecture tb of tb_dp_shiftreg is
-
-- See tb_dp_pkg.vhd for explanation and run time
-- DUT ready latency
@@ -96,9 +94,7 @@ architecture tb of tb_dp_shiftreg is
signal verify_done : std_logic;
signal exp_data : std_logic_vector(c_dp_data_w - 1 downto 0) := TO_UVEC(18951, c_dp_data_w);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -168,5 +164,4 @@ begin
src_in => out_siso, -- IN = request from downstream ST sink
src_out => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
index 8618312e29322865f8ab4d5a4e6bee235bbb7f0a..47278fc5b0eb9e6d7962c55ac16503b9f6f01434 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_split.vhd
@@ -40,9 +40,7 @@ entity tb_dp_split is
);
end tb_dp_split;
-
architecture tb of tb_dp_split is
-
constant c_period : time := 100 ns;
constant c_rl : natural := 1;
@@ -84,9 +82,7 @@ architecture tb of tb_dp_split is
signal expected_data_1 : std_logic_vector(g_data_w - 1 downto 0);
signal hold_out_sop_0 : std_logic;
signal hold_out_sop_1 : std_logic;
-
begin
-
rst <= '1', '0' after c_period * 7;
clk <= not clk or tb_end after c_period / 2;
@@ -188,5 +184,4 @@ begin
-- Check that the test has ran at all
proc_dp_verify_value(e_at_least, clk, verify_done, expected_data_0, out_data_0);
proc_dp_verify_value(e_at_least, clk, verify_done, expected_data_1, out_data_1);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
index ac39b4dcf652d7817faa323b958de32e4288988d..55c713be62ff85fb0e9a99f15cd70a6eea1e437f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_strobe_total_count.vhd
@@ -53,9 +53,7 @@ entity tb_dp_strobe_total_count is
);
end tb_dp_strobe_total_count;
-
architecture tb of tb_dp_strobe_total_count is
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -96,9 +94,7 @@ architecture tb of tb_dp_strobe_total_count is
signal rd_count_arr : t_natural_arr(c_nof_counts - 1 downto 0);
signal exp_count_arr : t_natural_arr(c_nof_counts - 1 downto 0) := (c_exp_nof_valid, c_exp_nof_sop, c_exp_nof_sync);
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -198,5 +194,4 @@ begin
tb_end <= '1';
wait;
end process;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
index f7c67797eb1a9eb12f32cd4561815fc31ac7c050..83b91d51143c56abb68679ec11e9689d0dff9d6f 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_switch.vhd
@@ -36,13 +36,10 @@ use common_lib.tb_common_mem_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_switch is
end tb_dp_switch;
-
architecture tb of tb_dp_switch is
-
constant c_nof_inputs : natural := 3;
constant c_data_w : natural := 32;
constant c_nof_packets : natural := 30;
@@ -74,9 +71,7 @@ architecture tb of tb_dp_switch is
signal reg_dp_switch_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_dp_switch_miso : t_mem_miso;
-
begin
-
-----------------------------------------------------------------------------
-- Clock,reset generation
-----------------------------------------------------------------------------
@@ -86,7 +81,6 @@ begin
mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * 7;
-
-----------------------------------------------------------------------------
-- Generate continuous packet streams, with and without gaps
-----------------------------------------------------------------------------
@@ -97,7 +91,6 @@ begin
begin
dp_gen_block_data_src_out_arr(i) <= c_dp_sosi_rst;
-
proc_common_wait_until_low(dp_clk, dp_rst);
--proc_common_wait_some_cycles(dp_clk, 4);
@@ -185,6 +178,4 @@ begin
reg_mosi => reg_dp_switch_mosi,
reg_miso => reg_dp_switch_miso
);
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
index 5b35a7a9d5425e93a2b30434834bb175e362cdc6..22cf16f4c6aa666ad36bd28409e444d227eb641d 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_checker.vhd
@@ -60,9 +60,7 @@ entity tb_dp_sync_checker is
);
end tb_dp_sync_checker;
-
architecture tb of tb_dp_sync_checker is
-
constant c_rl : natural := 1;
constant c_no_dut : boolean := true;
@@ -119,9 +117,7 @@ architecture tb of tb_dp_sync_checker is
signal verify_done : std_logic := '0';
signal expected_verify_snk_in : t_dp_sosi;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -143,7 +139,6 @@ begin
random_1(random_1'high) when g_flow_control_verify = e_random else
pulse_1 when g_flow_control_verify = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -197,7 +192,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -284,7 +278,4 @@ begin
verify_data <= verify_snk_in.data(g_in_dat_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data when verify_snk_in.valid = '1';
-
end tb;
-
-
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
index 2c615fd6955951cda120a3e46cf321f950a5df63..d11d579d64b5a951d678ab0d02581c33bc4bc741 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert.vhd
@@ -40,7 +40,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_sync_insert is
generic (
g_block_size_input : natural := 16;
@@ -53,9 +52,7 @@ entity tb_dp_sync_insert is
);
end tb_dp_sync_insert;
-
architecture tb of tb_dp_sync_insert is
-
constant c_dut_latency : natural := 2;
constant c_nof_replicated_sync : natural := g_block_size_input / g_nof_data_per_block * g_nof_blk_per_sync_input / g_nof_blk_per_sync;
@@ -76,9 +73,7 @@ architecture tb of tb_dp_sync_insert is
signal cnt_replicated_global_bsn : natural;
signal prev_out_sosi_global : t_dp_sosi := c_dp_sosi_rst;
signal prev_out_sosi_local : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -198,5 +193,4 @@ begin
-- Verify output packet block size
proc_dp_verify_block_size(exp_size, clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, cnt_size);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
index bc3fef9e794d34174ccab47cb605879601449066..481331ffe8aed6340372dc1eac8501f63bfa0beb 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_insert_v2.vhd
@@ -44,7 +44,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_sync_insert_v2 is
generic (
g_nof_streams : natural := 2;
@@ -58,9 +57,7 @@ entity tb_dp_sync_insert_v2 is
);
end tb_dp_sync_insert_v2;
-
architecture tb of tb_dp_sync_insert_v2 is
-
constant c_dut_latency : natural := 1;
constant c_nof_replicated_sync : natural := g_nof_blk_per_sync_input / g_nof_blk_per_sync;
@@ -88,9 +85,7 @@ architecture tb of tb_dp_sync_insert_v2 is
signal out_hold_sop : std_logic := '0';
signal exp_size : natural := g_block_size_input;
signal cnt_size_arr : t_natural_arr(0 to g_nof_streams - 1);
-
begin
-
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
rst <= '1', '0' after c_dp_clk_period * 7;
@@ -234,6 +229,4 @@ begin
proc_dp_verify_block_size(exp_size, dp_clk, out_sosi_arr(I).valid, out_sosi_arr(I).sop, out_sosi_arr(I).eop, cnt_size_arr(I));
end generate;
-
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
index f54683b6e63d82f78527d6b16c2a6f0f6a7366f3..3ec876e8a30820ff6a74d97518b3faa357b26fd7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_sync_recover.vhd
@@ -44,7 +44,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_dp_sync_recover is
generic (
g_nof_data_per_block : natural := 16;
@@ -58,9 +57,7 @@ entity tb_dp_sync_recover is
);
end tb_dp_sync_recover;
-
architecture tb of tb_dp_sync_recover is
-
constant c_dp_clk_period : time := 5 ns;
signal tb_end : std_logic := '0';
@@ -79,9 +76,7 @@ architecture tb of tb_dp_sync_recover is
signal out_hold_sop : std_logic := '0';
signal exp_size : natural := g_nof_data_per_block;
signal cnt_size : natural;
-
begin
-
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
rst <= '1', '0' after c_dp_clk_period * 7;
@@ -229,7 +224,4 @@ begin
proc_dp_verify_sop_and_eop(dp_clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, out_hold_sop);
-- Verify output packet block size
proc_dp_verify_block_size(exp_size, dp_clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, cnt_size);
-
-
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd b/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
index 0d0dd4e9594f7c9caae4b9df6ee2e08500174a33..7f85cf3f48ff9551ecf656e57c3ab0b35401c8d7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_tail_remove.vhd
@@ -36,11 +36,9 @@ entity tb_dp_tail_remove is
end tb_dp_tail_remove;
architecture tb of tb_dp_tail_remove is
-
constant c_clk_period : time := 100 ns;
constant c_rl : natural := 1;
-
constant c_nof_frames : natural := 3;
constant c_nof_symbols_per_frame : natural := 80;
constant c_nof_symbols_per_tail : natural := 12;
@@ -58,9 +56,7 @@ architecture tb of tb_dp_tail_remove is
signal detailed_siso : t_dp_siso := c_dp_siso_rdy;
signal detailed_sosi : t_dp_sosi;
-
begin
-
rst <= '1', '0' after c_clk_period * 7;
clk <= not clk or tb_end after c_clk_period / 2;
@@ -135,5 +131,4 @@ begin
src_in => detailed_siso,
src_out => detailed_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd b/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd
index 7b3716afa53d2b8c015b19239e534e44bca5296d..13cc297acc85ee5f1f8d966e6109650cee2e5021 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_throttle_sop.vhd
@@ -39,7 +39,6 @@ entity tb_dp_throttle_sop is
end tb_dp_throttle_sop;
architecture tb of tb_dp_throttle_sop is
-
constant c_period : natural := 100;
constant c_clk_period : time := 10 ns;
@@ -57,9 +56,7 @@ architecture tb of tb_dp_throttle_sop is
signal fifo_src_out : t_dp_sosi;
signal fifo_src_in : t_dp_siso;
-
begin
-
-----------------------------------------------------------------------------
-- Clock and reset generation
-----------------------------------------------------------------------------
@@ -126,5 +123,4 @@ begin
snk_out => fifo_src_in,
snk_in => fifo_src_out
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
index 02f3834cef14571e8078bf1309319977165db615..f9587df95d1a3e24b149e625b605eda6842bcfea 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_throttle_xon.vhd
@@ -40,7 +40,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_throttle_xon is
generic (
-- general
@@ -55,9 +54,7 @@ entity tb_dp_throttle_xon is
);
end tb_dp_throttle_xon;
-
architecture tb of tb_dp_throttle_xon is
-
constant c_nof_sync : natural := 20;
constant c_nof_valid_on : natural := g_nof_block_on * g_block_size;
constant c_nof_clk_off : natural := sel_a_b(g_nof_clk_off > g_block_size, g_nof_clk_off, 0);
@@ -103,9 +100,7 @@ architecture tb of tb_dp_throttle_xon is
signal xon_cnt : natural; -- count nof valid='1' cycles
signal xoff_cnt : natural; -- count nof valid='0' cycles
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -119,7 +114,6 @@ begin
stimuli_en <= random_0(random_0'high) when g_flow_control_stimuli = e_random else '1';
verify_snk_out.ready <= random_1(random_1'high) when g_flow_control_verify = e_random else '1';
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -158,7 +152,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -207,7 +200,6 @@ begin
else
-- no verification yet for restart at sync, add when necessary
end if;
-
end if;
else
-- no verification needed, because the ready flow control does not affect the xonoff
@@ -235,5 +227,4 @@ begin
src_in => verify_snk_out, -- flush control via out_siso.xon
src_out => verify_snk_in
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
index 549d6e57cf855a08718afb2f44c2deec17684af2..bd86e59c732776f7803aa5721b3e7e1687b344d7 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff.vhd
@@ -60,7 +60,6 @@ use common_lib.tb_common_pkg.all;
use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_dp_xonoff is
generic (
-- general
@@ -76,9 +75,7 @@ entity tb_dp_xonoff is
);
end tb_dp_xonoff;
-
architecture tb of tb_dp_xonoff is
-
constant c_rl : natural := 1;
constant c_nof_repeat : natural := g_nof_repeat + g_nof_dut;
@@ -134,9 +131,7 @@ architecture tb of tb_dp_xonoff is
signal expected_verify_snk_in : t_dp_sosi;
signal exp_size : natural;
signal cnt_size : natural;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -158,7 +153,6 @@ begin
random_1(random_1'high) when g_flow_control_verify = e_random else
pulse_1 when g_flow_control_verify = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -217,7 +211,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -300,7 +293,6 @@ begin
dut_siso_arr(g_nof_dut - 1) <= verify_snk_out;
verify_snk_in <= dut_sosi_arr(g_nof_dut - 1);
-
------------------------------------------------------------------------------
-- Auxiliary
------------------------------------------------------------------------------
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
index 37d8f4087989aa42ee73e484ca295e30bfa77bda..46d08b2d87f8d1669af908f897a87551fe2e6365 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_xonoff_reg_timeout.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
--
-- Usage:
-- > as 10
@@ -33,18 +32,13 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
-
-
entity tb_dp_xonoff_reg_timeout is
end tb_dp_xonoff_reg_timeout;
-
architecture tb of tb_dp_xonoff_reg_timeout is
-
constant clk_period : time := 20 ns; -- 50 MHz
constant st_clk_period : time := 5000 ps; -- 200 MHz
-
-- Minimum nof clk cycles between eop and sop
constant c_500ns_latency : natural := 500 / 20;
constant c_timeout_2us : natural := 2000 / 20;
@@ -58,16 +52,13 @@ architecture tb of tb_dp_xonoff_reg_timeout is
signal sla_out_miso : t_mem_miso := c_mem_miso_rst;
signal xonoff_reg : std_logic_vector(0 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
st_clk <= not st_clk or tb_end after st_clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
p_stimuli : process
begin
-
wait until rst = '0';
for I in 0 to c_500ns_latency - 1 loop wait until rising_edge(clk); end loop;
@@ -102,9 +93,6 @@ begin
wait;
end process;
-
-
-
u_dut : entity work.dp_xonoff_reg_timeout
generic map (
g_mm_timeout => 1,
@@ -121,5 +109,4 @@ begin
xonoff_reg => xonoff_reg
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
index d2b8f68425598dea658a2b966f890c90131a6831..78ff1107922be99fcc03ddd829a454cf448692a1 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_align_v2.vhd
@@ -50,9 +50,7 @@ entity tb_mmp_dp_bsn_align_v2 is
);
end tb_mmp_dp_bsn_align_v2;
-
architecture tb of tb_mmp_dp_bsn_align_v2 is
-
constant c_mm_clk_period : time := 40 ns;
constant c_dp_clk_period : time := 10 ns;
constant c_cross_clock_domain_latency : natural := 20;
@@ -190,9 +188,7 @@ architecture tb of tb_mmp_dp_bsn_align_v2 is
signal dbg_c_align_latency_nof_clk : natural := c_align_latency_nof_clk;
signal dbg_c_total_latency : natural := c_total_latency;
signal dbg_c_verify_nof_blocks : natural := c_verify_nof_blocks;
-
begin
-
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
dp_rst <= '1', '0' after c_dp_clk_period * 7;
@@ -376,6 +372,7 @@ begin
one_lost_input : if g_lost_input = true generate
-- Model missing enabled input stream at index c_lost_input = c_nof_streams-1
in_sosi_arr(c_nof_streams - 1) <= c_dp_sosi_rst;
+
gen_in_sosi_arr : for I in c_nof_streams - 2 downto 0 generate
in_sosi_arr(I) <= transport ref_sosi_arr(I) after func_input_delay(I) * c_dp_clk_period;
end generate;
@@ -469,5 +466,4 @@ begin
-- Output via streaming DP interface, when g_use_mm_output = TRUE.
out_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
index 56dbef924e69e9401140c30ea5aac9f34759d4d2..20d75a9e96538e0a879d3c595d753f01ea649bbf 100644
--- a/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mmp_dp_bsn_sync_scheduler.vhd
@@ -39,9 +39,7 @@ use work.tb_dp_pkg.all;
entity tb_mmp_dp_bsn_sync_scheduler is
end tb_mmp_dp_bsn_sync_scheduler;
-
architecture tb of tb_mmp_dp_bsn_sync_scheduler is
-
constant c_mm_clk_period : time := 40 ns;
constant c_dp_clk_period : time := 10 ns;
constant c_cross_clock_domain_latency : natural := 20;
@@ -89,9 +87,7 @@ architecture tb of tb_mmp_dp_bsn_sync_scheduler is
signal out_enable : std_logic;
signal verify_bsn_hi : std_logic := '0';
-
begin
-
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
dp_rst <= '1', '0' after c_dp_clk_period * 7;
@@ -417,5 +413,4 @@ begin
out_start => out_start,
out_enable => out_enable
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
index 464360979bd3c56d32669a062b83f92a57d6f4b6..ad32c921763e7e4f7ca031c48eca53bc3964ff31 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_align.vhd
@@ -32,7 +32,6 @@
-- BSN alignment thanks to verify_dis_arr these cases are also verified
-- automatically.
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -44,7 +43,6 @@ use common_lib.tb_common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_mms_dp_bsn_align is
generic (
g_block_size : natural := 11;
@@ -58,9 +56,7 @@ entity tb_mms_dp_bsn_align is
);
end tb_mms_dp_bsn_align;
-
architecture tb of tb_mms_dp_bsn_align is
-
constant c_mm_clk_period : time := 20 ns; -- 40 MHz
constant c_rl : natural := 1;
constant c_pulse_active : natural := 1;
@@ -153,9 +149,7 @@ architecture tb of tb_mms_dp_bsn_align is
signal mm_mosi : t_mem_mosi;
signal mm_miso : t_mem_miso;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -165,7 +159,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -333,7 +326,6 @@ begin
tb_state <= s_disable_one_input;
verify_dis_arr <= (others => '1');
-
-- in_en_event <= '1';
in_en_arr(c_event_input) <= '0'; -- switch an input off
-- proc_common_wait_some_cycles(clk, 1);
@@ -426,7 +418,6 @@ begin
proc_dp_verify_value(e_equal, clk, verify_done_arr(I), expected_out_bsn(I), prev_out_bsn(I));
end generate;
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -456,5 +447,4 @@ begin
src_in_arr => out_siso_arr,
src_out_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
index e2f52dd07a681b6712f7a01f1dde15fc85342dff..13cb45b509ea464702b6c627a0a84b91ed24fb89 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source.vhd
@@ -43,7 +43,6 @@ entity tb_mms_dp_bsn_source is
end tb_mms_dp_bsn_source;
architecture tb of tb_mms_dp_bsn_source is
-
constant c_clk_period : time := 10 ns;
constant c_pps_interval : natural := 1000;
@@ -76,9 +75,7 @@ architecture tb of tb_mms_dp_bsn_source is
signal mm_mosi : t_mem_mosi := c_mem_mosi_rst;
signal mm_miso : t_mem_miso;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -179,6 +176,4 @@ begin
-- Streaming clock domain
bs_sosi => bs_sosi
);
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
index c47ce8adbf8aa4ff43ea3cf739f0b3083e582bf2..a17112b675391a6860eea2cd7e987707435a3b99 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd
@@ -44,7 +44,6 @@ entity tb_mms_dp_bsn_source_v2 is
end tb_mms_dp_bsn_source_v2;
architecture tb of tb_mms_dp_bsn_source_v2 is
-
constant c_bsn_time_offset_w : natural := 10;
constant c_clk_period : time := 10 ns;
@@ -82,9 +81,7 @@ architecture tb of tb_mms_dp_bsn_source_v2 is
signal mm_mosi : t_mem_mosi := c_mem_mosi_rst;
signal mm_miso : t_mem_miso;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -204,6 +201,4 @@ begin
-- Streaming clock domain
bs_sosi => bs_sosi
);
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
index 55a275319510dcff3f118138000e4cbc7dcaf5c8..f37559d35294d2e80d2fbac675d336b5234596fa 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_fields.vhd
@@ -30,9 +30,7 @@ use common_lib.tb_common_mem_pkg.all;
entity tb_mms_dp_fields is
end tb_mms_dp_fields;
-
architecture tb of tb_mms_dp_fields is
-
constant clk_period : time := 10 ns;
constant c_delay_len : natural := 3;
@@ -52,9 +50,7 @@ architecture tb of tb_mms_dp_fields is
signal mm_mosi : t_mem_mosi;
signal mm_miso : t_mem_miso;
-
begin
-
clk <= not clk after clk_period / 2;
rst <= '0' after 100 ns;
@@ -102,5 +98,4 @@ begin
wait;
end process;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd
index 7fc96c30e14e24fc4496fda5834bc5637cd875ad..006cf2502a0dd7604329f506e1cebcf9c53d239a 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_fifo_fill.vhd
@@ -60,9 +60,7 @@ entity tb_mms_dp_fifo_fill is
);
end tb_mms_dp_fifo_fill;
-
architecture tb of tb_mms_dp_fifo_fill is
-
constant c_nof_regs_per_stream : natural := 3;
constant c_reg_used_words_offset : natural := 0;
constant c_reg_fifo_flags : natural := 1;
@@ -97,9 +95,7 @@ architecture tb of tb_mms_dp_fifo_fill is
signal in_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
signal out_siso_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -214,5 +210,4 @@ begin
src_in_arr => out_siso_arr,
src_out_arr => open
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
index e86703b12a8f14af81d6a3304db6d738dabf0e9b..3ec6d1732919742453554344f93c588e96728474 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_parallel_arr.vhd
@@ -28,7 +28,6 @@
-- In wave window view sosi.data,re,im in radix decimal
-- The tb is self stopping and self checking.
-
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -41,7 +40,6 @@ use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_mms_dp_force_data_parallel_arr is
generic (
g_flow_control_stimuli : t_dp_flow_control_enum := e_random; -- always active or random stimuli valid flow control
@@ -61,9 +59,7 @@ entity tb_mms_dp_force_data_parallel_arr is
);
end tb_mms_dp_force_data_parallel_arr;
-
architecture tb of tb_mms_dp_force_data_parallel_arr is
-
constant c_mm_clk_period : time := 20 ns;
constant c_dp_clk_period : time := 10 ns;
constant c_cross_clock_domain_latency : natural := 20;
@@ -105,9 +101,7 @@ architecture tb of tb_mms_dp_force_data_parallel_arr is
signal reg_force_data_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_force_data_miso : t_mem_miso;
-
begin
-
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
dp_rst <= '1', '0' after c_dp_clk_period * 7;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
index 56b7209aab7b36a60eb298fcdb9a10835adda135..4b9c1555db8bd952e4309078712723405c2ee357 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_force_data_serial_arr.vhd
@@ -28,7 +28,6 @@
-- In wave window view sosi.data,re,im in radix decimal
-- The tb is self stopping and self checking.
-
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -41,7 +40,6 @@ use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_mms_dp_force_data_serial_arr is
generic (
g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
@@ -59,9 +57,7 @@ entity tb_mms_dp_force_data_serial_arr is
);
end tb_mms_dp_force_data_serial_arr;
-
architecture tb of tb_mms_dp_force_data_serial_arr is
-
constant c_mm_clk_period : time := 20 ns;
constant c_dp_clk_period : time := 10 ns;
constant c_cross_clock_domain_latency : natural := 20;
@@ -103,9 +99,7 @@ architecture tb of tb_mms_dp_force_data_serial_arr is
signal reg_force_data_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_force_data_miso : t_mem_miso;
-
begin
-
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
dp_rst <= '1', '0' after c_dp_clk_period * 7;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
index ba8e803f1f010eeb6ff153a196ebe5234cd71efd..17f42645099e64f6308b8cf4ada29af437ac11ac 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_arr.vhd
@@ -27,7 +27,6 @@
-- > run -all
-- The tb is self stopping and self checking.
-
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -40,7 +39,6 @@ use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_mms_dp_gain_arr is
generic (
g_technology : natural := c_tech_select_default;
@@ -51,9 +49,7 @@ entity tb_mms_dp_gain_arr is
);
end tb_mms_dp_gain_arr;
-
architecture tb of tb_mms_dp_gain_arr is
-
constant c_mm_clk_period : time := 20 ns;
constant c_dp_clk_period : time := 10 ns;
constant c_cross_clock_domain_latency : natural := 20;
@@ -100,9 +96,7 @@ architecture tb of tb_mms_dp_gain_arr is
signal reg_gain_re_miso : t_mem_miso;
signal reg_gain_im_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_gain_im_miso : t_mem_miso;
-
begin
-
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
dp_rst <= '1', '0' after c_dp_clk_period * 7;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
index ac6a6dfac11a06d731fcc044739d9380ca64eee1..5c3eb335710ae69024aace5541034dd4cbbeed2a 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_gain_serial_arr.vhd
@@ -26,7 +26,6 @@
-- > run -all
-- The tb is self stopping and self checking.
-
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -39,7 +38,6 @@ use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_mms_dp_gain_serial_arr is
generic (
g_technology : natural := c_tech_select_default;
@@ -51,9 +49,7 @@ entity tb_mms_dp_gain_serial_arr is
);
end tb_mms_dp_gain_serial_arr;
-
architecture tb of tb_mms_dp_gain_serial_arr is
-
constant c_mm_clk_period : time := 20 ns;
constant c_dp_clk_period : time := 10 ns;
constant c_cross_clock_domain_latency : natural := 20;
@@ -110,9 +106,7 @@ architecture tb of tb_mms_dp_gain_serial_arr is
signal ram_gains_miso : t_mem_miso;
signal gains_rd_address : std_logic_vector(c_nof_gains_w - 1 downto 0) := TO_UVEC(0, c_nof_gains_w); -- DP read side, same read address for all streams
signal gains_rd_address_dly : std_logic_vector(c_nof_gains_w - 1 downto 0);
-
begin
-
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
dp_rst <= '1', '0' after c_dp_clk_period * 7;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
index d3012fd5dd87be7422d0d754da7fef502ef22f27..869118a7093356714846a9b1b875edcf20b6b106 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_scale.vhd
@@ -40,13 +40,10 @@ use work.dp_stream_pkg.all;
use work.tb_dp_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_mms_dp_scale is
end tb_mms_dp_scale;
-
architecture tb of tb_mms_dp_scale is
-
constant c_mm_clk_period : time := 20 ns;
constant c_dp_clk_period : time := 10 ns;
constant c_cross_clock_domain_latency : natural := 20;
@@ -89,9 +86,7 @@ architecture tb of tb_mms_dp_scale is
signal reg_gain_re_miso : t_mem_miso;
signal reg_gain_im_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_gain_im_miso : t_mem_miso;
-
begin
-
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
dp_rst <= '1', '0' after c_dp_clk_period * 7;
@@ -189,5 +184,4 @@ begin
in_sosi => in_sosi,
out_sosi => out_sosi
);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
index da263914f8b47d23b4d2a3bbfb101301944a5873..16982fd0cd2d2d5cb093db045f5c484db15be653 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_sync_checker.vhd
@@ -62,9 +62,7 @@ entity tb_mms_dp_sync_checker is
);
end tb_mms_dp_sync_checker;
-
architecture tb of tb_mms_dp_sync_checker is
-
constant c_mm_clk_period : time := 30 ns; -- 40 MHz
constant c_rl : natural := 1;
constant c_no_dut : boolean := true;
@@ -127,9 +125,7 @@ architecture tb of tb_mms_dp_sync_checker is
signal mm_nof_early_syncs : std_logic_vector(c_word_w - 1 downto 0);
signal mm_nof_late_syncs : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -153,7 +149,6 @@ begin
random_1(random_1'high) when g_flow_control_verify = e_random else
pulse_1 when g_flow_control_verify = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -290,8 +285,6 @@ begin
reg_dp_sync_checker_miso => mm_miso
);
-
-
-- Connect DUT source output stream to verification
dut_src_in <= verify_snk_out;
verify_snk_in <= dut_src_out;
@@ -305,7 +298,4 @@ begin
verify_data <= verify_snk_in.data(g_in_dat_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data when verify_snk_in.valid = '1';
-
end tb;
-
-
diff --git a/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
index 4121a346b62f4ab7bb2bb370669d9a7e851bc72d..25c9376f2c966daf026e5145b91bff0f0b88cdda 100644
--- a/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_mms_dp_xonoff.vhd
@@ -61,7 +61,6 @@ entity tb_mms_dp_xonoff is
end tb_mms_dp_xonoff;
architecture tb of tb_mms_dp_xonoff is
-
constant c_nof_streams : natural := 4;
constant c_pulse_active : natural := g_in_nof_words;
@@ -91,14 +90,10 @@ architecture tb of tb_mms_dp_xonoff is
signal mm_mosi : t_mem_mosi;
signal mm_miso : t_mem_miso;
-
begin
-
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -220,6 +215,4 @@ begin
wait;
end process;
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
index 3214efff2c19dab2cfbef2eb9fe12024629a2126..85eb2eafed9aa8456f06fddad6a6f9d1d65e8802 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb2_dp_demux.vhd
@@ -24,18 +24,15 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
-- > as 2
-- > run -all --> OK
entity tb_tb2_dp_demux is
end tb_tb2_dp_demux;
-
architecture tb of tb_tb2_dp_demux is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- in_en, src_in.ready, in_channel, nof_repeat, nof_streams, mode_demux, mode_mux, use_channel_lo, combined_demux
-- Framed mode 0
u0_rnd_rnd : entity work.tb2_dp_demux generic map (e_random, e_random, 1, 30, 3, 0, 0, true, false);
@@ -49,6 +46,4 @@ begin
u2_rnd_rnd : entity work.tb2_dp_demux generic map (e_random, e_random, 1, 30, 3, 2, 2, false, false);
u2_rnd_rnd_comb : entity work.tb2_dp_demux generic map (e_random, e_random, 1, 30, 3, 2, 2, false, true);
u2_rnd_pls : entity work.tb2_dp_demux generic map (e_random, e_pulse, 1, 30, 3, 2, 2, false, false);
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd
index fd91af5ef83f1eec69884b458289aaf471a6b613..a82257f8883763a4693ac6d6b4d3bb5d02c8c525 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb2_dp_mux.vhd
@@ -24,21 +24,16 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
-- > as 2
-- > run -all --> OK
entity tb_tb2_dp_mux is
end tb_tb2_dp_mux;
-
architecture tb of tb_tb2_dp_mux is
-
constant c_nof_repeat : natural := 10;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- Select next input when eop has occurred or when this input has had an active ready (so it has had a fair chance)
-- in_en, src_in.ready, g_mux_mode, g_mux_use_fifo, g_mux_fifo_fill, g_combined_demux, nof repeat
u0_act_act : entity work.tb2_dp_mux generic map (e_active, e_active, 0, false, 0, false, c_nof_repeat);
diff --git a/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd
index 1169f2266957ad8c378e28c7e0de036c51edaac6..5d6bee41f597727283dbd2d0cd40b85c27762993 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb3_dp_demux.vhd
@@ -24,22 +24,17 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
-- > as 2
-- > run -all --> OK
entity tb_tb3_dp_demux is
end tb_tb3_dp_demux;
-
architecture tb of tb_tb3_dp_demux is
-
constant c_nof_outputs : natural := 3;
constant c_nof_repeat : natural := c_nof_outputs * 10;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- Select input via sel_ctrl (g_mode=2)
-- in_en, src_in.ready, nof repeat, nof_outputs
u0_act_act : entity work.tb3_dp_demux generic map (e_active, e_active, c_nof_repeat, c_nof_outputs);
@@ -53,5 +48,4 @@ begin
u0_pls_act : entity work.tb3_dp_demux generic map (e_pulse, e_active, c_nof_repeat, c_nof_outputs);
u0_pls_rnd : entity work.tb3_dp_demux generic map (e_pulse, e_random, c_nof_repeat, c_nof_outputs);
u0_pls_pls : entity work.tb3_dp_demux generic map (e_pulse, e_pulse, c_nof_repeat, c_nof_outputs);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd
index af85f4c9dbb8cbccdb92948424b4c79af03a592e..140f3d8ff14c0a758aed373ec818844eee635f48 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb3_dp_mux.vhd
@@ -24,22 +24,17 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
-- > as 2
-- > run -all --> OK
entity tb_tb3_dp_mux is
end tb_tb3_dp_mux;
-
architecture tb of tb_tb3_dp_mux is
-
constant c_nof_inputs : natural := 3;
constant c_nof_repeat : natural := c_nof_inputs * 10;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- Select input via sel_ctrl (g_mode=2)
-- in_en, src_in.ready, nof repeat, nof_inputs
u0_act_act : entity work.tb3_dp_mux generic map (e_active, e_active, c_nof_repeat, c_nof_inputs);
@@ -53,5 +48,4 @@ begin
u0_pls_act : entity work.tb3_dp_mux generic map (e_pulse, e_active, c_nof_repeat, c_nof_inputs);
u0_pls_rnd : entity work.tb3_dp_mux generic map (e_pulse, e_random, c_nof_repeat, c_nof_inputs);
u0_pls_pls : entity work.tb3_dp_mux generic map (e_pulse, e_pulse, c_nof_repeat, c_nof_inputs);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
index d471109778b9a56dff0af8ab9db592ad3c0c2664..fcca299fdb1e63e1da649b0038fdff3f89b5b834 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_from_mm.vhd
@@ -33,11 +33,9 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_block_from_mm is
end tb_tb_dp_block_from_mm;
-
architecture tb of tb_tb_dp_block_from_mm is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
@@ -49,6 +47,4 @@ begin
u4_tst_2_6_256 : entity work.tb_dp_block_from_mm generic map (2, 6, 256);
u5_tst_2_8_256 : entity work.tb_dp_block_from_mm generic map (2, 8, 256);
u6_tst_3_6_17 : entity work.tb_dp_block_from_mm generic map (3, 6, 17);
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
index 598d37181be180959d9ee27cb71b175fc8a81d02..ccb522b9b6a5de66e60b7e9f1e4914b8d2103602 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen.vhd
@@ -23,15 +23,12 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_block_gen is
end tb_tb_dp_block_gen;
-
architecture tb of tb_tb_dp_block_gen is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 3
-- > run -all --> OK
@@ -48,5 +45,4 @@ begin
u_snk_in_valid_1 : entity work.tb_dp_block_gen generic map (false, 11, 1, e_active, e_active, 100);
u_snk_in_valid_8 : entity work.tb_dp_block_gen generic map (false, 11, 8, e_active, e_random, 100);
u_snk_in_valid_9 : entity work.tb_dp_block_gen generic map (false, 11, 9, e_pulse, e_random, 100);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
index 3edfc19a45749987077038c567396ff625c6fb2d..a48141d0301224f1073f152e8d493d2a85aff955 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
@@ -28,11 +28,9 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_block_gen_valid_arr is
end tb_tb_dp_block_gen_valid_arr;
-
architecture tb of tb_tb_dp_block_gen_valid_arr is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
@@ -61,5 +59,4 @@ begin
u_global_input_bsn : entity work.tb_dp_block_gen_valid_arr generic map (1, 11, 8, false, 0, true, e_active, e_active, 100);
u_global_input_bsn_check_sync : entity work.tb_dp_block_gen_valid_arr generic map (1, 11, 9, true, 0, true, e_active, e_active, 100);
u_buffer_global_input_bsn : entity work.tb_dp_block_gen_valid_arr generic map (1, 11, 5, false, 1, true, e_active, e_active, 100);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd
index 7c4b2ba3eb89f2844e6e44123d879db109e9e544..c9853ef71bf936d8a8e6d1fd46c29ac9ae52d945 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape.vhd
@@ -26,15 +26,12 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_block_reshape is
end tb_tb_dp_block_reshape;
-
architecture tb of tb_tb_dp_block_reshape is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 5
-- > run -all --> OK
@@ -42,5 +39,4 @@ begin
u_comb : entity work.tb_dp_block_reshape generic map (0);
u_pipe : entity work.tb_dp_block_reshape generic map (1);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
index 3d5c9a4b50de6ce0f70bdc59bcb9d26439f7ee23..d137defec7fea84cf0b0b760bbe2f292aa741fb6 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_reshape_sync.vhd
@@ -26,15 +26,12 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_block_reshape_sync is
end tb_tb_dp_block_reshape_sync;
-
architecture tb of tb_tb_dp_block_reshape_sync is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 5
-- > run -all --> OK
@@ -46,7 +43,6 @@ begin
-- g_pipeline_src_out : NATURAL := 0;
-- g_pipeline_src_in : NATURAL := 0
-
-- nof reshape sync > nof input sync, so reshape sync intervals are shorter
u_more_comb : entity work.tb_dp_block_reshape_sync generic map (9, 12, 18, 3, false, 0, 0);
u_more_pipe : entity work.tb_dp_block_reshape_sync generic map (9, 12, 18, 3, false, 0, 0);
@@ -56,5 +52,4 @@ begin
-- nof reshape sync < nof input sync, so reshape sync intervals are longer
u_less_bsn_channel_pipe_src_out : entity work.tb_dp_block_reshape_sync generic map (9, 12, 18, 12, true, 1, 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd
index efb2e23d31d86e1d6d3311fdcb0caebd99301604..e4ea053afe14cfa5de819d77d04b17a3fa2400fe 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_select.vhd
@@ -33,16 +33,12 @@ use IEEE.std_logic_1164.all;
entity tb_tb_dp_block_select is
end tb_tb_dp_block_select;
-
architecture tb of tb_tb_dp_block_select is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_length : natural := 5;
constant c_end : natural := c_length - 1;
-
begin
-
-- g_dut_pipeline : NATURAL := 1;
-- g_nof_blocks_per_sync : NATURAL := c_length;
-- g_index_lo : NATURAL := 0;
@@ -58,5 +54,4 @@ begin
u_end : entity work.tb_dp_block_select generic map(1, c_length, c_end - 1, c_end - 1); -- pass only block at last index
u_none : entity work.tb_dp_block_select generic map(1, c_length, 3, 2); -- pass no block because hi index < lo index
u_none_end : entity work.tb_dp_block_select generic map(1, c_length, c_end + 1, c_end + 1); -- pass no block because lo index >= c_length
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd
index d7b934cce40927ef748046fdda45185d6af12db4..5b129050dabd583f802ade516aed9641d4e96596 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_bsn_at_sync.vhd
@@ -32,14 +32,11 @@ use IEEE.std_logic_1164.all;
entity tb_tb_dp_block_validate_bsn_at_sync is
end tb_tb_dp_block_validate_bsn_at_sync;
-
architecture tb of tb_tb_dp_block_validate_bsn_at_sync is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_blk_per_sync : natural := 5;
constant c_data_per_blk : natural := 9;
-
begin
-- g_nof_blocks_per_sync : NATURAL := 5;
-- g_nof_data_per_blk : NATURAL := 6;
@@ -48,5 +45,4 @@ begin
u_smaller : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync - 4); -- g_bsn_init < g_nof_blocks_per_sync
u_equal : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync); -- g_bsn_init = g_nof_blocks_per_sync
u_larger : entity work.tb_dp_block_validate_bsn_at_sync generic map(c_blk_per_sync, c_data_per_blk, c_blk_per_sync + 4); -- g_bsn_init > g_nof_blocks_per_sync
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd
index 72b0bc3f909a47e7f77255b57253c4e9ce26bee6..b88c0ada78e20629293e9c54078a918100d1a28d 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_channel.vhd
@@ -32,15 +32,12 @@ use IEEE.std_logic_1164.all;
entity tb_tb_dp_block_validate_channel is
end tb_tb_dp_block_validate_channel;
-
architecture tb of tb_tb_dp_block_validate_channel is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_blk_per_sync : natural := 5;
constant c_data_per_blk : natural := 9;
constant c_gap_size : natural := 5;
-
begin
-- g_nof_blocks_per_sync : NATURAL := 8;
-- g_nof_data_per_blk : NATURAL := 8;
@@ -51,5 +48,4 @@ begin
u_equal : entity work.tb_dp_block_validate_channel generic map(c_blk_per_sync, c_data_per_blk, c_gap_size, 7, "=");
u_smaller : entity work.tb_dp_block_validate_channel generic map(c_blk_per_sync, c_data_per_blk, c_gap_size, 7, "<");
u_greater : entity work.tb_dp_block_validate_channel generic map(c_blk_per_sync, c_data_per_blk, c_gap_size, 7, ">");
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd
index 6ee7473a84bd1cffc996c60595dfa6a7a33560de..da1be4d735b6b2a9794649f363e63801b82558f9 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_err.vhd
@@ -32,16 +32,13 @@ use IEEE.std_logic_1164.all;
entity tb_tb_dp_block_validate_err is
end tb_tb_dp_block_validate_err;
-
architecture tb of tb_tb_dp_block_validate_err is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_blk_per_sync : natural := 5;
constant c_data_per_blk : natural := 9;
constant c_max_block_size : natural := 9;
constant c_nof_err_counts : natural := 5;
-
begin
-- g_nof_blocks_per_sync : NATURAL := 5;
-- g_nof_data_per_blk : NATURAL := 9;
@@ -57,5 +54,4 @@ begin
u_small_gap : entity work.tb_dp_block_validate_err generic map(c_blk_per_sync, c_data_per_blk, c_max_block_size, c_nof_err_counts, 1, 16);
u_large_gap : entity work.tb_dp_block_validate_err generic map(c_blk_per_sync, c_data_per_blk, c_max_block_size, c_nof_err_counts, 100, 16);
u_low_nof_cnt : entity work.tb_dp_block_validate_err generic map(c_blk_per_sync, c_data_per_blk, c_max_block_size, 1, 1, 16);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd
index d18309018a9611eb49b9acf4888f0e7548242f96..c5ec1d291f3a17a60ba6e59ffa5ac9921cabd9db 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_block_validate_length.vhd
@@ -32,18 +32,14 @@ use IEEE.std_logic_1164.all;
entity tb_tb_dp_block_validate_length is
end tb_tb_dp_block_validate_length;
-
architecture tb of tb_tb_dp_block_validate_length is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_blk_per_sync : natural := 5;
constant c_data_per_blk : natural := 9;
constant c_exp_length : natural := 9;
constant c_err_bi : natural := 3;
-
begin
-
-- g_nof_blocks_per_sync : NATURAL := 5;
-- g_nof_data_per_blk : NATURAL := 9;
-- g_expected_length : NATURAL := 3;
@@ -52,5 +48,4 @@ begin
u_equal : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length, c_err_bi); -- g_expected_length = g_nof_data_per_blk
u_smaller : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length - 3, c_err_bi); -- g_expected_length < g_nof_data_per_blk
u_larger : entity work.tb_dp_block_validate_length generic map(c_blk_per_sync, c_data_per_blk, c_exp_length + 3, c_err_bi); -- g_expected_length > g_nof_data_per_blk
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd
index dbb098d933fd49f70a176ee5d81f6092e65f755f..98e4893c43033657c41f21a070536c99fb1eda66 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align.vhd
@@ -23,13 +23,10 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_bsn_align is
end tb_tb_dp_bsn_align;
-
architecture tb of tb_tb_dp_bsn_align is
-
constant c_block_size : natural := 11;
constant c_diff_delay : natural := 20;
constant c_diff_bsn : natural := 3; -- g_diff_bsn = g_bsn_latency can just be aligned
@@ -38,7 +35,6 @@ architecture tb of tb_tb_dp_bsn_align is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 2
-- > run -all --> OK
@@ -60,5 +56,4 @@ begin
u_rnd_16_2 : entity work.tb_dp_bsn_align generic map (c_block_size, c_diff_delay, c_diff_bsn, 16, c_bsn_latency, 2, e_random, c_nof_repeat);
u_rnd_16_3 : entity work.tb_dp_bsn_align generic map (c_block_size, c_diff_delay, c_diff_bsn, 16, c_bsn_latency, 3, e_random, c_nof_repeat);
u_rnd_16_4 : entity work.tb_dp_bsn_align generic map (c_block_size, c_diff_delay, c_diff_bsn, 16, c_bsn_latency, 4, e_random, c_nof_repeat);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
index 395d1907802bddd7c64e8292f99a40ad3b0f7c50..d1ac6698b74d433a03b75d037ee651dafc42690b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_align_v2.vhd
@@ -27,21 +27,16 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_bsn_align_v2 is
end tb_tb_dp_bsn_align_v2;
-
architecture tb of tb_tb_dp_bsn_align_v2 is
-
constant c_block : natural := 11;
constant c_period : natural := 20;
constant c_nof_blk : natural := 30;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- DUT
-- g_nof_streams : NATURAL := 2; -- number of input and output streams
-- g_bsn_latency_max : NATURAL := 1; -- Maximum travel latency of a remote block in number of block periods T_blk
@@ -87,5 +82,4 @@ begin
u_diff_delay : entity work.tb_dp_bsn_align_v2 generic map (3, 1, 1, c_block, c_period, 32, 16, 17, 0, 0, 0, 3, false, 0, 0, 1, -1, 2, c_nof_blk);
u_nof_aligners : entity work.tb_dp_bsn_align_v2 generic map (2, 1, 8, c_block, c_period, 32, 16, 17, 0, 0, 0, 3, false, 0, 0, 1, 0, 2, c_nof_blk);
u_nof_aligners_diff_delay : entity work.tb_dp_bsn_align_v2 generic map (4, 1, 3, c_block, c_period, 32, 16, 17, 0, 0, 0, 3, false, 0, 0, 1, -1, 2, c_nof_blk);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
index e53132411dd065878f4cc01cb461ee35c238fac9..cf58ac3979680f51c4e2c4490e2a15a0b650884c 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
@@ -24,18 +24,14 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
-- > as 4
-- > run -all --> OK
entity tb_tb_dp_bsn_source_v2 is
end tb_tb_dp_bsn_source_v2;
-
architecture tb of tb_tb_dp_bsn_source_v2 is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-- from tb_dp_bsn_source_v2.vhd
--
@@ -71,6 +67,4 @@ begin
-- test some prime values
u_17_3 : entity work.tb_dp_bsn_source_v2 generic map (17, 3); -- 17 // 3 = 5, 17 MOD 3 = 2, 17/3 = 5.66 block/sync
u_101_17 : entity work.tb_dp_bsn_source_v2 generic map (101, 17); -- 101 // 17 = 5, 101 MOD 17 = 16, 101/17 = 5.9411 block/sync
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
index e1286df5cf1f3cf5d3cedc7bd5caf85929ecd609..23ff128bc48cb46e2d63ba907fd44af18251c189 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
@@ -26,14 +26,12 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
-- > as 4
-- > run -all --> OK
entity tb_tb_dp_bsn_sync_scheduler is
end tb_tb_dp_bsn_sync_scheduler;
-
architecture tb of tb_tb_dp_bsn_sync_scheduler is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
@@ -43,7 +41,6 @@ architecture tb of tb_tb_dp_bsn_sync_scheduler is
-- dp_bsn_scheduler.vhd.
constant c_nof_input_sync : natural := 25;
constant c_pipeline : natural := 1;
-
begin
-- from tb_dp_bsn_scheduler.vhd
--
@@ -81,4 +78,3 @@ begin
end generate;
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd
index 2a92925a254289a9ce781b792eaf1699b6c49b86..b3bf5be97e85af7f05328d5db14e210e0b0d1605 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_calculate_crc.vhd
@@ -40,18 +40,13 @@ use work.tb_dp_pkg.all;
entity tb_tb_dp_calculate_crc is
end tb_tb_dp_calculate_crc;
-
architecture tb of tb_tb_dp_calculate_crc is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_data_w : NATURAL := 28;
-- g_crc_w : NATURAL := 28;
-- g_gap_size : NATURAL := 10
u_no_gap : entity work.tb_dp_calculate_crc generic map (28, 28, 0);
u_gap : entity work.tb_dp_calculate_crc generic map (28, 28, 10);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd
index bbd6541b661352c87d8087e7d42d5bdc73cb1902..502254befc42e5c4685ef3211b90e0354dacfb09 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat.vhd
@@ -29,7 +29,6 @@ end tb_tb_dp_concat;
architecture tb of tb_tb_dp_concat is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run 300 us --> OK
@@ -44,5 +43,4 @@ begin
u_nof_2_rnd : entity work.tb_dp_concat generic map (2 * 16, 16, true);
u_nof_3_rnd : entity work.tb_dp_concat generic map (3 * 16, 16, true);
u_nof_4_rnd : entity work.tb_dp_concat generic map (4 * 16, 16, true);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd
index 6a8a85c3deb560ba1e80bcc394a6d0fced059a74..69e2c6d1f757a4890e9e79ce2f47ffe4d8f9cf46 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_concat_field_blk.vhd
@@ -25,20 +25,16 @@
-- > as 5
-- > run -all --> OK
-
library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_concat_field_blk is
end tb_tb_dp_concat_field_blk;
-
architecture tb of tb_tb_dp_concat_field_blk is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -50,5 +46,4 @@ begin
u_large_gap : entity work.tb_dp_concat_field_blk generic map (e_active, e_active, 64, 13, 100, 10); -- g_pkt_gap > header length
u_zero_gap : entity work.tb_dp_concat_field_blk generic map (e_active, e_active, 64, 13, 100, 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd
index 219f007cb23cc371448de5b5a95b224a0ea7d337..d97d8f4ae2c8c23306ebc94389ea08aa1aafde4a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_counter.vhd
@@ -34,13 +34,9 @@ use work.tb_dp_pkg.all;
entity tb_tb_dp_counter is
end tb_tb_dp_counter;
-
architecture tb of tb_tb_dp_counter is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
@@ -60,5 +56,4 @@ begin
u_rnd_rnd_comb : entity work.tb_dp_counter generic map (e_random, e_random, 0, 0, 3);
u_rnd_rnd_pipe_out : entity work.tb_dp_counter generic map (e_random, e_random, 1, 0, 3);
u_rnd_rnd_pipe_in : entity work.tb_dp_counter generic map (e_random, e_random, 0, 1, 3);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd
index 997d70b2bd46a170a8312fc487a93e9d6bd4882e..4f1ab4f582d5d132b46e3c6f3f5617525155be2a 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_interleave_to_one.vhd
@@ -34,16 +34,12 @@ use work.tb_dp_pkg.all;
entity tb_tb_dp_deinterleave_interleave_to_one is
end tb_tb_dp_deinterleave_interleave_to_one;
-
architecture tb of tb_tb_dp_deinterleave_interleave_to_one is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_rep_act : natural := 5;
constant c_rep_rnd : natural := 100;
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
-- -- specific
@@ -80,5 +76,4 @@ begin
u_act_3_12_0_complex : entity work.tb_dp_deinterleave_interleave_to_one generic map(e_active, true, c_rep_act, 3, 12, 0);
u_pls_3_12_0 : entity work.tb_dp_deinterleave_interleave_to_one generic map(e_pulse, false, c_rep_rnd, 3, 12, 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd
index 4920cb3708044e7342c982c4841ee934b793bf02..45d727f2a60c181bd25a5cda2d6718b0479b57e4 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_deinterleave_one_to_n_to_one.vhd
@@ -34,16 +34,12 @@ use work.tb_dp_pkg.all;
entity tb_tb_dp_deinterleave_one_to_n_to_one is
end tb_tb_dp_deinterleave_one_to_n_to_one;
-
architecture tb of tb_tb_dp_deinterleave_one_to_n_to_one is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_rep_act : natural := 5;
constant c_rep_rnd : natural := 100;
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -82,5 +78,4 @@ begin
u_pls_pls_pipe_3_12_0 : entity work.tb_dp_deinterleave_one_to_n_to_one generic map(e_pulse, e_pulse, true, false, 1, c_rep_rnd, 3, 12, 0);
u_rnd_rnd_comb_3_12_0 : entity work.tb_dp_deinterleave_one_to_n_to_one generic map(e_random, e_random, true, false, 0, c_rep_rnd, 3, 12, 0);
u_rnd_rnd_pipe_3_12_0 : entity work.tb_dp_deinterleave_one_to_n_to_one generic map(e_random, e_random, true, false, 1, c_rep_rnd, 3, 12, 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd
index 5bd8e9f12366b75c375c11e0f76e479eec973f93..a027706fbe9969188326b4320cd5c321f05d7311 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_demux.vhd
@@ -25,15 +25,12 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_demux is
end tb_tb_dp_demux;
-
architecture tb of tb_tb_dp_demux is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run 300 us --> OK
@@ -46,5 +43,4 @@ begin
u_nof_1_reg : entity work.tb_dp_demux generic map (1, false);
u_nof_2_reg : entity work.tb_dp_demux generic map (2, false);
u_nof_3_reg : entity work.tb_dp_demux generic map (3, false);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd
index dbcb3fa42959998110be5f0c66c14e4e5e55b0c6..50a0a330ecdc3ef19cf46a2a4022ef31955d5f1e 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_distribute.vhd
@@ -25,15 +25,12 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_distribute is
end tb_tb_dp_distribute;
-
architecture tb of tb_tb_dp_distribute is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run -all --> OK
@@ -92,5 +89,4 @@ begin
u_rnd_rnd_3_4_coding_fifo_tx : entity work.tb_dp_distribute generic map (e_random, e_random, 50, true, true, 15, false, 0, 10, 0, 3, 4, true);
u_rnd_rnd_4_3_coding_fifo_tx_rx : entity work.tb_dp_distribute generic map (e_random, e_random, 50, true, true, 15, true, 15, 10, 0, 4, 3, true);
u_rnd_rnd_3_4_coding_fifo_tx_rx : entity work.tb_dp_distribute generic map (e_random, e_random, 50, true, true, 15, true, 15, 10, 0, 3, 4, true);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd
index 07fdc0a274a04892214c68ce3e37da44f51ed2d1..df13417b871fcfd880f7d23d81ba3ffa01da6551 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_dut.vhd
@@ -34,18 +34,14 @@ use work.tb_dp_pkg.all;
entity tb_tb_dp_example_dut is
end tb_tb_dp_example_dut;
-
architecture tb of tb_tb_dp_example_dut is
-
constant c_nof_repeat : natural := 10;
constant c_flow : t_dp_flow_control_enum_arr := c_dp_flow_control_enum_arr;
constant c_bool : t_nat_boolean_arr := c_nat_boolean_arr;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
@@ -63,5 +59,4 @@ begin
end generate;
end generate;
end generate;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
index e15807ddd504e2f422a0c50ee0baee7bbd10675f..3da7df71cedbf8d9729d0d41e7a28ce362afd875 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_example_no_dut.vhd
@@ -33,14 +33,10 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_dp_example_no_dut is
end tb_tb_dp_example_no_dut;
-
architecture tb of tb_tb_dp_example_no_dut is
-
constant c_nof_repeat : natural := 10;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always active, random or pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
@@ -55,5 +51,4 @@ begin
u_rnd_act : entity work.tb_dp_example_no_dut generic map ( e_random, e_active, 16, 1, c_nof_repeat, 16, 4);
u_rnd_rnd : entity work.tb_dp_example_no_dut generic map ( e_random, e_random, 16, 1, c_nof_repeat, 16, 4);
u_pls_pls : entity work.tb_dp_example_no_dut generic map ( e_pulse, e_pulse, 16, 1, c_nof_repeat, 16, 4);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd
index ed39753a369a418cf6231c9c722ab14fe9069b11..46f94d01c39dd7ac977436eed19e994b2f8f7703 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc.vhd
@@ -23,15 +23,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_dp_fifo_dc is
end tb_tb_dp_fifo_dc;
-
architecture tb of tb_tb_dp_fifo_dc is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run g_dut_rd_clk_freq * 330 us --> OK
@@ -59,5 +56,4 @@ begin
u_no_channel : entity work.tb_dp_fifo_dc generic map (1, 1, true, true, false, true, true, 1);
u_no_sync : entity work.tb_dp_fifo_dc generic map (1, 1, true, true, true, false, true, 1);
u_no_ctrl : entity work.tb_dp_fifo_dc generic map (1, 1, true, true, true, true, false, 1);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
index 91a5b2a74808faf59c8a057a46e1f36f2552d144..2df85ef7d265b365d55a06ab03511763ad89f841 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_arr.vhd
@@ -26,15 +26,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_dp_fifo_dc_arr is
end tb_tb_dp_fifo_dc_arr;
-
architecture tb of tb_tb_dp_fifo_dc_arr is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run g_dut_rd_clk_freq * 330 us --> OK
@@ -63,5 +60,4 @@ begin
u_no_sync : entity work.tb_dp_fifo_dc_arr generic map (3, 1, 1, true, true, true, false, true, true, 1);
u_no_ctrl : entity work.tb_dp_fifo_dc_arr generic map (3, 1, 1, true, true, true, true, false, true, 1);
u_no_aux : entity work.tb_dp_fifo_dc_arr generic map (3, 1, 1, true, true, true, true, true, false, 1);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
index 61b8c7c6966c526b7d69ed5b6571a810be1e58fd..71f4afcd3252c3ef0a4757064aca5bd870f76417 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_dc_mixed_widths.vhd
@@ -22,15 +22,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_dp_fifo_dc_mixed_widths is
end tb_tb_dp_fifo_dc_mixed_widths;
-
architecture tb of tb_tb_dp_fifo_dc_mixed_widths is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 5
-- > run 100 us --> OK
@@ -66,5 +63,4 @@ begin
u_seq_nof_1_rl_1_rnd : entity work.tb_dp_fifo_dc_mixed_widths generic map ( true, 10 ns, 10 ns, 16, 1, false, 1);
u_seq_nof_2_rl_1_rnd : entity work.tb_dp_fifo_dc_mixed_widths generic map ( true, 10 ns, 10 ns, 16, 2, false, 1);
--u_seq_nof_3_rl_1_rnd : ENTITY work.tb_dp_fifo_dc_mixed_widths GENERIC MAP ( TRUE, 10 ns, 10 ns, 16, 3, FALSE, 1);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd
index 44537192f1806bc926876e4f2d09a7ca00cecade..8bed5bd9378792527c7d55c1c1ab2f388db1c237 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill.vhd
@@ -23,15 +23,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_dp_fifo_fill is
end tb_tb_dp_fifo_fill;
-
architecture tb of tb_tb_dp_fifo_fill is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run 300 us --> OK
@@ -50,5 +47,4 @@ begin
u_rl_0_fill_0 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 0, 64, 0); -- no fill ==> dp_fifo_sc
u_rl_0_fill_1 : entity work.tb_dp_fifo_fill generic map (false, false, false, false, 0, 64, 1);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
index 60fe18d02750d66821a9ea577a1cef2dcf705ffe..4c793ad5223d74a6977a46f7e99016fa72cea803 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_eop.vhd
@@ -37,11 +37,9 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_dp_fifo_fill_eop is
end tb_tb_dp_fifo_fill_eop;
-
architecture tb of tb_tb_dp_fifo_fill_eop is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
@@ -74,5 +72,4 @@ begin
u_dut_sc_1_blk_gt_fill : entity work.tb_dp_fifo_fill_eop generic map (g_dut_use_dual_clock => false, g_dut_fifo_rl => 1, g_dut_use_random_ctrl => false, g_dut_use_gap => false,
g_dut_fifo_fill => 10, g_block_size => 20);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
index 682440760229a827ca694fa51b6ad2f0efe09092..c6711c48e2362da593b3cfdbd8694d5e58eacb3e 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_fill_sc.vhd
@@ -23,15 +23,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_dp_fifo_fill_sc is
end tb_tb_dp_fifo_fill_sc;
-
architecture tb of tb_tb_dp_fifo_fill_sc is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run 300 us --> OK
@@ -53,5 +50,4 @@ begin
u_rl_0_fill_control : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 0, 64, 64, true);
u_rl_1_fill_control : entity work.tb_dp_fifo_fill_sc generic map (false, false, false, false, 1, 64, 64, true);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd
index 633ad861d6439636f9370fc46985da292ba67b1d..3a1e772519e1c3fb9866d188ef631c5a27071d1d 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_info.vhd
@@ -33,14 +33,10 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_dp_fifo_info is
end tb_tb_dp_fifo_info;
-
architecture tb of tb_tb_dp_fifo_info is
-
constant c_nof_repeat : natural := 100;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_random; -- always active, random or pulse flow control
@@ -76,5 +72,4 @@ begin
u_act_act_channel : entity work.tb_dp_fifo_info generic map ( e_active, e_active, false, false, true, false, false, 8, 25, 10, 35);
u_act_act_empty : entity work.tb_dp_fifo_info generic map ( e_active, e_active, false, false, false, true, false, 8, 25, 10, 35);
u_act_act_error : entity work.tb_dp_fifo_info generic map ( e_active, e_active, false, false, false, false, true, 8, 25, 10, 35);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd
index a4c840ed65335aea2891ed696a7de5cbdc641d16..fbfee6063762a22ea32e758847fdef6f10a6a791 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_fifo_sc.vhd
@@ -23,15 +23,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_dp_fifo_sc is
end tb_tb_dp_fifo_sc;
-
architecture tb of tb_tb_dp_fifo_sc is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 5
-- > run -a --> OK
@@ -63,5 +60,4 @@ begin
u_ram_no_channel : entity work.tb_dp_fifo_sc generic map (false, 64, 4, true, true, false, true, true, 1);
u_ram_no_sync : entity work.tb_dp_fifo_sc generic map (false, 64, 4, true, true, true, false, true, 1);
u_ram_no_ctrl : entity work.tb_dp_fifo_sc generic map (false, 64, 4, true, true, true, true, false, 1);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
index b8297054b8c057b0b8902fa458e1853225a764b1..1a43d7cf5794393865fd8288cdda7fb8ee705ca5 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_flush.vhd
@@ -34,11 +34,8 @@ entity tb_tb_dp_flush is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
end tb_tb_dp_flush;
-
architecture tb of tb_tb_dp_flush is
-
constant c_nof_repeat : natural := 100;
-
begin
-- g_rl, g_framed_xon, g_framed_xoff , g_in_en, g_out_ready, g_nof_repeat
u_0_frm_frm_act_act : entity work.tb_dp_flush generic map (0, true, true, e_active, e_active, c_nof_repeat);
@@ -60,6 +57,4 @@ begin
u_0_str_frm_rnd_rnd : entity work.tb_dp_flush generic map (0, false, true, e_random, e_random, c_nof_repeat);
u_1_str_frm_act_act : entity work.tb_dp_flush generic map (1, false, true, e_active, e_active, c_nof_repeat);
u_1_str_frm_rnd_rnd : entity work.tb_dp_flush generic map (1, false, true, e_random, e_random, c_nof_repeat);
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd
index bc1000d19278254250825e5fcf8560777125fb52..7b3a6d811204091a3d6857fea5893ae6e71305d1 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_frame_scheduler.vhd
@@ -23,15 +23,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_dp_frame_scheduler is
end tb_tb_dp_frame_scheduler;
-
architecture tb of tb_tb_dp_frame_scheduler is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run 12 ms --> OK
@@ -41,5 +38,4 @@ begin
u_scheduler : entity work.tb_dp_frame_scheduler generic map (false, 1);
u_scheduler_rl_0 : entity work.tb_dp_frame_scheduler generic map (false, 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
index f3509c059efe66fce4c25eadac9ff6cc43ad923d..b2d70fca28db910b965d2bfb4589c10a6449a95b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_latency_fifo.vhd
@@ -24,15 +24,12 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_latency_fifo is
end tb_tb_dp_latency_fifo;
-
architecture tb of tb_tb_dp_latency_fifo is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 2
-- > run -all --> OK
@@ -63,5 +60,4 @@ begin
u_fifo_2_rnd_rnd : entity work.tb_dp_latency_fifo generic map (false, 1, 1, 2, 51, 4, e_random, e_random);
u_fifo_2_pls_rnd : entity work.tb_dp_latency_fifo generic map (false, 1, 1, 2, 51, 4, e_pulse, e_random);
u_fifo_3_pls_rnd : entity work.tb_dp_latency_fifo generic map (false, 1, 1, 3, 51, 4, e_pulse, e_random);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd
index 9934decb3239a9c2d128bbe9c5f275786dd55761..582a55eaed04b964f3aea217ac0d904819473425 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_mux.vhd
@@ -25,13 +25,10 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_mux is
end tb_tb_dp_mux;
-
architecture tb of tb_tb_dp_mux is
-
-- Use array_init() function to assign value to an unconstrained array of size 1.
-- Simply doing:
-- CONSTANT c_natural_arr_init : t_natural_arr := (1024);
@@ -41,7 +38,6 @@ architecture tb of tb_tb_dp_mux is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run 300 us --> OK
@@ -70,5 +66,4 @@ begin
u_nof_3_fill : entity work.tb_dp_mux generic map (false, false, false, 0, 3, true, array_init(1024, 3), (8, 12, 17));
u_nof_3_fill_empty : entity work.tb_dp_mux generic map (true, false, false, 0, 3, true, array_init(1024, 3), (8, 12, 17));
u_nof_3_fill_sync : entity work.tb_dp_mux generic map (false, false, true, 0, 3, true, array_init(1024, 3), (8, 12, 17));
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd
index cdd77af84b449154b9fdc3be1df21e71806df328..615f42cfd52b8db909b618d93dd0380ef1bafbb2 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_offload_tx_v3.vhd
@@ -30,13 +30,9 @@ use work.tb_dp_pkg.all; -- for t_dp_flow_control_enum
entity tb_tb_dp_offload_tx_v3 is
end tb_tb_dp_offload_tx_v3;
-
architecture tb of tb_tb_dp_offload_tx_v3 is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always e_active, e_random or e_pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -60,5 +56,4 @@ begin
u_rnd_act_data_64_symbol_32 : entity work.tb_dp_offload_tx_v3 generic map (e_random, e_active, false, 64, 32, 1, 240, 16);
u_rnd_act_data_32_symbol_8 : entity work.tb_dp_offload_tx_v3 generic map (e_random, e_active, false, 32, 8, 1, 240, 16);
u_rnd_act_data_32_symbol_16 : entity work.tb_dp_offload_tx_v3 generic map (e_random, e_active, false, 32, 16, 1, 240, 16);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd
index e2a0bc2efd430433dace879e9af69b3d1bb1aa38..ed199b8dbb0827a34988bb2e68a79cb3ce773416 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet.vhd
@@ -33,14 +33,10 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_dp_packet is
end tb_tb_dp_packet;
-
architecture tb of tb_tb_dp_packet is
-
constant c_nof_repeat : natural := 10;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_data_w, in_en, src_in.ready, nof repeat
u_16_act_act : entity work.tb_dp_packet generic map (16, e_active, e_active, c_nof_repeat);
u_16_act_rnd : entity work.tb_dp_packet generic map (16, e_active, e_random, c_nof_repeat);
@@ -77,5 +73,4 @@ begin
u_32_pls_act : entity work.tb_dp_packet generic map (32, e_pulse, e_active, c_nof_repeat);
u_32_pls_rnd : entity work.tb_dp_packet generic map (32, e_pulse, e_random, c_nof_repeat);
u_32_pls_pls : entity work.tb_dp_packet generic map (32, e_pulse, e_pulse, c_nof_repeat);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
index e62fe8c16a891094fb94ad976a6b7b9ad54ba95e..46fbd725ba93af2716dab57266cc4a6f73bb8af1 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packet_merge.vhd
@@ -33,14 +33,10 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_dp_packet_merge is
end tb_tb_dp_packet_merge;
-
architecture tb of tb_tb_dp_packet_merge is
-
constant c_nof_repeat : natural := 100;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
@@ -79,5 +75,4 @@ begin
u_act_act_8_nof_3_err_11 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 11, false);
u_act_act_8_nof_3_err_12 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 12, false);
u_act_act_8_nof_3_err_13 : entity work.tb_dp_packet_merge generic map ( e_active, e_active, 8, c_nof_repeat, 3, 29, 0, false, true, 1, 13, false);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd
index 28d6e8d12a36e3d823cb9b7a916178d093bd2e82..f7df2030e1ec4abd9035d6b32c8f80bc33a495a0 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_packetizing.vhd
@@ -23,15 +23,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_dp_packetizing is
end tb_tb_dp_packetizing;
-
architecture tb of tb_tb_dp_packetizing is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run 30 us --> OK
@@ -48,5 +45,4 @@ begin
u_2_3_24_16 : entity work.tb_dp_packetizing generic map (2, 3, 24, 16); -- 2/3
u_4_1_8_32 : entity work.tb_dp_packetizing generic map (4, 1, 8, 32); -- 4/1
u_1_4_32_8 : entity work.tb_dp_packetizing generic map (1, 4, 32, 8); -- 1/4
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
index 2ed88677caa3978831eb97f8cd972fcedcf53a5a..b44aa851f661d49fd6f3d03517108f5e499f494b 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_pad_insert_remove.vhd
@@ -25,15 +25,12 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_pad_insert_remove is
end tb_tb_dp_pad_insert_remove;
-
architecture tb of tb_tb_dp_pad_insert_remove is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 2
-- > run -all --> OK
@@ -45,5 +42,4 @@ begin
u_pls_pls : entity work.tb_dp_pad_insert_remove generic map (64, 8, 51, 2, e_pulse, e_pulse);
u_rnd_pls : entity work.tb_dp_pad_insert_remove generic map (64, 8, 52, 2, e_random, e_pulse);
u_pls_rnd : entity work.tb_dp_pad_insert_remove generic map (64, 8, 53, 2, e_pulse, e_random);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd
index 18b60bcde4305e25e79b1c03d7b492eded8d55f0..bf7764dd7a38062c4f298dd0c17e44a83b74cbfc 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline.vhd
@@ -29,14 +29,11 @@ use IEEE.std_logic_1164.all;
entity tb_tb_dp_pipeline is
end tb_tb_dp_pipeline;
-
architecture tb of tb_tb_dp_pipeline is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
u_p0 : entity work.tb_dp_pipeline generic map (0);
u_p1 : entity work.tb_dp_pipeline generic map (1);
u_p2 : entity work.tb_dp_pipeline generic map (2);
u_p7 : entity work.tb_dp_pipeline generic map (7);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd
index 2046b8fe0636bca0f21882b11f9cc0e8eb409e57..78c897f85426a3a6cf0c223c8a036690bc44af16 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_pipeline_ready.vhd
@@ -24,21 +24,16 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
-- > as 2
-- > run -all --> OK
entity tb_tb_dp_pipeline_ready is
end tb_tb_dp_pipeline_ready;
-
architecture tb of tb_tb_dp_pipeline_ready is
-
constant c_nof_repeat : natural := 50;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- in_en, src_in.ready, in_latency, out_latency, nof repeat,
-- Random flow control for different RL
u_rnd_rnd_0_0 : entity work.tb_dp_pipeline_ready generic map (e_random, e_random, 0, 0, c_nof_repeat);
@@ -62,5 +57,4 @@ begin
u_pls_act_1_1 : entity work.tb_dp_pipeline_ready generic map (e_pulse, e_active, 1, 1, c_nof_repeat);
u_pls_rnd_1_1 : entity work.tb_dp_pipeline_ready generic map (e_pulse, e_random, 1, 1, c_nof_repeat);
u_pls_pls_1_1 : entity work.tb_dp_pipeline_ready generic map (e_pulse, e_pulse, 1, 1, c_nof_repeat);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
index f92622f3dbf4f32132964f8c570633682d96fbd7..f61ac825829346b955479db5f27696346389f5df 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_repack_data.vhd
@@ -34,18 +34,14 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_dp_repack_data is
end tb_tb_dp_repack_data;
-
architecture tb of tb_tb_dp_repack_data is
-
constant c_nof_repeat : natural := 5;
constant c_flow : t_dp_flow_control_enum_arr := c_dp_flow_control_enum_arr;
constant c_bool : t_nat_boolean_arr := c_nat_boolean_arr;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -159,8 +155,6 @@ begin
u_18_2_8_5_len_2_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 2, 0); -- g_pkt_len = g_in_nof_words
u_18_2_8_5_len_3_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 3, 0); -- g_pkt_len = fractional multiple of g_in_nof_words
u_18_2_8_5_len_10_gap_0 : entity work.tb_dp_repack_data generic map (c_flow(I), c_flow(J), 18, 2, 8, 5, false, false, 1, 1, c_nof_repeat, 10, 0); -- g_pkt_len = integer multiple of g_in_nof_words
-
end generate;
end generate;
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd
index f5840e0536ffb67efca98ce1d39e1aecb6904155..5ac3ae84d277764295373be3050d1a32e3ca59c3 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data.vhd
@@ -32,15 +32,11 @@ use work.tb_dp_pkg.all;
entity tb_tb_dp_reverse_n_data is
end tb_tb_dp_reverse_n_data;
-
architecture tb of tb_tb_dp_reverse_n_data is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_rep_act : natural := 3;
-
begin
-
-- g_pipeline : NATURAL := 1; -- 0 for combinatorial, > 0 for registers
-- g_nof_repeat : NATURAL := 5;
-- g_reverse_len : NATURAL := 4;
@@ -55,5 +51,4 @@ begin
u_pipe_2_0 : entity work.tb_dp_reverse_n_data generic map(1, c_rep_act, 2, 0);
u_comb_3_5 : entity work.tb_dp_reverse_n_data generic map(0, c_rep_act, 3, 5);
u_pipe_3_5 : entity work.tb_dp_reverse_n_data generic map(1, c_rep_act, 3, 5);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd
index ebac7a7adba6daf54959ee5f3ae5c7f4fedad9bb..85ad8c0022642198169b9b41fa3ab6c06d8e99cd 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_reverse_n_data_fc.vhd
@@ -32,16 +32,12 @@ use work.tb_dp_pkg.all;
entity tb_tb_dp_reverse_n_data_fc is
end tb_tb_dp_reverse_n_data_fc;
-
architecture tb of tb_tb_dp_reverse_n_data_fc is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
constant c_rep_act : natural := 3;
constant c_rep_rnd : natural := 100;
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -69,5 +65,4 @@ begin
u_pls_pls_pipe_3_0 : entity work.tb_dp_reverse_n_data_fc generic map(e_pulse, e_pulse, 1, c_rep_rnd, 3, 0);
u_rnd_rnd_comb_3_0 : entity work.tb_dp_reverse_n_data_fc generic map(e_random, e_random, 0, c_rep_rnd, 3, 0);
u_rnd_rnd_pipe_3_0 : entity work.tb_dp_reverse_n_data_fc generic map(e_random, e_random, 1, c_rep_rnd, 3, 0);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
index 02c69fd10c8c835089e0281fec2e8ab181603d7f..484aa4dba3ca0575a2ddcace7a82e2e403ab5bd0 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_rsn_source.vhd
@@ -31,15 +31,11 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_rsn_source is
end tb_tb_dp_rsn_source;
-
architecture tb of tb_tb_dp_rsn_source is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-- from tb_dp_rsn_source.vhd
--
@@ -92,6 +88,4 @@ begin
-- test some prime values
u_17_3 : entity work.tb_dp_rsn_source generic map (17, 3, 3); -- 17 // 3 = 5, 17 MOD 3 = 2, 17/3 = 5.66 block/sync
u_101_17 : entity work.tb_dp_rsn_source generic map (101, 17, 17); -- 101 // 17 = 5, 101 MOD 17 = 16, 101/17 = 5.9411 block/sync
-
end tb;
-
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd
index b4e4ded7398ce3e085d4d28ca27df407676cdd4d..c57e02ba186424772f3462cc185007e31cb97a4d 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_split.vhd
@@ -29,7 +29,6 @@ end tb_tb_dp_split;
architecture tb of tb_tb_dp_split is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 10
-- > run 300 us --> OK
@@ -39,5 +38,4 @@ begin
u_nof_2 : entity work.tb_dp_split generic map (32, 16, 50, true);
u_nof_3 : entity work.tb_dp_split generic map (48, 16, 50, true);
u_nof_4 : entity work.tb_dp_split generic map (64, 16, 50, true);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
index ead7204e7b4650efe4e1779a578c3db06d8f6b88..c7195a0344274b49ae9067bc68c868505763a535 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_strobe_total_count.vhd
@@ -31,11 +31,8 @@ use IEEE.std_logic_1164.all;
entity tb_tb_dp_strobe_total_count is
end tb_tb_dp_strobe_total_count;
-
architecture tb of tb_tb_dp_strobe_total_count is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
--g_mm_w : NATURAL := c_word_w;
--g_count_w : NATURAL := 16;
@@ -57,5 +54,4 @@ begin
u_mm8b_cnt16b_high : entity work.tb_dp_strobe_total_count generic map(8, 16, 10,10, 10, 3); -- use high part
u_mm8b_cnt9b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 9, 10,10, 10, 3); -- cause overflow to clip count high part
u_mm8b_cnt7b_overflow : entity work.tb_dp_strobe_total_count generic map(8, 7, 10,10, 10, 3); -- cause overflow to clip count low part
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd
index 23f051a75de660b5b80476dda75d9e838b93bbe3..155a8c4c9d455a2434f1aa3a073d870511c37a83 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_checker.vhd
@@ -33,14 +33,10 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_dp_sync_checker is
end tb_tb_dp_sync_checker;
-
architecture tb of tb_tb_dp_sync_checker is
-
constant c_nof_repeat : natural := 100;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active, random or pulse flow control
@@ -61,5 +57,4 @@ begin
u_rnd_sync_ok : entity work.tb_dp_sync_checker generic map(e_random, e_active, 16, 1, c_nof_repeat, 16, 0, 16, 16);
u_rnd_sync_early : entity work.tb_dp_sync_checker generic map(e_random, e_active, 16, 1, c_nof_repeat, 16, 0, 14, 16);
u_rnd_sync_late : entity work.tb_dp_sync_checker generic map(e_random, e_active, 16, 1, c_nof_repeat, 16, 0, 18, 16);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd
index 30f74c4653529f11156e28c5960e58e219fd9b4f..bb53bc054a6eb68f951bb45d3d8e1340d773acea 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert.vhd
@@ -32,14 +32,10 @@ use IEEE.std_logic_1164.all;
entity tb_tb_dp_sync_insert is
end tb_tb_dp_sync_insert;
-
architecture tb of tb_tb_dp_sync_insert is
-
constant c_nof_repeat : natural := 100;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_block_size_input : NATURAL := 16;
-- g_nof_blk_per_sync_input : NATURAL := 32;
-- g_gap_size_during_block : NATURAL := 0;
@@ -50,5 +46,4 @@ begin
u_no_gaps : entity work.tb_dp_sync_insert generic map(16, 32, 0, 0, 8, 4, 14);
u_no_gap : entity work.tb_dp_sync_insert generic map(16, 32, 1, 3, 8, 4, 14);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
index d7857dfc1faac0ee33b38f917c645eeb57318e00..78b416f87b68f92273d9b69d7376aa41a55acb29 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_insert_v2.vhd
@@ -36,7 +36,6 @@ end tb_tb_dp_sync_insert_v2;
architecture tb of tb_tb_dp_sync_insert_v2 is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_nof_streams : NATURAL := 2;
-- g_block_size_input : NATURAL := 16;
-- g_nof_blk_per_sync_input : NATURAL := 32;
@@ -50,5 +49,4 @@ begin
u_gap : entity work.tb_dp_sync_insert_v2 generic map(2, 16, 32, 1, 3, 8, 2, 14);
u_large_blk_per_sync : entity work.tb_dp_sync_insert_v2 generic map(2, 16, 32, 0, 0, 999, 2, 14);
u_fract_blk_per_sync : entity work.tb_dp_sync_insert_v2 generic map(2, 16, 32, 0, 0, 7, 2, 14);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
index a5047a87f80dbfd7d1f585958eaa674e08633902..31fedc8eb476bcdf4c6a817413676e867f7ceba2 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_sync_recover.vhd
@@ -36,7 +36,6 @@ end tb_tb_dp_sync_recover;
architecture tb of tb_tb_dp_sync_recover is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_nof_data_per_block : NATURAL := 16;
-- g_nof_blk_per_sync : NATURAL := 8;
-- g_gap_size_during_block : NATURAL := 0;
@@ -53,5 +52,4 @@ begin
u_restart_at_sync_lo : entity work.tb_dp_sync_recover generic map(16, 8, 1, 3, 3, 2 * 8 + 3, 1, 14);
u_high_latency : entity work.tb_dp_sync_recover generic map(16, 8, 1, 3, 3, 50, 100, 14);
u_low_latency : entity work.tb_dp_sync_recover generic map(16, 8, 1, 3, 3, 50, 1, 14);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd
index 885b4484bc2a6e18505ea24c49284d08152a6ecb..6b9190e1527520d0303ed79ae476a4502beaf4f4 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_throttle_xon.vhd
@@ -32,15 +32,12 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_throttle_xon is
end tb_tb_dp_throttle_xon;
-
architecture tb of tb_tb_dp_throttle_xon is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 3
-- > run -all --> OK
@@ -62,5 +59,4 @@ begin
u_act_block_size_is_2 : entity work.tb_dp_throttle_xon generic map (e_active, e_active, false, 2, 10, 10, 37);
u_act_block_size_is_3 : entity work.tb_dp_throttle_xon generic map (e_active, e_active, false, 3, 10, 10, 37);
u_rnd_xon_equal_to_sync_interval : entity work.tb_dp_throttle_xon generic map (e_random, e_random, false, 20, 10, 10, 37);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd b/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd
index aa6e4deefe8625961a03b4a09cbc59112516970f..cfa9826d635bfd139f8fd59aa71ac3bbfd5b1c66 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_dp_xonoff.vhd
@@ -32,17 +32,14 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_dp_xonoff is
end tb_tb_dp_xonoff;
-
architecture tb of tb_tb_dp_xonoff is
constant c_rep : natural := 1000;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 3
-- > run -all --> OK
@@ -63,5 +60,4 @@ begin
u_act_act_gap0 : entity work.tb_dp_xonoff generic map (e_active, e_active, 32, 1, c_rep, 10, 5, 0);
u_rnd_rnd_gap0 : entity work.tb_dp_xonoff generic map (e_random, e_random, 32, 1, c_rep, 10, 5, 0);
u_pls_pls : entity work.tb_dp_xonoff generic map (e_pulse, e_pulse, 32, 7, c_rep, 10, 5, 4);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
index 8dc6420dde558e3080b5bd887ab18819293ebb03..9d057991883e12585a9ae236b4ef926f9bc2c579 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mmp_dp_bsn_align_v2.vhd
@@ -27,20 +27,14 @@ library IEEE;
use IEEE.std_logic_1164.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_mmp_dp_bsn_align_v2 is
end tb_tb_mmp_dp_bsn_align_v2;
-
architecture tb of tb_tb_mmp_dp_bsn_align_v2 is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_lost_input : BOOLEAN := FALSE
u_no_lost_input : entity work.tb_mmp_dp_bsn_align_v2 generic map (false);
u_one_lost_input : entity work.tb_mmp_dp_bsn_align_v2 generic map (true);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
index 0365151c1351be28eea4efbaa729a519e5ec2869..bdde22c2c0a0004de9b8a367feebd254d87fd282 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_parallel_arr.vhd
@@ -35,11 +35,8 @@ entity tb_tb_mms_dp_force_data_parallel_arr is
end tb_tb_mms_dp_force_data_parallel_arr;
architecture tb of tb_tb_mms_dp_force_data_parallel_arr is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
-- g_nof_streams : NATURAL := 1; -- >= 1
@@ -62,5 +59,4 @@ begin
u_rnd_force_data_incr_stream1 : entity work.tb_mms_dp_force_data_parallel_arr generic map (e_random, e_random, 3, 16, 1, -1, 2, -3, 1, 1, 1, false, false, false);
u_rnd_force_data_incr_sync_stream2 : entity work.tb_mms_dp_force_data_parallel_arr generic map (e_random, e_random, 3, 16, 2, -1, 2, -3, 1, 1, 1, false, true, false);
u_rnd_force_data_incr_sop_stream1 : entity work.tb_mms_dp_force_data_parallel_arr generic map (e_random, e_random, 3, 16, 1, -1, 2, -3, 1, 1, 1, false, false, true);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
index c3749bd26b06e645a4abadbfcbdd6f4f69fb7402..b406e3c7e6c46c2f56e7b8f8abc196130dedc223 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_force_data_serial_arr.vhd
@@ -35,11 +35,8 @@ entity tb_tb_mms_dp_force_data_serial_arr is
end tb_tb_mms_dp_force_data_serial_arr;
architecture tb of tb_tb_mms_dp_force_data_serial_arr is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always active or random verify ready flow control
-- g_nof_streams : NATURAL := 1; -- >= 1
@@ -60,5 +57,4 @@ begin
u_rnd_force_data_value_block_stream2 : entity work.tb_mms_dp_force_data_serial_arr generic map (e_random, e_random, 3, 16, 2, true, 7, -1, 2, -3, 17, false);
u_rnd_force_data_transparant_sample_stream1 : entity work.tb_mms_dp_force_data_serial_arr generic map (e_random, e_random, 3, 16, 1, false, 7, -1, 2, -3, 17, true);
u_rnd_force_data_transparant_block_stream2 : entity work.tb_mms_dp_force_data_serial_arr generic map (e_random, e_random, 3, 16, 2, false, 7, -1, 2, -3, 17, false);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
index 3ce6852087b0f1ef0300b3248038b4ddee4d0af3..0902c69d976cdf7a166b45eeac0ff21228b459e1 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_arr.vhd
@@ -36,11 +36,8 @@ entity tb_tb_mms_dp_gain_arr is
end tb_tb_mms_dp_gain_arr;
architecture tb of tb_tb_mms_dp_gain_arr is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_technology : NATURAL := c_tech_select_default;
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
-- g_nof_streams : NATURAL := 1; -- >= 1
@@ -53,5 +50,4 @@ begin
u_rnd_complex_data_real_gain_1 : entity work.tb_mms_dp_gain_arr generic map (c_tech_select_default, e_random, 1, true, true);
u_rnd_real_data_real_gain_3 : entity work.tb_mms_dp_gain_arr generic map (c_tech_select_default, e_random, 3, false, false);
u_rnd_real_data_real_gain_1 : entity work.tb_mms_dp_gain_arr generic map (c_tech_select_default, e_random, 1, false, false);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd
index 9d586aaadd2195914a3c1a6e28ad9262b5f4c56b..96e76fd8d6549cfc1a3e7a710f9a1631b13c1ee8 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_mms_dp_gain_serial_arr.vhd
@@ -35,11 +35,8 @@ entity tb_tb_mms_dp_gain_serial_arr is
end tb_tb_mms_dp_gain_serial_arr;
architecture tb of tb_tb_mms_dp_gain_serial_arr is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_technology : NATURAL := c_tech_select_default;
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_active; -- always active or random stimuli valid flow control
-- g_nof_streams : NATURAL := 1; -- >= 1
@@ -53,5 +50,4 @@ begin
u_rnd_complex_data_real_gain_1 : entity work.tb_mms_dp_gain_serial_arr generic map (c_tech_select_default, e_active, 1, 113, true, true);
u_rnd_real_data_real_gain_3 : entity work.tb_mms_dp_gain_serial_arr generic map (c_tech_select_default, e_active, 3, 113, false, false);
u_rnd_real_data_real_gain_1 : entity work.tb_mms_dp_gain_serial_arr generic map (c_tech_select_default, e_active, 1, 113, false, false);
-
end tb;
diff --git a/libraries/base/dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd b/libraries/base/dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd
index beab667b260ef97c77c562e7244637720deebe35..0b9f0629d498b325d9fe1d11fe607b65d4ed4bec 100644
--- a/libraries/base/dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_tb_tb_dp_backpressure.vhd
@@ -28,20 +28,16 @@
-- > as 3
-- > run -all
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.tb_dp_pkg.all;
-
entity tb_tb_tb_dp_backpressure is
end tb_tb_tb_dp_backpressure;
-
architecture tb of tb_tb_tb_dp_backpressure is
begin
-
-- Single TB
u_tb_dp_fifo_to_mm : entity work.tb_dp_fifo_to_mm;
u_tb_dp_latency_adapter : entity work.tb_dp_latency_adapter;
@@ -77,5 +73,4 @@ begin
u_tb_tb3_dp_demux : entity work.tb_tb3_dp_demux;
u_tb_tb3_dp_mux : entity work.tb_tb3_dp_mux;
-
end tb;
diff --git a/libraries/base/mm/src/vhdl/mm_arbiter.vhd b/libraries/base/mm/src/vhdl/mm_arbiter.vhd
index 3c5695f7065f6f5177664c4e0cec64f72ab2bc18..0fe99f1a06ba5314bed8123b974efe0fe2caa505 100644
--- a/libraries/base/mm/src/vhdl/mm_arbiter.vhd
+++ b/libraries/base/mm/src/vhdl/mm_arbiter.vhd
@@ -44,9 +44,7 @@ entity mm_arbiter is
);
end mm_arbiter;
-
architecture str of mm_arbiter is
-
constant c_slave_base : std_logic_vector(g_nof_slaves * 32 - 1 downto 0) := nat_arr_to_concat_slv(g_slave_base_arr, g_nof_slaves); -- Concatenated addresses; one for each slave
constant c_slave_high : std_logic_vector(g_nof_slaves * 32 - 1 downto 0) := nat_arr_to_concat_slv(g_slave_high_arr, g_nof_slaves); -- Concatenated addresess; one for each slave
@@ -166,9 +164,7 @@ architecture str of mm_arbiter is
signal wbs_mosi_arr : t_wb_mosi_arr(g_nof_slaves - 1 downto 0);
signal wbs_miso_arr : t_wb_miso_arr(g_nof_slaves - 1 downto 0);
-
begin
-
-- wbs_arbiter #(
-- .NUM_SLAVES (N_WB_SLAVES),
-- .SLAVE_ADDR (SLAVE_BASE),
@@ -293,5 +289,4 @@ begin
wbs_dat_i => wbs_dat_i,
wbs_ack_i => wbs_ack_i
);
-
end str;
diff --git a/libraries/base/mm/src/vhdl/mm_bus.vhd b/libraries/base/mm/src/vhdl/mm_bus.vhd
index d7be2cd14f8ca5c7d512a3b1a0f87e82d11c6356..6c6bf43ccbc803bc2bad7dfdaac0f246898cf1a0 100644
--- a/libraries/base/mm/src/vhdl/mm_bus.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus.vhd
@@ -103,7 +103,6 @@
--
-------------------------------------------------------------------------------
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -132,12 +131,9 @@ entity mm_bus is
end mm_bus;
architecture str of mm_bus is
-
signal bus_mosi_arr : t_mem_mosi_arr(0 to g_nof_slaves - 1);
signal bus_miso_arr : t_mem_miso_arr(0 to g_nof_slaves - 1);
-
begin
-
-- MM bus
u_mm_bus_pipe : entity work.mm_bus_pipe
generic map (
diff --git a/libraries/base/mm/src/vhdl/mm_bus_comb.vhd b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
index ae5db39b10f50d26d3f05316aae76bbd8c17b16f..eb27973b62cefe53239d23991a0fbcc59b29c92f 100644
--- a/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus_comb.vhd
@@ -102,7 +102,6 @@
--
-------------------------------------------------------------------------------
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -125,7 +124,6 @@ entity mm_bus_comb is
end mm_bus_comb;
architecture rtl of mm_bus_comb is
-
-- Determine the address range of all slaves on the MM bus.
function func_derive_mm_bus_addr_w(g_base_arr, g_width_arr : t_nat_natural_arr) return natural is
variable v_base : natural := 0;
@@ -150,9 +148,7 @@ architecture rtl of mm_bus_comb is
constant c_rd_latency_max : natural := largest(g_rd_latency_arr);
signal slave_index_arr : t_nat_natural_arr(0 to c_rd_latency_max) := (others => 0);
-
begin
-
gen_single : if g_nof_slaves = 1 generate
slave_mosi_arr(0) <= master_mosi;
master_miso <= slave_miso_arr(0);
@@ -192,7 +188,6 @@ begin
end loop;
end process;
-
-- Slave response to read access after read latency mm_clk cycles
p_master_miso : process(slave_miso_arr, slave_index_arr)
variable v_rd_latency : natural;
diff --git a/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd b/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
index 178c1543dbe5af08f8056d0eb39371fac844c9d4..67bcb3211ca473285534d4dd1a68583017727ba9 100644
--- a/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
+++ b/libraries/base/mm/src/vhdl/mm_bus_pipe.vhd
@@ -126,7 +126,6 @@ entity mm_bus_pipe is
end mm_bus_pipe;
architecture str of mm_bus_pipe is
-
signal m_mosi : t_mem_mosi := c_mem_mosi_rst;
signal m_miso : t_mem_miso := c_mem_miso_rst;
signal m_miso_reg : t_mem_miso := c_mem_miso_rst;
@@ -137,9 +136,7 @@ architecture str of mm_bus_pipe is
signal pipe_miso_arr : t_mem_miso_arr(0 to g_nof_slaves - 1);
signal adapt_mosi_arr : t_mem_mosi_arr(0 to g_nof_slaves - 1);
signal adapt_miso_arr : t_mem_miso_arr(0 to g_nof_slaves - 1);
-
begin
-
assert not(g_pipeline_miso_wait = true and g_pipeline_mosi = true)
report "Do not use g_pipeline_mosi = true if g_pipeline_miso_wait = TRUE"
severity FAILURE;
@@ -219,5 +216,4 @@ begin
slave_mosi_arr <= adapt_mosi_arr;
adapt_miso_arr <= slave_miso_arr;
-
end str;
diff --git a/libraries/base/mm/src/vhdl/mm_fields.vhd b/libraries/base/mm/src/vhdl/mm_fields.vhd
index 5d244b8f1262665810c1ca63a2f0f72d3bd0a52e..6538f9f9122acabc1ae2ab647fe8af06779bbbde 100644
--- a/libraries/base/mm/src/vhdl/mm_fields.vhd
+++ b/libraries/base/mm/src/vhdl/mm_fields.vhd
@@ -95,9 +95,7 @@ entity mm_fields is
);
end mm_fields;
-
architecture str of mm_fields is
-
constant c_reg_nof_words : natural := field_nof_words(g_field_arr, c_word_w);
constant c_reg : t_c_mem := (latency => 1,
@@ -116,9 +114,7 @@ architecture str of mm_fields is
signal reg_slv_in : std_logic_vector(c_reg.dat_w * c_reg.nof_dat - 1 downto 0);
signal reg_slv_out : std_logic_vector(c_reg.dat_w * c_reg.nof_dat - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- reg_slv_out is persistent (always valid) while slv_in is not. Register
-- slv_in_arr so reg_slv_in is persistent also.
@@ -174,5 +170,4 @@ begin
in_reg => reg_slv_in,
out_reg => reg_slv_out
);
-
end str;
diff --git a/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
index 17075eeafb1c2ae62c6e5f7a85e580032a22e615..558c4202196059480b0f632175661bc7d10ceffe 100644
--- a/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
+++ b/libraries/base/mm/src/vhdl/mm_latency_adapter.vhd
@@ -53,9 +53,7 @@ entity mm_latency_adapter is
);
end mm_latency_adapter;
-
architecture str of mm_latency_adapter is
-
-- Sum of all t_mem_mosi fields widths (synthesis will optimize away unused address and data bits)
constant c_data_w : natural := c_mem_address_w + c_mem_data_w + 2; -- 32 + 72 + 1 (wr) + 1 (rd) = 106
@@ -66,9 +64,7 @@ architecture str of mm_latency_adapter is
signal out_ready : std_logic;
signal out_data : std_logic_vector(c_data_w - 1 downto 0);
signal out_val : std_logic;
-
begin
-
in_data <= func_slv_concat(in_mosi.address, in_mosi.wrdata, slv(in_mosi.wr), slv(in_mosi.rd));
in_val <= in_mosi.wr or in_mosi.rd;
@@ -105,5 +101,4 @@ begin
out_mosi.wrdata <= func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 1);
out_mosi.wr <= sl(func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 2));
out_mosi.rd <= sl(func_slv_extract(c_mem_address_w, c_mem_data_w, 1, 1, out_data, 3));
-
end str;
diff --git a/libraries/base/mm/src/vhdl/mm_master_mux.vhd b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
index 01f5fdc67e59bef212cb438adfeb4db36cfd2ea2..0eb66110d923d0a6903c1a12df28762a26adc1db 100644
--- a/libraries/base/mm/src/vhdl/mm_master_mux.vhd
+++ b/libraries/base/mm/src/vhdl/mm_master_mux.vhd
@@ -56,7 +56,6 @@
--
-------------------------------------------------------------------------------
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -77,19 +76,15 @@ entity mm_master_mux is
end mm_master_mux;
architecture rtl of mm_master_mux is
-
signal index : natural := 0;
signal index_hold : natural := 0;
-
begin
-
gen_single : if g_nof_masters = 1 generate
mux_mosi <= master_mosi_arr(0);
master_miso_arr(0) <= mux_miso;
end generate;
gen_multiple : if g_nof_masters > 1 generate
-
-- Detect which master in the array is active
-- The pre condition is that the input masters will only start an access
-- when the mux master is free. For a rd access this means that the
@@ -117,7 +112,6 @@ begin
index_hold <= index when rising_edge(mm_clk); -- hold index of last active master
-
-- Multiplex master access, can be write or read
mux_mosi <= master_mosi_arr(index);
diff --git a/libraries/base/mm/src/vhdl/mm_pipeline.vhd b/libraries/base/mm/src/vhdl/mm_pipeline.vhd
index fb7bcc1ec2554c05f6ae1542eae9b24d28fb2a31..bef70460dde95a8ed47837445161a6c647e80d13 100644
--- a/libraries/base/mm/src/vhdl/mm_pipeline.vhd
+++ b/libraries/base/mm/src/vhdl/mm_pipeline.vhd
@@ -109,15 +109,11 @@ entity mm_pipeline is
);
end mm_pipeline;
-
architecture rtl of mm_pipeline is
-
signal mosi_reg : t_mem_mosi := c_mem_mosi_rst;
signal nxt_mosi_reg : t_mem_mosi;
signal ready : std_logic;
-
begin
-
-- Pass on miso
in_miso <= out_miso;
@@ -150,5 +146,4 @@ begin
end if;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/mm/src/vhdl/mm_slave_enable.vhd b/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
index 9f0afdd1fad8de10b9a931a3fb2763afb4f65499..dad3178dbd6da0915f82035e63c39f1a990a9331 100644
--- a/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
+++ b/libraries/base/mm/src/vhdl/mm_slave_enable.vhd
@@ -69,15 +69,11 @@ entity mm_slave_enable is
);
end mm_slave_enable;
-
architecture rtl of mm_slave_enable is
-
signal rd : std_logic;
signal rdval : std_logic;
signal waitrequest : std_logic;
-
begin
-
-- Use mosi.rd to create miso.rdval for unconnected slave or for slaves that do not support rdval
u_rdval : entity common_lib.common_pipeline_sl
generic map (
@@ -90,7 +86,6 @@ begin
out_dat => rdval
);
-
no_slave : if g_enable = false generate
out_mosi <= c_mem_mosi_rst;
@@ -118,5 +113,4 @@ begin
in_miso.waitrequest <= waitrequest;
end process;
end generate;
-
end rtl;
diff --git a/libraries/base/mm/src/vhdl/mm_slave_mux.vhd b/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
index 93d9e66f5af1fc57f4ab894d3230d4bc98e8036f..09459a54a91bfa2baca83a2dd8ec974e634c9413 100644
--- a/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
+++ b/libraries/base/mm/src/vhdl/mm_slave_mux.vhd
@@ -29,7 +29,6 @@
-- for clk. If necessary apply pipelining via mm_bus.vhd.
-------------------------------------------------------------------------------
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -51,7 +50,6 @@ end mm_slave_mux;
architecture str of mm_slave_mux is
begin
-
u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
g_broadcast => g_broadcast,
@@ -66,5 +64,4 @@ begin
mosi_arr => mosi_arr,
miso_arr => miso_arr
);
-
end str;
diff --git a/libraries/base/mm/tb/vhdl/mm_file.vhd b/libraries/base/mm/tb/vhdl/mm_file.vhd
index d2ca971388fed143ea318650845699679edcff64..f04fb7d4b0b12414ad989f9ff6eaf97d7f09a669 100644
--- a/libraries/base/mm/tb/vhdl/mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file.vhd
@@ -105,9 +105,7 @@ entity mm_file is
);
end mm_file;
-
architecture str of mm_file is
-
constant c_rd_file_name : string := g_file_prefix & ".ctrl";
constant c_wr_file_name : string := g_file_prefix & ".stat";
@@ -119,9 +117,7 @@ architecture str of mm_file is
signal polling : std_logic := '0'; -- monitor signal to view in Wave window when mmf_mm_from_file() is busy
signal timebegin : time := 0 ns;
signal timeout : time := 0 ns;
-
begin
-
mm_master_out <= i_mm_master_out;
no_file : if g_file_enable = '0' generate
@@ -129,7 +125,6 @@ begin
end generate;
gen_file : if g_file_enable = '1' generate
-
p_file_to_mm : process
begin
i_mm_master_out <= c_mem_mosi_rst;
@@ -176,8 +171,6 @@ begin
end if;
end process;
end generate;
-
end generate;
end str;
-
diff --git a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
index 73e2d5a0cb014077038b7bac2728fd97498dfb95..c742fee2212f2208e92002aa56db6337d3f19d5f 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_pkg.vhd
@@ -124,7 +124,6 @@ use IEEE.std_logic_textio.all;
use common_lib.common_str_pkg.all;
package mm_file_pkg is
-
-- Constants used by mm_file.vhd
constant c_mmf_mm_clk_period : time := 100 ps; -- Default mm_clk period in simulation. Set much faster than DP clock to speed up
-- simulation of MM access. Without file IO throttling 100 ps is a good balance
@@ -250,7 +249,6 @@ package mm_file_pkg is
end mm_file_pkg;
package body mm_file_pkg is
-
procedure mmf_file_create(filename: in string) is
file created_file : TEXT open write_mode is filename;
begin
@@ -354,7 +352,6 @@ package body mm_file_pkg is
-- The END implicitely close the rd_file, if still necessary.
end;
-
procedure mmf_sim_ctrl_from_file(rd_filename: in string;
wr_filename: in string) is
@@ -410,7 +407,6 @@ package body mm_file_pkg is
-- The END implicitely close the rd_file, if still necessary.
end;
-
procedure mmf_poll_sim_ctrl_file(rd_file_name: in string; wr_file_name : in string) is
begin
-- Create the ctrl file that we're going to read from
@@ -424,7 +420,6 @@ package body mm_file_pkg is
end;
-
procedure mmf_poll_sim_ctrl_file(signal mm_clk : in std_logic;
rd_file_name: in string; wr_file_name : in string) is
begin
@@ -439,7 +434,6 @@ package body mm_file_pkg is
end;
-
procedure mmf_wait_for_file_status(rd_filename : in string; -- file name with extension
exit_on_empty : in boolean;
signal mm_clk : in std_logic) is
@@ -631,7 +625,6 @@ package body mm_file_pkg is
end loop;
end mmf_mm_wait_until_value;
-
procedure mmf_sim_get_now(filename : in string; -- file name without extension
signal rd_now : out string;
signal mm_clk : in std_logic) is
@@ -754,4 +747,3 @@ package body mm_file_pkg is
end;
end mm_file_pkg;
-
diff --git a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
index 4aabfcd69fd82cbab5564d9e3a71f23dabf95ecb..ded649d443f664fa0b687b2155861a762fb658a5 100644
--- a/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_file_unb_pkg.vhd
@@ -25,7 +25,6 @@ use common_lib.common_str_pkg.all;
use work.mm_file_pkg.all;
package mm_file_unb_pkg is
-
type t_c_mmf_unb_sys is record
nof_unb : natural; -- Nof used UniBoard in our system [0..nof_unb-1]
nof_fn : natural; -- Nof used FNs [0..nof_fn-1] per UniBoard
@@ -49,7 +48,6 @@ package mm_file_unb_pkg is
end mm_file_unb_pkg;
package body mm_file_unb_pkg is
-
function mmf_unb_file_prefix(sys: t_c_mmf_unb_sys; node: natural) return string is
-- This function is used to create files for node function instances that (can) run on
-- an FN or a BN. One generate loop can be used for all node instances, no need to
@@ -95,4 +93,3 @@ package body mm_file_unb_pkg is
end;
end mm_file_unb_pkg;
-
diff --git a/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd b/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
index 8c9acdf1be9ec1557163d502487dfc6559940d46..7584ee79839bcbafca5a926816cb91d0a16b03ba 100644
--- a/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
+++ b/libraries/base/mm/tb/vhdl/mm_waitrequest_model.vhd
@@ -47,7 +47,6 @@
--
-------------------------------------------------------------------------------
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -70,7 +69,6 @@ entity mm_waitrequest_model is
end mm_waitrequest_model;
architecture rtl of mm_waitrequest_model is
-
constant c_prsg_init : natural := g_seed + 1; -- PRSG init must be > 0
signal prsg : std_logic_vector(g_prsg_w - 1 downto 0) := TO_UVEC(c_prsg_init, g_prsg_w);
@@ -79,9 +77,7 @@ architecture rtl of mm_waitrequest_model is
signal prev_bus_mosi : t_mem_mosi;
signal prev_waitrequest : std_logic;
-
begin
-
no_waitrequest : if g_waitrequest = false generate
slave_mosi <= bus_mosi;
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
index 1419f5eda018a3884ca9c53b95ff45dca587a605..7c4046568a12ac401061a6446db41fb82def5e45 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_bus.vhd
@@ -69,9 +69,7 @@ end tb_mm_bus;
-- > as 10
-- > run -all
-
architecture tb of tb_mm_bus is
-
constant mm_clk_period : time := 10 ns;
constant c_repeat : natural := 10; -- sel_a_b(g_waitrequest, 10, 2); -- repeat 2 for deterministic, more often for random
@@ -113,9 +111,7 @@ architecture tb of tb_mm_bus is
signal dbg_c_base_arr : t_nat_natural_arr(0 to g_nof_slaves - 1) := c_base_arr;
signal dbg_c_width_arr : t_nat_natural_arr(0 to g_nof_slaves - 1) := c_width_arr;
signal dbg_c_rd_latency_arr : t_nat_natural_arr(0 to g_nof_slaves - 1) := c_rd_latency_arr;
-
begin
-
mm_clk <= not mm_clk or tb_end after mm_clk_period / 2;
mm_rst <= '1', '0' after mm_clk_period * 5;
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
index 0b4970bd25ad8b7cfe021c85701a0e785e0e615c..ce5bfc5ca2a82cfeda78388176b3b3040c6965e9 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_file.vhd
@@ -63,7 +63,6 @@ entity tb_mm_file is
end tb_mm_file;
architecture tb of tb_mm_file is
-
constant c_mm_clk_period : time := c_mmf_mm_clk_period; -- = 100 ps;
constant c_mm_nof_dat : natural := smallest(c_mem_reg_init_w / c_32, g_mm_nof_accesses);
constant c_mm_rd_latency : natural := 2;
@@ -111,9 +110,7 @@ architecture tb of tb_mm_file is
signal out_new : std_logic; -- Pulses '1' when new data has been written.
signal out_reg_arr : t_slv_32_arr(c_mem_reg.nof_dat - 1 downto 0);
-
begin
-
mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * 10;
@@ -233,5 +230,4 @@ begin
mmf_sim_get_now(c_sim_file_pathname, rd_now, mm_clk);
wait;
end process;
-
end tb;
diff --git a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
index 7320275dfb3828b5886005f10de3712548e07091..f939920bf73176a317cdbbce67781f25a51d159c 100644
--- a/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_mm_master_mux.vhd
@@ -66,9 +66,7 @@ end tb_mm_master_mux;
-- > as 10
-- > run -all
-
architecture tb of tb_mm_master_mux is
-
constant mm_clk_period : time := 10 ns;
constant c_repeat : natural := sel_a_b(g_waitrequest, 10, 2); -- repeat 2 for deterministic, more often for random
@@ -101,9 +99,7 @@ architecture tb of tb_mm_master_mux is
signal mux_miso : t_mem_miso := c_mem_miso_rst;
signal ram_mosi : t_mem_mosi := c_mem_mosi_rst;
signal ram_miso : t_mem_miso := c_mem_miso_rst;
-
begin
-
mm_clk <= not mm_clk or tb_end after mm_clk_period / 2;
mm_rst <= '1', '0' after mm_clk_period * 5;
@@ -220,6 +216,4 @@ begin
rd_dat => ram_miso.rddata(c_data_w - 1 downto 0),
rd_val => ram_miso.rdval
);
-
-
end tb;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
index e477ed224cec4e476e9addacb2e03bcece77a38d..508a66f587924d84d07affc77fb3c517ceeb9e96 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_bus.vhd
@@ -63,5 +63,4 @@ begin
-- Do not support simultaneous g_pipeline_mosi = TRUE and g_pipeline_miso_wait = TRUE, see mm_bus_pipe.vhd.
--u_waitrequest_pipe_mosi_miso_wait : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, TRUE, FALSE, TRUE);
--u_waitrequest_pipe_all : ENTITY work.tb_mm_bus GENERIC MAP ( 2, 0, 4, 1, TRUE, TRUE, TRUE, TRUE);
-
end tb;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd
index 12ef1e673696b6e7a9854725d5e76bbc9ca2c565..469bf972122fecf110462309c1dd6d365b031015 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_file.vhd
@@ -50,5 +50,4 @@ begin
u_with_gap_one_clk_mm_throttle : entity work.tb_mm_file generic map (5, 10000, 100 ns, 1 us, 3, false);
u_with_gap_cross_clk : entity work.tb_mm_file generic map (6, 1000, 0 ns, 1 us, 3, true);
u_with_gap_cross_clk_mm_throttle : entity work.tb_mm_file generic map (7, 1000, 100 ns, 1 us, 3, true);
-
end tb;
diff --git a/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd b/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
index d08ca2fdfefa44d6bc40f0a586b134856297eedd..fb6d289c65dc7db3a0353e3baa8f643b80c73dde 100644
--- a/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
+++ b/libraries/base/mm/tb/vhdl/tb_tb_mm_master_mux.vhd
@@ -57,5 +57,4 @@ begin
-- Do not support simultaneous g_pipeline_mosi = TRUE and g_pipeline_miso_wait = TRUE, see mm_bus_pipe.vhd.
--u_waitrequest_pipe_all : ENTITY work.tb_mm_master_mux GENERIC MAP (2, (0, 256), (4, 8), TRUE, TRUE, TRUE, TRUE);
-
end tb;
diff --git a/libraries/base/reorder/src/vhdl/mms_reorder_rewire.vhd b/libraries/base/reorder/src/vhdl/mms_reorder_rewire.vhd
index 8a28d3cdf62f02fb1a9ea2d5e5216d3eff925e3c..7769954f478567e2d3410c36b7cfb1681b5ab548 100644
--- a/libraries/base/reorder/src/vhdl/mms_reorder_rewire.vhd
+++ b/libraries/base/reorder/src/vhdl/mms_reorder_rewire.vhd
@@ -84,11 +84,8 @@ entity mms_reorder_rewire is
end mms_reorder_rewire;
architecture str of mms_reorder_rewire is
-
signal sel_reg : std_logic_vector(sel_a_b(g_use_sel_table, g_sel_in_w, g_sel_in_w * g_nof_streams) - 1 downto 0) := (others => '0');
-
begin
-
u_register : entity work.reorder_rewire_reg
generic map(
g_nof_streams => g_nof_streams,
@@ -129,5 +126,4 @@ begin
output_sosi_arr => src_out_arr,
output_siso_arr => src_in_arr
);
-
end str;
diff --git a/libraries/base/reorder/src/vhdl/reorder_col.vhd b/libraries/base/reorder/src/vhdl/reorder_col.vhd
index 79db37a81aaa790655ad3901b2f5fe2e61eddeb4..b169627075b5f4e70dbdc7e1c01fa6b25199d302 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col.vhd
@@ -88,7 +88,6 @@ entity reorder_col is
end reorder_col;
architecture str of reorder_col is
-
constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
constant c_store_buf : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_nof_ch_in),
@@ -127,9 +126,7 @@ architecture str of reorder_col is
signal retrieve_info_sosi : t_dp_sosi;
signal retrieve_sosi : t_dp_sosi;
signal retrieve_siso : t_dp_siso;
-
begin
-
-----------------------------------------------------------------------------
-- Throttle the incoming streams so they provide a consistent packet flow
-- (no bursting) by enforcing a minimum period of g_nof_ch_sel
@@ -282,6 +279,4 @@ begin
src_in => output_siso,
src_out => output_sosi
);
-
end str;
-
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
index 2fd6d8d3694f35d66d7c5f4b18ae8274355830da..2aac2334fc124334a0e7c429ba67e889522bf65d 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_select.vhd
@@ -91,7 +91,6 @@ entity reorder_col_select is
end reorder_col_select;
architecture str of reorder_col_select is
-
constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
constant c_store_buf : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_nof_ch_in),
@@ -132,9 +131,7 @@ architecture str of reorder_col_select is
signal nof_ch_in_reg : natural;
signal nof_ch_sel_reg : natural;
-
begin
-
reorder_busy <= i_reorder_busy;
nof_ch_in_reg <= nof_ch_in when rising_edge(dp_clk) and i_reorder_busy = '0';
nof_ch_sel_reg <= nof_ch_sel when rising_edge(dp_clk) and i_reorder_busy = '0';
@@ -285,6 +282,4 @@ begin
-- Account for retrieve rd latency is 1, for sop related info it is not
-- critical that it arrives early, but for eop related info it is.
output_sosi <= func_dp_stream_combine_info_and_data(info_sosi, retrieve_sosi);
-
end str;
-
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
index 4cc63def4f7208b02a4f18eada8f6a6cbc36f8cd..ce8a2c0bad5a07f1e71dca14bfe1e825c4aa0558 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide.vhd
@@ -66,16 +66,13 @@ entity reorder_col_wide is
end reorder_col_wide;
architecture str of reorder_col_wide is
-
constant c_mem_addr_w : natural := ceil_log2(g_nof_ch_sel);
constant c_nof_ch_in : natural := g_nof_ch_in;
constant c_nof_ch_sel : natural := g_nof_ch_sel;
signal ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(g_wb_factor - 1 downto 0);
signal ram_ss_ss_wide_miso_arr : t_mem_miso_arr(g_wb_factor - 1 downto 0) := (others => c_mem_miso_rst);
-
begin
-
---------------------------------------------------------------
-- COMBINE MEMORY MAPPED INTERFACES
---------------------------------------------------------------
@@ -125,4 +122,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
index 62e6db321606e6b5e0a918bcda6533bd54bac009..41916d90e0a366dc27f7eeb1e10aee86d6d85974 100644
--- a/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_col_wide_select.vhd
@@ -62,11 +62,8 @@ entity reorder_col_wide_select is
end reorder_col_wide_select;
architecture str of reorder_col_wide_select is
-
signal col_select_miso_arr : t_mem_miso_arr(g_nof_inputs - 1 downto 0);
-
begin
-
col_select_miso <= col_select_miso_arr(0); -- All inputs have the same mosi/miso
-- Instantiate reorder_col_select for multiple streams in parallel, to
@@ -99,4 +96,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
index 46a30e6afa8862646c827d5602c598a7ac1f31b3..49a71a802576d591ae915689b6163f099409595e 100644
--- a/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_matrix.vhd
@@ -88,12 +88,9 @@ entity reorder_matrix is
end reorder_matrix;
architecture str of reorder_matrix is
-
signal ss_wide_in_sosi_arr : t_dp_sosi_arr(g_nof_internals - 1 downto 0) := (others => c_dp_sosi_rst);
signal ss_wide_out_sosi_arr : t_dp_sosi_arr(g_nof_internals - 1 downto 0) := (others => c_dp_sosi_rst);
-
begin
-
-----------------------------------------------------------------------------
-- Throttle the incoming streams so they provide a consistent packet flow
-- (no bursting) by enforcing a minimum period of g_frame_size_out
@@ -195,6 +192,4 @@ begin
input_sosi_arr => ss_wide_out_sosi_arr,
output_sosi_arr => output_sosi_arr
);
-
end str;
-
diff --git a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
index 80136add774ed7aa11555f523ede39a27e7183f6..caad085b16c31d06a5e57bd1333a5279dc2f82a4 100644
--- a/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
package reorder_pkg is
-
type t_reorder_seq is record
wr_chunksize : positive; -- := 64;
rd_chunksize : positive; -- := 16;
@@ -99,7 +98,6 @@ package reorder_pkg is
end reorder_pkg;
package body reorder_pkg is
-
-- A transpose process and an undo transpose process can both use
-- func_reorder_transpose(), by swapping the transpose dimensions.
-- For example, to get transposed output with:
@@ -157,6 +155,7 @@ package body reorder_pkg is
if v.blk_cnt = nof_blocks_per_packet then
v.blk_cnt := 0;
end if;
+
v.addr := v.blk_cnt;
end if;
else
diff --git a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
index 099f85a16e4b0bec33889d98a660f8fd9ff333ce..b8b15f6837762a89bd8ef66349f42a5ab276c958 100644
--- a/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_retreive.vhd
@@ -71,9 +71,7 @@ entity reorder_retrieve is
);
end reorder_retrieve;
-
architecture rtl of reorder_retrieve is
-
constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
constant c_retrieve_lat : natural := 2; -- fixed 1 for select buf read + 1 for store buf read
@@ -87,9 +85,7 @@ architecture rtl of reorder_retrieve is
signal retrieve_sop_dly : std_logic_vector(0 to c_retrieve_lat);
signal retrieve_eop_dly : std_logic_vector(0 to c_retrieve_lat);
-
begin
-
p_reg : process (clk, rst)
begin
if rst = '1' then
@@ -111,7 +107,6 @@ begin
end if;
end process;
-
-- Enable retrieve when a block has been stored, disable retrieve when the block has been output
u_retrieve_en : entity common_lib.common_switch
generic map (
@@ -146,7 +141,6 @@ begin
nxt_ch_cnt <= ch_cnt + 1;
end if;
end if;
-
end process;
-- Optional SS output frame control
@@ -169,5 +163,4 @@ begin
output_sosi.valid <= retrieve_miso.rdval;
output_sosi.sop <= retrieve_sop_dly(c_retrieve_lat);
output_sosi.eop <= retrieve_eop_dly(c_retrieve_lat);
-
end rtl;
diff --git a/libraries/base/reorder/src/vhdl/reorder_rewire.vhd b/libraries/base/reorder/src/vhdl/reorder_rewire.vhd
index 04475b3dc37082ed3cf234eb2f039e04282d0455..63abd6919cc7f50d5560018d861852554f12acd4 100644
--- a/libraries/base/reorder/src/vhdl/reorder_rewire.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_rewire.vhd
@@ -78,7 +78,6 @@ entity reorder_rewire is
end reorder_rewire;
architecture str of reorder_rewire is
-
begin
---------------------------------------------------------------------------------------
-- Connect outputs in process using Selection Table
@@ -113,5 +112,4 @@ begin
end loop;
end process;
end generate;
-
end str;
diff --git a/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd b/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
index 9deaf608b03e68df2eb6dd5206a86b74dc940423..db85b9f4822be1737f3804342538840138dcbb62 100644
--- a/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_rewire_reg.vhd
@@ -39,7 +39,6 @@
-- | enable_input.. = [0] | g_nof_inputs-1
-- |-----------------------------------------------------------------------|
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -67,9 +66,7 @@ entity reorder_rewire_reg is
);
end reorder_rewire_reg;
-
architecture str of reorder_rewire_reg is
-
constant c_nof_required_bits : natural := g_nof_streams * g_sel_in_w; -- 24
constant c_nof_required_registers : natural := 1; -- c_nof_required_bits MOD c_word_w;
@@ -85,9 +82,7 @@ architecture str of reorder_rewire_reg is
-- Registers in st_clk domain
signal sel_in_reg : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
u_reg : entity common_lib.common_reg_r_w_dc
generic map (
g_cross_clock_domain => g_cross_clock_domain,
@@ -117,7 +112,4 @@ begin
);
sel_reg <= sel_in_reg(g_nof_streams * g_sel_in_w - 1 downto 0);
-
-
end str;
-
diff --git a/libraries/base/reorder/src/vhdl/reorder_row.vhd b/libraries/base/reorder/src/vhdl/reorder_row.vhd
index 32171e203fa7e4e5af145ce636821e3555d36035..b02b86889fb79b254037a901895f26f6a6c77f0f 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row.vhd
@@ -68,7 +68,6 @@ entity reorder_row is
end reorder_row;
architecture str of reorder_row is
-
constant c_sel_buf_read_lat : natural := 1; -- Latency introduced by the counter.
constant c_tot_pipeline : natural := g_pipeline_in + g_pipeline_in_m + g_pipeline_out + c_sel_buf_read_lat;
@@ -88,7 +87,6 @@ architecture str of reorder_row is
nof_dat => c_mem_nof_dat_mm,
init_sl => '0');
-
constant c_select_buf_dp : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_frame_size),
dat_w => c_mem_dat_w_dp,
@@ -112,7 +110,6 @@ architecture str of reorder_row is
signal reorder_select : std_logic_vector(c_mem_dat_w_dp - 1 downto 0);
--SIGNAL reorder_select : STD_LOGIC_VECTOR(g_nof_outputs*c_select_w-1 DOWNTO 0);
signal reorder_chan_cnt : std_logic_vector(c_select_buf_dp.adr_w - 1 downto 0);
-
begin
---------------------------------------------------------------
-- PREPARE THE INPUT DATA.
@@ -127,6 +124,7 @@ begin
r.pipe_sosi_2arr(0)(I).im(g_dsp_data_w - 1 downto 0) &
r.pipe_sosi_2arr(0)(I).re(g_dsp_data_w - 1 downto 0);
end generate;
+
use_data : if not g_use_complex generate
reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
r.pipe_sosi_2arr(0)(I).data(c_data_w - 1 downto 0);
@@ -251,6 +249,4 @@ begin
end process;
output_sosi_arr <= r.output_sosi_arr;
-
end str;
-
diff --git a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
index 447f4a1487ceaa8d4e3e69bf8e75f9ed5811895d..429639223a48daf2f9a0750c47ebae03e799f697 100644
--- a/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_row_select.vhd
@@ -60,7 +60,6 @@ entity reorder_row_select is
end reorder_row_select;
architecture str of reorder_row_select is
-
constant c_tot_pipeline : natural := g_pipeline_in + g_pipeline_in_m + g_pipeline_out;
constant c_data_w : natural := g_dsp_data_w * c_nof_complex;
@@ -75,9 +74,7 @@ architecture str of reorder_row_select is
signal reorder_in_dat : std_logic_vector(g_nof_inputs * c_data_w - 1 downto 0);
signal reorder_out_dat : std_logic_vector(g_nof_outputs * c_data_w - 1 downto 0);
-
begin
-
---------------------------------------------------------------
-- PREPARE THE INPUT DATA.
--
@@ -91,6 +88,7 @@ begin
input_sosi_arr(I).im(g_dsp_data_w - 1 downto 0) &
input_sosi_arr(I).re(g_dsp_data_w - 1 downto 0);
end generate;
+
use_data : if not g_use_complex generate
reorder_in_dat((I + 1) * c_data_w - 1 downto I * c_data_w) <=
input_sosi_arr(I).data(c_data_w - 1 downto 0);
@@ -159,6 +157,4 @@ begin
end process;
output_sosi_arr <= r.output_sosi_arr;
-
end str;
-
diff --git a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
index 11daf33e8ef6d728129bb4defeb1c6020a04738f..e23186e4399e343bc42e0aa41e36adc56f958412 100644
--- a/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_sequencer.vhd
@@ -142,7 +142,6 @@
-- It is not supported to write small chunks and read one big chunk.
-- 3) Also be sure that nof_blocks is larger than or equal to rd_chunksize
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -169,9 +168,7 @@ entity reorder_sequencer is
);
end reorder_sequencer;
-
architecture rtl of reorder_sequencer is
-
-- Rescale to memory addressing
constant c_wr_chunksize : positive := g_reorder_seq.wr_chunksize / g_data_w_ratio;
constant c_rd_chunksize : positive := g_reorder_seq.rd_chunksize / g_data_w_ratio;
@@ -201,9 +198,7 @@ architecture rtl of reorder_sequencer is
end record;
signal r, rin : reg_type;
-
begin
-
---------------------------------------------------------------
-- CHECK IF PROVIDED GENERICS ARE ALLOWED.
---------------------------------------------------------------
@@ -217,7 +212,6 @@ begin
p_comb : process(r, dp_rst, done)
variable v : reg_type;
begin
-
v := r;
v.ddr3_en := '0';
@@ -289,7 +283,6 @@ begin
when others =>
v.state := s_idle;
-
end case;
if(dp_rst = '1') then
@@ -309,7 +302,6 @@ begin
end if;
rin <= v;
-
end process;
p_regs : process(dp_clk)
@@ -323,6 +315,4 @@ begin
wr_not_rd <= r.wr_not_rd;
address <= TO_UVEC(r.start_addr, address'length);
burstsize <= TO_UVEC(r.burstsize, burstsize'length);
-
end rtl;
-
diff --git a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
index 0943789673ec056aeb7900d938d8839fa28a9fbb..e62740d57c941a0665ee8106efb5ff0090f1526c 100644
--- a/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
+++ b/libraries/base/reorder/src/vhdl/reorder_transpose.vhd
@@ -129,9 +129,7 @@ entity reorder_transpose is
);
end reorder_transpose;
-
architecture str of reorder_transpose is
-
constant c_blocksize : positive := g_reorder_seq.wr_chunksize + g_reorder_seq.gapsize;
constant c_pagesize : positive := g_reorder_seq.nof_blocks * c_blocksize;
constant c_mem_size : positive := 2 * c_pagesize;
@@ -200,9 +198,7 @@ architecture str of reorder_transpose is
signal dbg_src_out : t_dp_sosi;
signal dbg_src_out_re_concat : std_logic_vector(c_total_data_w - 1 downto 0);
signal dbg_src_out_im_concat : std_logic_vector(c_total_data_w - 1 downto 0);
-
begin
-
to_mem_src_out <= i_to_mem_src_out;
src_out_arr <= i_src_out_arr;
@@ -211,6 +207,7 @@ begin
dbg_to_mem_src_out <= i_to_mem_src_out;
dbg_from_mem_snk_in <= from_mem_snk_in;
dbg_src_out <= i_src_out_arr(0);
+
gen_debug : for I in 0 to g_nof_streams - 1 generate
-- g_use_complex = FALSE : view sosi.data
dbg_snk_in_data_concat( (I + 1) * g_in_dat_w - 1 downto I * g_in_dat_w) <= snk_in_arr(I).data( g_in_dat_w - 1 downto 0);
@@ -272,7 +269,6 @@ begin
src_out => pipe_merged_snk_in
);
-
u_sync_check_and_restore : entity dp_lib.mms_dp_sync_checker
generic map(
g_nof_blk_per_sync => g_reorder_seq.nof_blocks
@@ -332,7 +328,6 @@ begin
output_sosi => i_to_mem_src_out,
output_siso => to_mem_src_in
);
-
end generate;
gen_not_pre_transpose : if g_ena_pre_transp = false generate
@@ -500,7 +495,4 @@ begin
-- ST source
src_out_arr => i_src_out_arr
);
-
end str;
-
-
diff --git a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd
index 0cf2ae02da9ee38bbdc558bbc1144151e128cdcd..262a2b142eb60538ed9fc1a32d862866e263241e 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_matrix.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -63,7 +62,6 @@ entity tb_mmf_reorder_matrix is
end tb_mmf_reorder_matrix;
architecture tb of tb_mmf_reorder_matrix is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -138,9 +136,7 @@ architecture tb of tb_mmf_reorder_matrix is
signal out_sosi_arr : t_dp_sosi_arr(g_nof_outputs - 1 downto 0) := (others => c_dp_sosi_rst);
signal out_siso_arr : t_dp_siso_arr(g_nof_outputs - 1 downto 0) := (others => c_dp_siso_rdy);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -303,5 +299,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
index aa1c9ed98d8d842b41adbbe891f4fb96e3400d0e..ee1bdadda1f566d24992d8aa709b924fa878c00a 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mmf_reorder_row.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -65,7 +64,6 @@ entity tb_mmf_reorder_row is
end tb_mmf_reorder_row;
architecture tb of tb_mmf_reorder_row is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -134,9 +132,7 @@ architecture tb of tb_mmf_reorder_row is
signal out_sosi_arr : t_dp_sosi_arr(g_nof_outputs - 1 downto 0) := (others => c_dp_sosi_rst);
signal out_siso_arr : t_dp_siso_arr(g_nof_outputs - 1 downto 0) := (others => c_dp_siso_rdy);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -297,5 +293,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
index 5b3e90e50cee8bbd71a28b077276ae826a303c1d..5572720cd77f88818651c29408756de5700f538d 100644
--- a/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_mms_reorder_rewire.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -54,7 +53,6 @@ entity tb_mms_reorder_rewire is
end tb_mms_reorder_rewire;
architecture tb of tb_mms_reorder_rewire is
-
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
@@ -127,7 +125,6 @@ architecture tb of tb_mms_reorder_rewire is
(0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0)
);
-
-- Custom definitions of constants
constant c_bg_block_len : natural := 16;
constant c_db_block_len : natural := 16;
@@ -163,9 +160,7 @@ architecture tb of tb_mms_reorder_rewire is
signal out_sosi_arr : t_dp_sosi_arr(c_bg_nof_output_streams - 1 downto 0) := (others => c_dp_sosi_rst);
signal out_siso_arr : t_dp_siso_arr(c_bg_nof_output_streams - 1 downto 0) := (others => c_dp_siso_rdy);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -287,6 +282,4 @@ begin
in_sync => out_sosi_arr(0).sync,
in_sosi_arr => out_sosi_arr
);
-
end tb;
-
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
index 1f0e760b36fab10548cd59a49d77f71c1722ab7d..c0669ea2dfb18f5bffb521bb5de561c7898ccd49 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col.vhd
@@ -30,7 +30,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
-- Usage:
-- > as 10
-- > run -all
@@ -71,9 +70,7 @@ entity tb_reorder_col is
);
end tb_reorder_col;
-
architecture tb of tb_reorder_col is
-
constant clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -114,9 +111,7 @@ architecture tb of tb_reorder_col is
signal first_in_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
signal first_out_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 5;
@@ -156,7 +151,6 @@ begin
toggle when g_mode_out_ready = 1 else
not toggle;
-
------------------------------------------------------------------------------
-- Generate input data blocks
------------------------------------------------------------------------------
@@ -206,7 +200,6 @@ begin
dp_sosi.bsn <= TO_DP_BSN(bsn);
end process;
-
------------------------------------------------------------------------------
-- Compensate for reverse order read out of DUT so that proc_verify_* have incrementing data
------------------------------------------------------------------------------
@@ -316,7 +309,7 @@ begin
gen_verify_non_complex: if not(g_use_complex) generate
proc_dp_verify_data("out_sosi.data", c_unsigned_0, to_unsigned(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.data, prev_out_sosi.data);
end generate;
+
-- verify output framing
proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sosi.sop);
-
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
index 955c7a71843cff1ce24a7f1bee58ebd539d888da..c335260390e6fd8e1ab24f4091fc1df5c36061b9 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_select_all.vhd
@@ -88,9 +88,7 @@ entity tb_reorder_col_select_all is
);
end tb_reorder_col_select_all;
-
architecture tb of tb_reorder_col_select_all is
-
constant c_clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -147,9 +145,7 @@ architecture tb of tb_reorder_col_select_all is
signal d_transpose : t_reorder_transpose;
signal r_undo_transpose : t_reorder_transpose;
signal d_undo_transpose : t_reorder_transpose;
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd
index 482813a92b78fbb8689fadffde66e5fa675e4410..d6d5d66f9cd1064fdf8f547fe6ad7b88af5ef8d7 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide.vhd
@@ -29,7 +29,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
-- Usage:
-- > as 10
-- > run -all
@@ -40,9 +39,7 @@ use dp_lib.tb_dp_pkg.all;
entity tb_reorder_col_wide is
end tb_reorder_col_wide;
-
architecture tb of tb_reorder_col_wide is
-
constant c_clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -76,9 +73,7 @@ architecture tb of tb_reorder_col_wide is
signal out_siso_arr : t_dp_siso_arr(c_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy);
signal out_sosi_arr : t_dp_sosi_arr(c_wb_factor - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -180,5 +175,4 @@ begin
output_sosi_arr => out_sosi_arr,
output_siso_arr => out_siso_arr
);
-
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
index 294c4ed3a80e1217cef05fb0ab8a2b9ad8786f98..126bfc83b1da467a9966ae330fe6f043de34df28 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_col_wide_row_select.vhd
@@ -88,9 +88,7 @@ entity tb_reorder_col_wide_row_select is
);
end tb_reorder_col_wide_row_select;
-
architecture tb of tb_reorder_col_wide_row_select is
-
constant c_use_complex : boolean := true;
constant c_data_w : natural := c_nof_complex * g_dsp_data_w;
@@ -127,9 +125,7 @@ architecture tb of tb_reorder_col_wide_row_select is
signal reorder_row_in_select : std_logic_vector(c_in_select_w - 1 downto 0) := (others => '0');
signal in_select : std_logic_vector(c_in_select_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -318,5 +314,4 @@ begin
input_sosi_arr => col_wide_select_sosi_arr,
output_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
index cf95c398d8ef80e9ff4a609d12b5e1844ab5393c..62d32e038f01d0a8c9d1d0f5b9697e3c3c8686a8 100644
--- a/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -82,7 +81,6 @@ entity tb_reorder_transpose is
end tb_reorder_transpose;
architecture tb of tb_reorder_transpose is
-
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
@@ -151,13 +149,11 @@ architecture tb of tb_reorder_transpose is
constant c_wr_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
constant c_rd_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
-
constant c_use_complex : boolean := true;
constant c_total_data_w : natural := g_nof_streams * g_in_dat_w;
constant c_complex_data_w : natural := c_total_data_w * c_nof_complex;
constant c_data_w : natural := sel_a_b(c_use_complex, c_complex_data_w, c_total_data_w);
-
constant c_ctrl_ref_clk_period : time := 5000 ps;
-- Custom definitions of constants
@@ -198,10 +194,7 @@ architecture tb of tb_reorder_transpose is
signal phy_in : t_tech_ddr3_phy_in;
signal phy_io : t_tech_ddr3_phy_io;
signal phy_ou : t_tech_ddr3_phy_ou;
-
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -253,7 +246,6 @@ begin
u_mm_file_reg_io_ddr : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_IO_DDR")
port map(mm_rst, mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);
-
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
@@ -462,6 +454,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end tb;
-
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
index 84039294866814a4a8eab93523c13fb8bfa4f1f1..5e1b814ea4e76669c569afb79911a634561d2384 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col.vhd
@@ -26,13 +26,10 @@ entity tb_tb_reorder_col is
end tb_tb_reorder_col;
architecture tb of tb_tb_reorder_col is
-
constant c_nof_sync : natural := 20;
constant c_reverse_ss_map : boolean := true;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- > as 2
-- > run -all --> OK
@@ -63,5 +60,4 @@ begin
u_act_invert_toggle_32_16 : entity work.tb_reorder_col generic map (0, 2, c_nof_sync, c_reverse_ss_map, 32, 16, false);
u_rnd_invert_toggle_32_16 : entity work.tb_reorder_col generic map (1, 2, c_nof_sync, c_reverse_ss_map, 32, 16, false);
-
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
index bd66fd81f0cd9f3021c662a50fce8ed3cb750816..279f2bdb4b547d0112008dda43a17eca6180f443 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_select_all.vhd
@@ -36,7 +36,6 @@ end tb_tb_reorder_col_select_all;
architecture tb of tb_tb_reorder_col_select_all is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_dsp_data_w : natural := 16; -- complex data width, = c_data_w / 2
-- g_nof_sync : natural := 2;
-- g_nof_packets_per_sync : natural := 3;
@@ -56,5 +55,4 @@ begin
u_dynamic_data_5_3_no_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3, 0, 0, false, true);
u_dynamic_data_5_3_gaps : entity work.tb_reorder_col_select_all generic map(16, 3, 3, 5, 3,10,100, false, true);
-
end tb;
diff --git a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
index 6fd70a5c19f93ad61aba102bd5a6c568fccc3aca..1306c592df15126d11c403bd19903ed5e80fbde5 100644
--- a/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
+++ b/libraries/base/reorder/tb/vhdl/tb_tb_reorder_col_wide_row_select.vhd
@@ -34,13 +34,10 @@ entity tb_tb_reorder_col_wide_row_select is
end tb_tb_reorder_col_wide_row_select;
architecture tb of tb_tb_reorder_col_wide_row_select is
-
constant c_nof_sync : natural := 3;
constant c_dsp_data_w : natural := 16;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- Generics:
-- g_nof_inputs : NATURAL := 6; -- also nof rows
-- g_nof_outputs : NATURAL := 2;
@@ -59,5 +56,4 @@ begin
u_sdp : entity work.tb_reorder_col_wide_row_select generic map (6, 1, c_dsp_data_w, c_nof_sync, 4, 1024, 2, 2, (0, 16), 3, 0, 1, 1);
u_max_out : entity work.tb_reorder_col_wide_row_select generic map (8, 1, c_dsp_data_w, c_nof_sync, 1, 512, 8, 8, (0 ,64, 128, 192, 256, 320, 384, 448), 0, 0, 1, 1); -- rows * cols * offsets = 8*8*8 = 512
u_multiple_out : entity work.tb_reorder_col_wide_row_select generic map (2, 5, c_dsp_data_w, c_nof_sync, 4, 1024, 2, 2, (0, 16), 3, 0, 1, 1);
-
end tb;
diff --git a/libraries/base/ring/src/vhdl/ring_info.vhd b/libraries/base/ring/src/vhdl/ring_info.vhd
index b1773c9b283430da7ee09ea6deba714d5b8df9c9..f30cde027d9a0d3dc25787676ac624b52498ab97 100644
--- a/libraries/base/ring/src/vhdl/ring_info.vhd
+++ b/libraries/base/ring/src/vhdl/ring_info.vhd
@@ -53,13 +53,9 @@ entity ring_info is
);
end ring_info;
-
architecture str of ring_info is
-
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_ring_info_field_arr) - 1 downto 0);
-
begin
-
u_mm_fields: entity mm_lib.mm_fields
generic map(
g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
@@ -86,10 +82,4 @@ begin
ring_info.use_cable_to_previous_rn <= sl(mm_fields_out(field_hi(c_ring_info_field_arr, "use_cable_to_previous_rn") downto field_lo(c_ring_info_field_arr, "use_cable_to_previous_rn")));
ring_info.use_cable_to_next_rn <= sl(mm_fields_out(field_hi(c_ring_info_field_arr, "use_cable_to_next_rn") downto field_lo(c_ring_info_field_arr, "use_cable_to_next_rn")));
-
end str;
-
-
-
-
-
diff --git a/libraries/base/ring/src/vhdl/ring_lane.vhd b/libraries/base/ring/src/vhdl/ring_lane.vhd
index 374faeb6d6c02848496fae5dac13f8e24548e6b9..aae48c720df85105ba0946c067aa13ce8ab950be 100644
--- a/libraries/base/ring/src/vhdl/ring_lane.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane.vhd
@@ -86,12 +86,9 @@ entity ring_lane is
end ring_lane;
architecture str of ring_lane is
-
constant c_lane_direction : std_logic := sel_a_b(g_lane_direction, '1', '0');
signal lane_info : t_ring_lane_info;
-
begin
-
u_ring_lane_info : entity work.ring_lane_info
port map (
dp_rst => dp_rst,
@@ -107,7 +104,6 @@ begin
lane_info => lane_info
);
-
u_ring_rx : entity work.ring_rx
generic map (
g_use_dp_layer => g_use_dp_layer,
@@ -174,5 +170,4 @@ begin
this_rn => this_rn,
N_rn => N_rn
);
-
end str;
diff --git a/libraries/base/ring/src/vhdl/ring_lane_info.vhd b/libraries/base/ring/src/vhdl/ring_lane_info.vhd
index c905ccfae92d9f80d43fb1f1319204b3d9b3b08c..83c2cf4ca307c5408c5e57b1778609abe79defdc 100644
--- a/libraries/base/ring/src/vhdl/ring_lane_info.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane_info.vhd
@@ -57,13 +57,9 @@ entity ring_lane_info is
);
end ring_lane_info;
-
architecture str of ring_lane_info is
-
signal lane_info_ro: t_ring_lane_info; -- ro = read only
-
begin
-
u_mm_fields: entity work.ring_lane_info_reg
port map (
@@ -80,7 +76,5 @@ begin
lane_info => lane_info
);
-
lane_info_ro.lane_direction <= lane_direction;
-
end str;
diff --git a/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd b/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd
index ba4254765a62909b99972c294121e23e0cfa8d14..d2a145621ad91194d99a45e79f8c3868fd16bbfa 100644
--- a/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_lane_info_reg.vhd
@@ -55,17 +55,13 @@ entity ring_lane_info_reg is
);
end ring_lane_info_reg;
-
architecture str of ring_lane_info_reg is
-
signal mm_fields_in : std_logic_vector(field_slv_in_len(c_ring_lane_info_field_arr) - 1 downto 0);
signal mm_fields_out : std_logic_vector(field_slv_out_len(c_ring_lane_info_field_arr) - 1 downto 0);
signal lane_info_rd : t_ring_lane_info;
signal lane_info_wr : t_ring_lane_info;
-
begin
-
lane_info <= lane_info_rd;
p_lane_info_rd : process(lane_info_wr, lane_info_ro)
@@ -77,7 +73,6 @@ begin
lane_info_rd.lane_direction <= lane_info_ro.lane_direction;
end process;
-
u_mm_fields: entity mm_lib.mm_fields
generic map(
g_use_slv_in_val => false, -- use FALSE to save logic when always slv_in_val='1'
@@ -104,5 +99,4 @@ begin
-- get "RW" fields from mm_fields
lane_info_wr.transport_nof_hops <= mm_fields_out(field_hi(c_ring_lane_info_field_arr, "transport_nof_hops") downto field_lo(c_ring_lane_info_field_arr, "transport_nof_hops"));
-
end str;
diff --git a/libraries/base/ring/src/vhdl/ring_mux.vhd b/libraries/base/ring/src/vhdl/ring_mux.vhd
index 8a0e1450c7627c3c0d01d55fdf95c84329d4ffa5..da34e38528c5ac357e9460875f7c8e416b8216b9 100644
--- a/libraries/base/ring/src/vhdl/ring_mux.vhd
+++ b/libraries/base/ring/src/vhdl/ring_mux.vhd
@@ -67,12 +67,10 @@ entity ring_mux is
end ring_mux;
architecture str of ring_mux is
-
constant c_nof_input : natural := 2;
signal dp_mux_in_sosi_arr : t_dp_sosi_arr(0 to c_nof_input - 1);
signal dp_mux_in_siso_arr : t_dp_siso_arr(0 to c_nof_input - 1);
-
begin
-- rewire dp_mux inputs
dp_mux_in_sosi_arr(0) <= local_sosi;
@@ -108,5 +106,4 @@ begin
src_in => mux_siso,
src_out => mux_sosi
);
-
end str;
diff --git a/libraries/base/ring/src/vhdl/ring_pkg.vhd b/libraries/base/ring/src/vhdl/ring_pkg.vhd
index 1c22b26c92eed6e9879dab1fef99d343e05a38b3..58bb4193ddcc01c9f29e774916019a5318fe426e 100644
--- a/libraries/base/ring/src/vhdl/ring_pkg.vhd
+++ b/libraries/base/ring/src/vhdl/ring_pkg.vhd
@@ -98,7 +98,6 @@ package ring_pkg is
end package ring_pkg;
package body ring_pkg is
-
function func_ring_nof_hops_to_source_rn(hops, this_rn, N_rn, lane_dir : natural) return natural is
variable v_source_rn : integer;
variable v_source_rn_nat : natural;
@@ -128,4 +127,3 @@ package body ring_pkg is
end;
end ring_pkg;
-
diff --git a/libraries/base/ring/src/vhdl/ring_rx.vhd b/libraries/base/ring/src/vhdl/ring_rx.vhd
index ef3b18eb2ee27ed1f518f1ebb295d5164be221bc..42c1b8d2061d6f5b4f65d94b1865c94526e3bb00 100644
--- a/libraries/base/ring/src/vhdl/ring_rx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_rx.vhd
@@ -76,7 +76,6 @@ entity ring_rx is
end ring_rx;
architecture str of ring_rx is
-
constant c_nof_hdr_fields : natural := sel_a_b(g_use_dp_layer, c_ring_dp_nof_hdr_fields, c_ring_eth_nof_hdr_fields);
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_arr, c_ring_eth_hdr_field_arr);
constant c_hdr_field_size : natural := sel_a_b(g_use_dp_layer, c_ring_dp_hdr_field_size, c_ring_eth_hdr_field_size);
@@ -94,9 +93,7 @@ architecture str of ring_rx is
signal hdr_fields_out : std_logic_vector(1023 downto 0);
signal hdr_fields_raw : std_logic_vector(1023 downto 0);
-
begin
-
-- Select input based on rx_select
lane_rx_sosi <= lane_rx_cable_sosi when rx_select = '1' else lane_rx_board_sosi;
@@ -242,7 +239,6 @@ begin
in_sosi_arr => monitor_sosi_arr,
ref_sync => ref_sync
);
-
end generate;
-- Do not use dp layer
diff --git a/libraries/base/ring/src/vhdl/ring_tx.vhd b/libraries/base/ring/src/vhdl/ring_tx.vhd
index 0919bf8f8a0f5760cd1b9b090c93c0f97d0fd047..059e6fb0a3cb105549c0b655dcf479ac79468073 100644
--- a/libraries/base/ring/src/vhdl/ring_tx.vhd
+++ b/libraries/base/ring/src/vhdl/ring_tx.vhd
@@ -72,7 +72,6 @@ entity ring_tx is
end ring_tx;
architecture str of ring_tx is
-
constant c_use_empty : boolean := sel_a_b(g_symbol_w = g_data_w, false, true);
constant c_empty_w : natural := ceil_log2(g_data_w / g_symbol_w);
constant c_nof_hdr_fields : natural := sel_a_b(g_use_dp_layer, c_ring_dp_nof_hdr_fields, c_ring_eth_nof_hdr_fields);
@@ -92,7 +91,6 @@ architecture str of ring_tx is
signal hdr_fields_in : std_logic_vector(1023 downto 0);
signal hdr_fields_in_reg : std_logic_vector(1023 downto 0);
-
begin
-- Validate transport_nof_hops
gen_validate : if g_validate_channel generate
@@ -110,6 +108,7 @@ begin
remove_channel => remove_channel
);
end generate;
+
-- Don't validate transport_nof_hops
gen_no_validate : if not g_validate_channel generate
validated_sosi <= to_lane_sosi;
@@ -130,6 +129,7 @@ begin
hdr_fields_in(field_hi(c_hdr_field_arr, "eth_dst_mac" ) downto field_lo(c_hdr_field_arr, "eth_dst_mac" )) <= c_ring_eth_dst_mac;
hdr_fields_in(field_hi(c_hdr_field_arr, "eth_src_mac" ) downto field_lo(c_hdr_field_arr, "eth_src_mac" )) <= c_ring_eth_src_mac;
hdr_fields_in(field_hi(c_hdr_field_arr, "eth_type" ) downto field_lo(c_hdr_field_arr, "eth_type" )) <= g_ring_pkt_type;
+
gen_hdr_dp : if g_use_dp_layer generate
hdr_fields_in(field_hi(c_hdr_field_arr, "dp_channel" ) downto field_lo(c_hdr_field_arr, "dp_channel" )) <= tx_sosi.channel(c_halfword_w - 1 downto 0);
hdr_fields_in(field_hi(c_hdr_field_arr, "dp_sync" ) downto field_lo(c_hdr_field_arr, "dp_sync" )) <= slv(tx_sosi.sync);
@@ -237,7 +237,6 @@ begin
in_sosi_arr => monitor_sosi_arr,
ref_sync => ref_sync
);
-
end generate;
end str;
diff --git a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
index 97cab42dc762c556e96b95e55687949366731bf6..7ce96472307a11181609ce2427f412747b04b4fb 100644
--- a/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
+++ b/libraries/base/ring/tb/vhdl/tb_ring_lane_info.vhd
@@ -38,7 +38,6 @@ use common_lib.tb_common_pkg.all;
use common_lib.tb_common_mem_pkg.all;
use work.ring_pkg.all;
-
entity tb_ring_lane_info is
end tb_ring_lane_info;
@@ -91,7 +90,6 @@ begin
proc_mem_mm_bus_wr(c_mm_addr_lane_direction ,1 ,mm_clk, reg_miso, reg_mosi); -- RO
proc_common_wait_some_cycles(mm_clk, c_cross_clock_domain_latency);
-
proc_mem_mm_bus_rd(c_mm_addr_transport_nof_hops, mm_clk, reg_mosi); proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
mm_natural_response <= TO_UINT(reg_miso.rddata); proc_common_wait_some_cycles(mm_clk, 1);
assert mm_natural_response = 11 report "wrong c_mm_addr_transport_nof_hops" severity ERROR;
@@ -103,7 +101,6 @@ begin
proc_common_wait_some_cycles(mm_clk, 100);
tb_mm_reg_end <= '1';
wait;
-
end process;
-- check if values in lane_info match with expected values
@@ -119,7 +116,6 @@ begin
wait;
end process;
-
-- SDP info
u_dut: entity work.ring_lane_info
port map (
@@ -136,5 +132,4 @@ begin
lane_info => lane_info
);
-
end tb;
diff --git a/libraries/base/sens/src/vhdl/sens.vhd b/libraries/base/sens/src/vhdl/sens.vhd
index fe632ba60e5b7ca6aff66d5b6edbbfaefc192d54..b6dbc55dabeedc248878e9743907b8b270dbde47 100644
--- a/libraries/base/sens/src/vhdl/sens.vhd
+++ b/libraries/base/sens/src/vhdl/sens.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use i2c_lib.i2c_pkg.all;
-
entity sens is
generic (
g_temp_high : natural := 127;
@@ -45,9 +44,7 @@ entity sens is
);
end entity;
-
architecture str of sens is
-
constant cs_sim : boolean := is_true(g_sim);
-- SENS read out rate settings
@@ -69,9 +66,7 @@ architecture str of sens is
signal smbus_out_val : std_logic;
signal smbus_out_err : std_logic;
signal smbus_out_ack : std_logic;
-
begin
-
ctrl : entity work.sens_ctrl
generic map (
g_clk_cnt_w => c_update_clk_cnt_w,
@@ -108,5 +103,4 @@ begin
scl => scl,
sda => sda
);
-
end architecture;
diff --git a/libraries/base/sens/src/vhdl/sens_ctrl.vhd b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
index cec717fb84d61f2541d004707eac7dd6567db0b2..e3a0cc0b377ce888cf5469821964d2fe5732d5a7 100644
--- a/libraries/base/sens/src/vhdl/sens_ctrl.vhd
+++ b/libraries/base/sens/src/vhdl/sens_ctrl.vhd
@@ -26,7 +26,6 @@ use i2c_lib.i2c_smbus_pkg.all;
use i2c_lib.i2c_dev_max1617_pkg.all;
use i2c_lib.i2c_dev_max6652_pkg.all;
-
entity sens_ctrl is
generic (
g_clk_cnt_w : natural;
@@ -47,9 +46,7 @@ entity sens_ctrl is
);
end entity;
-
architecture rtl of sens_ctrl is
-
constant ADR_MAX6652 : natural := MAX6652_ADR_GND;
constant ADR_MAX1617_BP : natural := MAX1617_ADR_MID_MID;
constant ADR_MAX1617_AP0 : natural := MAX1617_ADR_LOW_LOW;
@@ -104,9 +101,7 @@ architecture rtl of sens_ctrl is
signal nxt_evt_dat : std_logic_vector(evt_dat_reg'range);
signal i_evt_dat_reg : std_logic_vector(evt_dat_reg'range);
signal nxt_evt_dat_reg : std_logic_vector(evt_dat_reg'range);
-
begin
-
evt_dat_reg <= i_evt_dat_reg;
regs: process(rst,clk)
@@ -160,5 +155,4 @@ begin
nxt_evt_val <= '1' when seq_cnt = SEQ'high - 1 and in_ack = '1' else '0';
nxt_evt_dat_reg <= evt_dat when evt_val = '1' else i_evt_dat_reg;
-
end rtl;
diff --git a/libraries/base/sens/tb/vhdl/tb_sens.vhd b/libraries/base/sens/tb/vhdl/tb_sens.vhd
index 029016593b59694e2ec650754b946813576f6ad4..db6ed53a022866225beba988ddaf3b989b9d2702 100644
--- a/libraries/base/sens/tb/vhdl/tb_sens.vhd
+++ b/libraries/base/sens/tb/vhdl/tb_sens.vhd
@@ -28,9 +28,7 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use common_lib.tb_common_pkg.all;
-
architecture tb of tb_sens is
-
constant c_clk_period : time := 5 ns;
constant c_rst_period : time := 4 * c_clk_period;
@@ -70,9 +68,7 @@ architecture tb of tb_sens is
signal sens_data_bytes : t_sens_data_arr;
signal exp_data_bytes : t_nat_natural_arr(0 to c_sens_temp_volt_sz - 1) := (92, 147, 127, 40, 60, 70, 71, 72, 73); -- expected 9 bytes as read by SEQUENCE in sens_ctrl
-
begin
-
-- run -all
rst <= '0' after 4 * c_clk_period;
@@ -193,6 +189,4 @@ begin
volt_vcc => c_volt_3v3,
temp => c_temp_pcb
);
-
end tb;
-
diff --git a/libraries/base/ss/src/vhdl/ss.vhd b/libraries/base/ss/src/vhdl/ss.vhd
index d6dea686beae05d105279d01729a25b55d7fc5d0..e53037f69f31bcd234a768a464af0b6ab7e1f946 100644
--- a/libraries/base/ss/src/vhdl/ss.vhd
+++ b/libraries/base/ss/src/vhdl/ss.vhd
@@ -87,9 +87,7 @@ entity ss is
);
end ss;
-
architecture str of ss is
-
constant c_store_buf : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_nof_ch_in),
dat_w => c_nof_complex * g_dsp_data_w,
@@ -127,9 +125,7 @@ architecture str of ss is
signal ss_sosi : t_dp_sosi;
signal ss_siso : t_dp_siso;
-
begin
-
-----------------------------------------------------------------------------
-- Throttle the incoming streams so they provide a consistent packet flow
-- (no bursting) by enforcing a minimum period of g_nof_ch_sel
@@ -282,6 +278,4 @@ begin
output_sosi <= func_dp_stream_combine_info_and_data(info_sosi, ss_sosi);
ss_siso <= output_siso;
-
end str;
-
diff --git a/libraries/base/ss/src/vhdl/ss_parallel.vhd b/libraries/base/ss/src/vhdl/ss_parallel.vhd
index c2373966f66dd014d5fb59a31fdec377378feb27..4a458c7ed4518b78377488f76ab2e6ca85df9a78 100644
--- a/libraries/base/ss/src/vhdl/ss_parallel.vhd
+++ b/libraries/base/ss/src/vhdl/ss_parallel.vhd
@@ -90,12 +90,9 @@ entity ss_parallel is
end ss_parallel;
architecture str of ss_parallel is
-
signal ss_wide_in_sosi_arr : t_dp_sosi_arr(g_nof_internals - 1 downto 0) := (others => c_dp_sosi_rst);
signal ss_wide_out_sosi_arr : t_dp_sosi_arr(g_nof_internals - 1 downto 0) := (others => c_dp_sosi_rst);
-
begin
-
-----------------------------------------------------------------------------
-- Throttle the incoming streams so they provide a consistent packet flow
-- (no bursting) by enforcing a minimum period of g_frame_size_out
@@ -200,6 +197,4 @@ begin
input_sosi_arr => ss_wide_out_sosi_arr,
output_sosi_arr => output_sosi_arr
);
-
end str;
-
diff --git a/libraries/base/ss/src/vhdl/ss_reorder.vhd b/libraries/base/ss/src/vhdl/ss_reorder.vhd
index 4b186470c44557b466fadfe365d8b7b88355bea6..1f00b179dd9a3003a186f10063d4b1ed9f1abe93 100644
--- a/libraries/base/ss/src/vhdl/ss_reorder.vhd
+++ b/libraries/base/ss/src/vhdl/ss_reorder.vhd
@@ -69,7 +69,6 @@ entity ss_reorder is
end ss_reorder;
architecture str of ss_reorder is
-
constant c_sel_buf_read_lat : natural := 1; -- Latency introduced by the counter.
constant c_tot_pipeline : natural := g_pipeline_in + g_pipeline_in_m + g_pipeline_out + c_sel_buf_read_lat;
@@ -86,7 +85,6 @@ architecture str of ss_reorder is
nof_dat => c_mem_nof_dat_mm,
init_sl => '0');
-
constant c_select_buf_dp : t_c_mem := (latency => 1,
adr_w => ceil_log2(g_frame_size),
dat_w => c_mem_dat_w_dp,
@@ -109,7 +107,6 @@ architecture str of ss_reorder is
signal reorder_select : std_logic_vector(c_mem_dat_w_dp - 1 downto 0);
--SIGNAL reorder_select : STD_LOGIC_VECTOR(g_nof_outputs*c_select_w-1 DOWNTO 0);
signal reorder_chan_cnt : std_logic_vector(c_select_buf_dp.adr_w - 1 downto 0);
-
begin
---------------------------------------------------------------
-- PREPARE THE INPUT DATA.
@@ -230,6 +227,4 @@ begin
end process;
output_sosi_arr <= r.output_sosi_arr;
-
end str;
-
diff --git a/libraries/base/ss/src/vhdl/ss_retrieve.vhd b/libraries/base/ss/src/vhdl/ss_retrieve.vhd
index 3ccdb36ae78f64132cdd378d98b897016162b714..2d4c2b3c4bcfe77921cfd4d363960a2a014b9fce 100644
--- a/libraries/base/ss/src/vhdl/ss_retrieve.vhd
+++ b/libraries/base/ss/src/vhdl/ss_retrieve.vhd
@@ -43,7 +43,6 @@ use dp_lib.dp_stream_pkg.all;
-- SS can store a frame and retrieve it immediately in any order, so worst
-- case the last stored data can be retrieved first.
-
entity ss_retrieve is
generic (
g_dsp_data_w : natural;
@@ -72,9 +71,7 @@ entity ss_retrieve is
);
end ss_retrieve;
-
architecture rtl of ss_retrieve is
-
constant c_retrieve_lat : natural := 2; -- fixed 1 for select buf read + 1 for store buf read
signal ch_cnt : integer range 0 to g_nof_ch_sel - 1;
@@ -87,9 +84,7 @@ architecture rtl of ss_retrieve is
signal retrieve_sop_dly : std_logic_vector(0 to c_retrieve_lat);
signal retrieve_eop_dly : std_logic_vector(0 to c_retrieve_lat);
-
begin
-
p_reg : process (clk, rst)
begin
if rst = '1' then
@@ -111,7 +106,6 @@ begin
end if;
end process;
-
-- Enable retrieve when a block has been stored, disable retrieve when the block has been output
u_retrieve_en : entity common_lib.common_switch
generic map (
@@ -143,7 +137,6 @@ begin
nxt_ch_cnt <= ch_cnt + 1;
end if;
end if;
-
end process;
-- Optional SS output frame control
@@ -165,5 +158,4 @@ begin
output_sosi.valid <= retrieve_miso.rdval;
output_sosi.sop <= retrieve_sop_dly(c_retrieve_lat);
output_sosi.eop <= retrieve_eop_dly(c_retrieve_lat);
-
end rtl;
diff --git a/libraries/base/ss/src/vhdl/ss_store.vhd b/libraries/base/ss/src/vhdl/ss_store.vhd
index 0e13eeae23477661695a73bd37e3349fe5c4e63b..b0acf7da04934d4c22104817ab993caeea891c3c 100644
--- a/libraries/base/ss/src/vhdl/ss_store.vhd
+++ b/libraries/base/ss/src/vhdl/ss_store.vhd
@@ -64,9 +64,7 @@ entity ss_store is
);
end ss_store;
-
architecture rtl of ss_store is
-
signal ch_cnt : integer range 0 to g_nof_ch_in - 1;
signal nxt_ch_cnt : integer;
@@ -74,9 +72,7 @@ architecture rtl of ss_store is
signal nxt_store_mosi : t_mem_mosi := c_mem_mosi_rst;
signal nxt_store_done : std_logic;
-
begin
-
store_mosi <= i_store_mosi;
p_reg : process (clk, rst)
diff --git a/libraries/base/ss/src/vhdl/ss_wide.vhd b/libraries/base/ss/src/vhdl/ss_wide.vhd
index 07d4923de18ffb860fe2e1bdc70b11fdecfa4293..37bb7363ccc4da379d7723f6daf5e13167ad545e 100644
--- a/libraries/base/ss/src/vhdl/ss_wide.vhd
+++ b/libraries/base/ss/src/vhdl/ss_wide.vhd
@@ -69,16 +69,13 @@ entity ss_wide is
end ss_wide;
architecture str of ss_wide is
-
constant c_mem_addr_w : natural := ceil_log2(g_nof_ch_sel);
constant c_nof_ch_in : natural := g_nof_ch_in;
constant c_nof_ch_sel : natural := g_nof_ch_sel;
signal ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(g_wb_factor - 1 downto 0);
signal ram_ss_ss_wide_miso_arr : t_mem_miso_arr(g_wb_factor - 1 downto 0) := (others => c_mem_miso_rst);
-
begin
-
---------------------------------------------------------------
-- COMBINE MEMORY MAPPED INTERFACES
---------------------------------------------------------------
@@ -129,4 +126,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd b/libraries/base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd
index 0eeb243c665cd6aacaa4c5b91630af7b53d3e9af..df1f3539298dfe20be9c76366897add67e399d28 100644
--- a/libraries/base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_mmf_ss_parallel.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -63,7 +62,6 @@ entity tb_mmf_ss_parallel is
end tb_mmf_ss_parallel;
architecture tb of tb_mmf_ss_parallel is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -138,9 +136,7 @@ architecture tb of tb_mmf_ss_parallel is
signal out_sosi_arr : t_dp_sosi_arr(g_nof_outputs - 1 downto 0) := (others => c_dp_sosi_rst);
signal out_siso_arr : t_dp_siso_arr(g_nof_outputs - 1 downto 0) := (others => c_dp_siso_rdy);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -303,5 +299,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd b/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd
index 41f059e0c506fa5a90e03bede5e360170f256a8c..589296951b02ebc8fc79201ed41eabf07e0ffd15 100644
--- a/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_mmf_ss_reorder.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -65,7 +64,6 @@ entity tb_mmf_ss_reorder is
end tb_mmf_ss_reorder;
architecture tb of tb_mmf_ss_reorder is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -134,9 +132,7 @@ architecture tb of tb_mmf_ss_reorder is
signal out_sosi_arr : t_dp_sosi_arr(g_nof_outputs - 1 downto 0) := (others => c_dp_sosi_rst);
signal out_siso_arr : t_dp_siso_arr(g_nof_outputs - 1 downto 0) := (others => c_dp_siso_rdy);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -297,5 +293,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/base/ss/tb/vhdl/tb_ss.vhd b/libraries/base/ss/tb/vhdl/tb_ss.vhd
index 6cec4b6ff14baaec0169f54949180c03f0678aee..35585289e6e8b6bee6ccb558681014c2b88c800c 100644
--- a/libraries/base/ss/tb/vhdl/tb_ss.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_ss.vhd
@@ -30,7 +30,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
-- Usage:
-- > as 10
-- > run -all
@@ -71,9 +70,7 @@ entity tb_ss is
);
end tb_ss;
-
architecture tb of tb_ss is
-
constant clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -114,9 +111,7 @@ architecture tb of tb_ss is
signal first_in_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
signal first_out_bsn : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 5;
@@ -156,7 +151,6 @@ begin
toggle when g_mode_out_ready = 1 else
not toggle;
-
------------------------------------------------------------------------------
-- Generate input data blocks
------------------------------------------------------------------------------
@@ -206,7 +200,6 @@ begin
dp_sosi.bsn <= TO_DP_BSN(bsn);
end process;
-
------------------------------------------------------------------------------
-- Compensate for reverse order read out of DUT so that proc_verify_* have incrementing data
------------------------------------------------------------------------------
@@ -316,7 +309,7 @@ begin
gen_verify_non_complex: if not(g_use_complex) generate
proc_dp_verify_data("out_sosi.data", c_unsigned_0, to_unsigned(c_nof_ch_gap,32), clk, verify_en, out_sosi.valid, out_sosi.data, prev_out_sosi.data);
end generate;
+
-- verify output framing
proc_dp_verify_sop_and_eop(clk, out_sosi.valid, out_sosi.sop, out_sosi.eop, hold_out_sosi.sop);
-
end tb;
diff --git a/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd b/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd
index 7fb3b08f0811e43fc0dda3ff5d34fd17f7b18064..c4b8e4051dc6dbf08266de759cd7e96cd437d2f2 100644
--- a/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_ss_wide.vhd
@@ -29,7 +29,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
-- Usage:
-- > as 10
-- > run -all
@@ -40,9 +39,7 @@ use dp_lib.tb_dp_pkg.all;
entity tb_ss_wide is
end tb_ss_wide;
-
architecture tb of tb_ss_wide is
-
constant c_clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -76,9 +73,7 @@ architecture tb of tb_ss_wide is
signal out_siso_arr : t_dp_siso_arr(c_wb_factor - 1 downto 0) := (others => c_dp_siso_rdy);
signal out_sosi_arr : t_dp_sosi_arr(c_wb_factor - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -180,5 +175,4 @@ begin
output_sosi_arr => out_sosi_arr,
output_siso_arr => out_siso_arr
);
-
end tb;
diff --git a/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd b/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd
index 48ee75c6202cec245102a0d673e35f9eb9fee7f1..48c9b93725957bcfbd6cc274e5754c8373e7e9a3 100644
--- a/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd
+++ b/libraries/base/ss/tb/vhdl/tb_tb_ss.vhd
@@ -26,13 +26,10 @@ entity tb_tb_ss is
end tb_tb_ss;
architecture tb of tb_tb_ss is
-
constant c_nof_sync : natural := 20;
constant c_reverse_ss_map : boolean := true;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- > as 2
-- > run -all --> OK
@@ -63,5 +60,4 @@ begin
u_act_invert_toggle_32_16 : entity work.tb_ss generic map (0, 2, c_nof_sync, c_reverse_ss_map, 32, 16, false);
u_rnd_invert_toggle_32_16 : entity work.tb_ss generic map (1, 2, c_nof_sync, c_reverse_ss_map, 32, 16, false);
-
end tb;
diff --git a/libraries/base/tst/src/vhdl/tst_input.vhd b/libraries/base/tst/src/vhdl/tst_input.vhd
index e6076abfd19fdf9d97a90effe4ffb96f677aff44..fbfbf672293e49e9381930590c64268c1acea033 100644
--- a/libraries/base/tst/src/vhdl/tst_input.vhd
+++ b/libraries/base/tst/src/vhdl/tst_input.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
-
entity tst_input is
generic (
g_file_name : string;
@@ -53,16 +52,13 @@ begin
severity ERROR;
end tst_input;
-
architecture beh of tst_input is
-
constant c_prag : character := '%';
constant c_prag_sync : string := c_prag & "SYNC";
constant c_prag_gap : string := c_prag & "GAP ";
constant c_prag_msg : string := c_prag & "MSG ";
constant c_prag_next : string := c_prag & "NEXT";
-
type STATE_TYPE is
( s_init, s_idle, s_next, s_read, s_enable, s_data, s_pragma, s_msg, s_sync, s_gap, s_eof);
@@ -86,9 +82,7 @@ architecture beh of tst_input is
signal nxt_gap_count : natural;
signal nxt_wait : std_logic;
signal nxt_sync : std_logic;
-
begin
-
out_dat <= rd_dat;
out_val <= rd_val;
out_eof <= eof;
@@ -134,7 +128,6 @@ begin
variable cycle_state : STATE_TYPE;
variable nxt_cycle_state : STATE_TYPE;
-
procedure show_msg(sev : in severity_level; msg : in string) is
begin
report msg & character'val(13)
@@ -143,7 +136,6 @@ begin
& " File: " & g_file_name
severity sev;
end show_msg;
-
begin
nxt_cycle_state := state;
cycle_lno := lno;
@@ -303,5 +295,4 @@ begin
nxt_lno <= cycle_lno;
nxt_rep <= cycle_rep;
end process;
-
end beh;
diff --git a/libraries/base/tst/src/vhdl/tst_output.vhd b/libraries/base/tst/src/vhdl/tst_output.vhd
index b4da110cec33e6effb568d0e64eb58b917b5cac1..2398cf1223bf1c63eacd6b5174957dc2a1b991aa 100644
--- a/libraries/base/tst/src/vhdl/tst_output.vhd
+++ b/libraries/base/tst/src/vhdl/tst_output.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.TEXTIO.all;
-
entity tst_output is
generic (
g_file_name : string;
@@ -44,7 +43,6 @@ begin
severity ERROR;
end tst_output;
-
architecture beh of tst_output is
file out_file : TEXT;
begin
diff --git a/libraries/base/uth/src/vhdl/uth_pkg.vhd b/libraries/base/uth/src/vhdl/uth_pkg.vhd
index b66e6349364bd6a65e9ab73622dea5daf34af58d..fc4b0c498bee6fe6b7bba517c60bef2cc5f3f67a 100644
--- a/libraries/base/uth/src/vhdl/uth_pkg.vhd
+++ b/libraries/base/uth/src/vhdl/uth_pkg.vhd
@@ -29,7 +29,6 @@ use easics_lib.PCK_CRC32_D32.all;
use easics_lib.PCK_CRC64_D64.all;
package uth_pkg is
-
--<constants>--
constant c_uth_data_max_w : natural := 256;
constant c_uth_crc64 : natural := 64; -- internally use CRC-8, 16, 32 or 64, use CRC-64 for data wider than 32 bits
@@ -52,12 +51,9 @@ package uth_pkg is
--<global functions>--
function func_uth_crc_w(c_data_w : natural) return natural;
function func_uth_next_crc(data, crc : std_logic_vector) return std_logic_vector;
-
end uth_pkg;
-
package body uth_pkg is
-
--<functions>--
-- Calculate parallel CRC for wide data
function func_uth_parallel_crc(data, crc : std_logic_vector) return std_logic_vector is
@@ -71,10 +67,10 @@ package body uth_pkg is
for I in 0 to c_nof_crc - 1 loop
v_crc((I + 1) * c_uth_crc64 - 1 downto I * c_uth_crc64) := nextCRC64_D64(v_data((I + 1) * c_uth_crc64 - 1 downto I * c_uth_crc64), crc((I + 1) * c_uth_crc64 - 1 downto I * c_uth_crc64));
end loop;
+
return v_crc;
end func_uth_parallel_crc;
-
------------------------------------------------------------------------------
-- Calculate CRC width based on input data width
------------------------------------------------------------------------------
@@ -117,4 +113,3 @@ package body uth_pkg is
end func_uth_next_crc;
end uth_pkg;
-
diff --git a/libraries/base/uth/src/vhdl/uth_rx.vhd b/libraries/base/uth/src/vhdl/uth_rx.vhd
index 7b45f7daa0a2fbc6040dd053875c984e2f76dd0f..6d186c500dcfc1e5d32953eb1f86a1e75de8b0fc 100644
--- a/libraries/base/uth/src/vhdl/uth_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_rx.vhd
@@ -134,7 +134,6 @@ use work.uth_pkg.all;
-- dp_hold_input at the input. The p_state machine now maintains the RL = 1
-- by using the outputs from the dp_hold_input.
-
entity uth_rx is
generic (
g_data_w : natural := c_uth_data_max_w;
@@ -158,9 +157,7 @@ entity uth_rx is
);
end uth_rx;
-
architecture rtl_adapt of uth_rx is
-
constant c_channel_w : natural := ceil_log2(g_nof_ch);
constant c_preamble : std_logic_vector := c_uth_preamble(g_data_w - 1 downto 0);
@@ -229,9 +226,7 @@ architecture rtl_adapt of uth_rx is
signal state : t_state;
signal nxt_state : t_state;
-
begin
-
-- Map to slv to ease monitoring in wave window
in_data <= snk_in.data(g_data_w - 1 downto 0);
hold_in_data <= snk_in_hld.data(g_data_w - 1 downto 0);
@@ -466,12 +461,9 @@ begin
nxt_state <= v_nxt_state;
end process;
-
end rtl_adapt;
-
architecture rtl_hold of uth_rx is
-
constant c_channel_w : natural := ceil_log2(g_nof_ch);
constant c_preamble : std_logic_vector := c_uth_preamble(g_data_w - 1 downto 0);
@@ -544,9 +536,7 @@ architecture rtl_hold of uth_rx is
signal state : t_state;
signal nxt_state : t_state;
-
begin
-
src_out <= i_src_out;
-- Map to slv to ease monitoring in wave window
@@ -786,6 +776,4 @@ begin
nxt_state <= v_nxt_state;
end process;
-
end rtl_hold;
-
diff --git a/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd b/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd
index 3445d0e974458b1c4236f12dee50f9904fee5674..77a4beeb5a2f6fa2568319d0dd68514be46c2c24 100644
--- a/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd
+++ b/libraries/base/uth/src/vhdl/uth_rx_tlen.vhd
@@ -67,15 +67,11 @@ entity uth_rx_tlen is
);
end uth_rx_tlen;
-
architecture rtl of uth_rx_tlen is
-
-- Map input t_natural_arr range to range 0 TO g_nof_ch-1
constant c_typ_arr : t_natural_arr(0 to g_nof_ch - 1) := g_typ_arr;
constant c_len_arr : t_natural_arr(0 to g_nof_ch - 1) := g_len_arr;
-
begin
-
process(tlen)
variable v_tlen : std_logic_vector(g_data_w - 1 downto 0);
begin
@@ -92,5 +88,4 @@ begin
end if;
end loop;
end process;
-
end rtl;
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd b/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
index 80144f79d827a0784f1a8412134464502311c5ff..4db9301b8b012b64f2b7b03d1a4b2f5957c6129b 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_bidir.vhd
@@ -28,7 +28,6 @@
-- . Some of the constants can be changed into generics when some future
-- application needs so.
-
library IEEE, common_lib, technology_lib, dp_lib, uth_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -91,9 +90,7 @@ entity uth_terminal_bidir is
);
end uth_terminal_bidir;
-
architecture str of uth_terminal_bidir is
-
-- DP/UTH packet
constant c_dp_packet_len : natural := func_dp_packet_overhead_len(g_packet_data_w) + g_usr_frame_len;
constant c_uth_packet_len : natural := c_dp_packet_len + c_uth_nof_overhead;
@@ -120,9 +117,7 @@ architecture str of uth_terminal_bidir is
-- Furthermore typically Rx does not need slack because frame headers and tails are stripped.
constant c_rx_input_fifo_fill : natural := 0;
constant c_rx_input_fifo_size : natural := c_bram_m9k_fifo_depth; -- choose to use full BRAM size = 256 for FIFO depth
-
begin
-
gen_tx : if g_use_tx = true generate
u_uth_terminal_tx : entity work.uth_terminal_tx
generic map (
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
index 3aec040cb0a72b28866ad3a697d4b55d11d51823..e31b47462351dcb0c20f5fcf3ab81e1edb9012b4 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_rx.vhd
@@ -91,9 +91,7 @@ entity uth_terminal_rx is
);
end uth_terminal_rx;
-
architecture str of uth_terminal_rx is
-
constant c_packet_channel_lo : natural := true_log2(g_uth_nof_ch);
constant c_complex_w : natural := g_data_w / 2; -- DP complex data width of Im, Re packet as Im & Re in g_data_w
@@ -108,9 +106,7 @@ architecture str of uth_terminal_rx is
signal out_sosi_arr : t_dp_sosi_arr(g_nof_output - 1 downto 0);
signal src_data_arr : t_dp_sosi_arr(g_nof_output - 1 downto 0);
-
begin
-
-- Make internal sosi available for debug monitoring
mon_pkt_sosi_arr <= pkt_sosi_arr;
mon_dist_sosi_arr <= dist_sosi_arr;
@@ -149,7 +145,6 @@ begin
end generate;
end generate;
-
------------------------------------------------------------------------------
-- UTHernet receiver
------------------------------------------------------------------------------
@@ -179,7 +174,6 @@ begin
);
end generate;
-
------------------------------------------------------------------------------
-- DP distribute: g_nof_input --> g_nof_output
------------------------------------------------------------------------------
@@ -210,7 +204,6 @@ begin
src_out_arr => dist_sosi_arr
);
-
------------------------------------------------------------------------------
-- Output FIFO (g_output_use_fifo)
------------------------------------------------------------------------------
@@ -249,7 +242,6 @@ begin
end generate;
end generate;
-
------------------------------------------------------------------------------
-- DP Packet decoder
------------------------------------------------------------------------------
@@ -275,7 +267,6 @@ begin
);
end generate;
-
------------------------------------------------------------------------------
-- Unmap sosi.data = sosi.im & sosi.re
------------------------------------------------------------------------------
@@ -288,5 +279,4 @@ begin
src_out_arr(I).re <= RESIZE_DP_DSP_DATA(src_data_arr(I).data( c_complex_w - 1 downto 0));
end loop;
end process;
-
end str;
diff --git a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
index 23db70cdbeee4f2ccc56cb73e41476e07bf5077b..9b177da33e6bae32d68d6417fea65010e75a15b3 100644
--- a/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_terminal_tx.vhd
@@ -92,9 +92,7 @@ entity uth_terminal_tx is
);
end uth_terminal_tx;
-
architecture str of uth_terminal_tx is
-
constant c_packet_channel_lo : natural := true_log2(g_uth_nof_ch);
constant c_complex_w : natural := g_data_w / 2;
@@ -109,9 +107,7 @@ architecture str of uth_terminal_tx is
signal dist_sosi_arr : t_dp_sosi_arr(g_nof_output - 1 downto 0);
signal out_siso_arr : t_dp_siso_arr(g_nof_output - 1 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(g_nof_output - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Forward sosi.data or complex fields as data
------------------------------------------------------------------------------
@@ -168,7 +164,6 @@ begin
end generate;
end generate;
-
------------------------------------------------------------------------------
-- DP Packet encoder
------------------------------------------------------------------------------
@@ -190,7 +185,6 @@ begin
);
end generate;
-
------------------------------------------------------------------------------
-- DP distribute: g_nof_input --> g_nof_output
------------------------------------------------------------------------------
@@ -220,7 +214,6 @@ begin
src_out_arr => dist_sosi_arr
);
-
------------------------------------------------------------------------------
-- UTHernet transmitter
------------------------------------------------------------------------------
@@ -244,7 +237,6 @@ begin
);
end generate;
-
------------------------------------------------------------------------------
-- Output FIFO (g_output_use_fifo)
------------------------------------------------------------------------------
@@ -277,5 +269,4 @@ begin
);
end generate;
end generate;
-
end str;
diff --git a/libraries/base/uth/src/vhdl/uth_tx.vhd b/libraries/base/uth/src/vhdl/uth_tx.vhd
index 473f380e633d0975450126a8216ca5738b5aad92..e06f41ba99b32a6f1b4d865e35133a8c8b2cedd2 100644
--- a/libraries/base/uth/src/vhdl/uth_tx.vhd
+++ b/libraries/base/uth/src/vhdl/uth_tx.vhd
@@ -122,7 +122,6 @@ use work.uth_pkg.all;
-- 6) Added duty-cycle pulse streaming control to tb_uth to be able to better
-- test uth_tx(rtl_delay).
-
entity uth_tx is
generic (
g_data_w : natural := c_uth_data_max_w;
@@ -142,9 +141,7 @@ entity uth_tx is
);
end uth_tx;
-
architecture rtl_delay of uth_tx is
-
constant c_idle : std_logic_vector := RESIZE_DP_DATA(c_uth_idle);
constant c_preamble : std_logic_vector := RESIZE_DP_DATA(c_uth_preamble);
constant c_sfd : std_logic_vector := RESIZE_DP_DATA(c_uth_sfd);
@@ -196,9 +193,7 @@ architecture rtl_delay of uth_tx is
signal frm_val : std_logic;
signal frm_sop : std_logic;
signal frm_eop : std_logic;
-
begin
-
snk_in_dly(0) <= snk_in; -- put combinatorial at index [0]
src_out <= adapt_sosi;
@@ -309,12 +304,9 @@ begin
src_in => src_in,
src_out => adapt_sosi
);
-
end rtl_delay;
-
architecture rtl_hold of uth_tx is
-
constant c_idle : std_logic_vector := RESIZE_DP_DATA(c_uth_idle);
constant c_preamble : std_logic_vector := RESIZE_DP_DATA(c_uth_preamble);
constant c_sfd : std_logic_vector := RESIZE_DP_DATA(c_uth_sfd);
@@ -346,9 +338,7 @@ architecture rtl_hold of uth_tx is
signal i_src_out : t_dp_sosi;
signal nxt_src_out : t_dp_sosi;
-
begin
-
src_out <= i_src_out;
p_clk : process (clk, rst)
@@ -464,5 +454,4 @@ begin
end if;
end case;
end process;
-
end rtl_hold;
diff --git a/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd b/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd
index 430927cf3d6f121c061c8db3c27b3aab589ec56c..dfdd04816a2dc4c4bfb1e1b42fb6a69eaf1ffc96 100644
--- a/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd
+++ b/libraries/base/uth/src/vhdl/uth_tx_tlen.vhd
@@ -68,17 +68,13 @@ entity uth_tx_tlen is
);
end uth_tx_tlen;
-
architecture rtl of uth_tx_tlen is
-
constant c_typ_ofs : natural := g_len_max + 1;
-- Map input t_natural_arr range to range 0 TO g_nof_ch-1
constant c_typ_arr : t_natural_arr(0 to g_nof_ch - 1) := g_typ_arr;
constant c_len_arr : t_natural_arr(0 to g_nof_ch - 1) := g_len_arr;
-
begin
-
assert ceil_log2(g_len_max) < g_data_w
report "uth_tx_tlen: g_len_max is too large to use tlen field as length" severity FAILURE;
@@ -98,5 +94,4 @@ begin
tlen <= RESIZE_SVEC(v_tlen, tlen'length);
end process;
-
end rtl;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_tb_uth_regression.vhd b/libraries/base/uth/tb/vhdl/tb_tb_tb_uth_regression.vhd
index f38871f9293dface1fdc3710faab6e1b50efa21e..09a01aca4794aead9357e3d440c153f558ff5c94 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_tb_uth_regression.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_tb_uth_regression.vhd
@@ -28,7 +28,6 @@
-- > as 3
-- > run -all
-
library IEEE;
use IEEE.std_logic_1164.all;
@@ -37,9 +36,7 @@ end tb_tb_tb_uth_regression;
architecture tb of tb_tb_tb_uth_regression is
begin
-
u_tb_tb_uth : entity work.tb_tb_uth;
u_tb_tb_uth_dp_packet : entity work.tb_tb_uth_dp_packet;
u_tb_tb_uth_terminals : entity work.tb_tb_uth_terminals;
-
end tb;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd b/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd
index ae7175ec632c0210d130fe2596bf50ac3fac166a..587b343f217a35806e986a8f2274273c895e90e6 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_uth.vhd
@@ -30,15 +30,11 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_uth is
end tb_tb_uth;
-
architecture tb of tb_tb_uth is
-
constant c_phy_link_valid_support : boolean := true;
constant c_nof_repeat : natural := 10;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- in_en = active, src_in.ready = active
u_hold_adapt_act_act : entity work.tb_uth generic map ( "HOLD", "ADAPT", c_phy_link_valid_support, e_active, e_active, c_nof_repeat);
u_hold_hold_act_act : entity work.tb_uth generic map ( "HOLD", "HOLD", c_phy_link_valid_support, e_active, e_active, c_nof_repeat);
@@ -74,5 +70,4 @@ begin
u_hold_hold_pls_pls : entity work.tb_uth generic map ( "HOLD", "HOLD", c_phy_link_valid_support, e_pulse, e_pulse, c_nof_repeat);
u_delay_adapt_pls_pls : entity work.tb_uth generic map ("DELAY", "ADAPT", c_phy_link_valid_support, e_pulse, e_pulse, c_nof_repeat); -- much faster than the uth_tx(rtl_hold)
u_delay_hold_pls_pls : entity work.tb_uth generic map ("DELAY", "HOLD", c_phy_link_valid_support, e_pulse, e_pulse, c_nof_repeat); -- much faster than the uth_tx(rtl_hold)
-
end tb;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd b/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd
index a95f95777211bf15ea4ae11a535aa86bac118d18..772792144e127fd9ec05324eff95136da87dd1a7 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_uth_dp_packet.vhd
@@ -30,15 +30,11 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_uth_dp_packet is
end tb_tb_uth_dp_packet;
-
architecture tb of tb_tb_uth_dp_packet is
-
constant c_phy_link_valid_support : boolean := true;
constant c_nof_repeat : natural := 10;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- g_phy_link_valid_support,
-- g_data_w, in_en,
-- src_in.ready, nof repeat
@@ -81,5 +77,4 @@ begin
u_8_pls_act : entity work.tb_uth_dp_packet generic map (true, 8, e_pulse, e_active, c_nof_repeat);
u_8_pls_rnd : entity work.tb_uth_dp_packet generic map (true, 8, e_pulse, e_random, c_nof_repeat);
u_8_pls_pls : entity work.tb_uth_dp_packet generic map (true, 8, e_pulse, e_pulse, c_nof_repeat);
-
end tb;
diff --git a/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd b/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd
index 3d14bf26a287cb70132b1d020291f97f0bcff40b..ee5ed3ed22403c801f7d34e0de30d7dd368190ac 100644
--- a/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_tb_uth_terminals.vhd
@@ -30,15 +30,11 @@ use dp_lib.tb_dp_pkg.all;
entity tb_tb_uth_terminals is
end tb_tb_uth_terminals;
-
architecture tb of tb_tb_uth_terminals is
-
constant c_phy_link_valid_support : boolean := true;
constant c_nof_repeat : natural := 100;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- in_en, out_ready, nof_repeat, phy_fifo_size, uth_rx_timeout_w, tx_use_fifo, tx_fifo_fill, rx_use_fifo, rx_fifo_fill, fifo_use_sync, fifo_use_bsn, nof_input, nof_serial
u_rnd_rnd_4_3 : entity work.tb_uth_terminals generic map (e_random, e_random, c_nof_repeat, 0, 0, false, 0, false, 0, false, false, 4, 3);
u_rnd_rnd_3_4 : entity work.tb_uth_terminals generic map (e_random, e_random, c_nof_repeat, 0, 0, false, 0, false, 0, false, false, 3, 4);
@@ -46,5 +42,4 @@ begin
u_rnd_rnd_3_4_fifo : entity work.tb_uth_terminals generic map (e_random, e_random, c_nof_repeat, 0, 0, true, 15, true, 15, false, false, 3, 4);
u_rnd_rnd_4_3_fifo_sync : entity work.tb_uth_terminals generic map (e_random, e_random, c_nof_repeat, 0, 0, true, 15, true, 15, true, true, 4, 3);
u_rnd_rnd_3_4_fifo_sync : entity work.tb_uth_terminals generic map (e_random, e_random, c_nof_repeat, 0, 0, true, 15, true, 15, true, true, 3, 4);
-
end tb;
diff --git a/libraries/base/uth/tb/vhdl/tb_uth.vhd b/libraries/base/uth/tb/vhdl/tb_uth.vhd
index 438df5d5a77d0654c857bd3c8404c7469d9f6abe..357f71bd7d4266865968f68880642ac7ae4dd35f 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth.vhd
@@ -35,7 +35,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_uth is
generic (
g_use_uth_tx_arch : string := "HOLD"; -- "HOLD" = use uth_tx(rtl_hold)
@@ -49,9 +48,7 @@ entity tb_uth is
);
end tb_uth;
-
architecture tb of tb_uth is
-
constant c_rl : natural := 1;
constant c_data_w : natural := 16;
constant c_typ_ofs : natural := sel_a_b(c_data_w < 16, 2**7, 2**15); -- avoid out of 32 bit INTEGER range for g_data_w > 30
@@ -116,9 +113,7 @@ architecture tb of tb_uth is
signal verify_done : std_logic := '0';
signal expected_uth_rx_data : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -128,7 +123,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse_1);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -146,7 +140,6 @@ begin
random_1(random_1'high) when g_out_ready = e_random else
pulse_1 when g_out_ready = e_pulse;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -196,14 +189,12 @@ begin
wait;
end process;
-
-- Map to slv to ease monitoring in wave window
in_data <= in_sosi.data(in_data'range);
in_val <= in_sosi.valid;
in_sop <= in_sosi.sop;
in_eop <= in_sosi.eop;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -215,7 +206,6 @@ begin
proc_dp_verify_sop_and_eop(clk, uth_rx_val, uth_rx_sop, uth_rx_eop, hold_rx_sop); -- Verify that sop and eop come in pairs
proc_dp_verify_value(e_equal, clk, verify_done, expected_uth_rx_data, prev_uth_rx_data); -- Verify that the stimuli have been applied at all
-
------------------------------------------------------------------------------
-- TRANSMITTER
------------------------------------------------------------------------------
@@ -267,7 +257,6 @@ begin
uth_tx_sop <= uth_tx_sosi.sop;
uth_tx_eop <= uth_tx_sosi.eop;
-
------------------------------------------------------------------------------
-- PHY LINK INTERFACE
------------------------------------------------------------------------------
@@ -293,7 +282,6 @@ begin
phy_link_err <= '0';
--phy_link_err <= '0', '1' AFTER 100.1*clk_period, '0' AFTER 101.1*clk_period; -- determine appropriate error pulse instant from the Wave window in a trial simualtion
-
------------------------------------------------------------------------------
-- RECEIVER
------------------------------------------------------------------------------
@@ -348,5 +336,4 @@ begin
uth_rx_eop <= uth_rx_sosi.eop;
uth_rx_channel <= uth_rx_sosi.channel(uth_rx_channel'range);
uth_rx_err <= uth_rx_sosi.err(uth_rx_err'range);
-
end tb;
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
index d907159bfb2eb8783bfa3f4caead232334451aa4..7ad85b075dfb7e19e94f8272e7c49280cd41bbe4 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_dp_packet.vhd
@@ -38,7 +38,6 @@ use dp_lib.dp_stream_pkg.all;
use dp_lib.dp_packet_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
entity tb_uth_dp_packet is
generic (
g_phy_link_valid_support : boolean := true; -- when TRUE then the PHY link can pass on valid control, else the valid not transported and implicitely always active
@@ -49,9 +48,7 @@ entity tb_uth_dp_packet is
);
end tb_uth_dp_packet;
-
architecture tb of tb_uth_dp_packet is
-
constant c_rl : natural := 1;
constant c_typ_ofs : natural := sel_a_b(g_data_w < 16, 2**7, 2**15); -- avoid out of 32 bit INTEGER range for g_data_w > 30
constant c_max_len : natural := c_typ_ofs - 1;
@@ -207,9 +204,7 @@ architecture tb of tb_uth_dp_packet is
signal in_ready_or : std_logic;
signal in_val_or : std_logic;
signal out_val_or : std_logic;
-
begin
-
tb_end <= '0', vector_and(tb_end_vec) after clk_period * g_nof_repeat * 100;
clk <= (not clk) or tb_end after clk_period / 2;
@@ -221,7 +216,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse_1);
-
------------------------------------------------------------------------------
-- LEVEL 1: STREAM CONTROL
------------------------------------------------------------------------------
@@ -241,7 +235,6 @@ begin
out_siso_2arr <= (others => (others => out_siso));
-
------------------------------------------------------------------------------
-- LEVEL 1: USER DATA GENERATION
------------------------------------------------------------------------------
@@ -313,7 +306,6 @@ begin
end generate;
end generate;
-
------------------------------------------------------------------------------
-- LEVEL 2: MULTIPLEXER
------------------------------------------------------------------------------
@@ -366,7 +358,6 @@ begin
tx_channel <= tx_sosi.channel(c_channel_w - 1 downto 0);
tx_err <= tx_sosi.err(c_err_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- LEVEL 2: MUX-DEMUX LOOPBACK
------------------------------------------------------------------------------
@@ -377,12 +368,12 @@ begin
tx_sosi <= mux_sosi;
demux_sosi <= rx_sosi;
end generate;
+
gen_loopback_mux : if c_loopback_mux = true generate
mux_siso <= demux_siso;
demux_sosi <= mux_sosi;
end generate;
-
------------------------------------------------------------------------------
-- LEVEL 2: DE-MULTIPLEXER
------------------------------------------------------------------------------
@@ -431,7 +422,6 @@ begin
out_val_or <= matrix_or(out_val, c_nof_tlen, c_nof_input);
-
------------------------------------------------------------------------------
-- LEVEL 3: TRANSMITTER DP SOSI ==> DP PACKET
------------------------------------------------------------------------------
@@ -461,7 +451,6 @@ begin
pkt_tx_channel <= pkt_tx_sosi.channel(c_channel_w - 1 downto 0);
pkt_tx_err <= pkt_tx_sosi.err(c_err_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- LEVEL 3: ENC-DEC LOOPBACK
------------------------------------------------------------------------------
@@ -472,12 +461,12 @@ begin
pkt_tx_sosi <= pkt_enc_sosi;
pkt_dec_sosi <= pkt_rx_sosi;
end generate;
+
gen_loopback_packet : if c_loopback_packet = true generate
pkt_enc_siso <= pkt_dec_siso;
pkt_dec_sosi <= pkt_enc_sosi;
end generate;
-
------------------------------------------------------------------------------
-- LEVEL 3: RECEIVER DP PACKET ==> DP SOSI
------------------------------------------------------------------------------
@@ -509,7 +498,6 @@ begin
rx_sync <= rx_sosi.sync;
rx_bsn <= rx_sosi.bsn(c_bsn_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- LEVEL 4: TRANSMITTER DP PACKET ==> UTH PACKET
------------------------------------------------------------------------------
@@ -538,7 +526,6 @@ begin
uth_tx_sop <= uth_tx_sosi.sop;
uth_tx_eop <= uth_tx_sosi.eop;
-
------------------------------------------------------------------------------
-- LEVEL 4: RECEIVER UTH PACKET ==> DP PACKET
------------------------------------------------------------------------------
@@ -571,7 +558,6 @@ begin
pkt_rx_channel <= pkt_rx_sosi.channel(c_channel_w - 1 downto 0);
pkt_rx_err <= pkt_rx_sosi.err(c_err_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- LEVEL 5: PHY LINK INTERFACE
------------------------------------------------------------------------------
@@ -603,5 +589,4 @@ begin
uth_rx_val <= uth_rx_sosi.valid;
uth_rx_sop <= uth_rx_sosi.sop;
uth_rx_eop <= uth_rx_sosi.eop;
-
end tb;
diff --git a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
index 28143e325784c01fb243429f61c7152104ab9625..3c5cf552cd23b1dbeca2f41a8400059ab3aa0b57 100644
--- a/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
+++ b/libraries/base/uth/tb/vhdl/tb_uth_terminals.vhd
@@ -70,9 +70,7 @@ entity tb_uth_terminals is
);
end tb_uth_terminals;
-
architecture tb of tb_uth_terminals is
-
constant c_rl : natural := 1;
constant c_data_init : integer := 0;
constant c_frame_len : integer := 10; -- 96
@@ -157,9 +155,7 @@ architecture tb of tb_uth_terminals is
signal expected_out_data : t_data_arr;
signal expected_out_bsn : t_data_arr;
signal expected_out_channel : t_data_arr;
-
begin
-
tb_end <= vector_and(tb_end_vec);
clk <= (not clk) or tb_end after clk_period / 2;
@@ -171,7 +167,6 @@ begin
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period, '1', rst, clk, pulse_en, pulse_0);
proc_common_gen_duty_pulse(c_pulse_active, c_pulse_period + 1, '1', rst, clk, pulse_en, pulse_1);
-
------------------------------------------------------------------------------
-- STREAM CONTROL
------------------------------------------------------------------------------
@@ -187,7 +182,6 @@ begin
out_siso_arr <= (others => out_siso);
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -232,13 +226,11 @@ begin
end process;
end generate;
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
gen_verify : for I in g_nof_input - 1 downto 0 generate
-
-- Verification logistics
verify_en(I) <= '1' when rising_edge(clk) and out_sosi_arr(I).sop = '1'; -- enable verify after first output sop
count_eop(I) <= count_eop(I) + 1 when rising_edge(clk) and out_sosi_arr(I).eop = '1'; -- count number of output eop
@@ -274,10 +266,8 @@ begin
out_sop(I) <= out_sosi_arr(I).sop;
out_eop(I) <= out_sosi_arr(I).eop;
out_channel(I) <= out_sosi_arr(I).channel(c_data_w - 1 downto 0);
-
end generate;
-
------------------------------------------------------------------------------
-- DUT uth_terminal_tx
------------------------------------------------------------------------------
@@ -319,7 +309,6 @@ begin
src_out_arr => tx_serial_sosi_arr
);
-
-- Model PHY link by a FIFO
no_phy_fifo : if g_phy_fifo_size = 0 generate
tx_serial_siso_arr <= rx_serial_siso_arr;
@@ -398,5 +387,4 @@ begin
src_in_arr => out_siso_arr,
src_out_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/base/util/src/vhdl/util_heater.vhd b/libraries/base/util/src/vhdl/util_heater.vhd
index 93ea856dfb4afd3a43d73e4d63275e1815ac00fd..14ca41286efd16db50f0d613e97bf8184b1e6667 100644
--- a/libraries/base/util/src/vhdl/util_heater.vhd
+++ b/libraries/base/util/src/vhdl/util_heater.vhd
@@ -52,7 +52,6 @@ use work.util_heater_pkg.all;
-- blocks for larger pipeline settings. Therefor g_nof_logic to instantiate
-- util_logic stages to enforce using logic (LUTs and FF).
-
entity util_heater is
generic (
g_technology: natural := c_tech_select_default;
@@ -72,9 +71,7 @@ entity util_heater is
);
end;
-
architecture rtl of util_heater is
-
-- Use MM bus data width = c_word_w = 32
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => c_util_heater_reg_addr_w,
@@ -148,9 +145,7 @@ architecture rtl of util_heater is
signal fifo_in_dat : t_fifo_dat_arr( 0 to g_nof_mac4 - 1);
signal fifo_out_dat : t_fifo_dat_arr( 0 to g_nof_mac4 - 1);
signal logic_dat : t_fifo_dat_arr( 0 to g_nof_mac4 - 1);
-
begin
-
------------------------------------------------------------------------------
-- MM clock domain
------------------------------------------------------------------------------
@@ -300,7 +295,6 @@ begin
-- Heater elements
------------------------------------------------------------------------------
gen_heat : for I in 0 to g_nof_mac4 - 1 generate
-
----------------------------------------------------------------------------
-- Multipliers
----------------------------------------------------------------------------
@@ -396,6 +390,7 @@ begin
out_dat => logic_dat(I)
);
end generate;
+
no_logic : if g_nof_logic = 0 generate
logic_dat(I) <= fifo_out_dat(I);
end generate;
@@ -403,5 +398,4 @@ begin
-- Preserve result, to avoid that the synthesis will optimize all heater element away
nxt_st_element_xor(I) <= vector_xor(logic_dat(I)); -- arbitrary function to group product bits into single output bit
end generate;
-
end rtl;
diff --git a/libraries/base/util/src/vhdl/util_heater_pkg.vhd b/libraries/base/util/src/vhdl/util_heater_pkg.vhd
index f16f0fa4d119379bab8732e31f2d3e0498047b3f..dae51ab7abef1797fe8b00786cb70a2ebefde26d 100644
--- a/libraries/base/util/src/vhdl/util_heater_pkg.vhd
+++ b/libraries/base/util/src/vhdl/util_heater_pkg.vhd
@@ -24,9 +24,7 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
package util_heater_pkg is
-
------------------------------------------------------------------------------
-- Definitions for MM register
------------------------------------------------------------------------------
@@ -55,7 +53,5 @@ package util_heater_pkg is
end util_heater_pkg;
-
package body util_heater_pkg is
end util_heater_pkg;
-
diff --git a/libraries/base/util/src/vhdl/util_logic.vhd b/libraries/base/util/src/vhdl/util_logic.vhd
index 3de245a52c6fe21d9d3ba7a46c5f2fc9913b7a39..b50cc43071a2662495ddaa632b4dc746eb9b44f6 100644
--- a/libraries/base/util/src/vhdl/util_logic.vhd
+++ b/libraries/base/util/src/vhdl/util_logic.vhd
@@ -19,7 +19,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose : Dummy function to use logic (LUTs and FF)
-- Description:
-- There are g_nof_reg >= 0 register stages in series. Each register stage
@@ -44,18 +43,14 @@ entity util_logic is
);
end util_logic;
-
architecture rtl of util_logic is
-
constant c_reset_value : std_logic_vector(out_dat'range) := (others => '0');
type t_out_dat is array (natural range <>) of std_logic_vector(out_dat'range);
signal out_dat_reg : t_out_dat(0 to g_nof_reg) := (others => c_reset_value);
signal nxt_out_dat_reg : t_out_dat(0 to g_nof_reg);
-
begin
-
gen_reg : for I in 1 to g_nof_reg generate
p_clk : process(clk)
begin
@@ -83,6 +78,4 @@ begin
end process;
out_dat <= out_dat_reg(g_nof_reg);
-
end rtl;
-
diff --git a/libraries/base/util/tb/vhdl/tb_util_heater.vhd b/libraries/base/util/tb/vhdl/tb_util_heater.vhd
index cef94561111b058a42b7906945f770f6e29f8ac7..6441abf5667c9a925f3d2bd015aa2760448e45d8 100644
--- a/libraries/base/util/tb/vhdl/tb_util_heater.vhd
+++ b/libraries/base/util/tb/vhdl/tb_util_heater.vhd
@@ -28,13 +28,10 @@ use common_lib.common_mem_pkg.all;
use common_lib.tb_common_mem_pkg.all;
use work.util_heater_pkg.all;
-
entity tb_util_heater is
end tb_util_heater;
-
architecture tb of tb_util_heater is
-
constant mm_clk_period : time := 8 ns;
constant st_clk_period : time := 5 ns;
@@ -59,9 +56,7 @@ architecture tb of tb_util_heater is
signal mm_mosi : t_mem_mosi;
signal mm_miso : t_mem_miso;
-
begin
-
-- as 10
-- run -all
@@ -120,5 +115,4 @@ begin
sla_in => mm_mosi,
sla_out => mm_miso
);
-
end tb;
diff --git a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
index a5769ada1dd2814fe3c5da037bf48b753feeb24f..25a30b681c5ccb464828024b2821286d28804b6e 100644
--- a/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
+++ b/libraries/dsp/beamformer/src/vhdl/beamformer.vhd
@@ -83,7 +83,6 @@ entity beamformer is
end beamformer;
architecture str of beamformer is
-
------------------------------------------------------------------------------
-- Weights RAM
------------------------------------------------------------------------------
@@ -130,15 +129,12 @@ architecture str of beamformer is
------------------------------------------------------------------------------
signal dp_complex_mult_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs - 1 downto 0);
signal dp_complex_mult_src_out_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Weights RAM
------------------------------------------------------------------------------
gen_weight_ram : if g_use_weight_ram = true generate
gen_common_ram_crw_crw : for i in 0 to g_nof_inputs - 1 generate
-
-- Read request on every incoming valid cycle
common_ram_crw_crw_rd_en_b_arr(i) <= snk_in_arr(i).valid;
@@ -177,7 +173,6 @@ begin
common_ram_crw_crw_src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_ram_crw_crw_rd_dat_b_arr(i)( g_weights_w - 1 downto 0));
common_ram_crw_crw_src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_ram_crw_crw_rd_dat_b_arr(i)(2 * g_weights_w - 1 downto g_weights_w));
common_ram_crw_crw_src_out_arr(i).valid <= common_ram_crw_crw_rd_val_b_arr(i);
-
end generate;
end generate;
@@ -186,7 +181,6 @@ begin
------------------------------------------------------------------------------
gen_weight_reg : if g_use_weight_reg = true generate
gen_common_reg_r_w_dc : for i in 0 to g_nof_inputs - 1 generate
-
u_common_reg_r_w_dc : entity common_lib.common_reg_r_w_dc
generic map (
g_cross_clock_domain => true,
@@ -219,7 +213,6 @@ begin
-- REG output rewired to 'RAM' SOSI array. The weight is indexed by reg_weight_addr.
common_ram_crw_crw_src_out_arr(i).re <= RESIZE_DP_DSP_DATA(common_reg_r_w_dc_out_reg_2arr(i)(TO_UINT(reg_weight_addr))( g_weights_w - 1 downto 0));
common_ram_crw_crw_src_out_arr(i).im <= RESIZE_DP_DSP_DATA(common_reg_r_w_dc_out_reg_2arr(i)(TO_UINT(reg_weight_addr))(2 * g_weights_w - 1 downto g_weights_w));
-
end generate;
gen_readback: if g_weights_ram_dual_port = true generate
@@ -309,5 +302,4 @@ begin
reg_weight_addr <= weight_addr;
end if;
end process;
-
end str;
diff --git a/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd b/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd
index b68d25c0826cdb74e7fe0d7c841ce0853a0de18d..1b949c26292a4ab4dbaeacb3aa1776a0c7a7be0c 100644
--- a/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd
+++ b/libraries/dsp/beamformer/tb/vhdl/tb_beamformer.vhd
@@ -53,7 +53,6 @@ entity tb_beamformer is
end tb_beamformer;
architecture tb of tb_beamformer is
-
-----------------------------------------------------------------------------
-- General
-----------------------------------------------------------------------------
@@ -96,7 +95,6 @@ architecture tb of tb_beamformer is
signal ram_beamformer_mosi : t_mem_mosi := c_mem_mosi_rst;
signal ram_beamformer_miso : t_mem_miso := c_mem_miso_rst;
-
signal beamformer_snk_in_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal beamformer_src_out : t_dp_sosi;
@@ -110,7 +108,6 @@ architecture tb of tb_beamformer is
-- used to set snk_in re data
signal snk_re_data : std_logic_vector(g_data_w - 1 downto 0) := TO_SVEC(1, g_data_w);
signal snk_im_data : std_logic_vector(g_data_w - 1 downto 0) := TO_SVEC(0, g_data_w);
-
begin
-----------------------------------------------------------------------------
-- Clocks and reset
@@ -292,7 +289,6 @@ architecture tb of tb_beamformer is
wait;
end process;
-
-----------------------------------------------------------------------------
-- beamformer for each TAB
-----------------------------------------------------------------------------
@@ -326,7 +322,4 @@ architecture tb of tb_beamformer is
snk_in_arr => beamformer_snk_in_arr,
src_out => beamformer_src_out
);
-
end tb;
-
-
diff --git a/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd b/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd
index be007a1b01bbdb64901151b155303fe581ce4ce7..cea840d0006c2ed21aa83e0628597bd5c721faf9 100644
--- a/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd
+++ b/libraries/dsp/beamformer/tb/vhdl/tb_tb_beamformer.vhd
@@ -35,7 +35,6 @@ end tb_tb_beamformer;
architecture tb of tb_tb_beamformer is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- Usage
-- > as 8
-- > run -all
@@ -60,5 +59,4 @@ sim_i32_ram_beamformer : entity work.tb_beamformer generic map (3, 32, 32, 8, tr
sim_i01_reg_beamformer : entity work.tb_beamformer generic map (4, 1, 32, 8, false, true);
sim_i02_reg_beamformer : entity work.tb_beamformer generic map (5, 2, 32, 8, false, true);
sim_i32_reg_beamformer : entity work.tb_beamformer generic map (6, 32, 32, 8, false, true);
-
end tb;
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
index 02907390b85ec88e0578b553dd5eacc21702e98c..d9fa0804e75ae2d367ed7790a6c45f2a712c2587 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/mmm_unb1_fn_bf.vhd
@@ -114,9 +114,7 @@ entity mmm_unb1_fn_bf is
);
end mmm_unb1_fn_bf;
-
architecture str of mmm_unb1_fn_bf is
-
-- Application specific constants (or generics)
constant c_bg_diag_wave_period : natural := 4;
@@ -145,7 +143,6 @@ architecture str of mmm_unb1_fn_bf is
constant c_dut_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"002286080001";
signal eth_psc_access : std_logic;
-
signal reg_ppsh_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_ppsh_miso : t_mem_miso := c_mem_miso_rst;
@@ -162,9 +159,7 @@ architecture str of mmm_unb1_fn_bf is
signal sim_eth_psc_access : std_logic;
signal sim_eth1g_reg_mosi : t_mem_mosi;
-
begin
-
mm_clk <= i_mm_clk;
eth1g_tse_clk <= i_tse_clk;
@@ -172,7 +167,6 @@ begin
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
@@ -230,7 +224,6 @@ begin
u_mm_file_ram_diag_bg : mm_file generic map(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "RAM_DIAG_BG")
port map(mm_rst, i_mm_clk, ram_diag_bg_mosi, ram_diag_bg_miso );
-
----------------------------------------------------------------------------
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
@@ -265,7 +258,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
-----------------------------------------------------------------------------
@@ -275,7 +267,6 @@ begin
-- SOPC for synthesis
----------------------------------------------------------------------------
gen_sopc : if g_sim = false generate
-
u_sopc : entity work.sopc_unb1_fn_bf
port map (
-- 1) global signals:
@@ -436,16 +427,3 @@ begin
);
end generate;
end;
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
index 33a4c4b6ee11f93bbb3c21b54f49887e751a7893..bcf58a48080b76b2f7eba62a8b04cae942a81b74 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/node_unb1_fn_bf.vhd
@@ -93,7 +93,6 @@ entity node_unb1_fn_bf is
end node_unb1_fn_bf;
architecture str of node_unb1_fn_bf is
-
-----------------------------------------------------------------------------
-- Block generator
-----------------------------------------------------------------------------
@@ -115,9 +114,7 @@ architecture str of node_unb1_fn_bf is
signal bg_out_sosi_arr : t_dp_sosi_arr( g_bf.nof_input_streams - 1 downto 0);
signal i_out_bst_sosi_arr : t_dp_sosi_arr(g_bf.nof_bf_units - 1 downto 0);
-
begin
-
out_bst_sosi_arr <= i_out_bst_sosi_arr;
---------------------------------------------------------------------------------------
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
index 2db32096c168033b0b7aedb182f305f1d215a063..39ea6ff5eab751d7ea13b0e372324c0c5752feea 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/src/vhdl/unb1_fn_bf.vhd
@@ -70,10 +70,7 @@ entity unb1_fn_bf is
);
end unb1_fn_bf;
-
architecture str of unb1_fn_bf is
-
-
constant c_bf_offload : boolean := false; -- Offload BF out(0) datapath to 1GbE UDP TX port
constant c_use_phy : t_c_unb1_board_use_phy := (1, 0, 0, 0, 0, 0, 0, 1);
constant c_fw_version : t_unb1_board_fw_version := (2, 3); -- firmware version x.y
@@ -159,7 +156,6 @@ architecture str of unb1_fn_bf is
signal reg_unb_sens_mosi : t_mem_mosi := c_mem_mosi_rst;
signal reg_unb_sens_miso : t_mem_miso;
-
signal reg_diagnostics_mosi : t_mem_mosi;
signal reg_diagnostics_miso : t_mem_miso;
-- . dp_ram_from_mm for DP offload (header insertion)
@@ -180,9 +176,7 @@ architecture str of unb1_fn_bf is
-- ST interface
signal beams_sosi_arr : t_dp_sosi_arr(g_bf.nof_bf_units - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- General control function
-----------------------------------------------------------------------------
@@ -275,7 +269,6 @@ begin
ETH_SGOUT => ETH_SGOUT
);
-
-----------------------------------------------------------------------------
-- MM master
-----------------------------------------------------------------------------
@@ -399,16 +392,3 @@ begin
bf_out_offload_tx_siso_arr => eth1g_udp_tx_siso_arr
);
end;
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd b/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
index b5302c7f45911beec6c58f214e964bcdfa93fd2d..2ab0d75b8dff6796229f04a989d97f0472f647ff 100644
--- a/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
+++ b/libraries/dsp/bf/designs/unb1_fn_bf/tb/vhdl/tb_unb1_fn_bf.vhd
@@ -24,7 +24,6 @@
-- The DUT can be targeted at unb 0, fn 3 with the same Python scripts
-- that are used on hardware.
-
library IEEE, common_lib, unb1_board_lib, i2c_lib, bf_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -56,7 +55,6 @@ generic(
end tb_unb1_fn_bf;
architecture tb of tb_unb1_fn_bf is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -102,9 +100,7 @@ architecture tb of tb_unb1_fn_bf is
constant c_uniboard_current : real := 5.0; -- = assume 5.0 A on UniBoard
constant c_uniboard_supply : real := 48.0; -- = assume 48.0 V on UniBoard
constant c_uniboard_adin : real := -1.0; -- = NC on UniBoard
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -158,5 +154,4 @@ begin
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp
);
-
end tb;
diff --git a/libraries/dsp/bf/src/vhdl/bf.vhd b/libraries/dsp/bf/src/vhdl/bf.vhd
index d7537331e76061f64526022a538ba4980c69a851..ef5b683e186410b65348c3ca2a251c0fb23f9c86 100644
--- a/libraries/dsp/bf/src/vhdl/bf.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf.vhd
@@ -67,7 +67,6 @@ entity bf is
end bf;
architecture str of bf is
-
constant c_frame_size_in : positive := g_bf.nof_subbands * g_bf.nof_signal_paths / g_bf.nof_input_streams;
constant c_reg_st_addr_w : positive := ceil_log2(2);
constant c_ram_st_addr_w : positive := ceil_log2(g_bf.stat_data_sz * g_bf.nof_weights * c_nof_complex); -- The "c_nof_complex" is due to the crosslets capability.
@@ -84,9 +83,7 @@ architecture str of bf is
signal reg_st_sst_miso_arr : t_mem_miso_arr(g_bf.nof_bf_units - 1 downto 0);
signal ram_ss_ss_wide_mosi_arr : t_mem_mosi_arr(g_bf.nof_bf_units - 1 downto 0);
signal ram_ss_ss_wide_miso_arr : t_mem_miso_arr(g_bf.nof_bf_units - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- The MM multiplexers
------------------------------------------------------------------------------
@@ -182,6 +179,4 @@ begin
end generate gen_bf_units;
in_siso_arr <= in_siso_2arr(0);
-
end str;
-
diff --git a/libraries/dsp/bf/src/vhdl/bf_pkg.vhd b/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
index 7b588222da933c1dfe285ca66e3c14c9b855129b..380a12f18f61a46bb3ebbef6896d457156ac45b8 100644
--- a/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package bf_pkg is
-
constant c_bf_note_fifo_is_ful : boolean := true;
constant c_bf_burst_nof_blocks : positive := 4; -- Use 1 for no initial burst, use > 1 to support initial blocks arriving in a burst (= c_nof_no_gap+1 in tb_bf.vhd)
constant c_bf_max_nof_bf_units : natural := 4; -- Setting the maximum number of bf_units in a FPGA.
@@ -56,4 +55,3 @@ end bf_pkg;
package body bf_pkg is
end bf_pkg;
-
diff --git a/libraries/dsp/bf/src/vhdl/bf_unit.vhd b/libraries/dsp/bf/src/vhdl/bf_unit.vhd
index d1e56063130d9da1356bc5ed79e94c9bf17f81d0..73d202ae11ab5603fe1ddd39df97484d7e05e239 100644
--- a/libraries/dsp/bf/src/vhdl/bf_unit.vhd
+++ b/libraries/dsp/bf/src/vhdl/bf_unit.vhd
@@ -89,7 +89,6 @@ entity bf_unit is
end bf_unit;
architecture str of bf_unit is
-
-- Operational mode:
constant c_unit_w : positive := g_bf.in_dat_w + g_bf.in_weight_w - c_sign_w; -- skip double sign bit
constant c_prod_w : positive := c_unit_w + c_sum_of_prod_w; -- keep bit for sum of products in complex multiply
@@ -173,9 +172,7 @@ architecture str of bf_unit is
signal dbg_weights_write_only : boolean := g_weights_write_only;
signal wr_last_weight : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Input registers
------------------------------------------------------------------------------
@@ -498,5 +495,4 @@ begin
reg_st_sst_mosi => reg_st_sst_mosi,
reg_st_sst_miso => reg_st_sst_miso
);
-
end str;
diff --git a/libraries/dsp/bf/tb/vhdl/tb_bf.vhd b/libraries/dsp/bf/tb/vhdl/tb_bf.vhd
index 405893b3d266f8274efac0ec6e2d1178f247ce6a..c8b63bdf6879b3e3a3d4e3374c363a28e08a86bd 100644
--- a/libraries/dsp/bf/tb/vhdl/tb_bf.vhd
+++ b/libraries/dsp/bf/tb/vhdl/tb_bf.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -72,7 +71,6 @@ entity tb_bf is
end tb_bf;
architecture tb of tb_bf is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -157,9 +155,7 @@ architecture tb of tb_bf is
signal beamlets_sosi_arr : t_dp_sosi_arr(c_bf.nof_bf_units - 1 downto 0) := (others => c_dp_sosi_rst);
signal out_siso_arr : t_dp_siso_arr(c_bf.nof_bf_units - 1 downto 0) := (others => c_dp_siso_rdy);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -331,5 +327,4 @@ begin
in_sync => OPEN,
in_sosi_arr => beamlets_sosi_arr
);
-
end tb;
diff --git a/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd b/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd
index eef5000dada3bbf2f85006d529bd7e619a9d1871..185dbec54cd017a0870b0760a69f4a38bed9439a 100644
--- a/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd
+++ b/libraries/dsp/bf/tb/vhdl/tb_bf_unit.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -73,7 +72,6 @@ entity tb_bf_unit is
end tb_bf_unit;
architecture tb of tb_bf_unit is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -157,9 +155,7 @@ architecture tb of tb_bf_unit is
signal bg_sosi_arr : t_dp_sosi_arr(c_bf.nof_input_streams - 1 downto 0);
signal out_sosi_arr : t_dp_sosi_arr(1 - 1 downto 0) := (others => c_dp_sosi_rst);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -332,5 +328,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
index 1c46c88c95006ae3be2eb741ee5997872c692d40..89a874799daa5ae35f72af8ba2667e81e4095ce3 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/mmm_unb1_correlator.vhd
@@ -86,12 +86,10 @@ entity mmm_unb1_correlator is
clk_clk_in_reset_reset_n : in std_logic;
altpll_1_c0_clk : out std_logic
-
);
end mmm_unb1_correlator;
architecture str of mmm_unb1_correlator is
-
constant c_mm_clk_period : time := 8 ns; -- 125 MHz
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr < 4, "FN", "BN");
@@ -192,16 +190,13 @@ architecture str of mmm_unb1_correlator is
altpll_1_locked_conduit_export : out std_logic
);
end component qsys_unb1_correlator;
-
begin
-
mm_clk <= i_mm_clk;
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
gen_mm_file_io : if g_sim = true generate
-
i_mm_clk <= not i_mm_clk after c_mm_clk_period / 2;
mm_locked <= '0', '1' after c_mm_clk_period * 5;
@@ -229,7 +224,6 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
----------------------------------------------------------------------------
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
index 67c4830a294b3790add672e55255faf03751ba56..d71467e0f74c26618c366a39b3a6a180744c39c5 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/src/vhdl/unb1_correlator.vhd
@@ -63,9 +63,7 @@ entity unb1_correlator is
);
end unb1_correlator;
-
architecture str of unb1_correlator is
-
-- Firmware version x.y
constant c_fw_version : t_unb1_board_fw_version := (1, 1);
-- In simulation we don't need the 1GbE core for MM control, deselect it in c_use_phy based on g_sim
@@ -162,9 +160,7 @@ architecture str of unb1_correlator is
signal ram_diag_data_buf_miso : t_mem_miso;
signal reg_diag_data_buf_mosi : t_mem_mosi;
signal reg_diag_data_buf_miso : t_mem_miso;
-
begin
-
-----------------------------------------------------------------------------
-- Block generators
-- . Each stream in block_gen_src_out_arr contains complex subband samples
@@ -432,6 +428,4 @@ begin
eth1g_ram_mosi => eth1g_ram_mosi,
eth1g_ram_miso => eth1g_ram_miso
);
-
end str;
-
diff --git a/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd b/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
index 44a7cd0ee44ebfa52677508e631b84817bf97bc3..2b9513a51598d494558f57275c15420f27c77d42 100644
--- a/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
+++ b/libraries/dsp/correlator/designs/unb1_correlator/tb/vhdl/tb_unb1_correlator.vhd
@@ -35,7 +35,6 @@ entity tb_unb1_correlator is
end tb_unb1_correlator;
architecture tb of tb_unb1_correlator is
-
constant c_sim : boolean := true;
constant c_unb_nr : natural := 0; -- UniBoard 0
@@ -69,9 +68,7 @@ architecture tb of tb_unb1_correlator is
signal sens_scl : std_logic;
signal sens_sda : std_logic;
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -119,5 +116,4 @@ begin
ETH_SGIN => eth_rxp,
ETH_SGOUT => eth_txp
);
-
end tb;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
index 3ae04fca64d3ef0b74f736a138be3c3788fe6211..2eb064ad70a2b65b2bbc596981df29897c5f83e9 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_accumulator.vhd
@@ -55,7 +55,6 @@ entity corr_accumulator is
end corr_accumulator;
architecture str of corr_accumulator is
-
-- Complex accumulator data width: wide enough to support g_nof_channel_accs accumulations
constant c_acc_data_w : natural := g_data_w + ceil_log2(g_nof_channel_accs);
@@ -74,9 +73,7 @@ architecture str of corr_accumulator is
signal output_cnt : std_logic_vector(ceil_log2(g_nof_channels) downto 0);
signal nxt_output_cnt : std_logic_vector(ceil_log2(g_nof_channels) downto 0);
signal output_sync : std_logic;
-
begin
-
-----------------------------------------------------------------------------
-- Adder inputs: current snk_in_arr + corresponding running sum from the FIFO.
-- On an input sync, we'll feed zeros into the second adder input to reset
@@ -179,5 +176,4 @@ begin
reg_snk_in_arr <= snk_in_arr;
end if;
end process;
-
end str;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_adder.vhd b/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
index 71c7a0449bff7bbd83b8377dfdc394789ac567a4..dd8151956247eb37a106a90777e65bdfb6ba1dd3 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_adder.vhd
@@ -48,7 +48,6 @@ entity corr_adder is
end corr_adder;
architecture str of corr_adder is
-
constant c_input_pipeline_depth : natural := 0;
constant c_output_pipeline_depth : natural := 1;
constant c_pipeline_depth : natural := c_input_pipeline_depth + c_output_pipeline_depth;
@@ -59,9 +58,7 @@ architecture str of corr_adder is
signal ranged_common_complex_add_sub_src_out_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal dp_pipeline_src_out_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Delay valid signal
-----------------------------------------------------------------------------
diff --git a/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd b/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd
index 718caae76a94eec684a9090ed352261af21e7375..3664435b342150d9d410d0799427cd069b91b857 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_carousel.vhd
@@ -42,7 +42,6 @@ use dp_lib.dp_stream_pkg.all;
-- . 1 cycle * 6 outputs
-- . Set your g_nof_outputs accordingly.
-
entity corr_carousel is
generic (
g_nof_inputs : natural := 8;
@@ -60,14 +59,11 @@ entity corr_carousel is
end corr_carousel;
architecture rtl of corr_carousel is
-
constant c_nof_permutations : natural := g_nof_inputs * (g_nof_inputs + 1) / 2;
signal nxt_reg_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs - 1 downto 0);
signal reg_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Carousel register shifting
-- . 3-input example, carousel rotation is counter-clockwise:
@@ -115,5 +111,4 @@ begin
reg_out_2arr_2 <= nxt_reg_out_2arr_2;
end if;
end process;
-
end rtl;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_folder.vhd b/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
index 236c3fbe5fa6547ac27008afaf703b928f991d23..99c1a7805c76892e654bf4ac0e501eeedfe24f61 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_folder.vhd
@@ -52,7 +52,6 @@ entity corr_folder is
end corr_folder;
architecture str of corr_folder is
-
component corr_folder is
generic (
g_nof_inputs : natural;
@@ -75,9 +74,7 @@ architecture str of corr_folder is
signal mux_src_out_arr : t_dp_sosi_arr(c_nof_muxes - 1 downto 0);
signal nxt_mux_src_out_arr : t_dp_sosi_arr(c_nof_muxes - 1 downto 0);
-
begin
-
gen_arch: if g_nof_folds /= 0 generate
-----------------------------------------------------------------------------
-- Wire input array to mux_snk_in_arr to make sure we have an even number
@@ -141,7 +138,6 @@ begin
mux_src_out_arr <= nxt_mux_src_out_arr;
end if;
end process;
-
end generate;
-----------------------------------------------------------------------------
@@ -152,4 +148,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd b/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
index 8ce50cd2382cf4ae45ca926f6ca51335c73390a5..0c96de29370718b2ceec2b04b7b4fe492afd4b30 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_folder_2arr_2.vhd
@@ -48,7 +48,6 @@ entity corr_folder_2arr_2 is
end corr_folder_2arr_2;
architecture str of corr_folder_2arr_2 is
-
constant c_nof_outputs : natural := sel_a_b(g_nof_folds >= 0, ceil_div(g_nof_inputs, ceil_pow2(g_nof_folds)), 1);
signal dp_pipeline_snk_in_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs - 1 downto 0);
@@ -59,9 +58,7 @@ architecture str of corr_folder_2arr_2 is
type t_corr_folder_src_out_2arr is array (2 - 1 downto 0) of t_dp_sosi_arr(c_nof_outputs - 1 downto 0);
signal corr_folder_src_out_2arr : t_corr_folder_src_out_2arr;
-
begin
-
------------------------------------------------------------------------------
-- Preserve only the sync of input stream (0)(0)
-- FIXME The above applies to a pulse sync which is always only present on
@@ -143,6 +140,4 @@ begin
src_out_2arr_2(i)(j) <= corr_folder_src_out_2arr(j)(i);
end generate;
end generate;
-
end str;
-
diff --git a/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd b/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
index 935202cbfc1c727b52cf83ed6ebfafaa9df9bdcc..97a02c1aa40a723f2fcdf7ca1263bbdae81114e1 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_multiplier.vhd
@@ -49,7 +49,6 @@ entity corr_multiplier is
end corr_multiplier;
architecture str of corr_multiplier is
-
constant c_pipeline_input : natural := 1;
constant c_pipeline_product : natural := 0;
constant c_pipeline_adder : natural := 1;
@@ -60,9 +59,7 @@ architecture str of corr_multiplier is
signal common_complex_mult_src_out_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal dp_pipeline_src_out_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Complex Multipliers
-----------------------------------------------------------------------------
@@ -113,5 +110,4 @@ begin
in_dat => snk_in_2arr_2(0)(0).sync,
out_dat => src_out_arr(0).sync
);
-
end str;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
index 16847ff430e3b266c8d2fea0229bc69e628f4bd4..dffbdd2202051d045b196b1435423d0c3f2b2937 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_output_framer.vhd
@@ -54,7 +54,6 @@ entity corr_output_framer is
end corr_output_framer;
architecture str of corr_output_framer is
-
signal dp_pipeline_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal dp_block_gen_src_out : t_dp_sosi;
@@ -65,9 +64,7 @@ architecture str of corr_output_framer is
signal folded_word_cnt : std_logic_vector(g_nof_folds - 1 downto 0);
signal nxt_folded_word_cnt : std_logic_vector(g_nof_folds - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- dp_block_gen to create correc SOP,EOP and Sync
-----------------------------------------------------------------------------
@@ -168,6 +165,4 @@ begin
src_out_arr(i).bsn <= channel_bsn_src_out.bsn;
end loop;
end process;
-
end str;
-
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
index 6ce9b9a8f12aa5235d5cc3d68d63906c7ea14b81..376b3babdd50144d0a7d13a230519ad9d3097ba6 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutator.vhd
@@ -57,7 +57,6 @@ entity corr_permutator is
end corr_permutator;
architecture rtl of corr_permutator is
-
constant c_nof_permutations : natural := g_nof_inputs * (g_nof_inputs + 1) / 2;
signal reg_snk_in_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
@@ -67,9 +66,7 @@ architecture rtl of corr_permutator is
signal permu_in_2arr : t_permu_in_2arr;
signal permu_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_permutations - 1 downto 0);
signal nxt_src_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_permutations - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Input wiring: copy the inputs g_nof_inputs times
-- . Direct wiring if we can output all permutations in parallel
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
index fd4b4f70d9d315f0bdbe0ed441cc4285d0f03a0b..9289aa48472f038e9d7e6332b842d12316209c46 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor.vhd
@@ -52,7 +52,6 @@ entity corr_permutor is
end corr_permutor;
architecture rtl of corr_permutor is
-
constant c_nof_permutations : natural := g_nof_inputs * (g_nof_inputs + 1) / 2;
constant c_permutation_table : t_corr_permutation_table := corr_permute(g_nof_inputs, g_nof_cycles); -- Returns 3D array of dimensions nof_folding_cycles*g_nof_outputs*2 input indices
@@ -74,9 +73,7 @@ architecture rtl of corr_permutor is
signal common_pulse_extend_ep_out_valid : std_logic;
signal common_pulse_extend_ep_out_sync : std_logic;
-
begin
-
-----------------------------------------------------------------------------
-- One set of input values is valid for only one clock cycle. We need to
-- preserve the input data for an additional g_nof_cycles-1 clock
@@ -84,7 +81,6 @@ begin
-----------------------------------------------------------------------------
gen_common_paged_reg : if g_nof_cycles > 1 generate
gen_common_paged_reg_i : for i in 0 to g_nof_inputs - 1 generate
-
common_paged_reg_wr_re_arr(i) <= snk_in_arr(i).re(g_data_w - 1 downto 0);
common_paged_reg_wr_im_arr(i) <= snk_in_arr(i).im(g_data_w - 1 downto 0);
@@ -220,5 +216,4 @@ begin
-- snk_out_arr <= nxt_snk_out_arr;
end if;
end process;
-
end rtl;
diff --git a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
index 9ed1df2885ec8afa07a65a5c2c74b4f35cd736f8..fe370e1429b7e61865a068a26a64c2f5785a2339 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_permutor_pkg.vhd
@@ -27,16 +27,13 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package corr_permutor_pkg is
-
-- 3D array of dimensions nof_folding_cycles*nof_outputs*2 input indices
type t_corr_permutation_table is array (integer range <>, integer range <>) of t_natural_arr(1 downto 0);
function corr_permute(nof_inputs : natural; nof_folding_cycles : natural) return t_corr_permutation_table;
-
end corr_permutor_pkg;
package body corr_permutor_pkg is
-
-----------------------------------------------------------------------------
-- Create a table with input->output permutation indices: returns all unique
-- pairs (permutations) of the input indices 0...nof_inputs-1.
@@ -65,6 +62,7 @@ package body corr_permutor_pkg is
for j in 0 to nof_inputs - 1 loop
v_input_index_mat(i,j) := c_input_index_arr(i);
end loop;
+
end loop;
-----------------------------------------------------------------------------
@@ -152,6 +150,3 @@ package body corr_permutor_pkg is
end corr_permute;
end corr_permutor_pkg;
-
-
-
diff --git a/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd b/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
index bf9c7b0dc4ca78589de3e4804946eaf41dc3b0cf..dc3d2e83c14ef0c67fa2ebeb1d622f123cac2ef2 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_unfolder.vhd
@@ -44,7 +44,6 @@ entity corr_unfolder is
end corr_unfolder;
architecture str of corr_unfolder is
-
component corr_unfolder is
generic (
g_nof_inputs : natural;
@@ -71,9 +70,7 @@ architecture str of corr_unfolder is
signal demux_src_out_arr : t_dp_sosi_arr(2 * c_nof_demuxes - 1 downto 0);
signal dp_pipeline_snk_in_arr : t_dp_sosi_arr(c_nof_outputs - 1 downto 0);
-
begin
-
gen_arch: if g_nof_unfolds /= 0 generate
-----------------------------------------------------------------------------
-- Simple 2-output demux logic
@@ -145,7 +142,6 @@ begin
output_sel_arr <= nxt_output_sel_arr;
end if;
end process;
-
end generate;
-----------------------------------------------------------------------------
@@ -156,4 +152,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd b/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
index 8fc8dbdb0e15f981e8751886da04b04f84e159a4..956bc3934e40d30a632009cd85a76eae0292167e 100644
--- a/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
+++ b/libraries/dsp/correlator/src/vhdl/corr_visibility_buffer.vhd
@@ -55,7 +55,6 @@ entity corr_visibility_buffer is
end corr_visibility_buffer;
architecture str of corr_visibility_buffer is
-
------------------------------------------------------------------------------
-- Example input: 6 visibilities, non-folded (g_nof_inputs = 6,
-- g_nof_pre_mult_folds = 0)
@@ -90,9 +89,7 @@ architecture str of corr_visibility_buffer is
signal dp_fifo_sc_src_out_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal dp_fifo_sc_src_in_arr : t_dp_siso_arr(g_nof_inputs - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Buffer the visibilities before the folding stage.
-- . All accumulators output blocks of visibilities at the same time. We need
@@ -167,5 +164,4 @@ begin
end generate;
src_out_arr <= dp_fifo_sc_src_out_arr;
-
end str;
diff --git a/libraries/dsp/correlator/src/vhdl/correlator.vhd b/libraries/dsp/correlator/src/vhdl/correlator.vhd
index 965f502b71f7e0fef9cdecba9afae962b7479c73..b460ccd574061463916d0d265a8dcdaabbb30199 100644
--- a/libraries/dsp/correlator/src/vhdl/correlator.vhd
+++ b/libraries/dsp/correlator/src/vhdl/correlator.vhd
@@ -55,7 +55,6 @@ entity correlator is
end correlator;
architecture str of correlator is
-
constant c_nof_inputs : natural := g_nof_input_streams * pow2(g_input_unfold_factor);
constant c_nof_visibilities : natural := (c_nof_inputs * (c_nof_inputs + 1)) / 2;
@@ -86,9 +85,7 @@ architecture str of correlator is
signal corr_accumulator_src_out_arr : t_dp_sosi_arr(c_nof_mults - 1 downto 0);
signal corr_visibility_buffer_src_out_arr : t_dp_sosi_arr(c_nof_mults - 1 downto 0);
-- SIGNAL corr_output_framer_snk_in_arr : t_dp_sosi_arr(1-1 DOWNTO 0);
-
begin
-
------------------------------------------------------------------------------
-- Check passed parameters
------------------------------------------------------------------------------
@@ -255,5 +252,4 @@ begin
--
-- src_out_arr => src_out_arr
-- );
-
end str;
diff --git a/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd b/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd
index 239c08ead53e44c717a9b4c7c83d422a7ccb8b5f..677ab17f96abeaed302ff12095dea7d5bf62fca3 100644
--- a/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd
+++ b/libraries/dsp/correlator/src/vhdl/correlator_dev.vhd
@@ -75,16 +75,13 @@ entity correlator_dev is
end correlator_dev;
architecture str of correlator_dev is
-
constant c_nof_accumulators : natural := g_nof_channels * g_nof_cycles;
constant c_mult_output_w : natural := 2 * g_data_w;
constant c_acc_data_w : natural := c_mult_output_w + ceil_log2(g_nof_channel_accs);
signal corr_permutor_src_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_mults - 1 downto 0); -- Array of (serialized) pairs
signal corr_multiplier_src_out_arr : t_dp_sosi_arr(g_nof_mults - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- Create all unique pair permutations of the input streams
-- . Also performs serialization
@@ -139,5 +136,4 @@ begin
snk_in_arr => corr_multiplier_src_out_arr,
src_out_arr => src_out_arr
);
-
end str;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
index 6e849f6c02fd881904c5c54b94723ca1acc88f89..ddfce89f279cdd5308105a2eda304b5faef76cdf 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_accumulator.vhd
@@ -40,7 +40,6 @@ entity tb_corr_accumulator is
end tb_corr_accumulator;
architecture tb of tb_corr_accumulator is
-
-----------------------------------------------------------------------------
-- Clock & reset
-----------------------------------------------------------------------------
@@ -87,9 +86,7 @@ architecture tb of tb_corr_accumulator is
signal verify_done : std_logic := '0';
signal out_valid_count : natural;
signal prv_out_valid_count : natural;
-
begin
-
-----------------------------------------------------------------------------
-- Clock & reset
-----------------------------------------------------------------------------
@@ -194,7 +191,6 @@ begin
end if;
out_valid_count <= prv_out_valid_count + 1;
-
end if;
end loop;
@@ -202,7 +198,6 @@ begin
if verify_done = '1' then
assert out_valid_count = c_nof_integration_periods * g_nof_channels report "Incorrect number of valid output cycles" severity ERROR;
end if;
-
end process;
p_clk : process (clk, rst)
@@ -221,5 +216,4 @@ begin
int_period_cnt <= nxt_int_period_cnt;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_carousel.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_carousel.vhd
index 4f82e59b6f2e8b3ac08fb21cf22ee56264e7d9ce..1bbabccac1d598d2e61e7a7b11c23edcfb8eab7c 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_carousel.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_carousel.vhd
@@ -35,7 +35,6 @@ entity tb_corr_carousel is
end tb_corr_carousel;
architecture tb of tb_corr_carousel is
-
constant c_clk_period : time := 10 ns;
constant c_data_w : natural := 32;
constant c_nof_permutations : natural := (g_nof_inputs * (g_nof_inputs + 1)) / 2;
@@ -47,9 +46,7 @@ architecture tb of tb_corr_carousel is
signal carousel_snk_in_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal carousel_src_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_outputs - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -84,5 +81,4 @@ begin
wait for (c_nof_clk_cycles_per_input_val - 1) * c_clk_period;
end loop;
end process;
-
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_folder.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_folder.vhd
index 26757f0f91ba05175308cb59f078776fb023f56a..7524b6166117dd5bd53ccc6295be07c2daf01444 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_folder.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_folder.vhd
@@ -34,7 +34,6 @@ entity tb_corr_folder is
end tb_corr_folder;
architecture tb of tb_corr_folder is
-
constant c_clk_period : time := 10 ns;
constant c_data_w : natural := 32;
@@ -44,10 +43,7 @@ architecture tb of tb_corr_folder is
signal folder_snk_in_2arr_2 : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal folder_src_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_inputs / g_folder_factor - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
-
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_multiplier.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_multiplier.vhd
index cfb4b20510f43d94ee59e3f08fa6df6cbd1f2251..665d96178b470e89829a2c1cb491646a8d64a8c7 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_multiplier.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_multiplier.vhd
@@ -34,17 +34,13 @@ entity tb_corr_multiplier is
end tb_corr_multiplier;
architecture tb of tb_corr_multiplier is
-
constant c_clk_period : time := 10 ns;
constant c_data_w : natural := 32;
signal tb_end : std_logic := '0';
signal clk : std_logic := '1';
signal rst : std_logic;
-
begin
-
clk <= not clk or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
-
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_permutator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_permutator.vhd
index ce03b321e31dc87d99edb9be87c79661580ef231..8dd5a4a8b4690d146e4f6b1939d8c7b08932fc5d 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_permutator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_permutator.vhd
@@ -33,7 +33,6 @@ entity tb_corr_permutator is
end tb_corr_permutator;
architecture tb of tb_corr_permutator is
-
constant c_clk_period : time := 10 ns;
constant c_data_w : natural := 32;
constant c_nof_permutations : natural := (g_nof_inputs * (g_nof_inputs + 1)) / 2;
@@ -44,9 +43,7 @@ architecture tb of tb_corr_permutator is
signal permutator_snk_in_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal permutator_src_out_2arr_2 : t_dp_sosi_2arr_2(c_nof_permutations - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -80,5 +77,4 @@ begin
wait for c_clk_period;
end loop;
end process;
-
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_corr_permutor.vhd b/libraries/dsp/correlator/tb/vhdl/tb_corr_permutor.vhd
index a112bd1ac455053148ed659d7899ea278375c078..0a4a7a28028ab2a421b4b41bcf33a4cef739667a 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_corr_permutor.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_corr_permutor.vhd
@@ -35,7 +35,6 @@ entity tb_corr_permutor is
end tb_corr_permutor;
architecture tb of tb_corr_permutor is
-
constant c_clk_period : time := 10 ns;
constant c_data_w : natural := 16;
constant c_input_gap_size : natural := g_nof_cycles - 1;
@@ -46,9 +45,7 @@ architecture tb of tb_corr_permutor is
signal permutor_snk_in_arr : t_dp_sosi_arr(g_nof_inputs - 1 downto 0);
signal permutor_src_out_2arr_2 : t_dp_sosi_2arr_2(g_nof_outputs - 1 downto 0);
-
begin
-
-------------------------------------------------------------------------------
-- Clk & reset
-------------------------------------------------------------------------------
@@ -97,8 +94,6 @@ begin
permutor_snk_in_arr(j).valid <= '0';
end loop;
wait for c_input_gap_size * c_clk_period;
-
end loop;
end process;
-
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
index e46db6d3cc95c57d450e8c4c968b6659911044ca..ee589c12ac72860640779d5dcaca91eddc08aad6 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator.vhd
@@ -45,7 +45,6 @@ entity tb_correlator is
end tb_correlator;
architecture tb of tb_correlator is
-
constant c_complex_data_w : natural := 8;
constant c_nof_input_streams : natural := g_nof_inputs / pow2(g_nof_input_folds);
@@ -68,7 +67,6 @@ architecture tb of tb_correlator is
constant c_bg_blocks_per_sync : natural := c_integration_period;
-
constant c_bg_ctrl : t_diag_block_gen := ('1', -- enable
'0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
@@ -99,9 +97,7 @@ architecture tb of tb_correlator is
signal ram_diag_data_buf_miso : t_mem_miso;
signal reg_diag_data_buf_mosi : t_mem_mosi;
signal reg_diag_data_buf_miso : t_mem_miso;
-
begin
-
-----------------------------------------------------------------------------
-- Clocks and reset
-----------------------------------------------------------------------------
@@ -291,5 +287,4 @@ begin
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
index b9042998fbdfc3b20003b6bbf8746c4022e0231b..2b5d9722394319eb1919df99a2ca358d57f4c41c 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_correlator_dev.vhd
@@ -50,7 +50,6 @@ entity tb_correlator_dev is
end tb_correlator_dev;
architecture tb of tb_correlator_dev is
-
-----------------------------------------------------------------------------
-- Clock & reset
-----------------------------------------------------------------------------
@@ -90,9 +89,7 @@ architecture tb of tb_correlator_dev is
signal out_valid_count : integer := 0;
-- SIGNAL nxt_out_valid_count : NATURAL;
-
begin
-
-----------------------------------------------------------------------------
-- Clocks and reset
-----------------------------------------------------------------------------
@@ -229,5 +226,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd b/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd
index 0ec632a40912897b6093ea591f09de92df758d33..c9b1cb9b507a10d8c11c4d902a813df5a9c497e1 100644
--- a/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd
+++ b/libraries/dsp/correlator/tb/vhdl/tb_tb_corr_accumulator.vhd
@@ -53,5 +53,4 @@ begin
u_tb_corr_accumulator_07_p : entity work.tb_corr_accumulator generic map( 1, 7, 65, 32, e_pulse);
u_tb_corr_accumulator_08_p : entity work.tb_corr_accumulator generic map( 1, 8, 127, 33, e_pulse);
u_tb_corr_accumulator_11_p : entity work.tb_corr_accumulator generic map( 1, 11, 129, 7, e_pulse);
-
end tb;
diff --git a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
index bb80f83717f0854f6a2184994d4da90dba7542ab..abd88be8522a176d72b78603322584ca6b1586d7 100644
--- a/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_lfsr.vhd
@@ -44,9 +44,7 @@ entity fft_lfsr is
);
end fft_lfsr;
-
architecture rtl of fft_lfsr is
-
-- uses preferred pair of pritive trinomials
-- x^41 + x^20 + 1 and x^41 + x^3 + 1
-- see XAPP217
@@ -60,9 +58,7 @@ architecture rtl of fft_lfsr is
signal s2 : std_logic_vector(c_len - 1 downto 0);
signal nxt_s2 : std_logic_vector(c_len - 1 downto 0);
-
begin
-
p_reg : process(rst,clk)
begin
if rst = '1' then
@@ -95,6 +91,4 @@ begin
nxt_s2(c2) <= s2(c_len - 1) xor s2(c2 - 1);
end if;
end process;
-
end rtl;
-
diff --git a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
index 4b773e51b6aa3f2f8c91d0532a850421bd85aa11..8dda8835b58237f265dff80a12a8cf12112d7bbb 100644
--- a/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_pkg.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package fft_pkg is
-
-- Default FFT switch and unswitch seeds from LOFAR1
constant c_fft_lfsr_len : natural := 41;
constant c_fft_switch_seed1 : std_logic_vector(c_fft_lfsr_len - 1 downto 0) := "01000101011101110101001011111000101100001";
@@ -93,7 +92,6 @@ package fft_pkg is
end package fft_pkg;
package body fft_pkg is
-
function fft_switch_new_seed(seed : std_logic_vector; offset : natural) return std_logic_vector is
begin
return INCR_UVEC(seed, offset); -- make new unique seed
@@ -140,7 +138,6 @@ package body fft_pkg is
return c_raw_fraction_w;
end func_fft_raw_fraction_w;
-
function to_fft_svec(n : integer) return std_logic_vector is
begin
return RESIZE_SVEC(TO_SVEC(n, 32), c_fft_slv_w);
@@ -169,4 +166,3 @@ package body fft_pkg is
end;
end fft_pkg;
-
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd
index c4af5eb53129336dfd14dd2b0bccd81b6bb87080..a18e851babfef605c0eb1aac7ec1aca04e2c9923 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_bf_par.vhd
@@ -61,7 +61,6 @@ entity fft_r2_bf_par is
end entity fft_r2_bf_par;
architecture str of fft_r2_bf_par is
-
-- The amplification factor per stage is 2, therefor bit growth defintion of 1.
-- Scale enable is defined by generic.
constant c_stage_bit_growth : natural := sel_a_b(g_scale_enable, 1, 0);
@@ -97,9 +96,7 @@ architecture str of fft_r2_bf_par is
signal mul_quant_im : std_logic_vector(y_out_im'range);
signal mul_out_val : std_logic;
signal mul_in_val : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- complex butterfly
------------------------------------------------------------------------------
@@ -347,5 +344,4 @@ begin
in_dat => mul_out_val,
out_dat => out_val
);
-
end str;
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
index 0a44707f9906fc55c6b9e9cdad3ae8d86da134a1..622cd822b86b148e231af3346b28585b8521339b 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_par.vhd
@@ -61,7 +61,6 @@ entity fft_r2_par is
end entity fft_r2_par;
architecture str of fft_r2_par is
-
------------------------------------------------------------------------------------------------
-- This function determines the input number (return value) to which the output of a butterfly
-- should be connected, based on the output-sequence-number(element), the stage number(stage)
@@ -160,9 +159,7 @@ architecture str of fft_r2_par is
signal dbg_c_in_scale_w : natural := c_in_scale_w;
signal dbg_c_raw_fraction_w : natural := c_raw_fraction_w;
signal dbg_c_raw_dat_w : natural := c_raw_dat_w;
-
begin
-
------------------------------------------------------------------------------
-- Inputs are prepared/shuffled for the input stage
------------------------------------------------------------------------------
@@ -227,6 +224,7 @@ begin
int_re_arr <= data_re(0);
int_im_arr <= data_im(0);
end generate;
+
int_val <= data_val(0)(0);
--------------------------------------------------------------------------------
@@ -371,6 +369,7 @@ begin
fft_re_arr(I) <= int_re_arr(I);
fft_im_arr(I) <= int_im_arr(I);
end generate;
+
fft_val <= int_val;
end generate;
@@ -417,7 +416,6 @@ begin
out_dat => out_im_arr(I),
out_ovr => open
);
-
end generate;
u_out_val : entity common_lib.common_pipeline_sl
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
index f05c06b8a4a44a02fdb8c7d76c53b4f2f65d335f..1df364ce44b5bc1b01a6bbc1834ef07e3020a856 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_pipe.vhd
@@ -99,7 +99,6 @@ entity fft_r2_pipe is
end entity fft_r2_pipe;
architecture str of fft_r2_pipe is
-
constant c_pipeline_remove_lsb : natural := 1; -- to easy timing closure
constant c_switch_en : boolean := g_fft.use_separate; -- default do apply switch/unswitch per real input to mitigate quantization crosstalk
@@ -149,9 +148,7 @@ architecture str of fft_r2_pipe is
signal dbg_c_in_scale_w : natural := c_in_scale_w;
signal dbg_c_raw_fraction_w : natural := c_raw_fraction_w;
signal dbg_c_raw_dat_w : natural := c_raw_dat_w;
-
begin
-
------------------------------------------------------------------------------
-- Mitigate quantization noise crosstalk between two real inputs by negating
-- the inputs per lock in a random pattern, when g_fft.use_separate = TRUE.
@@ -259,7 +256,6 @@ begin
-- c_raw_dat_w = g_fft.stage_dat_w + 1 when g_fft.use_separate = true
fft_out_re <= out_cplx( c_raw_dat_w - 1 downto 0);
fft_out_im <= out_cplx(2 * c_raw_dat_w - 1 downto c_raw_dat_w);
-
end generate;
no_reorder_no_seperate : if g_fft.use_separate = false and g_fft.use_reorder = false generate
@@ -379,6 +375,4 @@ begin
in_dat => raw_im,
out_dat => out_raw_im
);
-
end str;
-
diff --git a/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd b/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
index 7bd7d2708f4871cd81d8c16a592e4022da08df65..d2401d7cf4e0459e3702e84689f29cbbd1e263e2 100644
--- a/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_r2_wide.vhd
@@ -92,7 +92,6 @@ entity fft_r2_wide is
end entity fft_r2_wide;
architecture rtl of fft_r2_wide is
-
type t_fft_arr is array(integer range <> ) of t_fft; -- An array of t_fft's generics.
----------------------------------------------------------
@@ -181,9 +180,7 @@ architecture rtl of fft_r2_wide is
signal dbg_c_in_scale_w : natural := c_in_scale_w;
signal dbg_c_raw_fraction_w : natural := c_raw_fraction_w;
signal dbg_c_raw_dat_w : natural := c_raw_dat_w;
-
begin
-
-- Default to fft_r2_pipe when g_fft.wb_factor=1
gen_fft_r2_pipe : if g_fft.wb_factor = 1 generate
u_fft_r2_pipe : entity work.fft_r2_pipe
@@ -227,7 +224,6 @@ begin
-- Create wideband FFT as combinination of g_fft.wb_factor instances of fft_r2_pipe with one instance of fft_r2_par
gen_fft_r2_wide : if g_fft.wb_factor > 1 and g_fft.wb_factor < g_fft.nof_points generate
-
---------------------------------------------------------------
-- PIPELINED FFT STAGE
---------------------------------------------------------------
@@ -258,7 +254,6 @@ begin
);
end generate;
-
---------------------------------------------------------------
-- PARALLEL FFT STAGE
---------------------------------------------------------------
@@ -372,6 +367,5 @@ begin
in_dat => sep_out_val,
out_dat => out_val
);
-
end generate;
end rtl;
diff --git a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
index 6eec8d96eee02515ec831af1581cf917ebea0d4f..36d0e53f0d279d8a5c60b57a5345f9e9dc68d65d 100644
--- a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
@@ -59,7 +59,6 @@ entity fft_reorder_sepa_pipe is
end entity fft_reorder_sepa_pipe;
architecture rtl of fft_reorder_sepa_pipe is
-
constant c_nof_channels : natural := 2**g_nof_chan;
constant c_dat_w : natural := in_dat'length;
constant c_page_size : natural := g_nof_points * c_nof_channels;
@@ -112,9 +111,7 @@ architecture rtl of fft_reorder_sepa_pipe is
signal dbg_c_adr_points_w : natural := c_adr_points_w;
signal dbg_c_adr_chan_w : natural := c_adr_chan_w;
signal dbg_c_adr_tot_w : natural := c_adr_tot_w;
-
begin
-
out_dat_i <= rd_dat;
out_val_i <= rd_val;
@@ -132,27 +129,34 @@ begin
no_bit_flip : if g_bit_flip = false generate
wr_adr <= adr_tot_cnt;
end generate;
+
gen_bit_flip_spectrum_and_channels : if g_bit_flip = true and g_dont_flip_channels = false generate -- the channels get separated in time
+
gen_no_fft_shift_sac : if g_fft_shift = false generate
wr_adr <= adr_chan_cnt & adr_fft_flip;
end generate;
+
gen_fft_shift_sac : if g_fft_shift = true generate
wr_adr <= adr_chan_cnt & adr_fft_shift;
end generate;
end generate;
gen_bit_flip_spectrum_only : if g_bit_flip = true and g_dont_flip_channels = true generate -- the channel interleaving in time is preserved
+
gen_no_fft_shift_so : if g_fft_shift = false generate
wr_adr <= adr_fft_flip & adr_chan_cnt;
end generate;
+
gen_fft_shift_so : if g_fft_shift = true generate
wr_adr <= adr_fft_shift & adr_chan_cnt;
end generate;
end generate;
end generate;
+
gen_two_real : if g_separate = true generate
gen_bit_flip_spectrum_and_channels : if g_dont_flip_channels = false generate -- the channels get separated in time
wr_adr <= adr_chan_cnt & adr_fft_flip;
end generate;
+
gen_bit_flip_spectrum_only : if g_dont_flip_channels = true generate -- the channel interleaving in time is preserved
wr_adr <= adr_fft_flip & adr_chan_cnt;
end generate;
@@ -175,6 +179,7 @@ begin
one_chan : if c_nof_channels = 1 generate
cnt_ena <= '1' when in_val = '1' else '0';
end generate;
+
more_chan : if c_nof_channels > 1 generate
cnt_ena <= '1' when in_val = '1' and TO_UINT(adr_chan_cnt) = c_nof_channels - 1 else '0';
end generate;
@@ -234,7 +239,6 @@ begin
comb : process(r, rst, next_page)
variable v : reg_type;
begin
-
v := r;
v.rd_en := '0';
@@ -291,7 +295,6 @@ begin
when others =>
v.state := s_idle;
-
end case;
if(rst = '1') then
@@ -304,7 +307,6 @@ begin
end if;
rin <= v;
-
end process comb;
regs : process(clk)
@@ -348,5 +350,3 @@ begin
end generate;
end rtl;
-
-
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
index 9bfa824135f31f3995caf95fc4660c2a12b808ff..f9b660aaaeb668de28134b314eda21686b5e3494 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa.vhd
@@ -62,7 +62,6 @@ entity fft_sepa is
end entity fft_sepa;
architecture rtl of fft_sepa is
-
constant c_in_data_w : natural := in_dat'length / c_nof_complex;
constant c_in_complex_w : natural := c_nof_complex * c_in_data_w;
constant c_out_data_w : natural := c_in_data_w + 1;
@@ -88,9 +87,7 @@ architecture rtl of fft_sepa is
signal rin : t_reg;
signal sub_result : std_logic_vector(c_out_data_w - 1 downto 0); -- Result of the subtractor
signal add_result : std_logic_vector(c_out_data_w - 1 downto 0); -- Result of the adder
-
begin
-
---------------------------------------------------------------
-- ADDER AND SUBTRACTOR
---------------------------------------------------------------
@@ -172,7 +169,6 @@ begin
end if;
rin <= v;
-
end process comb;
regs : process(clk)
@@ -187,7 +183,4 @@ begin
---------------------------------------------------------------
out_dat <= r.out_dat;
out_val <= r.out_val;
-
end rtl;
-
-
diff --git a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
index ed4be37b558743bf55028a1a4d00d0797e1d5d03..720653a425aff14402dee71b8f337d2ef8815154 100644
--- a/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_sepa_wide.vhd
@@ -58,11 +58,9 @@ entity fft_sepa_wide is
out_im_arr : out t_fft_slv_arr(g_fft.wb_factor - 1 downto 0);
out_val : out std_logic
);
-
end entity fft_sepa_wide;
architecture rtl of fft_sepa_wide is
-
constant c_pipeline_output : natural := 0; -- no need for extra pipeline output, because output is already registered
constant c_page_size : natural := g_fft.nof_points / g_fft.wb_factor; -- Size of the memories
@@ -112,9 +110,7 @@ architecture rtl of fft_sepa_wide is
signal r : t_reg := c_reg_init;
signal rin : t_reg;
-
begin
-
---------------------------------------------------------------
-- DUAL PAGED RAMS
---------------------------------------------------------------
@@ -229,7 +225,6 @@ begin
comb : process(r, rst, next_page)
variable v : t_reg;
begin
-
v := r;
case r.state is
@@ -266,7 +261,6 @@ begin
when others =>
v.state := s_idle;
-
end case;
if rst = '1' then
@@ -274,7 +268,6 @@ begin
end if;
rin <= v;
-
end process comb;
regs : process(clk)
@@ -330,5 +323,3 @@ begin
end generate;
end rtl;
-
-
diff --git a/libraries/dsp/fft/src/vhdl/fft_switch.vhd b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
index 623dcfa820ecd0381d3a07efdaca108297fcd332..e1732d2a8153084a92c65a57f58d3f86ec81144f 100644
--- a/libraries/dsp/fft/src/vhdl/fft_switch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_switch.vhd
@@ -68,9 +68,7 @@ entity fft_switch is
);
end fft_switch;
-
architecture rtl of fft_switch is
-
constant c_nof_clk_per_block : natural := 2**g_fft_sz_w;
signal in_sop : std_logic;
@@ -85,9 +83,7 @@ architecture rtl of fft_switch is
signal nxt_out_re : std_logic_vector(in_re'range);
signal nxt_out_im : std_logic_vector(in_im'range);
-
begin
-
-- Create input strobes to view data blocks for debugging
u_in_strobes : entity common_lib.common_create_strobes_from_valid
generic map (
diff --git a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
index 47288cd6381844b3fec41230cbb5d9adb4fcc3d2..9d1ad5ef00b3fb3a60bbcb5e7c313c45f63b13fa 100644
--- a/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_unswitch.vhd
@@ -54,7 +54,6 @@ entity fft_unswitch is
end fft_unswitch;
architecture rtl of fft_unswitch is
-
constant c_nof_clk_per_block : natural := 2**g_fft_sz_w;
signal in_sop : std_logic;
@@ -70,9 +69,7 @@ architecture rtl of fft_unswitch is
signal nxt_out_re : std_logic_vector(in_re'range);
signal nxt_out_im : std_logic_vector(in_im'range);
-
begin
-
-- Create input strobes to view data blocks for debugging
u_in_strobes : entity common_lib.common_create_strobes_from_valid
generic map (
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
index 082de5258702e8614375f5af36e15e10f77f5a4e..3134ef587f4b2d7013c81bf27b70bc34e5b13344 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit.vhd
@@ -61,7 +61,6 @@ entity fft_wide_unit is
end entity fft_wide_unit;
architecture str of fft_wide_unit is
-
constant c_lsb_w_tester : integer := g_fft.out_dat_w - g_fft.stage_dat_w;
constant c_lsb_w : natural := sel_a_b(c_lsb_w_tester > 0, c_lsb_w_tester, 0);
constant c_nof_stats : natural := (2**g_fft.nof_chan) * g_fft.nof_points / g_fft.wb_factor;
@@ -84,9 +83,7 @@ architecture str of fft_wide_unit is
end record;
signal r, rin : reg_type;
-
begin
-
---------------------------------------------------------------
-- INPUT REGISTER FOR THE SOSI ARRAY
---------------------------------------------------------------
@@ -228,5 +225,3 @@ begin
end generate;
end str;
-
-
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
index 5cb7ec80e4577e5327758d1345ca8e3932ca0c37..c31e4c188132f18303c3fd9219c07a213af1e46d 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
@@ -61,7 +61,6 @@ entity fft_wide_unit_control is
end fft_wide_unit_control;
architecture rtl of fft_wide_unit_control is
-
constant c_pipe_data : natural := 3; -- Delay depth for the data
constant c_pipe_ctrl : natural := c_pipe_data - 1; -- Delay depth for the control signals
constant c_packet_size : natural := (2**g_fft.nof_chan) * g_fft.nof_points / g_fft.wb_factor; -- Definition of the packet size
@@ -90,9 +89,7 @@ architecture rtl of fft_wide_unit_control is
signal rd_req_i : std_logic;
signal rd_dat_i : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0);
signal rd_val_i : std_logic;
-
begin
-
---------------------------------------------------------------
-- INPUT FIFO FOR BSN
---------------------------------------------------------------
@@ -193,7 +190,6 @@ begin
comb : process(r, rst, ctrl_sosi, in_re_arr, in_im_arr, in_val, sync_bsn, bsn, err)
variable v : reg_type;
begin
-
v := r;
v.val_dly(0) := '0'; -- Some defaults, before entering the state machine.
@@ -263,7 +259,6 @@ begin
when others =>
v.state := s_idle;
-
end case;
if(rst = '1') then
@@ -277,7 +272,6 @@ begin
end if;
rin <= v;
-
end process comb;
regs : process(clk)
@@ -293,5 +287,3 @@ begin
end generate;
end rtl;
-
-
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
index bd206abe3523aa50b84ae484446e919a82e2bbb1..739b0cba34abd49e147c90654cf84d98417ba38b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_functions.vhd
@@ -39,7 +39,6 @@ entity tb_fft_functions is
end tb_fft_functions;
architecture tb of tb_fft_functions is
-
constant c_wb_factor : natural := 4;
constant c_nof_points : natural := 32;
constant c_w : natural := ceil_log2(c_nof_points);
@@ -69,9 +68,7 @@ architecture tb of tb_fft_functions is
signal bin_complex_reorder_transpose_arr : t_natural_arr(0 to c_nof_points - 1);
signal bin_two_real_reorder_arr : t_natural_arr(0 to c_nof_points - 1); -- separate(flip())
signal bin_two_real_reorder_transpose_arr : t_natural_arr(0 to c_nof_points - 1);
-
begin
-
p_bin : process
begin
for I in 0 to c_nof_points - 1 loop
@@ -94,6 +91,4 @@ begin
end loop;
wait;
end process;
-
end tb;
-
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
index accc2d27b4d3bdd078dd29a43ee664eaa2497f48..8acfe181c41a482079c693b6c05f35ad981b4c60 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_lfsr.vhd
@@ -39,7 +39,6 @@ entity tb_fft_lfsr is
end tb_fft_lfsr;
architecture tb of tb_fft_lfsr is
-
constant clk_period : time := 10 ns;
constant c_block_period : natural := 10;
@@ -54,9 +53,7 @@ architecture tb of tb_fft_lfsr is
signal u1_lfsr_bit1 : std_logic;
signal u0_lfsr_bit2 : std_logic;
signal u1_lfsr_bit2 : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 10 * clk_period;
tb_end <= '0', '1' after c_nof_block * c_block_period * clk_period;
@@ -88,5 +85,4 @@ begin
clk => clk,
rst => rst
);
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
index 81966fcc72dfb5bba3863c07147ff9c792401868..b566285a2932ee150bab7812781ad122b7aa8ee1 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_pkg.vhd
@@ -32,7 +32,6 @@ use dp_lib.dp_stream_pkg.all;
use work.fft_pkg.all;
package tb_fft_pkg is
-
constant c_fft_nof_subbands_max : natural := 256;
subtype t_fft_sst_arr is t_slv_64_arr(c_fft_nof_subbands_max - 1 downto 0); -- use subtype to allow using assignments via t_slv_64_arr as well
@@ -66,7 +65,6 @@ package tb_fft_pkg is
signal in_file_data : out t_integer_matrix;
file_name : in string);
-
procedure proc_fft_read_subband_statistics_memory(constant c_fft_lane : in natural;
constant c_fft : in t_fft;
signal clk : in std_logic;
@@ -74,7 +72,6 @@ package tb_fft_pkg is
signal mm_miso : in t_mem_miso;
signal statistics_arr : out t_slv_64_arr);
-
-- Private procedures
procedure proc_read_subband_stats(constant nof_subbands : in natural;
constant offset : in natural;
@@ -83,7 +80,6 @@ package tb_fft_pkg is
signal mm_miso : in t_mem_miso;
variable result : out t_slv_64_arr);
-
-- PROCEDURE proc_prepare_input_data(CONSTANT nof_subbands : IN NATURAL;
-- CONSTANT nof_inputs : IN NATURAL;
-- CONSTANT nof_input_streams : IN NATURAL;
@@ -91,11 +87,9 @@ package tb_fft_pkg is
-- VARIABLE re_arr : OUT t_integer_arr;
-- VARIABLE im_arr : OUT t_integer_arr;
-- file_name : IN STRING);
-
end tb_fft_pkg;
package body tb_fft_pkg is
-
function fft_index_to_bin_frequency(wb_factor, nof_points, index : natural; use_reorder, use_fft_shift, use_separate : boolean) return natural is
-- Purpose: map fft output index to bin frequency
-- Description:
@@ -323,6 +317,7 @@ package body tb_fft_pkg is
-- With HDL fft_shift
v_addr := to_uvec(index, c_addr_w); -- b = i
end if;
+
end if;
v_bin := to_uint(v_addr);
else
@@ -361,7 +356,6 @@ package body tb_fft_pkg is
return v_bin;
end fft_index_to_bin_frequency;
-
procedure proc_fft_out_control(wb_factor : natural;
nof_points : natural;
nof_channels : natural;
@@ -440,7 +434,6 @@ package body tb_fft_pkg is
end if;
end proc_fft_out_control;
-
------------------------------------------------------------------------------
-- PROCEDURE: Read input file.
-- Reads data (re, im, sync and val) from a file and writes values
@@ -539,7 +532,6 @@ package body tb_fft_pkg is
wait;
end proc_read_input_file;
-
------------------------------------------------------------------------------
-- PROCEDURE: Read the beamlet statistics memory into an matrix
------------------------------------------------------------------------------
@@ -560,7 +552,6 @@ package body tb_fft_pkg is
proc_common_wait_some_cycles(clk, 1); -- ensure that the last statistics_arr value gets assigned too
end proc_fft_read_subband_statistics_memory;
-
------------------------------------------------------------------------------
-- PROCEDURE: Reads the beamlet statistics into an array.
------------------------------------------------------------------------------
@@ -583,9 +574,6 @@ package body tb_fft_pkg is
end loop;
end proc_read_subband_stats;
-
-
-
------------------------------------------------------------------------------
-- PROCEDURE: Prepare input array.
-- Combinatorial read data from source file and re-arrange in such
@@ -616,4 +604,3 @@ package body tb_fft_pkg is
-- END proc_prepare_input_data;
end tb_fft_pkg;
-
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
index d40b86cb6eeb605e2517e185feddb0a2717b361f..18b7abe7eb2b8ed4cbcc1109a96878bc9005bf2b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_bf_par.vhd
@@ -49,7 +49,6 @@ entity tb_fft_r2_bf_par is
end tb_fft_r2_bf_par;
architecture tb of tb_fft_r2_bf_par is
-
constant c_pipeline : t_fft_pipeline := c_fft_pipeline; -- defined in rTwoSDF_lib.rTwoSDFPkg
constant c_clk_period : time := 10 ns;
@@ -106,9 +105,7 @@ architecture tb of tb_fft_r2_bf_par is
signal weight_re : wTyp;
signal weight_im : wTyp;
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 3;
@@ -208,7 +205,6 @@ begin
ref_y_out_re <= truncate_and_resize_svec(v_ref_y_prod_re, c_round_w, ref_y_out_re'length);
ref_y_out_im <= truncate_and_resize_svec(v_ref_y_prod_im, c_round_w, ref_y_out_im'length);
-
end process;
u_verify_pipeline_x_re : entity common_lib.common_pipeline
@@ -274,5 +270,4 @@ begin
end if;
end if;
end process p_tester;
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
index 134b6b6c1eb588a63bdfb63e96466123ba7b9c3d..b1a979ee6a3b8d646bd43c2b1cf4a7d3d8c7dc0b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_par.vhd
@@ -120,7 +120,6 @@ entity tb_fft_r2_par is
end entity tb_fft_r2_par;
architecture tb of tb_fft_r2_par is
-
constant c_clk_period : time := 10 ns;
constant c_in_complex : boolean := not g_fft.use_separate;
@@ -244,9 +243,7 @@ architecture tb of tb_fft_r2_par is
signal diff_im_a_scope : integer := 0;
signal diff_re_b_scope : integer := 0;
signal diff_im_b_scope : integer := 0;
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
dut_clk <= clk or tb_end_dut;
tb_clk <= clk and tb_end_dut;
@@ -455,6 +452,7 @@ begin
assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin report "Output data B real error" severity error;
assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin report "Output data B imag error" severity error;
end generate;
+
gen_verify_complex : if c_in_complex generate
assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin report "Output data C real error" severity error;
assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin report "Output data C imag error" severity error;
@@ -493,5 +491,4 @@ begin
diff_im_b_scope <= exp_im_b_scope - out_im_b_scope;
diff_re_c_scope <= exp_re_c_scope - out_re_c_scope;
diff_im_c_scope <= exp_im_c_scope - out_im_c_scope;
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
index 01fb8d4ea79030315f0f41d5740b6a51d74f18dc..93d3ba3dd3281658f41de6415881056cc097ec19 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_pipe.vhd
@@ -154,7 +154,6 @@ entity tb_fft_r2_pipe is
end entity tb_fft_r2_pipe;
architecture tb of tb_fft_r2_pipe is
-
constant c_clk_period : time := 10 ns;
constant c_in_complex : boolean := not g_fft.use_separate;
@@ -266,9 +265,7 @@ architecture tb of tb_fft_r2_pipe is
signal diff_im_a_scope : integer := 0;
signal diff_re_b_scope : integer := 0;
signal diff_im_b_scope : integer := 0;
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
random <= func_common_random(random) when rising_edge(clk);
@@ -406,6 +403,7 @@ begin
assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin report "Output data B real error" severity error;
assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin report "Output data B imag error" severity error;
end generate;
+
gen_verify_complex : if c_in_complex generate
assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin report "Output data C real error" severity error;
assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin report "Output data C imag error" severity error;
@@ -446,5 +444,4 @@ begin
diff_im_b_scope <= exp_im_b_scope - out_im_b_scope;
diff_re_c_scope <= exp_re_c_scope - out_re_c_scope;
diff_im_c_scope <= exp_im_c_scope - out_im_c_scope;
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
index a98b9991d75ec529833a3668f6ed0d3bb2fd787c..89835d3eeb2f52f46d50d40326b2dc9247ef70e6 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_r2_wide.vhd
@@ -125,7 +125,6 @@ entity tb_fft_r2_wide is
end entity tb_fft_r2_wide;
architecture tb of tb_fft_r2_wide is
-
constant c_clk_period : time := 10 ns;
constant c_sclk_period : time := c_clk_period / g_fft.wb_factor;
@@ -253,9 +252,7 @@ architecture tb of tb_fft_r2_wide is
signal diff_im_a_scope : integer := 0;
signal diff_re_b_scope : integer := 0;
signal diff_im_b_scope : integer := 0;
-
begin
-
sclk <= (not sclk) or tb_end after c_sclk_period / 2;
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -405,6 +402,7 @@ begin
assert diff_re_b_scope >= -g_diff_margin and diff_re_b_scope <= g_diff_margin report "Output data B real error" severity error;
assert diff_im_b_scope >= -g_diff_margin and diff_im_b_scope <= g_diff_margin report "Output data B imag error" severity error;
end generate;
+
gen_verify_complex : if c_in_complex generate
assert diff_re_c_scope >= -g_diff_margin and diff_re_c_scope <= g_diff_margin report "Output data C real error" severity error;
assert diff_im_c_scope >= -g_diff_margin and diff_im_c_scope <= g_diff_margin report "Output data C imag error" severity error;
@@ -533,5 +531,4 @@ begin
out_int => out_im_scope,
out_val => open
);
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
index 3eca94f8805cf4f8a7301d844f1ea5d875cfaa52..77204376033fcbdc6d96ffc57de7246e51f1c2c7 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_reorder_sepa_pipe.vhd
@@ -44,7 +44,6 @@ entity tb_fft_reorder_sepa_pipe is
end tb_fft_reorder_sepa_pipe;
architecture tb of tb_fft_reorder_sepa_pipe is
-
constant c_clk_period : time := 10 ns;
constant c_nof_points : natural := 16; -- Number of points should be a power of 2
constant c_in_dat_w : natural := 16;
@@ -88,9 +87,7 @@ architecture tb of tb_fft_reorder_sepa_pipe is
signal buf_output_b_im : t_input_buf_arr(c_nof_channels * c_nof_points / 2 - 1 downto 0);
signal buf_output_re : t_input_buf_arr(c_nof_channels * c_nof_points - 1 downto 0);
signal buf_output_im : t_input_buf_arr(c_nof_channels * c_nof_points - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 3;
@@ -254,5 +251,4 @@ begin
I := 0;
end if;
end process p_tester;
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
index 6746cc7e0a82f65fb5a4ac1bbe9c78eeae534f95..a38cdfba6556c8596a39677d85fe580010c95cf2 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_sepa.vhd
@@ -43,7 +43,6 @@ entity tb_fft_sepa is
end tb_fft_sepa;
architecture tb of tb_fft_sepa is
-
constant c_clk_period : time := 10 ns;
constant c_nof_points : natural := 8;
@@ -84,9 +83,7 @@ architecture tb of tb_fft_sepa is
signal buf_output_b_im : t_input_buf_arr(c_nof_points / 2 - 1 downto 0);
signal buf_output_re : t_input_buf_arr(c_nof_points - 1 downto 0);
signal buf_output_im : t_input_buf_arr(c_nof_points - 1 downto 0);
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 3;
@@ -167,7 +164,6 @@ begin
variable v_buf_output_a_im : t_input_buf_arr(c_nof_points / 2 - 1 downto 0);
variable v_buf_output_b_re : t_input_buf_arr(c_nof_points / 2 - 1 downto 0);
variable v_buf_output_b_im : t_input_buf_arr(c_nof_points / 2 - 1 downto 0);
-
begin
I := 0;
wait until in_sosi_arr(0).sync = '1';
@@ -211,8 +207,4 @@ begin
I := 0;
end if;
end process p_tester;
-
end tb;
-
-
-
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
index ba130080a3f926902b68d4d3e5ea6f35730a1d89..26a50b4369cffd9be145d4d26a69eca61b22ff7d 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_switch.vhd
@@ -67,7 +67,6 @@ entity tb_fft_switch is
end tb_fft_switch;
architecture tb of tb_fft_switch is
-
constant clk_period : time := 10 ns;
constant c_dat_w : natural := 16;
@@ -130,9 +129,7 @@ architecture tb of tb_fft_switch is
signal exp_b : integer;
signal verify_en : std_logic := '0';
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
p_in_val : process
@@ -176,17 +173,16 @@ begin
out_sync => in_sync
);
-
gen_increment_at_val : if g_increment_at_val = true generate
in_a <= INCR_SVEC(in_a, 1) when rising_edge(clk) and in_val = '1';
in_b <= INCR_SVEC(in_b, 1) when rising_edge(clk) and in_val = '1';
end generate;
+
gen_increment_at_eop : if g_increment_at_val = false generate
in_a <= INCR_SVEC(in_a, 1) when rising_edge(clk) and in_eop = '1';
in_b <= INCR_SVEC(in_b, 1) when rising_edge(clk) and in_eop = '1';
end generate;
-
u_fft_switch : entity work.fft_switch
generic map (
g_switch_en => g_switch_en,
@@ -230,7 +226,6 @@ begin
mux_im <= switch_a when mux_toggle = '1' else prev1_switch_b; -- a1, b1, ..
mux_val <= switch_val when rising_edge(clk);
-
u_fft_unswitch : entity work.fft_unswitch
generic map (
g_switch_en => g_switch_en,
@@ -316,5 +311,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
index 82f97458c8ea0a57beeff6713261947d280d4e8e..c021f0cdfbcd402afcd91b46d856622e8ee0571b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_fft_wide_unit.vhd
@@ -75,7 +75,6 @@ entity tb_fft_wide_unit is
end entity tb_fft_wide_unit;
architecture tb of tb_fft_wide_unit is
-
constant c_clk_period : time := 100 ns;
-- input/output data width
@@ -196,9 +195,7 @@ architecture tb of tb_fft_wide_unit is
signal result_sst_arr : t_slv_64_arr(g_fft.nof_points - 1 downto 0);
-- . Expected result
signal expected_sst_arr : t_slv_64_arr(g_fft.nof_points - 1 downto 0) := (others => (others => '0'));
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -348,6 +345,7 @@ begin
out_re_arr(I) <= RESIZE_SVEC(result_sosi_arr(I).re, out_re_arr(I)'length);
out_im_arr(I) <= RESIZE_SVEC(result_sosi_arr(I).im, out_im_arr(I)'length);
end generate;
+
out_val <= result_sosi_arr(0).valid;
---------------------------------------------------------------
@@ -425,7 +423,6 @@ begin
end loop;
gold_sync <= gold_file_sync(v_bin_index);
-
end process;
-- Verify the output of the DUT with the expected output from the golden reference file
@@ -443,5 +440,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd
index f378cb2fa03e4614e1f0e902eb3bf6c404de334c..3551d700653c7f3a813d3007d3efcb0bf0ec9fed 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -44,7 +43,6 @@
-- > Check the results of the python script.
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-
library IEEE, common_lib, mm_lib, diag_lib, dp_lib, rTwoSDF_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -75,7 +73,6 @@ entity tb_mmf_fft_r2 is
end tb_mmf_fft_r2;
architecture tb of tb_mmf_fft_r2 is
-
constant c_fft : t_fft := (true, false, g_use_separate, g_nof_chan, g_wb_factor, 0, g_nof_points, g_in_dat_w, g_out_dat_w, 0, c_dsp_mult_w, 2, true, 56, 2);
-- type t_rtwo_fft is record
-- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
@@ -159,9 +156,7 @@ architecture tb of tb_mmf_fft_r2 is
signal scope_in_sosi : t_dp_sosi_integer;
signal scope_out_sosi : t_dp_sosi_integer;
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -384,5 +379,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd
index 68cafe816866bbed46135c7698979f2494c1966d..2a417eabe34d99cb906490978017b3db3a1804b6 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_par.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -35,7 +34,6 @@
-- > Check the results of the python script.
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-
library IEEE, common_lib, unb_common_lib, mm_lib, diag_lib, dp_lib, rTwoSDF_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -74,7 +72,6 @@ entity tb_mmf_fft_r2_par is
end tb_mmf_fft_r2_par;
architecture tb of tb_mmf_fft_r2_par is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -136,9 +133,7 @@ architecture tb of tb_mmf_fft_r2_par is
signal out_re_arr : t_fft_slv_arr(g_fft.nof_points - 1 downto 0);
signal out_im_arr : t_fft_slv_arr(g_fft.nof_points - 1 downto 0);
signal out_val : std_logic := '0';
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -298,5 +293,4 @@ begin
in_sync => ss_out_sosi_im_arr(0).sync,
in_sosi_arr => ss_out_sosi_im_arr
);
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd
index 577d0be261d017ca41815336aba27f717b2d9218..39505893a1e74df511195a6126dec3c0b7e51b8c 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_r2_pipe.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -73,7 +72,6 @@ entity tb_mmf_fft_r2_pipe is
end tb_mmf_fft_r2_pipe;
architecture tb of tb_mmf_fft_r2_pipe is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -137,9 +135,7 @@ architecture tb of tb_mmf_fft_r2_pipe is
signal out_re : std_logic_vector(g_fft.out_dat_w - 1 downto 0);
signal out_im : std_logic_vector(g_fft.out_dat_w - 1 downto 0);
signal out_val : std_logic := '0';
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -237,7 +233,6 @@ begin
ss_out_sosi_im_arr(0).valid <= out_val;
ss_out_sosi_im_arr(0).sync <= out_val;
-
----------------------------------------------------------------------------
-- Sink: data buffer real
----------------------------------------------------------------------------
@@ -295,5 +290,4 @@ begin
in_sync => ss_out_sosi_im_arr(0).sync,
in_sosi_arr => ss_out_sosi_im_arr
);
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd
index e94a9dda2de289a24a7e1ea94363c52283189201..acc5adb12335c174634fa5519fb76d6cd1c8ba4b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_mmf_fft_wide_unit.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -43,7 +42,6 @@
-- > Check the results of the python script.
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-
library IEEE, common_lib, mm_lib, diag_lib, dp_lib, rTwoSDF_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -73,7 +71,6 @@ entity tb_mmf_fft_wide_unit is
end tb_mmf_fft_wide_unit;
architecture tb of tb_mmf_fft_wide_unit is
-
constant c_fft : t_fft := (true, false, g_use_separate, g_nof_chan, g_wb_factor, 0, g_nof_points, g_in_dat_w, g_out_dat_w, 0, c_dsp_mult_w, 2, true, 56, 2);
-- type t_rtwo_fft is record
-- use_reorder : boolean; -- = false for bit-reversed output, true for normal output
@@ -153,9 +150,7 @@ architecture tb of tb_mmf_fft_wide_unit is
signal ss_out_sosi_re_arr : t_dp_sosi_arr(c_fft.wb_factor - 1 downto 0) := (others => c_dp_sosi_rst);
signal ss_out_sosi_im_arr : t_dp_sosi_arr(c_fft.wb_factor - 1 downto 0) := (others => c_dp_sosi_rst);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -313,5 +308,4 @@ begin
in_sync => ss_out_sosi_im_arr(0).sync,
in_sosi_arr => ss_out_sosi_im_arr
);
-
end tb;
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
index 1b4e1a73f347a3af11a7141cded0040e08bb2fa9..090afe6549ebe2b22a30c126786824e7431d5818 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_par.vhd
@@ -38,7 +38,6 @@ entity tb_tb_fft_r2_par is
end tb_tb_fft_r2_par;
architecture tb of tb_tb_fft_r2_par is
-
constant c_fft_two_real : t_fft := ( true, false, true, 0, 1, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
constant c_fft_complex : t_fft := ( true, false, false, 0, 1, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
constant c_fft_complex_fft_shift : t_fft := ( true, true, false, 0, 1, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
@@ -60,9 +59,7 @@ architecture tb of tb_tb_fft_r2_par is
constant c_unused : string := "UNUSED";
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- DUT generics
-- g_fft : t_fft := (true, false, true, 0, 1, 0, 128, 9, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
-- -- type t_rtwo_fft is record
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
index 73fb439b709e839d5056cf65bcbfbf545329a618..2a72e3c1debfd1911644188ff18c1a0115b6653b 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_pipe.vhd
@@ -38,7 +38,6 @@ entity tb_tb_fft_r2_pipe is
end tb_tb_fft_r2_pipe;
architecture tb of tb_tb_fft_r2_pipe is
-
constant c_fft_two_real : t_fft := ( true, false, true, 0, 1, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
constant c_fft_two_real_more_channels : t_fft := ( true, false, true, 1, 1, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
constant c_fft_complex : t_fft := ( true, false, false, 0, 1, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
@@ -65,9 +64,7 @@ architecture tb of tb_tb_fft_r2_pipe is
constant c_unused : string := "UNUSED";
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- DUT generics
-- g_fft : t_fft := (true, false, true, 0, 1, 0, 128, 9, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
-- -- type t_rtwo_fft is record
diff --git a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
index b97ef5b5207959508885bf4cfb9f6dd4ae088734..e48519e06488aa21fd264b6990cbbb25c3c8c8de 100644
--- a/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
+++ b/libraries/dsp/fft/tb/vhdl/tb_tb_fft_r2_wide.vhd
@@ -40,7 +40,6 @@ entity tb_tb_fft_r2_wide is
end tb_tb_fft_r2_wide;
architecture tb of tb_tb_fft_r2_wide is
-
constant c_fft_wb4_two_real : t_fft := ( true, false, true, 0, 4, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
constant c_fft_wb4_complex_fft_shift : t_fft := ( true, true, false, 0, 4, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
constant c_fft_wb4_complex_flipped : t_fft := (false, false, false, 0, 4, 0, 64, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2);
@@ -65,9 +64,7 @@ architecture tb of tb_tb_fft_r2_wide is
constant c_unused : string := "UNUSED";
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- DUT generics
-- --g_fft : t_fft := ( true, false, true, 0, 4, 0, 128, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
-- g_fft : t_fft := ( true, false, true, 0, 4, 0, 32, 8, 16, 0, c_dsp_mult_w, 2, true, 56, 2); -- two real inputs A and B
diff --git a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
index 9d400afe3770223c69ea4e0e3a355d3b88625571..0526a3ce5ecbaa98eec8d26bc75235c70956880a 100644
--- a/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_pkg.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package fil_pkg is
-
-- Parameters for the (wideband) poly phase filter.
type t_fil_ppf is record
wb_factor : natural; -- = 1, the wideband factor
@@ -70,4 +69,3 @@ end package fil_pkg;
package body fil_pkg is
end fil_pkg;
-
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
index df0fd9db85ec4f392fc8ca3a1c57d7fafcef2613..b77dcee842f9d7d1b8b0c4e95ab2215fccf8ea44 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_ctrl.vhd
@@ -137,7 +137,6 @@ begin
end if;
rin <= v;
-
end process comb;
regs : process(clk)
@@ -152,5 +151,4 @@ begin
taps_wren <= r.wr_en;
taps_out_vec <= r.taps_out_vec;
out_val <= r.val_dly(c_tot_latency - 1) and r.out_val_ena;
-
end rtl;
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
index 2c65de8a3609c77d2e1f69dd951b8a3d8c360f6d..d1e6c814ba9153ee28976ceb44f0fe90bb6a7503 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_filter.vhd
@@ -51,7 +51,6 @@ entity fil_ppf_filter is
end fil_ppf_filter;
architecture rtl of fil_ppf_filter is
-
constant c_in_dat_w : natural := g_fil_ppf.backoff_w + g_fil_ppf.in_dat_w; -- add optional input backoff to fit output overshoot
constant c_prod_w : natural := c_in_dat_w + g_fil_ppf.coef_dat_w - c_sign_w; -- skip double sign bit
constant c_gain_w : natural := 0; -- no need for adder bit growth so fixed 0, because filter coefficients should have DC gain <= 1.
@@ -65,9 +64,7 @@ architecture rtl of fil_ppf_filter is
signal in_taps : std_logic_vector(g_fil_ppf.in_dat_w * g_fil_ppf.nof_taps - 1 downto 0); -- taps input data as stored in RAM
signal in_taps_backoff : std_logic_vector( c_in_dat_w * g_fil_ppf.nof_taps - 1 downto 0); -- taps input data with backoff as use in FIR
-
begin
-
in_taps <= taps; -- Use this help signal to create a 'HIGH downto 0 vector again.
---------------------------------------------------------------
-- GENERATE THE MUTIPLIERS
@@ -141,6 +138,4 @@ begin
);
result <= RESIZE_SVEC(requant_out, result'length);
-
end rtl;
-
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd
index 4c0efb8d62e761173c534bddcec04c412e50c972..57baa9b3d81173fd21aed4064e85f68dd5160027 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_single.vhd
@@ -93,7 +93,6 @@ entity fil_ppf_single is
end fil_ppf_single;
architecture rtl of fil_ppf_single is
-
constant c_coefs_postfix : string := ".mif";
constant c_taps_mem_addr_w : natural := ceil_log2(g_fil_ppf.nof_bands * (2**g_fil_ppf.nof_chan));
constant c_coef_mem_addr_w : natural := ceil_log2(g_fil_ppf.nof_bands);
@@ -123,9 +122,7 @@ architecture rtl of fil_ppf_single is
signal taps_mem_in_vec : std_logic_vector(c_taps_mem_data_w * g_fil_ppf.nof_streams - 1 downto 0);
signal coef_rdaddr : std_logic_vector(c_coef_mem_addr_w - 1 downto 0);
signal coef_vec : std_logic_vector(c_coef_mem_data_w * g_fil_ppf.nof_taps - 1 downto 0);
-
begin
-
---------------------------------------------------------------
-- MEMORY FOR THE HISTORICAL TAP DATA
---------------------------------------------------------------
@@ -147,6 +144,7 @@ begin
rd_val => open
);
end generate;
+
---------------------------------------------------------------
-- COMBINE MEMORY MAPPED INTERFACES
---------------------------------------------------------------
diff --git a/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd b/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
index c11c6c0eb2d0412932701f3bb6a7c58a9c089506..fa57b10ec687002f24b5ce222d5b89a86a2f3e30 100644
--- a/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/src/vhdl/fil_ppf_wide.vhd
@@ -140,7 +140,6 @@ entity fil_ppf_wide is
end fil_ppf_wide;
architecture rtl of fil_ppf_wide is
-
constant c_nof_mif_files : natural := g_fil_ppf.wb_factor * g_fil_ppf.nof_taps;
constant c_file_index_arr : t_nat_natural_arr := array_init(0, c_nof_mif_files, 1); -- use the instance index as file index 0, 1, 2, 3, 4 ...
@@ -194,7 +193,6 @@ architecture rtl of fil_ppf_wide is
signal streams_in_arr : t_streams_in_arr( g_fil_ppf.wb_factor - 1 downto 0);
signal streams_out_arr : t_streams_out_arr(g_fil_ppf.wb_factor - 1 downto 0);
signal streams_out_val_arr : std_logic_vector( g_fil_ppf.wb_factor - 1 downto 0);
-
begin
---------------------------------------------------------------
-- COMBINE MEMORY MAPPED INTERFACES
@@ -270,5 +268,4 @@ begin
end process;
out_val <= streams_out_val_arr(0);
-
end rtl;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
index 78bd355ce5361da3603103ba6d0b014f830049db..a46728b9cf67359b74bdee7e2b11c1828fe0054b 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_single.vhd
@@ -177,7 +177,6 @@ entity tb_fil_ppf_single is
end entity tb_fil_ppf_single;
architecture tb of tb_fil_ppf_single is
-
constant c_clk_period : time := 10 ns;
constant c_nof_channels : natural := 2**g_fil_ppf.nof_chan;
@@ -233,9 +232,7 @@ architecture tb of tb_fil_ppf_single is
signal ref_dat : integer := 0;
signal read_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read via MM from the coefs memories
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
random <= func_common_random(random) when rising_edge(clk);
@@ -433,5 +430,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
index 42b76f62439bb9681e36e62b9e9a067893ca6ec6..0e166466f4fb589b36c1da95435862a0d78883c3 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide.vhd
@@ -83,7 +83,6 @@ entity tb_fil_ppf_wide is
end entity tb_fil_ppf_wide;
architecture tb of tb_fil_ppf_wide is
-
constant c_clk_period : time := 10 ns;
constant c_nof_channels : natural := 2**g_fil_ppf.nof_chan;
@@ -143,9 +142,7 @@ architecture tb of tb_fil_ppf_wide is
signal ref_dat_arr : t_integer_arr(0 to g_fil_ppf.wb_factor - 1) := (others => 0);
signal read_coefs_arr : t_integer_arr(c_nof_coefs - 1 downto 0) := (others => 0); -- = PFIR coef for all taps as read via MM from the coefs memories
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
random <= func_common_random(random) when rising_edge(clk);
@@ -353,5 +350,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
index 55b1ec0d5240980dd80fd8e0dbabe4f69a646fec..1e2c17cee976309b626feea49a95359b1765a953 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_fil_ppf_wide_file_data.vhd
@@ -127,7 +127,6 @@ entity tb_fil_ppf_wide_file_data is
end entity tb_fil_ppf_wide_file_data;
architecture tb of tb_fil_ppf_wide_file_data is
-
constant c_clk_period : time := 10 ns;
constant c_sclk_period : time := c_clk_period / g_fil_ppf.wb_factor;
@@ -195,9 +194,7 @@ architecture tb of tb_fil_ppf_wide_file_data is
signal out_val_cnt : natural := 0;
signal out_sub_val : std_logic;
signal out_sub_val_cnt : natural := 0;
-
begin
-
sclk <= (not sclk) or tb_end after c_sclk_period / 2;
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -490,5 +487,4 @@ begin
diff_data_scope >= -c_diff_margin report "Output data scope error" severity error;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_single.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_single.vhd
index a7c4b5c3f8357fd2a2cb6cd8102cc7c9fc5c9b1c..246318460d1d8dd3c3bf94b0e8a9dc939a5554a2 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_single.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_single.vhd
@@ -35,14 +35,11 @@ entity tb_tb_fil_ppf_single is
end tb_tb_fil_ppf_single;
architecture tb of tb_tb_fil_ppf_single is
-
constant c_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
constant c_prefix : string := "hex/run_pfir_coeff_m_incrementing";
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
--g_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
-- -- type t_fil_pipeline is record
-- -- -- generic for the taps and coefficients memory
@@ -78,5 +75,4 @@ begin
u_rnd_9taps : entity work.tb_fil_ppf_single generic map ((1, 1, 1, 1, 1, 1, 0), (1, 0, 64, 9, 1, 0, 8, 17, 16), c_prefix, true);
u_rnd_3streams : entity work.tb_fil_ppf_single generic map ((1, 1, 1, 1, 1, 1, 0), (1, 0, 64, 9, 3, 0, 8, 18, 16), c_prefix, true);
u_rnd_4channels : entity work.tb_fil_ppf_single generic map ((1, 1, 1, 1, 1, 1, 0), (1, 2, 64, 9, 3, 0, 8, 22, 16), c_prefix, true);
-
end tb;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd
index c7d545849ffab5ee5bf40190f3c5b4dcd495ffa1..fd5ce1f498b0c3cab27f2bb0839468c7f78de714 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide.vhd
@@ -35,14 +35,11 @@ entity tb_tb_fil_ppf_wide is
end tb_tb_fil_ppf_wide;
architecture tb of tb_tb_fil_ppf_wide is
-
constant c_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
constant c_prefix : string := "hex/run_pfir_coeff_m_incrementing";
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
--g_big_endian_wb_in : boolean := true;
--g_big_endian_wb_out : boolean := true;
--g_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
@@ -90,5 +87,4 @@ begin
u4_rnd_9taps : entity work.tb_fil_ppf_wide generic map ( true, true, (1, 1, 1, 1, 1, 1, 0), (4, 0, 64, 9, 1, 0, 8, 17, 16), c_prefix, true);
u4_rnd_3streams : entity work.tb_fil_ppf_wide generic map ( true, true, (1, 1, 1, 1, 1, 1, 0), (4, 0, 64, 9, 3, 0, 8, 18, 16), c_prefix, true);
u4_rnd_4channels : entity work.tb_fil_ppf_wide generic map ( true, true, (1, 1, 1, 1, 1, 1, 0), (4, 2, 64, 9, 3, 0, 8, 22, 16), c_prefix, true);
-
end tb;
diff --git a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
index 31c0ae3f78fe8b994c1cd365d4980b46808b4770..2aaff2311589c1c1bae5a91f6203b62b4d9abc99 100644
--- a/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
+++ b/libraries/dsp/filter/tb/vhdl/tb_tb_fil_ppf_wide_file_data.vhd
@@ -37,7 +37,6 @@ entity tb_tb_fil_ppf_wide_file_data is
end tb_tb_fil_ppf_wide_file_data;
architecture tb of tb_tb_fil_ppf_wide_file_data is
-
constant c_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
constant c_coeff_prefix : string := "hex/run_pfir_m_pfir_coeff_fircls1";
@@ -45,9 +44,7 @@ architecture tb of tb_tb_fil_ppf_wide_file_data is
constant c_data15 : string := "data/run_pfir_m_sinusoid_chirp_8b_15taps_128points_16b_16b.dat"; -- coefs, input and output data for 1 stream
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
--g_big_endian_wb_in : boolean := true;
--g_big_endian_wb_out : boolean := true;
--g_fil_ppf_pipeline : t_fil_ppf_pipeline := (1, 1, 1, 1, 1, 1, 0);
@@ -97,5 +94,4 @@ begin
u4_act_15taps : entity work.tb_fil_ppf_wide_file_data generic map ( true, true, c_pipeline, (4, 0, 128, 15, 1, 1, 8, 16, 16), c_coeff_prefix, c_data15, 25600, 5000, false);
u4_rnd : entity work.tb_fil_ppf_wide_file_data generic map ( true, true, c_pipeline, (4, 0, 128, 16, 1, 1, 8, 16, 16), c_coeff_prefix, c_data, 25600, 5000, true);
u4_rnd_channels_streams : entity work.tb_fil_ppf_wide_file_data generic map ( true, true, c_pipeline, (4, 1, 128, 16, 4, 1, 8, 16, 16), c_coeff_prefix, c_data, 25600, 5000, true);
-
end tb;
diff --git a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
index 7f74e63a76b5b32cdc0c81cab2e62be91ad1d056..65f193f20a9016327936b9688527f53dba485f16 100644
--- a/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/src/vhdl/fringe_stop_unit.vhd
@@ -34,7 +34,6 @@ use common_lib.common_math_pkg.all;
use technology_lib.technology_select_pkg.all;
use dp_lib.dp_stream_pkg.all;
-
entity fringe_stop_unit is
generic (
g_technology : natural := c_tech_select_default;
@@ -66,7 +65,6 @@ entity fringe_stop_unit is
end fringe_stop_unit;
architecture str of fringe_stop_unit is
-
-- invert the c_lookup_imag waveform, because the look up address phi for exp(-j*phi) is calculated,
-- but u_multiplier applies it as exp(j*phi)
-- . g_phi_minus_sign = FALSE : exp(j* phi) = cos(phi) + j*sin(phi)
@@ -131,9 +129,7 @@ architecture str of fringe_stop_unit is
signal phasor_imag : std_logic_vector(g_phasor_w - 1 downto 0);
signal result_re : std_logic_vector(c_product_w - 1 downto 0);
signal result_im : std_logic_vector(c_product_w - 1 downto 0);
-
begin
-
assert dbg_lookup_real_dc = 0 report "Fringe stop lookup COS must have DC = 0" severity ERROR;
assert dbg_lookup_imag_dc = 0 report "Fringe stop lookup SIN must have DC = 0" severity ERROR;
@@ -328,7 +324,6 @@ begin
rd_val_b => fs_step_data_valid
);
-
------------------------------------------------------------------------------
-- Pipeline offset to align with step accumulation
------------------------------------------------------------------------------
@@ -470,9 +465,4 @@ begin
out_sosi.re <= RESIZE_DP_DSP_DATA(result_re);
out_sosi.im <= RESIZE_DP_DSP_DATA(result_im);
end process;
-
end str;
-
-
-
-
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
index 505a615c7713b9b0f41b43f55c4cd67bb714f827..d2225c2df6b4b7af24e4316dfaabc98dc952020b 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_fringe_stop_unit.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -42,7 +41,6 @@ use technology_lib.technology_select_pkg.all;
use dp_lib.dp_stream_pkg.all;
use diag_lib.diag_pkg.all;
-
entity tb_fringe_stop_unit is
generic(
g_sim_type : natural := 2; -- 0 = Increment, 1 = Increment over the maximum, 2 = Decrease, 3 = Decrease over the minimum
@@ -57,7 +55,6 @@ entity tb_fringe_stop_unit is
end tb_fringe_stop_unit;
architecture tb of tb_fringe_stop_unit is
-
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
@@ -106,7 +103,6 @@ architecture tb of tb_fringe_stop_unit is
constant c_bg_nof_blocks_per_sync : natural := 128;
constant c_bg_mem_high_addr : natural := g_nof_channels - 1;
-
constant c_bg_ctrl : t_diag_block_gen := ( '0', -- enable: On by default in simulation; MM enable required on hardware.
'0', -- enable_sync
TO_UVEC( c_block_size, c_diag_bg_samples_per_packet_w),
@@ -151,9 +147,7 @@ architecture tb of tb_fringe_stop_unit is
signal r : reg_type := c_reg_type_rst;
signal rin : reg_type := c_reg_type_rst;
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -431,8 +425,4 @@ begin
end process;
tb_end <= '1' when r.loop_cnt = 4 else '0';
-
end tb;
-
-
-
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
index dd28809da6ce2f655770f186c00f9ba924569582..7fd9d4c2a183e94c5b67c3f526cecf016b5455cf 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_mmf_fringe_stop_unit.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2017
@@ -69,7 +68,6 @@ use mm_lib.mm_file_unb_pkg.all;
use mm_lib.mm_file_pkg.all;
use dp_lib.dp_stream_pkg.all;
-
entity tb_mmf_fringe_stop_unit is
generic(
g_tb_index : natural := 0; -- use different index to avoid MM file conflict in multi tb
@@ -81,7 +79,6 @@ entity tb_mmf_fringe_stop_unit is
end tb_mmf_fringe_stop_unit;
architecture tb of tb_mmf_fringe_stop_unit is
-
----------------------------------------------------------------------------
-- Clocks and resets
----------------------------------------------------------------------------
@@ -157,9 +154,7 @@ architecture tb of tb_mmf_fringe_stop_unit is
signal out_im_sum : integer := 0;
signal verify_out_en : std_logic := '0';
signal verify_sum_en : std_logic := '0';
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -319,7 +314,6 @@ begin
out_sosi => out_sosi
);
-
----------------------------------------------------------------------------
-- Verify FS output
----------------------------------------------------------------------------
@@ -391,8 +385,4 @@ begin
end if;
wait;
end process;
-
end tb;
-
-
-
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd
index 19601d088b6a44616b6b6cb2a4d10b0a9703511d..9a49efb0b76468711202bece508568c89eb56185 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_fringe_stop_unit.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -38,7 +37,6 @@ end tb_tb_fringe_stop_unit;
architecture tb of tb_tb_fringe_stop_unit is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- Usage
-- > as 8
-- > run -all
@@ -60,6 +58,3 @@ begin
end generate;
end tb;
-
-
-
diff --git a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd
index 5b6de6df3dead1bd4db5beed0bdfec23c436da9d..776e1d86b76b3a5b9e0a8d3fd5d57ec2c7de74e5 100644
--- a/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd
+++ b/libraries/dsp/fringe_stop/tb/vhdl/tb_tb_mmf_fringe_stop_unit.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -35,7 +34,6 @@ end tb_tb_mmf_fringe_stop_unit;
architecture tb of tb_tb_mmf_fringe_stop_unit is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_tb_index : NATURAL := 0; -- use different index to avoid MM file conflict in multi tb
-- g_mm_stimuli_enable : BOOLEAN := FALSE; -- use TRUE to activate p_mm_stimuli, else FALSE to apply mm_file IO via Python
-- g_mm_clk_faster_than_dp_clk : BOOLEAN := TRUE; -- when TRUE than mm_clk > dp_clk.
@@ -43,8 +41,4 @@ begin
u_mm_slower_no_gap : entity work.tb_mmf_fringe_stop_unit generic map (0, true, false, 0); -- use no gap to enable verification of phasor period
u_mm_faster_with_gap : entity work.tb_mmf_fringe_stop_unit generic map (1, true, true, 1); -- use gap to verify valid gaps
-
end tb;
-
-
-
diff --git a/libraries/dsp/iquv/src/vhdl/iquv.vhd b/libraries/dsp/iquv/src/vhdl/iquv.vhd
index 09bd9053bacfde2302ee604b69298048727b6b2c..e2f245afddb259829d76dd72834892261f820f74 100644
--- a/libraries/dsp/iquv/src/vhdl/iquv.vhd
+++ b/libraries/dsp/iquv/src/vhdl/iquv.vhd
@@ -35,16 +35,12 @@
-- Q and U are real
-- V is imaginary
-
-
-
library IEEE, common_lib, common_mult_lib, technology_lib, dp_lib, iquv_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity iquv is
generic (
g_sim : boolean := false;
@@ -70,9 +66,7 @@ entity iquv is
);
end iquv;
-
architecture str of iquv is
-
constant c_multprod_w : natural := g_in_data_w * 2;
constant c_iquv_w : natural := c_multprod_w + 1;
constant c_nof_int : natural := sel_a_b(g_use_accum, g_nof_int, 1); -- force nof_int to 1 if accum is not used
@@ -105,9 +99,7 @@ architecture str of iquv is
signal q_out_raw_sosi : t_dp_sosi := c_dp_sosi_rst;
signal u_out_raw_sosi : t_dp_sosi := c_dp_sosi_rst;
signal v_out_raw_sosi : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
------------------------------------------------------------------------------
-- control counter to demultiplex the X and Y polarizations
------------------------------------------------------------------------------
@@ -174,8 +166,6 @@ begin
out_dat => in_complex_valid_d1
);
-
-
------------------------------------------------------------------------------
-- Two complex multipliers (XX'. XY' and YY')
------------------------------------------------------------------------------
@@ -261,7 +251,6 @@ begin
out_dat => product_xx
);
-
------------------------------------------------------------------------------
-- I = XX' + YY'
------------------------------------------------------------------------------
@@ -280,8 +269,6 @@ begin
result => i_result
);
-
-
------------------------------------------------------------------------------
-- Q = XX' - YY'
------------------------------------------------------------------------------
@@ -300,8 +287,6 @@ begin
result => q_result
);
-
-
------------------------------------------------------------------------------
-- Delay XY' to match adders, then bitshift to calculate
-- U = 2 * Re(XY')
@@ -339,7 +324,6 @@ begin
out_dat => product_xy_im_dly
);
-
u_result <= product_xy_re_dly(c_multprod_w - 1 downto 0) & '0';
v_result <= product_xy_im_dly(c_multprod_w - 1 downto 0) & '0';
@@ -359,7 +343,6 @@ begin
out_dat => products_valid_vec_dly
);
-
------------------------------------------------------------------------------
-- Accumulators to integrate the Stokes products
------------------------------------------------------------------------------
@@ -395,8 +378,6 @@ begin
v_out_raw_sosi.valid <= products_valid_vec_dly(0);
end generate;
-
-
------------------------------------------------------------------------------
-- Requantize the outputs to the desired bit width
------------------------------------------------------------------------------
@@ -491,5 +472,4 @@ begin
src_out => v_out,
out_ovr => open
);
-
end str;
diff --git a/libraries/dsp/iquv/src/vhdl/iquv_accum.vhd b/libraries/dsp/iquv/src/vhdl/iquv_accum.vhd
index 33cefd25cc0ee93748a04bd46617d7701025edf8..3a348a2e60fbde316d64766dd299b954efff7624 100644
--- a/libraries/dsp/iquv/src/vhdl/iquv_accum.vhd
+++ b/libraries/dsp/iquv/src/vhdl/iquv_accum.vhd
@@ -31,15 +31,11 @@
-- Remarks
-- The outputs including the pipelined valid are placed in the data field of a dp_sosi record
-
-
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
-
entity iquv_accum is
generic (
g_accumcount_w : natural := 3; -- log2 of the number of samples to integrate
@@ -61,16 +57,13 @@ entity iquv_accum is
);
end iquv_accum;
-
architecture str of iquv_accum is
-
constant c_accum_count_zero : std_logic_vector(g_accumcount_w - 1 downto 0) := (others => '0');
signal accum_ctrl_count : std_logic_vector(g_accumcount_w - 1 downto 0);
signal accum_ctrl : std_logic;
signal enable_output_valid : std_logic := '0';
signal nxt_enable_output_valid : std_logic := '0';
-
begin
------------------------------------------------------------------------------
-- control counter to generate an end of integration period strobe
@@ -108,7 +101,6 @@ begin
out_dat => i_out_sosi.data
);
-
u_accum_q : entity common_lib.common_accumulate
generic map (
g_representation => "SIGNED"
@@ -123,7 +115,6 @@ begin
out_dat => q_out_sosi.data
);
-
u_accum_u : entity common_lib.common_accumulate
generic map (
g_representation => "SIGNED"
@@ -138,7 +129,6 @@ begin
out_dat => u_out_sosi.data
);
-
u_accum_v : entity common_lib.common_accumulate
generic map (
g_representation => "SIGNED"
@@ -153,7 +143,6 @@ begin
out_dat => v_out_sosi.data
);
-
p_clk : process (dp_clk, dp_rst)
begin
if dp_rst = '1' then
@@ -171,6 +160,4 @@ begin
q_out_sosi.valid <= accum_ctrl and in_valid and enable_output_valid;
u_out_sosi.valid <= accum_ctrl and in_valid and enable_output_valid;
v_out_sosi.valid <= accum_ctrl and in_valid and enable_output_valid;
-
-
end str;
diff --git a/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd b/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
index b38d5b8b24ab5263669a2f915a5844b4c461917f..5c60653c136df0a522cff0cf5c6b7fc5b2c05ab8 100644
--- a/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
+++ b/libraries/dsp/iquv/src/vhdl/iquv_iab.vhd
@@ -33,7 +33,6 @@
-- The output valid is taken from stream 0
-- If g_use_accum is true the integration is done after adding the g_nof_streams, otherwise it is done in the IQUV modules
-
library IEEE, common_lib, common_mult_lib, technology_lib, dp_lib, iquv_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -41,7 +40,6 @@ use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity iquv_iab is
generic (
g_sim : boolean := false;
@@ -80,7 +78,6 @@ entity iquv_iab is
end iquv_iab;
architecture str of iquv_iab is
-
constant c_accum_in_iquv : boolean := not g_use_accum;
constant c_accumcount_w : natural := ceil_log2(g_nof_int);
constant c_iquv_out_w : natural := 18;
@@ -146,16 +143,11 @@ architecture str of iquv_iab is
signal diag_v : t_diag;
type t_diag_in_complex_arr is array (0 to 2 * g_nof_streams - 1) of std_logic_vector(g_in_data_w - 1 downto 0);
signal diag_in_complex_arr : t_diag_in_complex_arr;
-
begin
-
-
-
------------------------------------------------------------------------------
-- Calculate the integrated I, Q, U and V for each input stream
------------------------------------------------------------------------------
gen_iquv : for stream in 0 to g_nof_streams - 1 generate
-
dut : entity work.iquv
generic map (
g_sim => g_sim,
@@ -179,10 +171,8 @@ begin
iquv_q_linear((stream + 1) * c_iquv_out_w - 1 downto stream * c_iquv_out_w) <= iquv_q_sosi(stream).data(c_iquv_out_w - 1 downto 0);
iquv_u_linear((stream + 1) * c_iquv_out_w - 1 downto stream * c_iquv_out_w) <= iquv_u_sosi(stream).data(c_iquv_out_w - 1 downto 0);
iquv_v_linear((stream + 1) * c_iquv_out_w - 1 downto stream * c_iquv_out_w) <= iquv_v_sosi(stream).data(c_iquv_out_w - 1 downto 0);
-
end generate;
-
------------------------------------------------------------------------------
-- Add up all the I, Q, U and V values from all the streams
------------------------------------------------------------------------------
@@ -238,7 +228,6 @@ begin
sum => v_summed
);
-
------------------------------------------------------------------------------
-- Delay the valid signal to match the pipeline delay through the adders
------------------------------------------------------------------------------
@@ -258,7 +247,6 @@ begin
out_dat => iquv_valid_dly
);
-
------------------------------------------------------------------------------
-- Optional accumulators to integrate the combined Stokes products
------------------------------------------------------------------------------
@@ -294,7 +282,6 @@ begin
v_sum_raw_sosi.valid <= iquv_valid_dly(0);
end generate;
-
------------------------------------------------------------------------------
-- Optional fine gain control
-- First the 25 bit data from the accumulator is truncated to 22 and requantized to 18
@@ -302,7 +289,6 @@ begin
------------------------------------------------------------------------------
gen_gain_ctrl : if g_use_gain_ctrl = true generate
-
-- I
u_dp_gain_requantize_i : entity dp_lib.dp_requantize
generic map (
@@ -488,7 +474,6 @@ begin
);
end generate;
-
gen_nogain_ctrl : if g_use_gain_ctrl = false generate
dp_requantize_i_snk_in <= i_sum_raw_sosi;
dp_requantize_q_snk_in <= q_sum_raw_sosi;
@@ -591,7 +576,6 @@ begin
out_ovr => open
);
-
-------------------------------------------------------------------------------
-- Diagnostic to display the I signal flow in simulation
-------------------------------------------------------------------------------
@@ -604,6 +588,7 @@ begin
diag_u.data_in_arr(stream) <= iquv_u_sosi(stream).data(c_iquv_out_w - 1 downto 0);
diag_v.data_in_arr(stream) <= iquv_v_sosi(stream).data(c_iquv_out_w - 1 downto 0);
end generate;
+
diag_i.valid_in <= iquv_i_sosi(0).valid;
diag_q.valid_in <= iquv_q_sosi(0).valid;
diag_u.valid_in <= iquv_u_sosi(0).valid;
@@ -641,7 +626,4 @@ begin
diag_u.valid_gain_out <= dp_requantize_u_snk_in.valid;
diag_v.valid_gain_out <= dp_requantize_v_snk_in.valid;
end generate;
-
-
end str;
-
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
index b50d804d9e99b7f2c136cffe6aa965703f8f1289..51e20a0fa1ab482958301b4cd0ced1fa3fd39d5d 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv.vhd
@@ -30,7 +30,6 @@
-- do wave_iquv.do
-- run -all
-
library IEEE, common_lib, dp_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -39,7 +38,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_iquv is
generic (
g_nof_int : natural := 16; -- number of successive subbands to integrate
@@ -49,9 +47,7 @@ entity tb_iquv is
);
end tb_iquv;
-
architecture tb of tb_iquv is
-
constant clk_period : time := 10 ns;
constant c_npoints : natural := 4 * g_nof_int; -- number of subbands (size of block) at present only used to generate test vectors
constant c_fsd_w : natural := g_in_data_w * 2 + 1 + ceil_log2(g_nof_int); -- The number of bits used for the accumulated result inside the DUT
@@ -76,7 +72,6 @@ architecture tb of tb_iquv is
signal random0 : std_logic_vector(7 downto 0) := (others => '0');
signal valid_enable : std_logic := '0';
-
-- expected data values
constant i_nint8_exp_arr : t_integer_arr(0 to 35) := (140,1100,3084,6092,
140,1100,3084,6092,
@@ -151,12 +146,7 @@ architecture tb of tb_iquv is
0,0,0,0,
- 60928, -60928, -60928, -60928,
0,0,0,0);
-
-
-
-
begin
-
dp_clk <= not dp_clk or tb_end after clk_period / 2;
dp_rst <= '0' after clk_period * 10;
random0 <= func_common_random(random0) when rising_edge(dp_clk);
@@ -166,7 +156,6 @@ begin
-- Valid signal stimuli
------------------------------------------------------------------------------
-
p_valstimuli : process
begin
in_complex.valid <= '0';
@@ -184,7 +173,6 @@ begin
-- Input stimuli
------------------------------------------------------------------------------
-
p_stimuli : process
begin
in_complex.re <= TO_DP_DSP_DATA(0);
@@ -263,7 +251,6 @@ begin
in_complex.im <= TO_DP_DSP_DATA(-2047); -- The im part of the Y pol is fixed
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
-
end loop;
for I in 0 to 9 loop wait until rising_edge(dp_clk); end loop;
@@ -329,7 +316,4 @@ begin
end if;
end if;
end process;
-
-
-
end tb;
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
index 59bd66a8dc23ddd9ba97db1965da040905085d5b..1060e8f869e95eeff71bbfe4a1e311650fb74d39 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_file_data.vhd
@@ -30,7 +30,6 @@
-- as 4
-- run -all
-
library IEEE, common_lib, dp_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -40,7 +39,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_iquv_file_data is
generic (
g_random_valid : boolean := true; -- Put gaps in the valid signal
@@ -52,14 +50,11 @@ entity tb_iquv_file_data is
);
end tb_iquv_file_data;
-
architecture tb of tb_iquv_file_data is
-
constant clk_period : time := 10 ns;
constant c_fsd_w : natural := g_in_data_w * 2 + 1 + true_log2(g_nof_int); -- The number of bits used for the accumulated result inside the DUT
constant c_lsb_w : natural := c_fsd_w - g_out_data_w; -- number of lsbs to remove from the expected result
-
signal tb_end : std_logic := '0';
signal dp_rst : std_logic := '1';
signal dp_clk : std_logic := '0';
@@ -103,10 +98,7 @@ architecture tb of tb_iquv_file_data is
signal q_noint_exp_arr : t_integer_arr(0 to c_nof_lines - 1) := (others => 0);
signal u_noint_exp_arr : t_integer_arr(0 to c_nof_lines - 1) := (others => 0);
signal v_noint_exp_arr : t_integer_arr(0 to c_nof_lines - 1) := (others => 0);
-
begin
-
-
dp_clk <= not dp_clk or tb_end after clk_period / 2;
dp_rst <= '0' after clk_period * 10;
random0 <= func_common_random(random0) when rising_edge(dp_clk);
@@ -116,7 +108,6 @@ begin
-- Valid signal stimuli
------------------------------------------------------------------------------
-
p_valstimuli : process
begin
in_complex.valid <= '0';
@@ -130,14 +121,10 @@ begin
wait;
end process;
-
-
-
------------------------------------------------------------------------------
-- Read stimuli and expected results from file
------------------------------------------------------------------------------
-
p_stimuli : process
begin
proc_common_read_integer_file(g_data_file, 0, c_nof_lines, c_nof_cols, file_data_arr);
@@ -237,7 +224,6 @@ begin
diag_v_out_data <= v_out.data(c_word_w - 1 downto 0);
diag_out_valid <= i_out.valid;
-
------------------------------------------------------------------------------
-- Results Checker
------------------------------------------------------------------------------
@@ -290,7 +276,4 @@ begin
end if;
end if;
end process;
-
-
-
end tb;
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
index bccdaa1fb11760d00eb63f0ff34d1803eb024d03..6b3e8f6cd12ab7b8c7e643ba398e4fac7d7b481f 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab.vhd
@@ -30,7 +30,6 @@
-- do wave_iquv_iab.do
-- run -all
-
library IEEE, common_lib, dp_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -39,7 +38,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_iquv_iab is
generic (
g_nof_int : natural := 16; -- number of successive subbands to integrate
@@ -50,9 +48,7 @@ entity tb_iquv_iab is
);
end tb_iquv_iab;
-
architecture tb of tb_iquv_iab is
-
constant clk_period : time := 10 ns;
constant c_npoints : natural := 4 * g_nof_int; -- number of subbands (size of block) at present only used to generate test vectors
constant c_iquv_out_w : natural := 18; -- number of bits the IQUV module truncates to
@@ -102,10 +98,7 @@ architecture tb of tb_iquv_iab is
- 1571328, -1571328, -1571328, -1571328);
constant v_nint16_exp_arr : t_integer_arr(0 to 7) := (9660,5460, -37140, -118140,
0,0,0,0);
-
-
begin
-
dp_clk <= not dp_clk or tb_end after clk_period / 2;
dp_rst <= '0' after clk_period * 10;
random0 <= func_common_random(random0) when rising_edge(dp_clk);
@@ -115,7 +108,6 @@ begin
in_complex_arr(inputstream) <= in_complex;
end generate;
-
------------------------------------------------------------------------------
-- Valid signal stimuli
------------------------------------------------------------------------------
@@ -162,8 +154,6 @@ begin
in_complex.im <= TO_DP_DSP_DATA(-2047); -- Set the imag part of the Y pol
wait until rising_edge(dp_clk) and valid_enable = '1';
end loop;
-
-
end loop;
for I in 0 to 19 loop wait until rising_edge(dp_clk); end loop;
@@ -171,7 +161,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -203,7 +192,6 @@ begin
diag_v_out_data <= v_out.data(c_word_w - 1 downto 0);
diag_out_valid <= i_out.valid;
-
p_verify : process(dp_clk, diag_out_valid, diag_i_out_data, diag_q_out_data, diag_u_out_data, diag_v_out_data)
variable v_index : integer := 0;
begin
@@ -231,7 +219,4 @@ begin
end if;
end if;
end process;
-
-
-
end tb;
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
index cfe0e44772d34fd415949ffd7720c216bc293d1f..981d9fb509aea364b8f53ba877a25ef0d56c2650 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_iquv_iab_file_data.vhd
@@ -30,7 +30,6 @@
-- as 4
-- run -all
-
library IEEE, common_lib, dp_lib, technology_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -40,7 +39,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_iquv_iab_file_data is
generic (
g_random_valid : boolean := true; -- Put gaps in the valid signal
@@ -53,9 +51,7 @@ entity tb_iquv_iab_file_data is
);
end tb_iquv_iab_file_data;
-
architecture tb of tb_iquv_iab_file_data is
-
constant clk_period : time := 10 ns;
constant c_out_iquv_w : natural := 18; -- number of bits the IQUV module truncates to
constant c_iquv_accum_w: natural := sel_a_b(g_use_accum, 0, true_log2(g_nof_int)); -- Bitgrowth of the IQUV accumulator
@@ -70,7 +66,6 @@ architecture tb of tb_iquv_iab_file_data is
constant c_nof_iab_int : natural := sel_a_b(g_use_accum, g_nof_int, 1); -- Used to simulate the IAB accumulator
-
signal tb_end : std_logic := '0';
signal dp_rst : std_logic := '1';
signal dp_clk : std_logic := '0';
@@ -119,10 +114,7 @@ architecture tb of tb_iquv_iab_file_data is
shared variable activestream : natural := 0;
signal activestream_dly: natural := 0;
-
begin
-
-
dp_clk <= not dp_clk or tb_end after clk_period / 2;
dp_rst <= '0' after clk_period * 10;
random0 <= func_common_random(random0) when rising_edge(dp_clk);
@@ -139,7 +131,6 @@ begin
-- Valid signal stimuli
------------------------------------------------------------------------------
-
p_valstimuli : process
begin
in_complex_data.valid <= '0';
@@ -154,14 +145,10 @@ begin
wait;
end process;
-
-
-
------------------------------------------------------------------------------
-- Read stimuli and expected results from file
------------------------------------------------------------------------------
-
p_stimuli : process
begin
proc_common_read_integer_file(g_data_file, 0, c_nof_lines, c_nof_cols, file_data_arr);
@@ -220,7 +207,6 @@ begin
-- DUT
------------------------------------------------------------------------------
-
dut : entity work.iquv_iab
generic map (
g_sim => true,
@@ -241,7 +227,6 @@ begin
v_out => v_out
);
-
-- diag signals to make outputs visible in Modelsim wave
diag_i_out_data <= i_out.data(c_word_w - 1 downto 0);
@@ -250,7 +235,6 @@ begin
diag_v_out_data <= v_out.data(c_word_w - 1 downto 0);
diag_out_valid <= i_out.valid;
-
------------------------------------------------------------------------------
-- Results Checker
------------------------------------------------------------------------------
@@ -312,7 +296,6 @@ begin
--REPORT "U expected IAB = " & integer'image(to_sint(s_round(u_expected_iab, c_lsb_w, TRUE)));
--REPORT "U actual = " & integer'image(TO_sINT(u_out.data));
-
--REPORT "I = " & integer'image(to_uint(i_out.data)) & ", Q = " & integer'image(to_sint(q_out.data)) &
-- ", U = " & integer'image(to_sint(u_out.data)) & ", V = " & integer'image(to_sint(v_out.data));
if v_index = c_nof_lines - 1 then
@@ -323,7 +306,4 @@ begin
end if;
end if;
end process;
-
-
-
end tb;
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd
index e1df0a8567c4c52e678bd1c6fd3b3f9f16c695d6..1dc8c856761c16a0919d57bb39f75f0282dae1b4 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_file_data.vhd
@@ -34,14 +34,10 @@ entity tb_tb_iquv_file_data is
end tb_tb_iquv_file_data;
architecture tb of tb_tb_iquv_file_data is
-
constant c_file_name : string := "iquv_stimuli_1.dat";
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-
-- Parameter list (random valid, stimuli file, enable accumulator, samples to integrate, input data width, output data width);
u_tc0 : entity work.tb_iquv_file_data generic map (true, c_file_name, true, 8, 12, 18);
u_tc1 : entity work.tb_iquv_file_data generic map (true, c_file_name, true, 16, 12, 18);
@@ -49,5 +45,4 @@ begin
u_tc3 : entity work.tb_iquv_file_data generic map (true, c_file_name, true, 8, 12, 8);
u_tc4 : entity work.tb_iquv_file_data generic map (true, c_file_name, true, 16, 12, 8);
u_tc5 : entity work.tb_iquv_file_data generic map (true, c_file_name, false, 1, 12, 8);
-
end tb;
diff --git a/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd b/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd
index 2f25ab59b5578aeda90ab05f1b6adbe8dfd7921f..c39a01cde195e3ee7c2dabbb3bb82796b573b54f 100644
--- a/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd
+++ b/libraries/dsp/iquv/tb/vhdl/tb_tb_iquv_iab_file_data.vhd
@@ -34,14 +34,10 @@ entity tb_tb_iquv_iab_file_data is
end tb_tb_iquv_iab_file_data;
architecture tb of tb_tb_iquv_iab_file_data is
-
constant c_file_name : string := "iquv_stimuli_1.dat";
constant c_nof_streams : natural := 3;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-
-- Parameter list (random valid, stimuli file, enable IAB accumulator, number of streams samples to integrate, in data width, out data width);
u_tc0 : entity work.tb_iquv_iab_file_data generic map (true, c_file_name, false, c_nof_streams, 8, 12, 18);
u_tc1 : entity work.tb_iquv_iab_file_data generic map (true, c_file_name, false, c_nof_streams, 16, 12, 18);
@@ -51,5 +47,4 @@ begin
u_tc5 : entity work.tb_iquv_iab_file_data generic map (true, c_file_name, true, c_nof_streams, 16, 12, 18);
u_tc6 : entity work.tb_iquv_iab_file_data generic map (true, c_file_name, true, c_nof_streams, 8, 12, 8);
u_tc7 : entity work.tb_iquv_iab_file_data generic map (true, c_file_name, true, c_nof_streams, 16, 12, 8);
-
end tb;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd
index 49d059fecb8611fa0e6077e19da1aa235859a0f0..b69305190699438f9e368ae991a02416c52b76d2 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoBF.vhd
@@ -62,12 +62,9 @@ entity rTwoBF is
end;
architecture rtl of rTwoBF is
-
signal in_a_dly : std_logic_vector(in_a'range);
signal out_d_ely : std_logic_vector(out_d'range);
-
begin
-
-- Optionally some z-1 delay gets move here into this BF stage, default 0
u_in_dly : entity common_lib.common_delay
generic map (
@@ -96,5 +93,4 @@ begin
-- BF function: add, subtract or pass the data on dependent on in_sel
out_c <= ADD_SVEC(in_a_dly, in_b, out_c'length) when in_sel = '1' else in_a_dly;
out_d_ely <= SUB_SVEC(in_a_dly, in_b, out_d'length) when in_sel = '1' else in_b;
-
end rtl;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd
index f53c5c7c7d5699f5654d3cb67893f62becdbb040..73302be0901e1a2c82d25d7c1fa8f047510ddc52 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoBFStage.vhd
@@ -49,7 +49,6 @@ entity rTwoBFStage is
end entity rTwoBFStage;
architecture str of rTwoBFStage is
-
-- Optionally move some z-1 delay into this BF stage, default 0
constant c_bf_in_a_zdly : natural := sel_a_b(g_stage >= g_bf_use_zdly, g_bf_in_a_zdly, 0);
constant c_bf_out_b_zdly : natural := sel_a_b(g_stage >= g_bf_use_zdly, g_bf_out_d_zdly, 0);
@@ -78,9 +77,7 @@ architecture str of rTwoBFStage is
signal stage_im : std_logic_vector(out_im'range);
signal stage_sel : std_logic;
signal stage_val : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- butterfly
------------------------------------------------------------------------------
@@ -115,7 +112,6 @@ begin
out_d => bf_im
);
-
------------------------------------------------------------------------------
-- feedback fifo
------------------------------------------------------------------------------
@@ -171,7 +167,6 @@ begin
-- after the z^(-1) stage delay the bf_val_dly goes high and remains high and acts as an enable for in_val to out_val
stage_val <= in_val and bf_val_dly;
-
------------------------------------------------------------------------------
-- stage output pipelining
------------------------------------------------------------------------------
@@ -212,5 +207,4 @@ begin
in_dat => stage_val,
out_dat => out_val
);
-
end str;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd
index a0a4b64cbec595bcd6dbfe7bcb93be31bd70eba3..2119f5395f665b651829d856a7332890c150e322 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoOrder.vhd
@@ -42,7 +42,6 @@ entity rTwoOrder is
end entity rTwoOrder;
architecture rtl of rTwoOrder is
-
constant c_nof_channels : natural := 2**g_nof_chan;
constant c_dat_w : natural := in_dat'length;
constant c_page_size : natural := g_nof_points * c_nof_channels;
@@ -70,9 +69,7 @@ architecture rtl of rTwoOrder is
signal rd_adr : std_logic_vector(c_adr_tot_w - 1 downto 0);
signal rd_dat : std_logic_vector(c_dat_w - 1 downto 0);
signal rd_val : std_logic;
-
begin
-
out_dat <= rd_dat;
out_val <= rd_val;
@@ -100,6 +97,7 @@ begin
gen_bit_flip : if g_bit_flip = true generate
wr_adr <= adr_chan_cnt & flip(adr_points_cnt); -- flip the addresses to perform the reorder
end generate;
+
no_bit_flip : if g_bit_flip = false generate
wr_adr <= adr_tot_cnt; -- do not flip the addresses for easier debugging with tb_rTwoOrder
end generate;
@@ -123,6 +121,7 @@ begin
one_chan : if c_nof_channels = 1 generate
cnt_ena <= '1' when in_val = '1' else '0';
end generate;
+
more_chan : if c_nof_channels > 1 generate
cnt_ena <= '1' when in_val = '1' and TO_UINT(adr_chan_cnt) = c_nof_channels - 1 else '0';
end generate;
@@ -163,5 +162,4 @@ begin
rd_dat => rd_dat,
rd_val => rd_val
);
-
end rtl;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd
index 34d10e59cd091aed49f01f603d02ad4523d3ee4c..73a859198ecdbbf9335841c5364f5cbd65e07551 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDF.vhd
@@ -26,7 +26,6 @@
-- Description: ASTRON-RP-755
-- Remarks: doc/readme.txt
-
library ieee, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -60,7 +59,6 @@ entity rTwoSDF is
end entity rTwoSDF;
architecture str of rTwoSDF is
-
constant c_nof_stages : natural := ceil_log2(g_nof_points);
constant c_stage_offset : natural := 0; -- In "normal" pipelined fft operation the stage offset is 0
constant c_twiddle_offset : natural := 0; -- In "normal" pipelined fft operation the twiddle offset is 0
@@ -85,9 +83,7 @@ architecture str of rTwoSDF is
signal raw_out_re : std_logic_vector(g_stage_dat_w - 1 downto 0);
signal raw_out_im : std_logic_vector(g_stage_dat_w - 1 downto 0);
signal raw_out_val : std_logic;
-
begin
-
-- Inputs
data_re( c_nof_stages) <= scale_and_resize_svec(in_re, c_in_scale_w, g_stage_dat_w);
data_im( c_nof_stages) <= scale_and_resize_svec(in_im, c_in_scale_w, g_stage_dat_w);
@@ -200,5 +196,4 @@ begin
-- Valid Output
out_val <= raw_out_val;
-
end str;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd
index 44eec4ed5830684fce83828c9980f6cc23594024..a21087320728da102867c6656a7802ad1222e838 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFPkg.vhd
@@ -23,7 +23,6 @@ library ieee;
use IEEE.std_logic_1164.all;
package rTwoSDFPkg is
-
-- Internal pipeline latencies and Z^(-1) pipeline settings for a stage in the rTwoSDF FFT
-- Also used for other preallele and wideband FFT implementations (fft_lib)
type t_fft_pipeline is record
@@ -45,4 +44,3 @@ end package rTwoSDFPkg;
package body rTwoSDFPkg is
end rTwoSDFPkg;
-
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd
index b2719e3b2cd3e79047883798c6e013e1bce4ee5e..82605e715170a7559056d8839fafbfd892822867 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoSDFStage.vhd
@@ -48,7 +48,6 @@ entity rTwoSDFStage is
end entity rTwoSDFStage;
architecture str of rTwoSDFStage is
-
-- The amplification factor per stage is 2, therefor bit growth defintion of 1.
-- Scale enable is defined by generic.
constant c_r2_stage_bit_growth : natural := sel_a_b(g_scale_enable, 1, 0);
@@ -76,9 +75,7 @@ architecture str of rTwoSDFStage is
signal quant_out_re : std_logic_vector(out_re'range);
signal quant_out_im : std_logic_vector(out_im'range);
-
begin
-
------------------------------------------------------------------------------
-- stage counter
------------------------------------------------------------------------------
@@ -248,5 +245,4 @@ begin
in_dat => mul_out_val,
out_dat => out_val
);
-
end str;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
index a4741228b2b297252923b0132af1b8e1c6dbdadc..875f9a660826c83d0e0f58be0e9daea6e46462ce 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWMul.vhd
@@ -48,7 +48,6 @@ entity rTwoWMul is
end entity rTwoWMul;
architecture str of rTwoWMul is
-
-- Use multiplier product truncate or signed rounding (= away from zero). On hardware for Fsub in
-- Apertif and using the WG at various frequencies at subband or between subbands it appears that
-- using truncate or sround does not make a noticable difference in the SST. Still choose to use
@@ -91,9 +90,7 @@ architecture str of rTwoWMul is
signal round_re : std_logic_vector(out_re'range);
signal round_im : std_logic_vector(out_re'range);
signal out_sel : std_logic;
-
begin
-
-- Total latency check
assert c_total_lat = g_lat
report "rTwoWMul: total pipeline error"
@@ -177,13 +174,13 @@ begin
round_re <= truncate_and_resize_svec(product_re, c_round_w, c_out_dat_w);
round_im <= truncate_and_resize_svec(product_im, c_round_w, c_out_dat_w);
end generate;
+
gen_reg : if c_round_lat = 1 generate
round_re <= truncate_and_resize_svec(product_re, c_round_w, c_out_dat_w) when rising_edge(clk);
round_im <= truncate_and_resize_svec(product_im, c_round_w, c_out_dat_w) when rising_edge(clk);
end generate;
end generate;
-
gen_sround : if c_use_truncate = false generate
u_requantize_re : entity common_lib.common_requantize
generic map (
@@ -228,7 +225,6 @@ begin
);
end generate;
-
------------------------------------------------------------------------------
-- Propagate data and control signals for input/output choice at WMult output
------------------------------------------------------------------------------
@@ -286,5 +282,4 @@ begin
------------------------------------------------------------------------------
out_re <= round_re when out_sel = '1' else scale(in_re_dly, c_out_extra_w);
out_im <= round_im when out_sel = '1' else scale(in_im_dly, c_out_extra_w);
-
end str;
diff --git a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd
index 8955d9fc15dd65937842e2e3e85553609c2c5842..5f7b31c5ce915cab37dc04cdf5cd045396441157 100644
--- a/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd
+++ b/libraries/dsp/rTwoSDF/src/vhdl/rTwoWeights.vhd
@@ -19,7 +19,6 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-
-- Purpose: Get twiddles from ROM
-- Description:
-- The twiddles ROM is generated twiddlesPkg.vhd.
@@ -52,7 +51,6 @@ entity rTwoWeights is
end;
architecture rtl of rTwoWeights is
-
constant c_virtual_stage : integer := g_stage + g_stage_offset; -- Virtual stage based on the real stage and the stage_offset.
constant c_nof_shifts : integer := -1 * g_stage_offset; -- Shift factor when fft is used in wfft configuration
@@ -61,9 +59,7 @@ architecture rtl of rTwoWeights is
signal wAdr_shift : std_logic_vector(c_virtual_stage-1 downto 1);
signal wAdr_unshift : std_logic_vector(c_virtual_stage-1 downto 1);
signal wAdr_tw_offset: integer := 0;
-
begin
-
-- Estimate the correct twiddle address.
-- In case of a wfft configuration the address will be shifted and the twiddle offset will be added.
wAdr_unshift <= RESIZE_UVEC(in_wAdr, wAdr_unshift'length);
@@ -99,5 +95,4 @@ begin
end generate;
assert g_lat <= 1 report "rTwoWeights : g_lat must be 0 or 1" severity failure;
-
end rtl;
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd
index a6e3302320872b213a375e50eaa05e4b87de7e41..2781ff5e6ea7226f6a474d9925e0ee59fc1e5c60 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoOrder.vhd
@@ -39,7 +39,6 @@ entity tb_rTwoOrder is
end tb_rTwoOrder;
architecture tb of tb_rTwoOrder is
-
constant c_clk_period : time := 10 ns;
constant c_nof_points : natural := 8;
@@ -56,9 +55,7 @@ architecture tb of tb_rTwoOrder is
signal out_dat : std_logic_vector(c_dat_w - 1 downto 0);
signal out_val : std_logic;
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 3;
@@ -108,5 +105,4 @@ begin
out_dat => out_dat,
out_val => out_val
);
-
end tb;
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
index 8490add97d73c3b6dbc96f51d5155eee1d43bc6e..1dac5bc00bd01bffeca324bec34d6ee80ef24a4c 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_rTwoSDF.vhd
@@ -84,7 +84,6 @@ use common_lib.tb_common_pkg.all;
use work.rTwoSDFPkg.all;
use work.twiddlesPkg.all;
-
entity tb_rTwoSDF is
generic(
-- generics for tb
@@ -99,9 +98,7 @@ entity tb_rTwoSDF is
);
end entity tb_rTwoSDF;
-
architecture tb of tb_rTwoSDF is
-
constant c_clk_period : time := 20 ns;
constant c_nof_points_w : natural := ceil_log2(g_nof_points);
@@ -166,16 +163,13 @@ architecture tb of tb_rTwoSDF is
signal gold_sync : std_logic;
signal gold_re : integer;
signal gold_im : integer;
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
enable <= '0', '1' after c_clk_period * 23;
random <= func_common_random(random) when rising_edge(clk);
in_en <= '1' when g_in_en = 1 else random(random'high);
-
p_read_input_file : process
file v_input : TEXT open READ_MODE is c_inputFile; -- this is LRM 1076-1987 style and implies that only simulator start and quit can open and close the file
variable v_log_line : LINE;
@@ -255,7 +249,6 @@ begin
end if;
end if;
end if;
-
end if;
end process;
@@ -364,5 +357,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd b/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd
index 9c3f855972da1cfb13be9aeda2f992976327ef7f..eaaaa888480aaf53d446291076428305ab790e16 100644
--- a/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd
+++ b/libraries/dsp/rTwoSDF/tb/vhdl/tb_tb_rTwoSDF.vhd
@@ -34,16 +34,12 @@ use STD.textio.all;
use common_lib.common_pkg.all;
use work.rTwoSDFPkg.all;
-
entity tb_tb_rTwoSDF is
end entity tb_tb_rTwoSDF;
architecture tb of tb_tb_rTwoSDF is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- generics for tb
-- g_use_uniNoise_file : boolean := true;
-- g_in_en : natural := 0; -- 1 = always active, others = random control
@@ -58,5 +54,4 @@ begin
u_act_noise_1024p_8i_14o : entity work.tb_rTwoSDF generic map (true, 1, true, 1024, 8, 14, 2);
u_rnd_noise_1024p_8i_14o : entity work.tb_rTwoSDF generic map (true, 0, true, 1024, 8, 14, 2);
u_rnd_noise_1024p_8i_14o_flipped : entity work.tb_rTwoSDF generic map (true, 0, false, 1024, 8, 14, 2);
-
end tb;
diff --git a/libraries/dsp/si/src/vhdl/si.vhd b/libraries/dsp/si/src/vhdl/si.vhd
index e815c408c71f598ac91a83a285a2b3f2077842df..6e5a85aff3e9b328c85538f97a9ff5205fae8b60 100755
--- a/libraries/dsp/si/src/vhdl/si.vhd
+++ b/libraries/dsp/si/src/vhdl/si.vhd
@@ -54,7 +54,6 @@ entity si is
end si;
architecture rtl of si is
-
signal plus : std_logic;
signal plus_reg : std_logic;
signal si_plus : std_logic;
@@ -63,9 +62,7 @@ architecture rtl of si is
-- For view in Wave window
signal in_data : std_logic_vector(g_dat_w - 1 downto 0);
signal si_data : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
in_data <= in_sosi.data(g_dat_w - 1 downto 0);
si_data <= si_sosi.data(g_dat_w - 1 downto 0);
@@ -113,5 +110,4 @@ begin
snk_in => si_sosi,
src_out => out_sosi
);
-
end rtl;
diff --git a/libraries/dsp/si/src/vhdl/si_arr.vhd b/libraries/dsp/si/src/vhdl/si_arr.vhd
index 484843993cb94bcfcd9690842d2968d057539f6d..2ef041cda1e33cd0e84d0fa2f09a5fb4a8d76f9d 100755
--- a/libraries/dsp/si/src/vhdl/si_arr.vhd
+++ b/libraries/dsp/si/src/vhdl/si_arr.vhd
@@ -55,7 +55,6 @@ entity si_arr is
end si_arr;
architecture str of si_arr is
-
--TYPE t_c_mem IS RECORD
-- latency : NATURAL; -- read latency
-- adr_w : NATURAL;
@@ -70,9 +69,7 @@ architecture str of si_arr is
constant c_si_mem_reg : t_c_mem := (c_mem_reg_rd_latency, 1, g_nof_streams, 1, '0');
signal reg_si_en : std_logic_vector(g_nof_streams - 1 downto 0);
-
begin
-
u_mms_common_reg : entity common_lib.mms_common_reg
generic map (
g_mm_reg => c_si_mem_reg
diff --git a/libraries/dsp/si/tb/vhdl/tb_si.vhd b/libraries/dsp/si/tb/vhdl/tb_si.vhd
index b08ce6888440a1146e7b44d142a7acf97c34ea17..98cc1d9762ef1c18df3e60e9f1f8702a32392934 100755
--- a/libraries/dsp/si/tb/vhdl/tb_si.vhd
+++ b/libraries/dsp/si/tb/vhdl/tb_si.vhd
@@ -42,7 +42,6 @@ entity tb_si is
end tb_si;
architecture tb of tb_si is
-
constant c_clk_period : time := 10 ns;
constant c_dat_w : natural := 5;
@@ -72,9 +71,7 @@ architecture tb of tb_si is
signal clip_odd : std_logic;
signal cnt_even : natural;
signal cnt_odd : natural;
-
begin
-
rst <= '1', '0' after c_clk_period;
clk <= not(clk) or tb_end after c_clk_period / 2;
@@ -247,6 +244,4 @@ begin
-- Count number of clip_even and clip_odd
cnt_even <= cnt_even + 1 when rising_edge(clk) and clip_even = '1';
cnt_odd <= cnt_odd + 1 when rising_edge(clk) and clip_odd = '1';
-
end tb;
-
diff --git a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
index 343b1af9e1a4cffc3a094dcabde7a4a28c8a7ffd..011a1479fc07a0d07cc0f5706f3346ee20876662 100644
--- a/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/mmp_st_histogram.vhd
@@ -33,7 +33,6 @@
-- . one dual clock block RAM here to provide the read access to the
-- page with the hold bin values via the mm_clk domain.
-
library IEEE, common_lib, mm_lib, technology_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -64,7 +63,6 @@ entity mmp_st_histogram is
end mmp_st_histogram;
architecture str of mmp_st_histogram is
-
-------------------------------------------------------------------------------
-- st_histogram instances
-------------------------------------------------------------------------------
@@ -103,10 +101,7 @@ architecture str of mmp_st_histogram is
-------------------------------------------------------------------------------
signal ram_copi_arr : t_mem_copi_arr(g_nof_instances - 1 downto 0);
signal ram_cipo_arr : t_mem_cipo_arr(g_nof_instances - 1 downto 0);
-
-
begin
-
-------------------------------------------------------------------------------
-- st_histogram instances
-------------------------------------------------------------------------------
@@ -224,6 +219,4 @@ begin
mosi_arr => ram_copi_arr,
miso_arr => ram_cipo_arr
);
-
end str;
-
diff --git a/libraries/dsp/st/src/vhdl/st_acc.vhd b/libraries/dsp/st/src/vhdl/st_acc.vhd
index 4e89132846a9dfb67cbcde405f6eef6b5ae9d56a..62ffc2e0963c77ee7fcc83a914e9f2ab91101956 100644
--- a/libraries/dsp/st/src/vhdl/st_acc.vhd
+++ b/libraries/dsp/st/src/vhdl/st_acc.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
-- Purpose:
-- Accumulate input data to an accumulator that is stored externally. In this
-- way blocks of input samples (e.g. subband products) can be accumulated to
@@ -61,9 +60,7 @@ entity st_acc is
);
end st_acc;
-
architecture rtl of st_acc is
-
constant c_pipeline : natural := g_pipeline_input + g_pipeline_output;
-- Input signals
@@ -79,9 +76,7 @@ architecture rtl of st_acc is
-- Pipeline control signals, map to slv to be able to use common_pipeline
signal in_val_slv : std_logic_vector(0 downto 0);
signal out_val_slv : std_logic_vector(0 downto 0);
-
begin
-
assert not(g_acc_w < g_dat_w)
report "st_acc: output accumulator width must be >= input data width"
severity FAILURE;
@@ -107,6 +102,7 @@ begin
use_in_load : if g_hold_load = false generate
acc_clr <= in_load; -- the in_load may already be extended during in_val
end generate;
+
use_hld_load : if g_hold_load = true generate
acc_clr <= in_load or (hld_load and not in_val);
end generate;
@@ -119,6 +115,7 @@ begin
reg_dat <= nxt_reg_dat;
reg_acc <= nxt_reg_acc;
end generate;
+
gen_input_reg : if g_pipeline_input > 0 generate
p_reg : process(clk)
begin
@@ -131,7 +128,6 @@ begin
end process;
end generate;
-
------------------------------------------------------------------------------
-- Adder for the external accumulator
------------------------------------------------------------------------------
@@ -153,7 +149,6 @@ begin
result => out_acc
);
-
------------------------------------------------------------------------------
-- Parallel output control pipeline
------------------------------------------------------------------------------
@@ -175,5 +170,4 @@ begin
in_dat => slv(in_val),
out_dat => out_val_slv
);
-
end rtl;
diff --git a/libraries/dsp/st/src/vhdl/st_calc.vhd b/libraries/dsp/st/src/vhdl/st_calc.vhd
index 577ebad0957ab5bc5421dd9488256ebd65262ef1..5e895907bdf2e33662392f70e0bf21c92c8547e2 100644
--- a/libraries/dsp/st/src/vhdl/st_calc.vhd
+++ b/libraries/dsp/st/src/vhdl/st_calc.vhd
@@ -79,9 +79,7 @@ entity st_calc is
);
end;
-
architecture str of st_calc is
-
constant c_complex_mult_variant : string := sel_a_b(g_in_dat_w <= c_dsp_mult_w, "IP", "RTL");
constant c_mux_w : natural := true_log2(g_nof_mux);
@@ -100,7 +98,6 @@ architecture str of st_calc is
constant c_rd_latency : natural := 2;
constant c_mem_acc : t_c_mem := (c_rd_latency, c_adr_w, c_acc_w, g_nof_mux * g_nof_stat, 'X'); -- 1 M9K
-
signal mult_re : std_logic_vector(c_mult_w - 1 downto 0);
signal mult_im : std_logic_vector(c_mult_w - 1 downto 0);
@@ -131,9 +128,7 @@ architecture str of st_calc is
signal wr_im : std_logic_vector(c_acc_w - 1 downto 0);
signal out_adr_m : std_logic_vector(c_adr_w - 1 downto 0);
-
begin
-
regs: process(rst,clk)
begin
if rst = '1' then
diff --git a/libraries/dsp/st/src/vhdl/st_ctrl.vhd b/libraries/dsp/st/src/vhdl/st_ctrl.vhd
index c15be72bac1807b6f6544fa428d485e3987382a7..ee08d4e8f413fb83a8e23d598407b965c3956775 100644
--- a/libraries/dsp/st/src/vhdl/st_ctrl.vhd
+++ b/libraries/dsp/st/src/vhdl/st_ctrl.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity st_ctrl is
generic (
g_nof_mux : natural := 1;
@@ -58,9 +57,7 @@ entity st_ctrl is
);
end;
-
architecture rtl of st_ctrl is
-
constant c_mux_w : natural := true_log2(g_nof_mux);
constant c_tin_mul : natural := 0;
@@ -93,9 +90,7 @@ architecture rtl of st_ctrl is
signal i_out_val : std_logic;
signal nxt_load : std_logic;
-
begin
-
-- hardwired
dly_val (0) <= in_val;
diff --git a/libraries/dsp/st/src/vhdl/st_histogram.vhd b/libraries/dsp/st/src/vhdl/st_histogram.vhd
index f078b78e54374223fa6fb33db915d9c052a813e5..10e3901f52c22f4ea4d30a2e4185ae5f5fd4233a 100644
--- a/libraries/dsp/st/src/vhdl/st_histogram.vhd
+++ b/libraries/dsp/st/src/vhdl/st_histogram.vhd
@@ -118,9 +118,7 @@ entity st_histogram is
);
end st_histogram;
-
architecture rtl of st_histogram is
-
-------------------------------------------------------------------------------
-- Main Constants
-------------------------------------------------------------------------------
@@ -204,10 +202,7 @@ architecture rtl of st_histogram is
signal nxt_ram_clear_address : std_logic_vector(c_ram_adr_w - 1 downto 0);
signal nxt_ram_clearing : std_logic;
-
-
begin
-
-------------------------------------------------------------------------------
-- Select range from snk_in.data and interpret as (un)signed
-------------------------------------------------------------------------------
@@ -229,7 +224,6 @@ begin
snk_in_data <= offset_binary(snk_in.data(g_data_w - 1 downto c_adr_low));
end generate;
-
-------------------------------------------------------------------------------
-- Slightly reduce the incoming data to prevent simultineous read/write
-- . Take out every 2nd and 3rd duplicate data value (set valid='0')
@@ -297,7 +291,6 @@ begin
end if;
end process;
-
-------------------------------------------------------------------------------
-- ram_pointer: Keep track of what RAM to target
-- . Target either RAM 0 or 1 per sync period
@@ -318,7 +311,6 @@ begin
-- Toggle the RAM pointer on the sync
ram_pointer <= not prv_ram_pointer when snk_in_reg.sync = '1' else prv_ram_pointer;
-
-------------------------------------------------------------------------------
-- bin_reader : reads bin from RAM, sends bin to bin_writer.
-- . Input : snk_in_reg (input data stream)
@@ -350,7 +342,6 @@ begin
bin_reader_to_writer_mosi.address <= prv_bin_reader_mosi.address;
nxt_bin_reader_to_writer_count <= TO_UINT(snk_in_reg.channel); -- Use register (_nxt) to align count with rdval instead of snk_in_reg.valid
-
-------------------------------------------------------------------------------
-- bin_writer : Increment the bin, do write request
-- . Input : bin_reader_to_writer_mosi (from bin_reader = bin + bin count)
@@ -371,7 +362,6 @@ begin
end if;
end process;
-
-------------------------------------------------------------------------------
-- Two RAM (common_ram_r_w) instances. The user can read the histogram from the
-- instance that is not being written to by the bin_writer.
@@ -430,7 +420,6 @@ begin
);
end generate;
-
-------------------------------------------------------------------------------
-- Clear the RAM just before the next sync interval
-------------------------------------------------------------------------------
@@ -465,11 +454,9 @@ begin
end if;
end process;
-
-------------------------------------------------------------------------------
-- Expose the MM buses to the user
-------------------------------------------------------------------------------
ram_miso <= histogram_rd_miso;
histogram_rd_mosi <= ram_mosi;
-
end rtl;
diff --git a/libraries/dsp/st/src/vhdl/st_sst.vhd b/libraries/dsp/st/src/vhdl/st_sst.vhd
index 484830a5b14e66569e168f4ec6e5e793ee520b47..97fa6e9e29e6f45280fbb999650e38f901d4a083 100644
--- a/libraries/dsp/st/src/vhdl/st_sst.vhd
+++ b/libraries/dsp/st/src/vhdl/st_sst.vhd
@@ -85,9 +85,7 @@ entity st_sst is
);
end st_sst;
-
architecture str of st_sst is
-
constant c_nof_stat_w : natural := ceil_log2(g_nof_stat);
constant c_nof_word : natural := g_stat_data_sz * g_nof_stat;
constant c_nof_word_w : natural := ceil_log2(c_nof_word);
@@ -136,9 +134,7 @@ architecture str of st_sst is
signal ram_st_sst_mosi_arr : t_mem_mosi_arr(c_nof_complex - 1 downto 0) := (others => c_mem_mosi_rst);
signal ram_st_sst_miso_arr : t_mem_miso_arr(c_nof_complex - 1 downto 0) := (others => c_mem_miso_rst);
-
begin
-
------------------------------------------------------------------------------
-- Register map for the treshold register
------------------------------------------------------------------------------
diff --git a/libraries/dsp/st/src/vhdl/st_xsq.vhd b/libraries/dsp/st/src/vhdl/st_xsq.vhd
index b7a38d2cf0cfd82dd43ecb21d6cb621608ff1f5f..d09aeec6c15c1030957a64d11fcdfad686eddb13 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq.vhd
@@ -78,7 +78,6 @@ entity st_xsq is
end st_xsq;
architecture str of st_xsq is
-
constant c_xsq : natural := g_nof_signal_inputs * g_nof_signal_inputs;
constant c_nof_statistics : natural := g_nof_crosslets * c_xsq;
constant c_nof_stat_w : natural := ceil_log2(c_nof_statistics);
@@ -119,7 +118,6 @@ architecture str of st_xsq is
signal ram_st_xsq_mosi_arr : t_mem_mosi_arr(c_nof_complex - 1 downto 0) := (others => c_mem_mosi_rst);
signal ram_st_xsq_miso_arr : t_mem_miso_arr(c_nof_complex - 1 downto 0) := (others => c_mem_miso_rst);
signal remapped_ram_st_xsq_mosi : t_mem_mosi;
-
begin
---------------------------------------------------------------
-- pipeline inputs to increase latency with 1 in comparison to sync for st_calc
@@ -277,5 +275,4 @@ begin
rd_dat_b => OPEN,
rd_val_b => open
);
-
end str;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd b/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd
index 80d350293f5dac115b15d0e98cae97cdedffc393..0ab5d69614d34e897a0b9b51f2f4efbcfc19c15d 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_arr.vhd
@@ -31,6 +31,7 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use common_lib.common_field_pkg.all;
use dp_lib.dp_stream_pkg.all;
+
entity st_xsq_arr is
generic (
g_nof_streams : natural := 1;
@@ -57,7 +58,6 @@ entity st_xsq_arr is
end st_xsq_arr;
architecture str of st_xsq_arr is
-
constant c_xsq : natural := g_nof_signal_inputs * g_nof_signal_inputs;
constant c_nof_statistics : natural := g_nof_crosslets * c_xsq;
constant c_nof_word : natural := g_stat_data_sz * c_nof_statistics * c_nof_complex;
@@ -65,7 +65,6 @@ architecture str of st_xsq_arr is
signal ram_st_xsq_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0) := (others => c_mem_mosi_rst);
signal ram_st_xsq_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0) := (others => c_mem_miso_rst);
-
begin
-- st_xsq instances
gen_xsq : for I in 0 to g_nof_streams - 1 generate
@@ -109,6 +108,4 @@ begin
mosi_arr => ram_st_xsq_mosi_arr,
miso_arr => ram_st_xsq_miso_arr
);
-
-
end str;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
index 606e6766689fe228db67a99a637f420dbe842c5b..2f9d05977c95c9e92ff4ce590ccb28ea7e3dcc51 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_dp_to_mm.vhd
@@ -49,9 +49,7 @@ entity st_xsq_dp_to_mm is
);
end st_xsq_dp_to_mm;
-
architecture rtl of st_xsq_dp_to_mm is
-
constant c_nof_data : natural := g_nof_crosslets * g_nof_signal_inputs;
constant c_mm_ram_adr_w : natural := ceil_log2(c_nof_data);
constant c_mm_ram_dat_w : natural := c_nof_complex * g_dsp_data_w;
@@ -60,9 +58,7 @@ architecture rtl of st_xsq_dp_to_mm is
signal reg_sosi_info : t_dp_sosi := c_dp_sosi_rst;
signal next_page : std_logic;
-
begin
-
u_dp_block_to_mm : entity dp_lib.dp_block_to_mm
generic map(
g_data_size => 1,
@@ -98,7 +94,6 @@ begin
rd_val => mm_miso.rdval
);
-
p_control : process(rst, clk)
begin
if rst = '1' then
@@ -120,6 +115,4 @@ begin
end if;
end if;
end process;
-
-
end rtl;
diff --git a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
index 63c6ee33f30ab0e78877b0996ca4d009d28e1465..8d4fc6a96510274df76bd64cf90481d7ff28a6cb 100644
--- a/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xsq_mm_to_dp.vhd
@@ -52,9 +52,7 @@ entity st_xsq_mm_to_dp is
);
end st_xsq_mm_to_dp;
-
architecture rtl of st_xsq_mm_to_dp is
-
type t_reg is record
in_sosi_strobe : t_dp_sosi;
out_sosi_ctrl : t_dp_sosi;
@@ -69,9 +67,7 @@ architecture rtl of st_xsq_mm_to_dp is
signal r : t_reg;
signal nxt_r : t_reg;
-
begin
-
mm_mosi <= nxt_r.mm_mosi;
u_sosi : process(r, mm_miso_arr)
@@ -142,5 +138,4 @@ begin
end if;
nxt_r <= v;
end process;
-
end rtl;
diff --git a/libraries/dsp/st/src/vhdl/st_xst.vhd b/libraries/dsp/st/src/vhdl/st_xst.vhd
index 9783589ba48e9357b4b2c493b1545140c42f6b49..33908871418a6a47deb48f6fa55d7110d7ee6de6 100644
--- a/libraries/dsp/st/src/vhdl/st_xst.vhd
+++ b/libraries/dsp/st/src/vhdl/st_xst.vhd
@@ -35,6 +35,7 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use common_lib.common_field_pkg.all;
use dp_lib.dp_stream_pkg.all;
+
entity st_xst is
generic (
g_nof_streams : natural := 1;
@@ -64,7 +65,6 @@ entity st_xst is
end st_xst;
architecture str of st_xst is
-
type t_reg is record
busy : std_logic;
in_a_index : natural;
@@ -82,9 +82,7 @@ architecture str of st_xst is
signal in_a_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal in_b_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
signal x_sosi_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0);
-
begin
-
-- MM -> DP
st_xsq_mm_to_dp : entity work.st_xsq_mm_to_dp
generic map(
@@ -197,6 +195,4 @@ begin
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso
);
-
-
end str;
diff --git a/libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd b/libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd
index 3fe4ef64d47c153061af54e76e89f96f85c0462e..5001ac90f810382249f2e755040a27e3a4e2a9bb 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mmf_st_sst.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -58,7 +57,6 @@ entity tb_mmf_st_sst is
end tb_mmf_st_sst;
architecture tb of tb_mmf_st_sst is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -113,9 +111,7 @@ architecture tb of tb_mmf_st_sst is
-- Signal declarations to connect block generator to the DUT
signal bg_siso_arr : t_dp_siso_arr(c_bg_nof_output_streams - 1 downto 0) := (others => c_dp_siso_rdy);
signal bg_sosi_arr : t_dp_sosi_arr(c_bg_nof_output_streams - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
diff --git a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
index e4b4f4da51cce95a2cff57174d0061c58d7955b3..72d545e3f59c53698d5e97273d7b6d6b9f714cb1 100644
--- a/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_mmp_st_histogram.vhd
@@ -57,9 +57,7 @@ entity tb_mmp_st_histogram is
); -- longer, shorter, etc. E.g. LOFAR2 uses 200M+-512 samples per sync.
end tb_mmp_st_histogram;
-
architecture tb of tb_mmp_st_histogram is
-
---------------------------------------------------------------------------
-- Constants derived from generics
---------------------------------------------------------------------------
@@ -108,9 +106,7 @@ architecture tb of tb_mmp_st_histogram is
signal verification_done : std_logic;
signal ver_long_sync_interval : boolean;
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -120,7 +116,6 @@ begin
mm_clk <= not mm_clk or tb_end after c_mm_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * 10;
-
----------------------------------------------------------------------------
-- DP Stimuli: generate st_histogram input (counter) data
----------------------------------------------------------------------------
@@ -160,7 +155,6 @@ begin
wait;
end process;
-
----------------------------------------------------------------------------
-- mmp_st_histogram
----------------------------------------------------------------------------
@@ -189,7 +183,6 @@ begin
ram_cipo => st_histogram_ram_cipo
);
-
----------------------------------------------------------------------------
-- Readout and verification of RAM contents
-- . The table below shows what RAM we are reading here ('RAM read') via the
@@ -295,7 +288,4 @@ begin
prv_st_histogram_ram_copi <= st_histogram_ram_copi;
end if;
end process;
-
-
-
end tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd b/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd
index 62ea4b66f480a2e620852faa8845802dd86364e9..738ce81a41798b7c4b04e56a7fa3dedffaa503d8 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_acc.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_st_acc is
generic (
g_dat_w : natural := 6;
@@ -35,9 +34,7 @@ entity tb_st_acc is
);
end tb_st_acc;
-
architecture tb of tb_st_acc is
-
constant clk_period : time := 10 ns;
constant c_pipeline : natural := g_pipeline_input + g_pipeline_output;
@@ -72,9 +69,7 @@ architecture tb of tb_st_acc is
signal expected_acc_p : std_logic_vector(g_acc_w - 1 downto 0);
signal expected_acc : std_logic_vector(g_acc_w - 1 downto 0);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
------------------------------------------------------------------------------
@@ -113,7 +108,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
@@ -140,7 +134,6 @@ begin
in_acc <= out_acc when c_pipeline > 0 else
out_acc when rising_edge(clk); -- if DUT has no pipeline, then register feedback to avoid combinatorial loop
-
------------------------------------------------------------------------------
-- Verify
------------------------------------------------------------------------------
@@ -170,5 +163,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_calc.vhd b/libraries/dsp/st/tb/vhdl/tb_st_calc.vhd
index 23f4035cfed796d827890f29e44e4e8356b4d59f..9442ccec2acbcc4d9e30fbb50184356b1d40ddb9 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_calc.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_calc.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_st_calc is
generic (
g_in_dat_w : natural := 16;
@@ -32,9 +31,7 @@ entity tb_st_calc is
);
end tb_st_calc;
-
architecture tb of tb_st_calc is
-
constant clk_period : time := 10 ns;
constant c_nof_sync : natural := 3;
@@ -61,9 +58,7 @@ architecture tb of tb_st_calc is
signal out_re : std_logic_vector(g_out_dat_w - 1 downto 0);
signal out_im : std_logic_vector(g_out_dat_w - 1 downto 0);
signal out_val : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
in_a_re <= in_dat;
@@ -126,5 +121,4 @@ begin
out_val => out_val,
out_val_m => open
);
-
end tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
index 09206c5117db4eddef018969ae23840dd5aeac96..85a515726d869bd92817c23014cfa4368bd37658 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_histogram.vhd
@@ -82,9 +82,7 @@ entity tb_st_histogram is
); -- FALSE produces a dense histogram as the drifting sine wave hits more levels.
end tb_st_histogram;
-
architecture tb of tb_st_histogram is
-
---------------------------------------------------------------------------
-- Constants derived from generics
---------------------------------------------------------------------------
@@ -140,17 +138,13 @@ architecture tb of tb_st_histogram is
signal sum_of_bins : natural;
signal verification_done : std_logic;
-
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
dp_clk <= not dp_clk or tb_end after c_dp_clk_period / 2;
dp_rst <= '1', '0' after c_dp_clk_period * 10;
-
----------------------------------------------------------------------------
-- Stimuli: generate st_histogram input data
----------------------------------------------------------------------------
@@ -239,7 +233,6 @@ begin
-- signal to verify histogram by eye in the wave window
stimuli_data <= stimuli_src_out.data(g_data_w - 1 downto 0);
-
----------------------------------------------------------------------------
-- st_histogram
----------------------------------------------------------------------------
@@ -341,7 +334,6 @@ begin
if i > 0 then -- Skip sync 0 (histogram still all zeros)
assert sum_of_bins = g_nof_data_per_sync report "Sum of bins not equal to g_nof_data_per_sync (expected " & integer'image(g_nof_data_per_sync) & ", actual " & integer'image(sum_of_bins) & ")" severity ERROR;
end if;
-
end loop;
verification_done <= '1'; -- We have blocking proc_common_wait_until_high procedures above so we need to know if we make it here.
wait;
@@ -365,5 +357,4 @@ begin
prv_st_histogram_ram_mosi <= st_histogram_ram_mosi;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_pkg.vhd b/libraries/dsp/st/tb/vhdl/tb_st_pkg.vhd
index 21f23353962a6fbfa569f3f909da310d13bc93e9..4d3b6d56458cbd20174a53044481d718b597ba5e 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_pkg.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_pkg.vhd
@@ -26,13 +26,10 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package tb_st_pkg is
-
function func_st_calculate_expected_xsq(a_re, a_im, b_re, b_im : t_integer_arr; N_crosslets, N_int : natural) return t_integer_arr;
-
end tb_st_pkg;
package body tb_st_pkg is
-
function func_st_calculate_expected_xsq(a_re, a_im, b_re, b_im : t_integer_arr; N_crosslets, N_int : natural) return t_integer_arr is
constant c_N_s : natural := a_re'length / N_crosslets;
constant c_xsq : natural := c_N_s * c_N_s;
@@ -46,6 +43,7 @@ package body tb_st_pkg is
v_exp_xsq(c_nof_complex * (N * c_xsq + I * c_N_s + J) ) := N_int * COMPLEX_MULT_REAL(a_re(N * c_N_s + I), a_im(N * c_N_s + I), b_re(N * c_N_s + J), -1 * b_im(N * c_N_s + J));
v_exp_xsq(c_nof_complex * (N * c_xsq + I * c_N_s + J) + 1) := N_int * COMPLEX_MULT_IMAG(a_re(N * c_N_s + I), a_im(N * c_N_s + I), b_re(N * c_N_s + J), -1 * b_im(N * c_N_s + J));
end loop;
+
end loop;
end loop;
return v_exp_xsq;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd b/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
index 009bbdba049bdc040877510e9cd6aaede0e6be60..d3217150a2e8d5e477f2af44345446d975ded98a 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_xsq.vhd
@@ -63,7 +63,6 @@ entity tb_st_xsq is
end tb_st_xsq;
architecture tb of tb_st_xsq is
-
constant c_sim : boolean := true;
constant c_rl : natural := 1;
constant c_block_size : natural := g_nof_crosslets * g_nof_signal_inputs;
@@ -107,7 +106,6 @@ architecture tb of tb_st_xsq is
signal ram_st_xsq_miso : t_mem_miso := c_mem_miso_rst;
signal st_xsq_out_arr : t_slv_32_arr(0 to c_nof_statistics * c_nof_complex * g_stat_data_sz - 1) := (others => (others => '0'));
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -228,5 +226,4 @@ begin
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso
);
-
end tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
index 3df7a07f58015ec287ed3a5f1fb233f5641cb4a4..51fd62c3f9e3deddf3e3103fbf212f8a5e50b22c 100644
--- a/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_st_xst.vhd
@@ -64,7 +64,6 @@ entity tb_st_xst is
end tb_st_xst;
architecture tb of tb_st_xst is
-
constant c_sim : boolean := true;
constant c_rl : natural := 1;
constant c_block_size : natural := g_nof_crosslets * g_nof_signal_inputs;
@@ -121,7 +120,6 @@ architecture tb of tb_st_xst is
-- Output array
----------------------------------------------------------------------------
signal st_xsq_out_2arr : t_xsq_out_2arr(0 to g_nof_streams - 1) := (others => (others => (others => '0')));
-
begin
-- random input and expected xsq
gen_in_exp : for I in 0 to g_nof_streams - 1 generate
@@ -222,7 +220,6 @@ begin
wait;
end process;
-
----------------------------------------------------------------------------
-- RAMs that contain a block of crosslets for each stream
----------------------------------------------------------------------------
@@ -276,5 +273,4 @@ begin
ram_st_xsq_mosi => ram_st_xsq_mosi,
ram_st_xsq_miso => ram_st_xsq_miso
);
-
end tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
index b8d227c8b0fe6944f190ae800a93ada06edbbb76..304a91ab0f34fff97ade1b2d9d03dd07f1284bf5 100644
--- a/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_histogram.vhd
@@ -38,7 +38,6 @@ end tb_tb_st_histogram;
architecture tb of tb_tb_st_histogram is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_nof_sync : NATURAL := 4;
-- g_data_w : NATURAL := 8;
-- g_nof_bins : NATURAL := 256;
@@ -81,5 +80,4 @@ u_tb_st_histogram_21: entity work.tb_st_histogram generic map ( 6, 6, 64, 20
u_tb_st_histogram_22: entity work.tb_st_histogram generic map ( 9, 8, 256, 2000, "random", "signed");
u_tb_st_histogram_23: entity work.tb_st_histogram generic map (17, 10, 256, 3455, "random", "signed");
u_tb_st_histogram_24: entity work.tb_st_histogram generic map (13, 14, 1024, 8111, "random", "signed");
-
end tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd
index d585106bba335849a71085a702783c869efa1e84..7317c264fab4a8273c24259c660c429807cea146 100644
--- a/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_xsq.vhd
@@ -34,11 +34,9 @@ entity tb_tb_st_xsq is
end tb_tb_st_xsq;
architecture tb of tb_tb_st_xsq is
-
constant c_nof_sync : natural := 3;
constant c_dsp_data_w : natural := 16;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-- GENERICS:
-- g_nof_crosslets : NATURAL := 2;
@@ -52,5 +50,4 @@ begin
u_sdp : entity work.tb_st_xsq generic map (1, 12, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
u_max : entity work.tb_st_xsq generic map (16, 8, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024); -- g_nof_crosslets * g_nof_signal_inputs**2 = 16 * 8 * 8 = 1024 = g_nof_clk_per_blk
-
end tb;
diff --git a/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd b/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd
index 4fe3fbc6397276f2e692d1baf7a35790df787e77..956b184c80dd2d336ce12df36408f510b47dd780 100644
--- a/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd
+++ b/libraries/dsp/st/tb/vhdl/tb_tb_st_xst.vhd
@@ -34,11 +34,9 @@ entity tb_tb_st_xst is
end tb_tb_st_xst;
architecture tb of tb_tb_st_xst is
-
constant c_nof_sync : natural := 3;
constant c_dsp_data_w : natural := 16;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-- GENERICS:
-- g_nof_streams : NATURAL := 9;
@@ -56,5 +54,4 @@ begin
u_sdp_mult_crosslets : entity work.tb_st_xst generic map (9, 7, 12, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024);
-- Note: u_max shows that the dut will skip sync periods if nof_statistics is not < g_nof_clk_per_blk
u_max : entity work.tb_st_xst generic map (2, 16, 8, c_dsp_data_w, c_nof_sync, 64, 2, 5, 1024); -- g_nof_crosslets * g_nof_signal_inputs**2 = 16 * 8 * 8 = 1024 = g_nof_clk_per_blk
-
end tb;
diff --git a/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
index 4da75e9be2726fb578edfc77a6d102c2e2b36517..0813eb85dc3b7d3baffc5a5ab3718da786f20607 100644
--- a/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_tb_verify_pfb_wg.vhd
@@ -56,7 +56,6 @@ entity tb_tb_verify_pfb_wg is
end entity tb_tb_verify_pfb_wg;
architecture tb of tb_tb_verify_pfb_wg is
-
-- LOFAR1
constant c_fil_coefs : string := "data/Coeffs16384Kaiser-quant_1wb";
@@ -109,9 +108,7 @@ architecture tb of tb_tb_verify_pfb_wg is
constant c_gen_vary_extra_w : boolean := false;
constant c_gen_2020_dec : boolean := false;
constant c_gen_2022_mar : boolean := false;
-
begin
-
-- generics of tb_verify_pfb_wg
-- g_tb_index : NATURAL := 0; -- use g_tb_index to identify and separate print_str() loggings from multi tb
-- g_sel_pfb : STRING := "WPFB"; -- "WPFB" for APERTIF PFB, "PFB2" for LOFAR1 PBF
@@ -163,7 +160,6 @@ begin
-- g_fft_guard_w : NATURAL := 1 -- = 2
-- g_switch_en : STD_LOGIC := '0'; -- two real input decorrelation option in PFB2
-
-- g_tb_index
-- . g_sel_pfb
-- . . g_subband_index_a
@@ -230,7 +226,6 @@ gen_ref : if c_gen_ref generate -- . . . . . . . .
--* For g_fft_stage_dat_w <= 22 the processing gain increases ~3 dB per extra g_fft_stage_dat_w bit, therefore choose 22, 23 or 24, more than 24 bit has not benefit.
end generate;
-
gen_g_fil_backoff_w_1 : if c_gen_g_fil_backoff_w_1 generate
-- g_subband_index_a = 60.4, to check that with g_fil_backoff_w = 1 there is no FIR filter overflow
u_149 : entity work.tb_verify_pfb_wg generic map (149, "WPFB", 60.4, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 18, 1, '0');
@@ -272,7 +267,6 @@ gen_g_fil_backoff_w_1 : if c_gen_g_fil_backoff_w_1 generate
-- scaled down by the factor 2 of g_fil_backoff_w = 1.
end generate;
-
gen_vary_g_fil_backoff_w : if c_gen_vary_g_fil_backoff_w generate
u_1000 : entity work.tb_verify_pfb_wg generic map (1000, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
u_1001 : entity work.tb_verify_pfb_wg generic map (1001, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 17, 18, 0, 22, 0, '0');
@@ -285,7 +279,6 @@ gen_vary_g_fil_backoff_w : if c_gen_vary_g_fil_backoff_w generate
-- . wpfb_measured_proc_gain_a_dB = 15.89 [dB]
end generate;
-
gen_vary_g_fft_out_dat_w : if c_gen_vary_g_fft_out_dat_w generate
-- WPFB
u_100 : entity work.tb_verify_pfb_wg generic map (100, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_wpfb_stage22
@@ -326,7 +319,6 @@ gen_2020_jan_18 : if c_gen_2020_jan_18 generate
-- tb-206 . wpfb_measured_proc_gain_a_dB = 14.62 [dB] + g_fft_stage_dat_w = 20 instead of 18, g_r2_mul_extra_w = 2, g_sepa_extra_w = 2
end generate;
-
gen_vary_wg_integer_freq : if c_gen_vary_wg_integer_freq generate
u_2001 : entity work.tb_verify_pfb_wg generic map (2001, "WPFB", 1.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
u_2002 : entity work.tb_verify_pfb_wg generic map (2002, "WPFB", 2.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18
@@ -365,7 +357,6 @@ gen_vary_wg_integer_freq : if c_gen_vary_wg_integer_freq generate
-- 503 . wpfb_measured_proc_gain_a_dB = 6.67 [dB]
end generate;
-
gen_vary_wg_fractional_freq : if c_gen_vary_wg_fractional_freq generate
-- Use fractions that fit integer number of periods in sync interval c_N_blk = c_wpfb.nof_blk_per_sync = 10, so c_N_blk*fraction must be integer, to have stable SST value
-- Need to use g_amplitude_a = 0.9 ~< 0.95 to avoid overflow in PFS output, that occurs for some fractional g_subband_index_a
@@ -423,7 +414,6 @@ gen_vary_wg_fractional_freq : if c_gen_vary_wg_fractional_freq generate
-- 62.0 . wpfb_measured_proc_gain_a_dB = 6.06 [dB]
end generate;
-
gen_vary_g_fft_stage_dat_w : if c_gen_vary_g_fft_stage_dat_w generate
-- g_internal_dat_w = constant
-- WPFB
@@ -508,7 +498,6 @@ gen_vary_g_fft_stage_dat_w : if c_gen_vary_g_fft_stage_dat_w generate
-- . c_twiddle_w = 18 18 16 16 18 16
end generate;
-
gen_vary_g_fil_in_dat_w : if c_gen_vary_g_fil_in_dat_w generate
u_400 : entity work.tb_verify_pfb_wg generic map (400, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 8, 17, 18, 0, 20, 1, '0');
u_401 : entity work.tb_verify_pfb_wg generic map (401, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 9, 17, 18, 0, 20, 1, '0');
@@ -559,7 +548,6 @@ gen_vary_g_fil_in_dat_w : if c_gen_vary_g_fil_in_dat_w generate
-- 14. wpfb_measured_proc_gain_a_dB = 12.38 [dB] 15.24 [dB] 16.36 [dB] 22.11 [dB]
end generate;
-
-- 2021_jan_11
gen_vary_g_amplitude_a : if c_gen_vary_g_amplitude_a generate
u_760 : entity work.tb_verify_pfb_wg generic map (760, "WPFB", 61.0, 61.0, 1.0 , 0.0, 0.0, 0.0, c_fil_coefs, 16, 0, 14, 17, 18, 0, 18, 1, '0'); -- = u_wpfb_stage18, 1.0
@@ -579,7 +567,6 @@ gen_vary_g_amplitude_a : if c_gen_vary_g_amplitude_a generate
--tb-766 . wpfb_measured_proc_gain_a_dB = 7.03 [dB]
end generate;
-
gen_vary_c_twiddle_w : if c_gen_vary_c_twiddle_w generate
-- WPFB only FFT
u_0 : entity work.tb_verify_pfb_wg generic map (0, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_bypass, 16, 0, 14, 17, 18, 0, 22, 1, '0'); -- = u_324
@@ -604,7 +591,6 @@ gen_vary_c_twiddle_w : if c_gen_vary_c_twiddle_w generate
-- 21 : wpfb_measured_proc_gain_a_dB = 24.75 [dB] 28.22 [dB]
end generate;
-
gen_vary_extra_w : if c_gen_vary_extra_w generate
--Conclusion:
--* If g_fft_stage_dat_w is large enough (~=> 24), then using extra_w has no benefit (as expected)
@@ -615,7 +601,6 @@ gen_vary_extra_w : if c_gen_vary_extra_w generate
-- using g_fft_stage_dat_w = 24 with extra_w 1, 1 yields 20.31 [dB] so ~= 0.72 dB better, but with 2, 2 it is even slightly less.
end generate;
-
gen_2020_dec : if c_gen_2020_dec generate
-- g_internal_dat_w = g_fft_stage_dat_w - g_fft_guard_w
-- g_fft_out_dat_w = 18
@@ -759,7 +744,6 @@ gen_2022_mar_21 : if c_gen_2022_mar generate
--u_2026 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2026, "WPFB", 59.0, 59.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 14, 0, 19, 1, 24, 1, '0'); -- = 2001
--u_2027 : ENTITY work.tb_verify_pfb_wg GENERIC MAP (2027, "WPFB", 61.0, 61.0, 1.0, 0.0, 0.0, 0.0, c_fil_coefs, 16, 1, 15, 0, 19, 1, 24, 1, '0');
-
-- Results:
-- c_twiddle_w = 18
-- g_fil_backoff_w = 1
@@ -905,7 +889,5 @@ gen_2022_mar_21 : if c_gen_2022_mar generate
-- The expected SST level for an integration interval of N_int subband blocks
-- is then:
-- SST = func_wpfb_sst_level(A_sub, N_blk)
-
end generate;
-
end tb;
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
index 642d59ac0145d28c27b254021d8d2420560715d8..efc4f67069d6e2ab1d606b109eaf3d2b2a5ea1b0 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_response.vhd
@@ -79,7 +79,6 @@ entity tb_verify_pfb_response is
end entity tb_verify_pfb_response;
architecture tb of tb_verify_pfb_response is
-
constant c_mm_clk_period : time := 1 ns;
constant c_dp_clk_period : time := 10 ns;
@@ -222,9 +221,7 @@ architecture tb of tb_verify_pfb_response is
signal reg_out_val : std_logic;
signal reg_out_bin : natural := 0;
signal reg_out_blk_cnt : natural := 0;
-
begin
-
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * 7;
@@ -492,5 +489,4 @@ begin
reg_out_im_b_scope <= out_im when rising_edge(dp_clk) and out_val_b = '1';
reg_out_power_b_scope <= out_power when rising_edge(dp_clk) and out_val_b = '1';
reg_out_phase_b_scope <= out_phase when rising_edge(dp_clk) and out_val_b = '1';
-
end tb;
diff --git a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
index 22b445f338bd5d828d5a9b25992e9c59128ec90c..ee4a173a4ab9271e6aa5c90cdb826516ff7fdec3 100644
--- a/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
+++ b/libraries/dsp/verify_pfb/tb_verify_pfb_wg.vhd
@@ -163,7 +163,6 @@ entity tb_verify_pfb_wg is
end entity tb_verify_pfb_wg;
architecture tb of tb_verify_pfb_wg is
-
constant c_mm_clk_period : time := 1 ns;
constant c_dp_clk_period : time := 10 ns;
@@ -518,9 +517,7 @@ architecture tb of tb_verify_pfb_wg is
signal dbg_c_bin_a_frac_en : boolean := c_bin_a_frac_en;
signal dbg_c_bin_b : natural := c_bin_b;
signal dbg_c_bin_b_frac_en : boolean := c_bin_b_frac_en;
-
begin
-
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * 7;
@@ -563,7 +560,6 @@ begin
wait;
end process;
-
-----------------------------------------------------------------------------
-- Run waveform generator (WG) input A and B
-----------------------------------------------------------------------------
@@ -1180,7 +1176,6 @@ begin
);
end generate;
-
p_fil_sosi : process(fil_sosi_arr, fil_val_cnt_per_sop)
begin
fil_sosi <= fil_sosi_arr(0);
@@ -1238,5 +1233,4 @@ begin
reg_out_im_a_scope <= out_im when rising_edge(dp_clk) and out_val_a = '1';
reg_out_re_b_scope <= out_re when rising_edge(dp_clk) and out_val_b = '1';
reg_out_im_b_scope <= out_im when rising_edge(dp_clk) and out_val_b = '1';
-
end tb;
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
index a0e0773787157c95d79cf9b5c570478620846da6..0d717d9f4d2487538b533a52ee31fb12acf38d42 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_pkg.vhd
@@ -28,7 +28,6 @@ use fft_lib.fft_pkg.all;
use filter_lib.fil_pkg.all;
package wpfb_pkg is
-
-- Parameters for the (wideband) poly phase filter.
type t_wpfb is record
-- General parameters for the wideband poly phase filter
@@ -269,7 +268,6 @@ package wpfb_pkg is
end package wpfb_pkg;
package body wpfb_pkg is
-
function func_wpfb_map_wpfb_parameters_to_fil_ppf(g_wpfb : t_wpfb) return t_fil_ppf is
constant c_fil_ppf : t_fil_ppf := (g_wpfb.wb_factor,
g_wpfb.nof_chan,
@@ -304,7 +302,6 @@ package body wpfb_pkg is
return c_fft;
end func_wpfb_map_wpfb_parameters_to_fft;
-
function func_wpfb_map_real_input_wpfb_parameters_to_complex_input(g_wpfb : t_wpfb) return t_wpfb is
variable v_wpfb : t_wpfb := g_wpfb;
begin
@@ -313,7 +310,6 @@ package body wpfb_pkg is
return v_wpfb;
end func_wpfb_map_real_input_wpfb_parameters_to_complex_input;
-
function func_wpfb_subband_scale_w(wpfb : t_wpfb) return natural is
begin
return wpfb.fft_out_dat_w + wpfb.fft_out_gain_w - (wpfb.fil_in_dat_w + wpfb.fil_backoff_w);
@@ -356,4 +352,3 @@ package body wpfb_pkg is
end func_wpfb_set_nof_block_per_sync;
end wpfb_pkg;
-
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
index 4c5f7f4fa139def2e1df06c51b817fcc8b281e2a..c75f7f8c998e8d62aabd887630cffe9e0e0a1e47 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit.vhd
@@ -87,7 +87,6 @@ entity wpfb_unit is
end entity wpfb_unit;
architecture str of wpfb_unit is
-
constant c_nof_stats : natural := 2**g_wpfb.nof_chan * g_wpfb.nof_points / g_wpfb.wb_factor;
constant c_fil_ppf : t_fil_ppf := func_wpfb_map_wpfb_parameters_to_fil_ppf(g_wpfb);
@@ -122,9 +121,7 @@ architecture str of wpfb_unit is
end record;
signal r, rin : reg_type;
-
begin
-
---------------------------------------------------------------
-- CHECK IF PROVIDED GENERICS ARE ALLOWED.
---------------------------------------------------------------
@@ -324,7 +321,6 @@ begin
ctrl_sosi => r.in_sosi_arr(0),
out_sosi_arr => fft_out_sosi_arr
);
-
end generate;
----------------------------------------------------------------------------
@@ -395,8 +391,4 @@ begin
out_sosi_arr(I * g_wpfb.wb_factor + J) <= fft_out_sosi_arr(I * g_wpfb.wb_factor + J);
end generate;
end generate;
-
end str;
-
-
-
diff --git a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
index 52be8780670ba9ea9b075a338019cb07f97b67e4..3385973b5266d184abde65a7e9c2d86b695ee086 100644
--- a/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/src/vhdl/wpfb_unit_dev.vhd
@@ -400,7 +400,6 @@ entity wpfb_unit_dev is
end entity wpfb_unit_dev;
architecture str of wpfb_unit_dev is
-
constant c_nof_channels : natural := 2**g_wpfb.nof_chan;
constant c_nof_data_per_block : natural := c_nof_channels * g_wpfb.nof_points;
@@ -456,9 +455,7 @@ architecture str of wpfb_unit_dev is
signal dbg_c_fft : t_fft := c_fft;
signal dbg_c_raw_fraction_w : natural := c_raw_fraction_w;
signal dbg_c_raw_dat_w : natural := c_raw_dat_w;
-
begin
-
-- The complete input sosi arry is registered.
comb : process(r, in_sosi_arr, dp_bsn_source_restart)
variable v : reg_type;
@@ -724,8 +721,4 @@ begin
-- Connect to the outside world
out_quant_sosi_arr <= pfb_out_quant_sosi_arr;
-
end str;
-
-
-
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd
index 05d7493da2dcd19070a62e10f74e978a958714f7..6676271bd0de13aa61cdd46869086ef3a4501560 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_mmf_wpfb_unit.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -48,7 +47,6 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > For fractional frequencies set g_nof_blocks=32 to be able to simulate a sufficent number of periods without transition.
-
library IEEE, common_lib, mm_lib, diag_lib, dp_lib, rTwoSDF_lib, fft_lib, filter_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -69,7 +67,6 @@ use fft_lib.fft_pkg.all;
use filter_lib.fil_pkg.all;
use work.wpfb_pkg.all;
-
entity tb_mmf_wpfb_unit is
generic(
g_wb_factor : natural := 1; -- = default 1, wideband factor
@@ -87,7 +84,6 @@ entity tb_mmf_wpfb_unit is
end tb_mmf_wpfb_unit;
architecture tb of tb_mmf_wpfb_unit is
-
constant c_in_backoff_w : natural := 0; -- = 0, number of bits for input backoff to avoid FIR output overflow
constant c_nof_blk_per_sync : natural := 20;
@@ -207,9 +203,7 @@ architecture tb of tb_mmf_wpfb_unit is
signal scope_out_band : natural;
signal scope_out_ampl_x : real := 0.0;
signal scope_out_ampl_y : real := 0.0;
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -310,6 +304,7 @@ begin
scope_sosi => scope_in_sosi(I)
);
end generate;
+
----------------------------------------------------------------------------
-- DUT = Device Under Test
----------------------------------------------------------------------------
@@ -444,5 +439,4 @@ begin
in_sync => out_sosi_arr(0).sync,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
index 1662a447a64c3ab81850b9832e5b40d99654fe4d..94cf0d06208b7ccc50ed2d727a10b2dedbb5b471 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_tb_wpfb_unit_wide.vhd
@@ -41,7 +41,6 @@ entity tb_tb_wpfb_unit_wide is
end tb_tb_wpfb_unit_wide;
architecture tb of tb_tb_wpfb_unit_wide is
-
constant c_stage_dat_extra_w : natural := c_dsp_mult_w + 10;
constant c_nof_blk_per_sync : natural := 20;
@@ -209,9 +208,7 @@ architecture tb of tb_tb_wpfb_unit_wide is
constant c_un : string := "UNUSED"; -- zero's data
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- DUT generics
-- g_wpfb : t_wpfb := (4, 32, 0, 1,
-- 16, 1, 8, 16, 16,
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
index a57255cc42a68efaab7b7f4989fe905992552217..c8be3118e2f27f0620b78c0b61b8bc9a4027507a 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit.vhd
@@ -113,11 +113,9 @@ entity tb_wpfb_unit is
g_coefs_file_prefix : string := "data/coefs_wide"
);
-
end entity tb_wpfb_unit;
architecture tb of tb_wpfb_unit is
-
constant c_clk_period : time := 100 ns;
constant c_fft : t_fft := (g_wpfb.use_reorder,
@@ -233,9 +231,7 @@ architecture tb of tb_wpfb_unit is
signal coefs_mem_write : boolean := false;
signal temp_reg : integer;
-
begin
-
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -405,7 +401,6 @@ begin
assert expected_sst_arr = result_sst_arr report "Output statistics error" severity error;
assert expected_sst_arr /= result_sst_arr report "Output statistics OK!!!!" severity note;
-
end loop;
end process;
@@ -442,6 +437,7 @@ begin
out_re_arr(I) <= RESIZE_SVEC(result_sosi_arr(I).re, out_re_arr(I)'length);
out_im_arr(I) <= RESIZE_SVEC(result_sosi_arr(I).im, out_im_arr(I)'length);
end generate;
+
out_val <= result_sosi_arr(0).valid;
---------------------------------------------------------------
@@ -493,7 +489,6 @@ begin
v_int_time := v_int_time + 1;
end if;
end if;
-
end process;
---------------------------------------------------------------
@@ -522,7 +517,6 @@ begin
else
v_list_index := v_list_index + 1;
end if;
-
end if;
for I in 0 to g_wpfb.wb_factor - 1 loop
@@ -531,7 +525,6 @@ begin
end loop;
gold_sync <= gold_file_sync(v_bin_index);
-
end process;
-- Verify the output of the DUT with the expected output from the golden reference file
@@ -590,5 +583,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
index 304a6c6a5c0ec4394e21e22b4b6c3126bcf3c4a5..bfc0eef5a84346339fd0688ec61a74ddbf48c315 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_dev.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -48,7 +47,6 @@
-- > Stop the simulation manually in Modelsim by pressing the stop-button.
-- > For fractional frequencies set g_nof_blocks=32 to be able to simulate a sufficent number of periods without transition.
-
library IEEE, common_lib, mm_lib, diag_lib, dp_lib, rTwoSDF_lib, fft_lib, filter_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -69,7 +67,6 @@ use fft_lib.fft_pkg.all;
use filter_lib.fil_pkg.all;
use work.wpfb_pkg.all;
-
entity tb_wpfb_unit_dev is
generic(
g_wb_factor : natural := 1; -- = default 1, wideband factor
@@ -88,7 +85,6 @@ entity tb_wpfb_unit_dev is
end tb_wpfb_unit_dev;
architecture tb of tb_wpfb_unit_dev is
-
constant c_wpfb : t_wpfb := (g_wb_factor, g_nof_points, g_nof_chan, g_nof_wb_streams,
g_nof_taps, 0, g_in_dat_w, 16, 16,
true, false, g_use_separate, 16, g_out_dat_w, 0, 18, 2, true, 56, 2, 20,
@@ -203,9 +199,7 @@ architecture tb of tb_wpfb_unit_dev is
signal scope_out_band : natural;
signal scope_out_ampl_x : real := 0.0;
signal scope_out_ampl_y : real := 0.0;
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -306,6 +300,7 @@ begin
scope_sosi => scope_in_sosi(I)
);
end generate;
+
----------------------------------------------------------------------------
-- DUT = Device Under Test
----------------------------------------------------------------------------
@@ -442,5 +437,4 @@ begin
in_sync => out_sosi_arr(0).sync,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
index ec8565ad4081771fdef67fcff0cdbf576cdd64fc..bcccc8f0fa31e1664aae2e7e1243f84cd18db896 100644
--- a/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
+++ b/libraries/dsp/wpfb/tb/vhdl/tb_wpfb_unit_wide.vhd
@@ -157,7 +157,6 @@ entity tb_wpfb_unit_wide is
end entity tb_wpfb_unit_wide;
architecture tb of tb_wpfb_unit_wide is
-
constant c_big_endian_wb_in : boolean := true;
constant c_clk_period : time := 10 ns;
@@ -343,9 +342,7 @@ architecture tb of tb_wpfb_unit_wide is
signal diff_im_a_scope : integer := 0;
signal diff_re_b_scope : integer := 0;
signal diff_im_b_scope : integer := 0;
-
begin
-
sclk <= (not sclk) or tb_end after c_sclk_period / 2;
clk <= (not clk) or tb_end after c_clk_period / 2;
rst <= '1', '0' after c_clk_period * 7;
@@ -804,5 +801,4 @@ begin
out_int => out_im_scope,
out_val => open
);
-
end tb;
diff --git a/libraries/io/aduh/src/vhdl/aduh_dd.vhd b/libraries/io/aduh/src/vhdl/aduh_dd.vhd
index 7bd60f4592cb7b99713f3e0ab844c140cc520578..1049b42901e2346e305cb0e2391a5395e118934e 100644
--- a/libraries/io/aduh/src/vhdl/aduh_dd.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_dd.vhd
@@ -96,9 +96,7 @@ entity aduh_dd is
);
end aduh_dd;
-
architecture str of aduh_dd is
-
constant c_use_lvdsh_dd_phs4 : boolean := g_nof_dp_phs_clk > 1;
constant c_dp_factor : natural := g_ai.rx_factor * g_ai.dd_factor;
@@ -138,9 +136,7 @@ architecture str of aduh_dd is
signal rx_dat_cd : std_logic_vector(c_rx_dat_w - 1 downto 0);
signal rx_val_ab : std_logic;
signal rx_val_cd : std_logic;
-
begin
-
assert g_ai.nof_sp = 4 and g_ai.nof_adu = 2 and g_ai.nof_ports = 2
report "aduh_dd : expects input 4 signal paths via 2 ports from 2 ADU"
severity FAILURE;
@@ -319,7 +315,6 @@ begin
);
end generate;
-
-- Use register stage to map offset binary to two's complement, this will allow synthesis to use the FF q_not output for the high bit and the FF q output for the other bits
p_dp_clk : process(dp_clk)
begin
@@ -332,5 +327,4 @@ begin
rx_val_cd <= obin_val_cd;
end if;
end process;
-
end str;
diff --git a/libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd b/libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd
index 18b049792ffc535f45738dbeae79f6f25cd56d32..01bd165fc42f86d0ca4107318b86081748bbcc07 100644
--- a/libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_dd_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
package aduh_dd_pkg is
-
-- ADU Interface
type t_c_aduh_delays is record -- Input de-skew buffer delays: unit 50 ps, range 0..15
clk_delay_a : natural;
@@ -54,7 +53,6 @@ package aduh_dd_pkg is
constant c_aduh_dd_ai : t_c_aduh_dd_ai := (4, 2, 2, 8, 2, 2, true, false, c_aduh_delays);
-
end aduh_dd_pkg;
package body aduh_dd_pkg is
diff --git a/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd b/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd
index 75b31ed537e965b84d54c23260943eed987399e0..03ac392efcb7d236aaee0e361d844f15f240e463 100644
--- a/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_mean_sum.vhd
@@ -31,7 +31,6 @@ library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
-
entity aduh_mean_sum is
generic (
g_symbol_w : natural := 12;
@@ -55,9 +54,7 @@ entity aduh_mean_sum is
);
end aduh_mean_sum;
-
architecture rtl of aduh_mean_sum is
-
constant c_acc_w : natural := g_symbol_w + ceil_log2(g_nof_accumulations / g_nof_symbols_per_data);
constant c_acc_sum_nof_stages : natural := ceil_log2(g_nof_symbols_per_data);
constant c_acc_sum_pipeline : natural := 1;
@@ -74,9 +71,7 @@ architecture rtl of aduh_mean_sum is
signal i_sum : std_logic_vector(g_sum_w - 1 downto 0);
signal nxt_sum : std_logic_vector(g_sum_w - 1 downto 0);
signal nxt_sum_sync : std_logic;
-
begin
-
sum <= i_sum;
regs : process(rst,clk)
diff --git a/libraries/io/aduh/src/vhdl/aduh_monitor.vhd b/libraries/io/aduh/src/vhdl/aduh_monitor.vhd
index 3f9d873d8008bc3033e035e8a1842a3e0c5d4473..d88e08481c21c62dc19d30c78f4d04a1cd620439 100644
--- a/libraries/io/aduh/src/vhdl/aduh_monitor.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_monitor.vhd
@@ -73,15 +73,11 @@ entity aduh_monitor is
);
end aduh_monitor;
-
architecture str of aduh_monitor is
-
constant c_data_w : natural := g_nof_symbols_per_data * g_symbol_w; -- = 32, must be <= 32 to fit the u_data_buffer
constant c_stat_w : natural := 2 * c_word_w; -- support upto 64 bit sum width, this is more than enough without truncation and no accumulator overflow
constant c_buffer_nof_data : natural := g_buffer_nof_symbols / g_nof_symbols_per_data;
-
begin
-
u_mean : entity work.aduh_mean_sum
generic map (
g_symbol_w => g_symbol_w,
@@ -148,5 +144,4 @@ begin
in_sync => in_sosi.sync,
in_val => in_sosi.valid
);
-
end str;
diff --git a/libraries/io/aduh/src/vhdl/aduh_monitor_reg.vhd b/libraries/io/aduh/src/vhdl/aduh_monitor_reg.vhd
index 98460f8982b085e91989dd2c565735017ca535f1..d0e218257dd80fee4abca99ce38c1a43bb2195c4 100644
--- a/libraries/io/aduh/src/vhdl/aduh_monitor_reg.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_monitor_reg.vhd
@@ -63,9 +63,7 @@ entity aduh_monitor_reg is
);
end aduh_monitor_reg;
-
architecture rtl of aduh_monitor_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => 2,
@@ -80,9 +78,7 @@ architecture rtl of aduh_monitor_reg is
signal mm_mon_power_sum_hi : std_logic_vector(c_word_w - 1 downto 0);
-- Registers in st_clk domain
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
diff --git a/libraries/io/aduh/src/vhdl/aduh_pll.vhd b/libraries/io/aduh/src/vhdl/aduh_pll.vhd
index ba6fa3ed171308d2a3dc1e0bd7f7683f1a4440ae..4f0723adec991243a41e39e50a72eab5781958e2 100644
--- a/libraries/io/aduh/src/vhdl/aduh_pll.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_pll.vhd
@@ -109,9 +109,7 @@ entity aduh_pll is
);
end aduh_pll;
-
architecture str of aduh_pll is
-
-----------------------------------------------------------------------------
-- LVDS domain
-----------------------------------------------------------------------------
@@ -155,9 +153,7 @@ architecture str of aduh_pll is
signal dp_ovr : t_sl_arr( 0 to g_ai.nof_sp - 1); -- [0:3]=[AB,AB,CD,CD] or [0:3]=[ 0, 0, CD,CD], vector OR of porth_dat overflow bits at t0,t1,t2,t3
signal dp_dat : t_dp_dat_arr(0 to g_ai.nof_sp - 1); -- [0:3]=[ A, B, C, D] or [0:3]=[ 0, 0, C, D]
signal dp_val : t_sl_arr( 0 to g_ai.nof_sp - 1); -- [0:3]=[ A, B, C, D] or [0:3]=[ 0, 0, C, D]
-
begin
-
-- nof_clocks use_lvds_clk supported
-- 1 TRUE YES
-- 1 FALSE YES , use dp_clk
diff --git a/libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd b/libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd
index ea281c13ecd51d73d5981c29fa16d8f100d2bc01..f9d4ff32066f5729f9f1a190d0752808ba6e74c5 100644
--- a/libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_pll_pkg.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
package aduh_pll_pkg is
-
-- ADU Interface
type t_c_aduh_pll_ai is record
nof_sp : natural; -- = 4; -- Fixed support 4 signal paths A,B,C,D, whether they contain active data depends on nof_adu
@@ -54,9 +53,7 @@ package aduh_pll_pkg is
end aduh_pll_pkg;
-
package body aduh_pll_pkg is
-
function func_aduh_pll_adu_dat_w(ai : t_c_aduh_pll_ai) return natural is
begin
-- fixed fixed
diff --git a/libraries/io/aduh/src/vhdl/aduh_power_sum.vhd b/libraries/io/aduh/src/vhdl/aduh_power_sum.vhd
index c076a80e247c5e6532f9445fb970e7ff908ebc43..4b0f5a0cee1ef4dcc4e32542f67af25f1b781430 100644
--- a/libraries/io/aduh/src/vhdl/aduh_power_sum.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_power_sum.vhd
@@ -32,7 +32,6 @@ use IEEE.std_logic_1164.all;
use technology_lib.technology_select_pkg.all;
use common_lib.common_pkg.all;
-
entity aduh_power_sum is
generic (
g_technology : natural := c_tech_select_default;
@@ -58,9 +57,7 @@ entity aduh_power_sum is
);
end aduh_power_sum;
-
architecture str of aduh_power_sum is
-
constant c_prod_w : natural := 2 * g_symbol_w;
constant c_pipeline_prod : natural := 1;
@@ -74,9 +71,7 @@ architecture str of aduh_power_sum is
-- Debug signals
signal symbol_arr : t_symbol_arr(0 to g_nof_symbols_per_data - 1);
signal prod_arr : t_prod_arr(0 to g_nof_symbols_per_data - 1);
-
begin
-
u_prod_data : entity common_mult_lib.common_mult
generic map (
g_technology => g_technology,
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad.vhd b/libraries/io/aduh/src/vhdl/aduh_quad.vhd
index 577ac1008387e28570d84aa8de99caa2343302d9..1d93bfab80e3d775c5f7414f737925cfa03da25d 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad.vhd
@@ -22,7 +22,6 @@
-- Purpose: Capture input from four ADC [A,B,C,D] on two ADU and support
-- pattern verify for each ADC
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -77,9 +76,7 @@ entity aduh_quad is
);
end aduh_quad;
-
architecture str of aduh_quad is
-
constant c_dp_factor : natural := g_ai.rx_factor * g_ai.dd_factor;
constant c_wideband_factor : natural := c_dp_factor; -- Wideband rate factor = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
@@ -89,9 +86,7 @@ architecture str of aduh_quad is
signal aduh_cd_dp_phs_clk_en_vec : std_logic_vector(g_nof_dp_phs_clk - 1 downto 0);
signal i_aduh_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = [0:3] = ADC_BI ports [A,B,C,D]
-
begin
-
-- ADC [A,B,C,D] input samples
aduh_sosi_arr <= i_aduh_sosi_arr;
@@ -139,7 +134,6 @@ begin
src_out_arr => i_aduh_sosi_arr
);
-
-- ADC pattern verification
gen_verify : for I in 0 to g_ai.nof_sp - 1 generate
aduh_verify_res(I)(c_word_w - 1 downto g_ai.port_w + 1) <= (others => '0'); -- unused bits [31:9]
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd b/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd
index 186c95bb213b6303e81c42631bb56d0afd7356f6..f048db7912d07bc2d7a453e609826a997f82b1f1 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad_reg.vhd
@@ -97,9 +97,7 @@ entity aduh_quad_reg is
);
end aduh_quad_reg;
-
architecture rtl of aduh_quad_reg is
-
-- Define the actual size of the MM slave register
constant c_nof_dat : natural := 8;
constant c_mm_reg : t_c_mem := (latency => 1,
@@ -135,9 +133,7 @@ architecture rtl of aduh_quad_reg is
signal mm_aduh_c_verify_res_val : std_logic;
signal mm_aduh_d_verify_res : std_logic_vector(c_word_w - 1 downto 0);
signal mm_aduh_d_verify_res_val : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -536,4 +532,3 @@ begin
end generate; -- gen_cross
end rtl;
-
diff --git a/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd b/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd
index e19032ce28d46621616d787ddb96f8681c2a3dcd..061f02161ba6b9da748f3f11d2cc292c43925558 100644
--- a/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_quad_scope.vhd
@@ -24,7 +24,6 @@
-- Remark:
-- . Only for simulation
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -46,15 +45,11 @@ entity aduh_quad_scope is
);
end aduh_quad_scope;
-
architecture beh of aduh_quad_scope is
-
constant c_wideband_factor : natural := g_ai.rx_factor * g_ai.dd_factor; -- Wideband rate factor = 4 for dp_clk is 200 MHz frequency and sample frequency Fs is 800 MHz
signal dp_sosi_arr : t_dp_sosi_arr(0 to g_ai.nof_sp - 1); -- = DP [3:0] = ADU Signal Paths [D,C,B,A]
-
begin
-
-- Reverse wire ADUH range [0:3] = A,B,C,D to DP [3:0] range
rewire : for I in 0 to g_ai.nof_sp - 1 generate
dp_sosi_arr(I) <= sp_sosi_arr(I);
@@ -77,5 +72,4 @@ begin
-- Streaming samples
sp_sosi_arr => dp_sosi_arr -- = [3:0] = Signal Paths [D,C,B,A]
);
-
end beh;
diff --git a/libraries/io/aduh/src/vhdl/aduh_verify.vhd b/libraries/io/aduh/src/vhdl/aduh_verify.vhd
index 7f5e88362546591d175c3a9720f3d72ea6a66848..b198cf47acfbe6a96e80d3d7cb69166baee1b0db 100644
--- a/libraries/io/aduh/src/vhdl/aduh_verify.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_verify.vhd
@@ -26,7 +26,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
-
-- Purpose: Verify the adc08d1020 test pattern on ADU for one signal path
-- Description:
-- The adc08d1020 has two ADCs I and Q, so it outputs two signal paths. Both
@@ -95,7 +94,6 @@ use dp_lib.dp_stream_pkg.all;
-- words (i.e. 8 symbols of the 10) are sufficient to know the next test
-- pattern data word. This is implemented by func_tp_seq in aduh_verify_bit.
-
entity aduh_verify is
generic (
g_symbol_w : natural := 8; -- Fixed
@@ -116,9 +114,7 @@ entity aduh_verify is
);
end aduh_verify;
-
architecture rtl of aduh_verify is
-
constant c_tp_symbol : t_slv_8_arr(0 to 1) := (X"02", X"01"); -- = (I, Q), use patter_sel to select
type t_nibble_arr is array (integer range <>) of std_logic_vector(0 to g_nof_symbols_per_data - 1); -- here use index [0:3] for the big endian nibbles
@@ -136,9 +132,7 @@ architecture rtl of aduh_verify is
signal nxt_in_symb_err : std_logic;
signal in_bits : t_nibble_arr(g_symbol_w - 1 downto 0);
signal nxt_in_bits : t_nibble_arr(g_symbol_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- 1) Prepare the nibble (width g_nof_symbols_per_data) streams for:
-- . the aggregate symbol bit (in_symb)
diff --git a/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd b/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd
index b2895fecc1c93292a158e3473789e27931e40eef..92b1cb9eca414554815d2ce222bdeb70915ff5cc 100644
--- a/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd
+++ b/libraries/io/aduh/src/vhdl/aduh_verify_bit.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
-- Purpose: Verify the adc08d1020 test pattern 0 1 0 0 1 1 0 0 1 0 per bit
-- Description:
-- Used in aduh_verify, see there for explanation
@@ -50,9 +49,7 @@ entity aduh_verify_bit is
);
end aduh_verify_bit;
-
architecture rtl of aduh_verify_bit is
-
constant c_nof_init : natural := 2; -- need two dat words to initialize the ref_dat
type t_state is (s_init, s_verify);
@@ -87,9 +84,7 @@ architecture rtl of aduh_verify_bit is
signal nxt_verify_res : std_logic;
signal i_verify_res_val : std_logic;
signal nxt_verify_res_val : std_logic;
-
begin
-
verify_res <= i_verify_res;
verify_res_val <= i_verify_res_val;
@@ -112,7 +107,6 @@ begin
end if;
end process;
-
p_state : process(ref_dat, prev_ref_dat, init_done, i_verify_res, i_verify_res_val, state, in_val, in_dat_err, in_dat, verify_res_ack)
begin
nxt_ref_dat <= ref_dat;
@@ -158,5 +152,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd.vhd
index 141ef15e05fe5df6d7acaffbfa7839788d2373f4..5fe812727c8326a2a0463d2438331509d4bd6e66 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd.vhd
@@ -105,9 +105,7 @@ entity lvdsh_dd is
);
end lvdsh_dd;
-
architecture str of lvdsh_dd is
-
constant c_rx_fifo_lsusedw_w : natural := true_log2(g_rx_factor); -- nof least significant bits of wrusedw that are skipped for rdusedw due to parallelization by g_rx_factor
constant c_rx_fifo_rdusedw_w : natural := ceil_log2(g_rx_fifo_size);
constant c_rx_fifo_wrusedw_w : natural := c_rx_fifo_rdusedw_w + c_rx_fifo_lsusedw_w;
@@ -146,9 +144,7 @@ architecture str of lvdsh_dd is
-- Rx clock domain (rx_clk = rd_clk) for DSP
signal rx_fifo_rd_req : std_logic;
signal rx_fifo_rd_dat : std_logic_vector(rx_dat'range);
-
begin
-
-----------------------------------------------------------------------------
-- Optional input buffer delay control via generic
-----------------------------------------------------------------------------
@@ -177,7 +173,6 @@ begin
in_dly <= in_vec;
end generate;
-
-----------------------------------------------------------------------------
-- Register double data rate input data
-----------------------------------------------------------------------------
@@ -196,7 +191,6 @@ begin
out_dat_lo => wr_dat_lo
);
-
-----------------------------------------------------------------------------
-- Reset in_clk from rx_clk domain
-----------------------------------------------------------------------------
@@ -219,7 +213,6 @@ begin
in_clk_rst <= i_in_clk_rst(0);
-
-----------------------------------------------------------------------------
-- Register release of dc_fifo_rst into the wr_clk domain with 'fixed' delay
-----------------------------------------------------------------------------
@@ -241,7 +234,6 @@ begin
out_cap => wr_fifo_rst
);
-
-----------------------------------------------------------------------------
-- Register wrusedw into the rd_clk domain with 'fixed' delay
-----------------------------------------------------------------------------
@@ -269,7 +261,6 @@ begin
out_cap => rx_fifo_rdusedw
);
-
------------------------------------------------------------------------------
-- Output direct at input clock rate and double width
------------------------------------------------------------------------------
@@ -280,7 +271,6 @@ begin
out_dat_hi <= wr_dat_hi;
out_dat_lo <= wr_dat_lo;
-
------------------------------------------------------------------------------
-- Output via FIFO at same clock rate or at lower clock rate in rx_clk domain
------------------------------------------------------------------------------
@@ -300,7 +290,6 @@ begin
out_dat => fifo_wr_dat
);
-
-- Input FIFO dual clock lock control
u_fifo_dc_lock_control : entity common_lib.common_fifo_dc_lock_control
generic map (
@@ -325,7 +314,6 @@ begin
dc_stable_ack => rx_stable_ack
);
-
-- No need to check on fifo_wr_ful for fifo_wr_req, because wr_init in common_fifo_dc* takes care that fifo_wr_req is only passed on after fifo_wr_ful went low after reset release.
fifo_wr_req <= '1';
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
index a52504ef41f4dc0452381bb185a3b763d99c59e6..66abbf9d9fb7bc899413b3f570e7c29f346ba432 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4.vhd
@@ -143,9 +143,7 @@ entity lvdsh_dd_phs4 is
);
end lvdsh_dd_phs4;
-
architecture str of lvdsh_dd_phs4 is
-
constant c_word_align_en : boolean := true;
constant c_dd_factor : natural := 2; -- fixed double data rate factor
@@ -314,9 +312,7 @@ architecture str of lvdsh_dd_phs4 is
signal wb_roundtrip_expected : std_logic;
signal wb_roundtrip_lock : std_logic;
signal wb_roundtrip_stable : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- Reset input section when lock is lost
------------------------------------------------------------------------------
@@ -448,7 +444,6 @@ begin
nxt_r_dp.wb_sync <= '1' when wb_sync_cap = '1' and r_dp.wb_sync_cap = '0' else '0';
-
------------------------------------------------------------------------------
-- Detect and align to the dp_clk phase
------------------------------------------------------------------------------
@@ -748,7 +743,6 @@ begin
end if;
end if;
end if;
-
end if;
-- Course check roundtrip latency and FIFO fill level at any time
@@ -766,7 +760,6 @@ begin
-- Monitor fifo_rdusedw, use >min and <max instead of >=min and <=max to over constrain it compared to the checks in p_dp_word_lock
dp_fifo_fill_lock <= '1' when unsigned(fifo_rdusedw) > c_wb_fifo_fill_min and unsigned(fifo_rdusedw) < c_wb_fifo_fill_max else '0';
-
------------------------------------------------------------------------------
-- Monitor the dp_clk phase alignment
------------------------------------------------------------------------------
@@ -865,7 +858,6 @@ begin
dout => in_maintain_phs
);
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -913,5 +905,4 @@ begin
r_dp <= nxt_r_dp;
end if;
end process;
-
end str;
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd
index 70a509c0ab277aa4bd54d0f22e03672f747e8a9d..ac360a443eb4f34d7929ed05be2ef3956f1bcbc7 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_phs4_align.vhd
@@ -66,9 +66,7 @@ entity lvdsh_dd_phs4_align is
);
end lvdsh_dd_phs4_align;
-
architecture str of lvdsh_dd_phs4_align is
-
constant c_ref_pipeline : natural := 1; -- need pipeline to achieve 400 MHz when g_nof_dp_phs_clk=8
constant c_align_pipeline : natural := 1; -- use pipeline to achieve 400 MHz
constant c_offset_delay_len : integer := c_ref_pipeline + c_align_pipeline; -- = 1+1
@@ -142,9 +140,7 @@ architecture str of lvdsh_dd_phs4_align is
signal nxt_r : t_in_reg;
signal dd_phs_detected_ok : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- Detect the dp_phs_clk reference
------------------------------------------------------------------------------
@@ -271,7 +267,6 @@ begin
nxt_r.sync_r <= '0' when r.sync_init = '1' else sync_r;
nxt_r.sync_f <= '0' when r.sync_init = '1' else sync_f;
-
------------------------------------------------------------------------------
-- Adjust single sample phase offset
------------------------------------------------------------------------------
@@ -360,7 +355,6 @@ begin
nxt_r.dd_phs_locked <= '0' when dd_phs_detected_ok = '0' else
'1' when dd_phs_detected_ok = '1' and r.dd_sync = "0000" else r.dd_phs_locked;
-
------------------------------------------------------------------------------
-- Output
------------------------------------------------------------------------------
@@ -414,5 +408,4 @@ begin
r <= nxt_r;
end if;
end process;
-
end str;
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd b/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
index 8039b49dd1e9ca17a8f171df1b009f240891ab55..23773da0a6501691d47ea9729e3fdfc2a58d168b 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_dd_wb4.vhd
@@ -104,9 +104,7 @@ entity lvdsh_dd_wb4 is
);
end lvdsh_dd_wb4;
-
architecture str of lvdsh_dd_wb4 is
-
-- Debug constants for development only, default FALSE for functional
constant c_use_dbg_dat : boolean := false;
constant c_swap_in_hi_lo : boolean := false;
@@ -196,9 +194,7 @@ architecture str of lvdsh_dd_wb4 is
signal dd_phase : std_logic;
signal prev_dd_phase : std_logic;
signal dd_phase_det : std_logic;
-
begin
-
-- Map outputs
in_clk_rst <= i_in_clk_rst(0) when g_use_in_clk_rst = true else '0';
@@ -281,6 +277,7 @@ begin
gen_hw : if g_sim = false generate
in_rst <= in_rst_cap;
end generate;
+
gen_sim : if g_sim = true generate
-- Model in_clk to dp_clk divide by 2 uncertainty by delaying the in_rst one in_clk cycle in case g_sim_phase is even
gen_even : if g_sim_phase = 0 or g_sim_phase = 1 generate in_rst <= in_rst_cap when rising_edge(in_clk); end generate;
@@ -586,5 +583,4 @@ begin
in_dat_lo => dp_in_clk_rst,
out_dat => i_in_clk_rst
);
-
end str;
diff --git a/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd b/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd
index 7bfe9c479f16e96dca9d829840054b8753b0e3c2..c4d13dbe00914037cbe5a6482969102c55a49d9d 100644
--- a/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd
+++ b/libraries/io/aduh/src/vhdl/lvdsh_pll.vhd
@@ -99,9 +99,7 @@ entity lvdsh_pll is
);
end lvdsh_pll;
-
architecture rtl of lvdsh_pll is
-
-- Default use c_use_dp_clk_for_cda_reset is TRUE to use dp_clk to reset the
-- CDA to avoid g_deser_factor lvds_clk divider phase uncertainty. Else use
-- rx_clk for investigation purposes to try whether lvds_clk divider phase
@@ -155,9 +153,7 @@ architecture rtl of lvdsh_pll is
signal rx_dat : std_logic_vector(c_rx_dat_w - 1 downto 0);
signal rx_val : std_logic;
signal nxt_rx_val : std_logic;
-
begin
-
assert g_use_ddio = false
report "lvdsh_pll.vhd: LVDS Rx using DDIO without PLL is not supported yet" severity FAILURE;
@@ -226,7 +222,6 @@ begin
---------------------------------------------------------------------------
no_dpa : if g_use_dpa = false generate
-
u_lvds_rx : entity work.lvds_rx
generic map (
g_lvds_w => g_lvds_w,
@@ -247,7 +242,6 @@ begin
);
nxt_rx_eye_locked <= rx_pll_locked;
-
end generate; -- no_dpa
---------------------------------------------------------------------------
@@ -255,7 +249,6 @@ begin
---------------------------------------------------------------------------
gen_dpa : if g_use_dpa = true generate
-
u_lvds_rx_dpa : entity work.lvds_rx_dpa
generic map (
g_lvds_w => g_lvds_w,
@@ -305,7 +298,6 @@ begin
);
rx_fifo_reset_slv <= (others => rx_fifo_reset);
-
end generate; -- gen_dpa
p_rx_dpa_reg : process(dp_pll_reset, rx_clk)
@@ -319,7 +311,6 @@ begin
end if;
end process;
-
---------------------------------------------------------------------------
-- Apply Channel Data Alignment (CDA)
---------------------------------------------------------------------------
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_monitor.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_monitor.vhd
index 9b9453500a0e1e54bd0817888e90fb433a132569..7596ed7d3f238130bb4313f31be3c65f0afd51c1 100644
--- a/libraries/io/aduh/src/vhdl/mms_aduh_monitor.vhd
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_monitor.vhd
@@ -60,16 +60,12 @@ entity mms_aduh_monitor is
);
end mms_aduh_monitor;
-
architecture str of mms_aduh_monitor is
-
-- Monitor outputs
signal mon_mean_sum : std_logic_vector(c_longword_w - 1 downto 0); -- use fixed 64 bit sum width
signal mon_power_sum : std_logic_vector(c_longword_w - 1 downto 0); -- use fixed 64 bit sum width
signal mon_sync : std_logic; -- at the mon_sync there are new mean_sum and pwr_sum statistics available
-
begin
-
u_mm_reg : entity work.aduh_monitor_reg
generic map (
g_cross_clock_domain => g_cross_clock_domain
@@ -117,5 +113,4 @@ begin
stat_pwr_sum => mon_power_sum,
stat_sync => mon_sync
);
-
end str;
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
index 97576b4f5cb8ba2776ad0ce53906ff2a2cb0998e..e3407f76de1905261e1e7ba7c5529cf9cdceb7ec 100644
--- a/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_monitor_arr.vhd
@@ -58,9 +58,7 @@ entity mms_aduh_monitor_arr is
);
end mms_aduh_monitor_arr;
-
architecture str of mms_aduh_monitor_arr is
-
constant c_reg_adr_w : natural := 2;
constant c_buf_adr_w : natural := ceil_log2(g_buffer_nof_symbols);
@@ -68,10 +66,7 @@ architecture str of mms_aduh_monitor_arr is
signal reg_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
signal buf_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal buf_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
-
-
begin
-
u_common_mem_mux_reg : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
diff --git a/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd b/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
index 8132cd46f7dcf3f6d24478e0ef7b86215d5efdcc..fa266c8ac29c8aaf567413f4060699f6eb5af014 100644
--- a/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
+++ b/libraries/io/aduh/src/vhdl/mms_aduh_quad.vhd
@@ -22,7 +22,6 @@
-- Purpose: Capture input from four ADC [A,B,C,D] and provide MM slave read
-- only register for aduh_quad
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -70,9 +69,7 @@ entity mms_aduh_quad is
);
end mms_aduh_quad;
-
architecture str of mms_aduh_quad is
-
signal aduh_ab_status : std_logic_vector(c_word_w - 1 downto 0);
signal aduh_ab_locked : std_logic;
signal aduh_ab_stable : std_logic;
@@ -88,9 +85,7 @@ architecture str of mms_aduh_quad is
signal aduh_verify_res : t_slv_32_arr(0 to g_ai.nof_sp - 1); -- [8,7:0]
signal aduh_verify_res_val : std_logic_vector(0 to g_ai.nof_sp - 1);
signal aduh_verify_res_ack : std_logic_vector(0 to g_ai.nof_sp - 1);
-
begin
-
-----------------------------------------------------------------------------
-- MM control register for the data input modules
-----------------------------------------------------------------------------
@@ -189,5 +184,4 @@ begin
aduh_verify_res_val => aduh_verify_res_val,
aduh_verify_res_ack => aduh_verify_res_ack
);
-
end str;
diff --git a/libraries/io/aduh/tb/vhdl/adc08d1020.vhd b/libraries/io/aduh/tb/vhdl/adc08d1020.vhd
index 8963c1089297840a0b3cb4646a541c73aab7419e..0aa985cab26f1f293e946da78a0637df7c68268b 100644
--- a/libraries/io/aduh/tb/vhdl/adc08d1020.vhd
+++ b/libraries/io/aduh/tb/vhdl/adc08d1020.vhd
@@ -57,9 +57,7 @@ entity adc08d1020 is
);
end adc08d1020;
-
architecture beh of adc08d1020 is
-
constant c_nof_adc : natural := 2; -- for AI and AQ
type t_adc_dat_arr is array (integer range <>) of std_logic_vector(7 downto 0);
@@ -71,9 +69,7 @@ architecture beh of adc08d1020 is
signal dclk_dis : std_logic := '0';
signal ddr_clk : std_logic := sel_a_b(g_dclk_init_phase, '1', '0');
-
begin
-
-- Sample the analogue I and Q input using the falling edge of the sample clock CLK
p_sample : process(CLK)
begin
@@ -133,5 +129,4 @@ begin
OVR <= transport adc_ovr after lvds_skew_ovr * 1 ps;
DCLK <= transport ddr_clk after lvds_skew_dclk * 1 ps;
-
end beh;
diff --git a/libraries/io/aduh/tb/vhdl/adu_half.vhd b/libraries/io/aduh/tb/vhdl/adu_half.vhd
index f5a3f435b2fca6ec11c08c6a2c6eac51835a143d..a63ad7e17f9d25078972eedb83daf8cc44f86e97 100644
--- a/libraries/io/aduh/tb/vhdl/adu_half.vhd
+++ b/libraries/io/aduh/tb/vhdl/adu_half.vhd
@@ -59,9 +59,7 @@ entity adu_half is
);
end adu_half;
-
architecture beh of adu_half is
-
constant c_dclk_rst_invert : boolean := false; -- Default FALSE because DCLK_RST on ADC is active high, use TRUE to model for a P/N cross
-- Model I2C slaves on the bus
@@ -93,9 +91,7 @@ architecture beh of adu_half is
signal adu_ctrl_3_modem_on : std_logic;
signal adu_atten_ctrl : std_logic_vector(5 downto 0);
-
begin
-
-- I port A and C wire default
DI <= DI_rewire;
@@ -175,5 +171,4 @@ begin
adu_ctrl_3_modem_on <= adu_ctrl(3);
adu_atten_ctrl <= iobank1(5 downto 0);
-
end beh;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
index 79513ec5e0c0ce0db74b932865d96d1e1b28144e..628f882bf3b38ba3b2398bd61efadc839893a14b 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_dd.vhd
@@ -36,7 +36,6 @@ entity tb_aduh_dd is
end tb_aduh_dd;
architecture tb of tb_aduh_dd is
-
-- ADU board
constant c_adc_w : natural := 8;
constant c_ana_diff : natural := 16; -- analogue offset value between the port A, B, C, D
@@ -135,9 +134,7 @@ architecture tb of tb_aduh_dd is
signal sl0 : std_logic := '0';
signal sl1 : std_logic := '1';
signal slv0 : std_logic_vector(1 downto 0) := "00";
-
begin
-
tb_end <= '0', '1' after 10 us;
-----------------------------------------------------------------------------
@@ -284,7 +281,6 @@ begin
verify_valid(3) <= dp_sosi_arr(3).valid;
gen_verify : for I in 0 to c_ai.nof_sp - 1 generate
-
-- Enable verify after first valid data and keep it enabled
proc_dp_verify_en(c_verify_delay, dp_rst, dp_clk, verify_valid(I), verify_en(I));
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd
index 2c6e3a86b411709716db89af9b258e6a2c1d56a9..b2f46d0e3544b6393b2e9b74044d0e50a9bfa078 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_mean_sum.vhd
@@ -29,7 +29,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
-- Usage:
-- > as 10
-- > run 1 us
@@ -39,7 +38,6 @@ use dp_lib.tb_dp_pkg.all;
-- . sum([16:31]) = 376
-- . sum([32:47]) = 632
-
entity tb_aduh_mean_sum is
generic (
g_nof_symbols_per_data : natural := 1; -- choose 1 or 4, nof symbols (= ADC samples) per data word
@@ -47,9 +45,7 @@ entity tb_aduh_mean_sum is
);
end tb_aduh_mean_sum;
-
architecture tb of tb_aduh_mean_sum is
-
constant clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -88,9 +84,7 @@ architecture tb of tb_aduh_mean_sum is
signal sum_sync : std_logic;
signal verify_done : std_logic := '0';
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 5;
@@ -181,5 +175,4 @@ begin
assert verify_done = '1' report "No sum output" severity ERROR;
wait;
end process;
-
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
index f92cba4f7166db99c917413fab027d5d4ad597ee..ca47377b5db52ab8045708d26ccdb18e57965c0c 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_pll.vhd
@@ -31,7 +31,6 @@ entity tb_aduh_pll is
end tb_aduh_pll;
architecture tb of tb_aduh_pll is
-
-- Conclusion from the c_model_rx_clk_* investigations:
-- . It appears that it is not possible to avoid the DCLK->rx_clk divide by 2
-- phase uncertainty by releasing the CDA reset in the dp-clk domain.
@@ -163,9 +162,7 @@ architecture tb of tb_aduh_pll is
signal sl0 : std_logic := '0';
signal sl1 : std_logic := '1';
signal slv0 : std_logic_vector(0 downto 0) := "0";
-
begin
-
-----------------------------------------------------------------------------
-- ADU0 and ADU1 for BN port A,B and C,D
-----------------------------------------------------------------------------
@@ -315,7 +312,6 @@ begin
wait;
end process;
-
-----------------------------------------------------------------------------
-- DUT: ADUH with PLL
-----------------------------------------------------------------------------
@@ -356,7 +352,6 @@ begin
src_out => dp_sosi -- = [0:3] = ADC_BI ports [A,B,C,D]
);
-
-----------------------------------------------------------------------------
-- Verify dp_sosi
-- . verify that there is valid data, i.e. that the test has run at all
@@ -405,5 +400,4 @@ begin
end if;
end process;
end generate; -- gen_verify_alignment
-
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd
index 67e348fa56b0b7ce699f5e6bfa825adb6a23ce3f..05a46a4529b24f42ef5d771d42522302c4523a06 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_power_sum.vhd
@@ -29,7 +29,6 @@ use common_lib.common_lfsr_sequences_pkg.all;
use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
-
-- Usage:
-- > as 10
-- > run 1 us
@@ -46,9 +45,7 @@ entity tb_aduh_power_sum is
);
end tb_aduh_power_sum;
-
architecture tb of tb_aduh_power_sum is
-
constant clk_period : time := 10 ns;
constant c_rl : natural := 1;
@@ -85,9 +82,7 @@ architecture tb of tb_aduh_power_sum is
signal pwr_sum_sync : std_logic;
signal verify_done : std_logic := '0';
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 5;
@@ -179,5 +174,4 @@ begin
assert verify_done = '1' report "No power sum output" severity ERROR;
wait;
end process;
-
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd b/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
index 904dbb3f90f8223f97ffdcb0047f752f33ac9914..6140c2af10c0223f8835cb838f58141ca5b1965a 100644
--- a/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_aduh_verify.vhd
@@ -35,7 +35,6 @@ entity tb_aduh_verify is
end tb_aduh_verify;
architecture tb of tb_aduh_verify is
-
--TYPE t_c_aduh_dd_ai IS RECORD
-- nof_sp : NATURAL; -- = 4
-- nof_adu : NATURAL; -- = 2
@@ -93,9 +92,7 @@ architecture tb of tb_aduh_verify is
signal b_verify_res : std_logic_vector(c_ai.port_w downto 0);
signal b_verify_res_val : std_logic;
signal b_verify_res_ack : std_logic;
-
begin
-
-----------------------------------------------------------------------------
-- ADUH_VERIFY port A and B
-----------------------------------------------------------------------------
@@ -202,7 +199,6 @@ begin
test_pattern_en => test_pattern_en
);
-
-----------------------------------------------------------------------------
-- ADUH_DD using only port A,B
-----------------------------------------------------------------------------
@@ -256,5 +252,4 @@ begin
-- . Streaming
src_out_arr => aduh_sosi_arr
);
-
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd
index 30187c3d7672145243b414998fcb9f1f93002c09..86a3bdb9b0adab0c1e1f28f77ef444e82368945e 100644
--- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd.vhd
@@ -32,7 +32,6 @@ end tb_lvdsh_dd;
-- > run 10 us
architecture tb of tb_lvdsh_dd is
-
constant c_config_clk_period : time := 10 ns;
constant c_sp_clk_period : time := 1250 ps; -- 800 MSps sample clock
constant c_in_clk_period : time := c_sp_clk_period * 2; -- 400 MHz double data rate clock
@@ -71,9 +70,7 @@ architecture tb of tb_lvdsh_dd is
signal rx_locked : std_logic;
signal rx_stable : std_logic;
signal rx_stable_ack : std_logic := '0';
-
begin
-
config_clk <= not config_clk or tb_end after c_config_clk_period / 2;
config_rst <= '1', '0' after c_config_clk_period * 7;
@@ -138,5 +135,4 @@ begin
rx_stable => rx_stable,
rx_stable_ack => rx_stable_ack
);
-
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd
index cad4354731a0336a1b67f69da55cdaeaf9220d1a..c40e2ec4f3215b1909a805446cd450a995bd2510 100644
--- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_phs4.vhd
@@ -70,7 +70,6 @@ entity tb_lvdsh_dd_phs4 is
end tb_lvdsh_dd_phs4;
architecture tb of tb_lvdsh_dd_phs4 is
-
constant c_dd_factor : natural := 2;
constant c_rx_factor : natural := 2;
constant c_wb_factor : natural := c_dd_factor * c_rx_factor;
@@ -143,9 +142,7 @@ architecture tb of tb_lvdsh_dd_phs4 is
signal dp_word_locked : std_logic;
signal dp_word_stable : std_logic;
signal dp_word_stable_ack : std_logic;
-
begin
-
-- ADU clocking with optional on/off and drift
adc_s_clk <= not adc_s_clk or tb_end after c_adc_s_clk_period / 2;
adc_d_clk <= not adc_d_clk when rising_edge(adc_s_clk);
@@ -297,5 +294,4 @@ begin
-- Scope output samples
out_dat => dp_sample_dat
);
-
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd
index 68151bd61577bf755fe166bd78a43b4f054c5cb7..83c07b0cabdc84ea95aed6bb499fe2e12803d7c5 100644
--- a/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_lvdsh_dd_wb4.vhd
@@ -40,7 +40,6 @@ entity tb_lvdsh_dd_wb4 is
end tb_lvdsh_dd_wb4;
architecture tb of tb_lvdsh_dd_wb4 is
-
constant c_sim : boolean := true;
constant c_tb_duration : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 1000, 10); -- nof tb intervals for tb duration
constant c_tb_init : natural := sel_a_b(g_dclk_drift /= 0 ps or g_dclk_offon = true, 50, 5); -- nof tb intervals for tb init before verify_en
@@ -102,9 +101,7 @@ architecture tb of tb_lvdsh_dd_wb4 is
signal dp_locked : std_logic;
signal dp_stable : std_logic;
signal dp_stable_ack : std_logic;
-
begin
-
d_clk_off <= not d_clk_off or tb_end after c_offon_interval * c_dp_clk_period when g_dclk_offon = true;
s_clk <= not s_clk or tb_end after c_sclk_period / 2;
@@ -226,5 +223,4 @@ begin
-- Scope output samples
out_dat => dp_sample_dat
);
-
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd b/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
index b193305aceb518e3bcde1db99e3eec81f0b667bc..e3afe02e4dd069485bda88d42e5aa2c83254ca63 100644
--- a/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_mms_aduh_quad.vhd
@@ -38,7 +38,6 @@ entity tb_mms_aduh_quad is
end tb_mms_aduh_quad;
architecture tb of tb_mms_aduh_quad is
-
--TYPE t_c_aduh_dd_ai IS RECORD
-- nof_sp : NATURAL; -- = 4
-- nof_adu : NATURAL; -- = 2
@@ -125,9 +124,7 @@ architecture tb of tb_mms_aduh_quad is
signal test_pattern_en : std_logic;
signal state : string(1 to 8) := "INIT ";
-
begin
-
dp_rst <= '1', '0' after c_dp_clk_period * 7;
dp_clk <= (not dp_clk) or tb_end after c_dp_clk_period / 2;
@@ -227,7 +224,6 @@ begin
proc_common_wait_some_cycles(mm_clk, 1);
proc_verify_bist_expect_errors(aduh_a_verify, aduh_b_verify, aduh_c_verify, aduh_d_verify);
-
----------------------------------------------------------------------------
-- Expect aduh BIST OK for A, B, C, D
----------------------------------------------------------------------------
@@ -245,7 +241,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- ADUH_QUAD for ADC port [ABCD]
------------------------------------------------------------------------------
@@ -303,7 +298,6 @@ begin
sp_sosi_arr => aduh_sosi_arr
);
-
------------------------------------------------------------------------------
-- ADU-[AB, CD] ADC ports both in test pattern mode
------------------------------------------------------------------------------
@@ -334,5 +328,4 @@ begin
test_pattern_en => test_pattern_en
);
-
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd b/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
index 99ac446f65b0c4b001a50cd699ed7764bf1ff5f1..17cf28b17d78790290144ff56dc9bce813acbad8 100644
--- a/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_phs4.vhd
@@ -23,18 +23,13 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_lvdsh_dd_phs4 is
end tb_tb_lvdsh_dd_phs4;
-
architecture tb of tb_tb_lvdsh_dd_phs4 is
-
constant c_dp_phs_clk_period : natural := 32;
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- > as 3
-- > run -all
@@ -50,5 +45,4 @@ begin
u_phase_1 : entity work.tb_lvdsh_dd_phs4 generic map (0 ps, false, c_dp_phs_clk_period, 1, 16#FF#, false, 1);
u_phase_2 : entity work.tb_lvdsh_dd_phs4 generic map (0 ps, false, c_dp_phs_clk_period, 1, 16#FF#, false, 2);
u_phase_3 : entity work.tb_lvdsh_dd_phs4 generic map (0 ps, false, c_dp_phs_clk_period, 1, 16#FF#, false, 3);
-
end tb;
diff --git a/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd b/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
index 5e915300d3a9f4581a97e3d9f5385d9322ba4730..b8a9829f2f99b0a06dca746401372971382b5306 100644
--- a/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
+++ b/libraries/io/aduh/tb/vhdl/tb_tb_lvdsh_dd_wb4.vhd
@@ -23,15 +23,12 @@
library IEEE;
use IEEE.std_logic_1164.all;
-
entity tb_tb_lvdsh_dd_wb4 is
end tb_tb_lvdsh_dd_wb4;
-
architecture tb of tb_tb_lvdsh_dd_wb4 is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- > as 3
-- > run -all
@@ -43,5 +40,4 @@ begin
u_phase_1 : entity work.tb_lvdsh_dd_wb4 generic map (0 ps, false, 1);
u_phase_2 : entity work.tb_lvdsh_dd_wb4 generic map (0 ps, false, 2);
u_phase_3 : entity work.tb_lvdsh_dd_wb4 generic map (0 ps, false, 3);
-
end tb;
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index b0545127e23d3fa9fa8c59497c125a4d260072f2..354f571a7053fc7debabc577e870572ad5762111 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -227,9 +227,7 @@ entity io_ddr is
);
end io_ddr;
-
architecture str of io_ddr is
-
constant c_wr_use_sync : boolean := sel_a_b(g_wr_flush_mode = "SYN", true, false);
constant c_wr_use_ctrl : boolean := sel_a_b(g_wr_flush_mode = "SOP", true, false);
constant c_wr_fifo_use_ctrl : boolean := c_wr_use_sync or c_wr_use_ctrl;
@@ -286,9 +284,7 @@ architecture str of io_ddr is
signal ctlr_rst_out_i : std_logic;
signal mm_reg_io_ddr : std_logic_vector(c_mem_reg_nof_data * c_mem_reg_dat_w - 1 downto 0);
-
begin
-
ctlr_wr_flush_en_o <= ctlr_wr_flush_en;
u_io_ddr_cross_domain : entity work.io_ddr_cross_domain
@@ -555,6 +551,4 @@ begin
in_reg => mm_reg_io_ddr,
out_reg => open
);
-
end str;
-
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd b/libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd
index 79117877803dd4e657db6001dc5606bbc0b2497d..b7b98bd5c279e5162a91e80218b2e0bb2f344c61 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_cross_domain.vhd
@@ -68,14 +68,10 @@ entity io_ddr_cross_domain is
);
end io_ddr_cross_domain;
-
architecture str of io_ddr_cross_domain is
-
signal dvr_en_busy : std_logic;
signal new_dvr_done : std_logic;
-
begin
-
no_cross : if g_cross_domain = false generate
-- dvr_clk --> ctlr_clk
ctlr_dvr_en <= dvr_en;
@@ -137,7 +133,6 @@ begin
-- Ensure previous dvr_done goes low after new dvr_en
dvr_done <= new_dvr_done and not dvr_en_busy;
-
end generate;
end str;
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
index 51f97ed7839e65b59a768c076ccf2a844addcea9..f6d57ea25d3390821ac3d43f6829d5a24689f686 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver.vhd
@@ -55,7 +55,6 @@
-- run full if the rd data width is smaller than the ctlr data width and/or
-- if the rd side can notread on every rd_clk cycle.
-
library IEEE, tech_ddr_lib, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -86,9 +85,7 @@ entity io_ddr_driver is
);
end io_ddr_driver;
-
architecture str of io_ddr_driver is
-
constant c_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr);
type t_state_enum is (s_init, s_idle, s_wait, s_rd_request, s_wr_request, s_wr_burst);
@@ -117,9 +114,7 @@ architecture str of io_ddr_driver is
signal nxt_address_cnt : std_logic_vector(c_ctlr_address_w - 1 downto 0);
signal address_cnt_is_0 : std_logic;
signal nxt_address_cnt_is_0 : std_logic;
-
begin
-
-- Map original dvr interface signals to t_mem_ctlr_mosi/miso
dvr_miso.done <= dvr_done; -- Requested wr or rd sequence is done
dvr_en <= dvr_mosi.burstbegin;
@@ -272,9 +267,6 @@ begin
if ctlr_miso.done = '1' then
nxt_state <= s_idle; -- and assert dvr_done when in s_idle to indicate ctlr_miso.done
end if;
-
end case;
end process;
-
end str;
-
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
index 3012e51ac83b20f924d7ce51a103d54286e5cc1b..5300dd78d81f2e32ff1c8695bca041c463c25c64 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_driver_flush_ctrl.vhd
@@ -65,9 +65,7 @@ entity io_ddr_driver_flush_ctrl is
);
end io_ddr_driver_flush_ctrl;
-
architecture str of io_ddr_driver_flush_ctrl is
-
constant c_channel_w : natural := ceil_log2(g_nof_channels);
type t_state is (s_idle, s_flush, s_stop);
@@ -80,9 +78,7 @@ architecture str of io_ddr_driver_flush_ctrl is
signal flush_dis : std_logic;
signal nxt_ctlr_wr_flush_en : std_logic;
-
begin
-
-- Flush disable control
no_channel: if g_use_channel = false generate
gen_valid : if g_mode = "VAL" generate flush_dis <= ctlr_wr_sosi.valid; end generate;
@@ -135,6 +131,4 @@ begin
end if;
end case;
end process;
-
end str;
-
diff --git a/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd b/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
index 1b4d182327943f12ec090f560f8f239421ffe7df..c86a29d671dca2f7c9d94dbf23284a47054fda00 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr_reg.vhd
@@ -55,7 +55,6 @@ use common_lib.common_pkg.all;
use common_lib.common_mem_pkg.all;
use diag_lib.diag_pkg.all;
-
entity io_ddr_reg is
port (
-- Clocks and reset
@@ -72,9 +71,7 @@ entity io_ddr_reg is
);
end io_ddr_reg;
-
architecture rtl of io_ddr_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(8),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
@@ -82,9 +79,7 @@ architecture rtl of io_ddr_reg is
init_sl => '0');
signal i_dvr_mosi : t_mem_ctlr_mosi;
-
begin
-
dvr_mosi <= i_dvr_mosi;
------------------------------------------------------------------------------
@@ -140,6 +135,4 @@ begin
end if;
end if;
end process;
-
end rtl;
-
diff --git a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
index 15023591033d2d76ef03f5abd3b63e5dd8c8404b..b2d2043afdd1c1fef515e5f5d9250e75369cd64f 100644
--- a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -95,17 +94,13 @@ entity mms_io_ddr is
);
end mms_io_ddr;
-
architecture str of mms_io_ddr is
-
signal mm_dvr_miso : t_mem_ctlr_miso;
signal mm_dvr_mosi : t_mem_ctlr_mosi;
signal reg_io_ddr_mosi_arr : t_mem_mosi_arr(1 downto 0);
signal reg_io_ddr_miso_arr : t_mem_miso_arr(1 downto 0);
-
begin
-
-- Combine the reg map of io_ddr and io_ddr_reg
u_common_mem_mux : entity common_lib.common_mem_mux
generic map (
@@ -204,6 +199,4 @@ begin
dvr_miso => mm_dvr_miso,
dvr_mosi => mm_dvr_mosi
);
-
end str;
-
diff --git a/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd b/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
index a87c6f05f21885a1a706f21d311779f91c92a37a..be2513f6b93f75347ec33acfea1a0e859227fcd5 100644
--- a/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
+++ b/libraries/io/ddr/src/vhdl/mms_io_ddr_diag.vhd
@@ -139,9 +139,7 @@ entity mms_io_ddr_diag is
);
end mms_io_ddr_diag;
-
architecture str of mms_io_ddr_diag is
-
constant c_io_wr_fifo_depth : natural := (g_dp_wr_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr); -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
constant c_io_rd_fifo_depth : natural := (g_dp_rd_fifo_depth * g_dp_data_w) / func_tech_ddr_ctlr_data_w(g_io_tech_ddr); -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
@@ -150,9 +148,7 @@ architecture str of mms_io_ddr_diag is
signal db_siso_arr : t_dp_siso_arr(0 downto 0) := (others => c_dp_siso_rdy); -- Default ready='1'
signal db_sosi_arr : t_dp_sosi_arr(0 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- IO_DDR
------------------------------------------------------------------------------
@@ -287,5 +283,4 @@ begin
-- ST interface
in_sosi_arr => db_sosi_arr
);
-
end str;
diff --git a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
index 8db1d40fbd4bc229be5c736a5e2fdecfd2b90dd0..912ae3b3eb5ccc6b9f54f6eea6ee3842351e523f 100644
--- a/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_io_ddr.vhd
@@ -66,7 +66,6 @@ entity tb_io_ddr is
end entity tb_io_ddr;
architecture str of tb_io_ddr is
-
-- Select DDR3 or DDR4 dependent on the technology and sim model
constant c_mem_ddr : t_c_tech_ddr := func_tech_sel_ddr(g_technology, g_tech_ddr3, g_tech_ddr4);
@@ -239,9 +238,7 @@ architecture str of tb_io_ddr is
signal phy4_in : t_tech_ddr4_phy_in;
signal phy4_io : t_tech_ddr4_phy_io;
signal phy4_ou : t_tech_ddr4_phy_ou;
-
begin
-
ctlr_ref_clk <= not ctlr_ref_clk or i_tb_end after c_ctlr_ref_clk_period / 2;
dvr_clk <= not dvr_clk or i_tb_end after g_dvr_clk_period / 2;
@@ -429,7 +426,6 @@ begin
end if;
end process;
-
-- Map original dvr interface signals to t_mem_ctlr_mosi/miso
dvr_done <= dvr_miso.done; -- Requested wr or rd sequence is done
dvr_mosi.burstbegin <= dvr_en;
@@ -520,7 +516,4 @@ begin
mem4_in => phy4_ou,
mem4_io => phy4_io
);
-
end architecture str;
-
-
diff --git a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
index c281a022b060e4e24f8389e95a9a4b85a91cc098..664d68451b79dc659ed4b483e4c3b1f15046c7b4 100644
--- a/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
+++ b/libraries/io/ddr/tb/vhdl/tb_tb_io_ddr.vhd
@@ -34,13 +34,10 @@ use technology_lib.technology_select_pkg.all;
use tech_ddr_lib.tech_ddr_pkg.all;
use common_lib.tb_common_pkg.all;
-
entity tb_tb_io_ddr is
end tb_tb_io_ddr;
-
architecture tb of tb_tb_io_ddr is
-
constant c_technology : natural := c_tech_select_default;
constant c_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
--CONSTANT c_tech_ddr4 : t_c_tech_ddr := c_tech_ddr4_4g_1600m;
@@ -50,9 +47,7 @@ architecture tb of tb_tb_io_ddr is
constant c_tb_end_vec : std_logic_vector(15 downto 0) := (others => '1');
signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
-
begin
-
-- g_sim_model : BOOLEAN := FALSE;
-- g_technology : NATURAL := c_tech_select_default;
-- g_tech_ddr3 : t_c_tech_ddr := c_tech_ddr3_4g_800m_master;
@@ -106,5 +101,4 @@ begin
report "Multi tb simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3.vhd b/libraries/io/ddr3/src/vhdl/ddr3.vhd
index 6bd368349beb1538b0948497dd23c7bf50746a8a..0798866d0fb50015b3fad9619f1ba5f6c357993a 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3.vhd
@@ -108,9 +108,7 @@ entity ddr3 is
);
end ddr3;
-
architecture str of ddr3 is
-
constant c_wr_fifo_depth : natural := g_wr_fifo_depth * (c_ddr3_ctlr_data_w / g_wr_data_w); -- Multiply fifo depth by the fifo's rd/wr width ratio to get write side depth
constant c_latency : natural := 1;
@@ -157,9 +155,7 @@ architecture str of ddr3 is
signal ctlr_tech_mosi : t_mem_ctlr_mosi;
signal ctlr_tech_miso : t_mem_ctlr_miso;
-
begin
-
dvr_done <= i_dvr_done;
ctlr_gen_clk <= i_ctlr_gen_clk;
@@ -324,7 +320,6 @@ begin
mm_reg_io_ddr <= RESIZE_UVEC(local_cal_fail & local_cal_success & i_ctlr_gen_rst & flush_ena & i_ctlr_rdy & i_ctlr_init_done, 32);
-
ser_term_ctrl_out <= term_ctrl_out.seriesterminationcontrol;
par_term_ctrl_out <= term_ctrl_out.parallelterminationcontrol;
term_ctrl_in.seriesterminationcontrol <= ser_term_ctrl_in;
@@ -344,7 +339,6 @@ begin
local_cal_success <= ctlr_tech_miso.cal_ok;
local_cal_fail <= ctlr_tech_miso.cal_fail;
-
u_tech_ddr : entity tech_ddr_lib.tech_ddr
generic map (
g_technology => c_tech_stratixiv,
@@ -372,6 +366,4 @@ begin
phy3_io => phy_io,
phy3_ou => phy_ou
);
-
end str;
-
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd b/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
index b7135dbf4fa5bc88f4d477c6ad46707193d41d57..77dc5117a99f21672b57d83657b4d3d2ab0bc5a5 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_driver.vhd
@@ -58,9 +58,7 @@ entity ddr3_driver is
);
end ddr3_driver;
-
architecture str of ddr3_driver is
-
constant c_chip_addr_w : natural := ceil_log2(g_ddr.cs_w); -- Chip sel lines converted to logical address
constant c_address_w : natural := c_chip_addr_w + g_ddr.ba_w + g_ddr.a_w + g_ddr.a_col_w + 1; -- 1 bit added to detect overflow
@@ -100,9 +98,7 @@ architecture str of ddr3_driver is
signal reg_addresses_rem : std_logic_vector(31 downto 0); -- nof words (on the user side interface) to rd/wr until end addr is reached
signal reg_wr_fifo_usedw : std_logic_vector(ceil_log2(g_wr_fifo_depth) - 1 downto 0); -- read side depth of the write FIFO
-
begin
-
ctlr_burst_size <= i_ctlr_burst_size;
dvr_done <= i_dvr_done;
@@ -260,10 +256,8 @@ begin
if ctlr_init_done = '1' then
nxt_state <= s_idle;
end if;
-
end case;
end process;
-
end_address <= RESIZE_UVEC( end_addr.chip & end_addr.bank & end_addr.row(g_ddr.a_w - 1 downto 0) & end_addr.column(g_ddr.a_col_w - 1 downto 0), c_address_w);
start_address <= RESIZE_UVEC(start_addr.chip & start_addr.bank & start_addr.row(g_ddr.a_w - 1 downto 0) & start_addr.column(g_ddr.a_col_w - 1 downto 0), c_address_w);
@@ -271,6 +265,4 @@ begin
cur_addr.bank( g_ddr.ba_w - 1 downto 0) <= cur_address( g_ddr.ba_w + g_ddr.a_w + g_ddr.a_col_w - 1 downto g_ddr.a_w + g_ddr.a_col_w);
cur_addr.row( g_ddr.a_w - 1 downto 0) <= cur_address( g_ddr.a_w + g_ddr.a_col_w - 1 downto g_ddr.a_col_w);
cur_addr.column(g_ddr.a_col_w - 1 downto 0) <= cur_address( g_ddr.a_col_w - 1 downto 0);
-
end str;
-
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd b/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
index d040135dd8f4eba23fa44827e1ff43efa4057c72..8f59eddac9f720d41848965ec3339d7760fb19ad 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_flush_ctrl.vhd
@@ -76,9 +76,7 @@ entity ddr3_flush_ctrl is
);
end ddr3_flush_ctrl;
-
architecture str of ddr3_flush_ctrl is
-
constant c_nof_channels : natural := sel_a_b(g_nof_channels = 0, 1, g_nof_channels);
constant c_channel_w : natural := ceil_log2(c_nof_channels);
@@ -88,9 +86,7 @@ architecture str of ddr3_flush_ctrl is
signal nxt_state : t_state;
signal flush_dis : std_logic;
-
begin
-
-- Flush ddr3 module's FIFO (keep sinking the stream but simply discard the
-- data) after reset to prevent ddr3 write fifo from filling up - which would
-- cause problems downstream (dp_mux uses two fifos that cannot be
@@ -150,6 +146,4 @@ begin
end if;
end case;
end process;
-
end str;
-
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index f3778c5dbc55c6c475567f7bac6ea48f331d14c1..9805ce05f447b20129cfd0ea6e91afebd082efab 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -25,7 +25,6 @@ use common_lib.common_pkg.all;
use IEEE.numeric_std.all;
package ddr3_pkg is
-
-- DDR3 (definitions similar as in ug_altmemphy.pdf)
type t_c_ddr3_phy is record
a_w : natural; -- = 16;
@@ -224,7 +223,6 @@ package ddr3_pkg is
);
end component;
-
component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en is
generic (
MEM_IF_ADDR_WIDTH : integer := 0;
@@ -275,6 +273,4 @@ package ddr3_pkg is
end ddr3_pkg;
package body ddr3_pkg is
-
end ddr3_pkg;
-
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd
index 6d8f60bbb43fa9e5ae2a56d5a46c47840419eeb3..6cefa51713fd98b935a4ba013ecbad71bd9ce535 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_reg.vhd
@@ -74,9 +74,7 @@ entity ddr3_reg is
);
end ddr3_reg;
-
architecture rtl of ddr3_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(7),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
@@ -95,9 +93,7 @@ architecture rtl of ddr3_reg is
signal mm_done : std_logic;
signal mm_init_done : std_logic;
signal mm_ctlr_rdy : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -266,6 +262,4 @@ begin
out_dat => st_start_address,
out_new => open
);
-
end rtl;
-
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
index da861d5828938c17f9eb728d31c5bb39ae115051..f73e223e0a9390c9a795c0dae746d1b2c4f72aa5 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_seq.vhd
@@ -50,9 +50,7 @@ entity ddr3_seq is
);
end ddr3_seq;
-
architecture rtl of ddr3_seq is
-
constant c_blocksize : positive := g_ddr3_seq.wr_nof_chunks * (g_ddr3_seq.wr_chunksize + g_ddr3_seq.gapsize);
constant c_page_size : positive := c_blocksize * g_ddr3_seq.nof_blocks;
constant c_nof_wr_access : positive := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.nof_blocks;
@@ -83,9 +81,7 @@ architecture rtl of ddr3_seq is
end record;
signal r, rin : reg_type;
-
begin
-
---------------------------------------------------------------
-- CHECK IF PROVIDED GENERICS ARE ALLOWED.
---------------------------------------------------------------
@@ -94,7 +90,6 @@ begin
p_comb : process(r, dp_rst, init_done, done, ctlr_rdy, sync_ok_in)
variable v : reg_type;
begin
-
v := r;
v.ddr3_en := '0';
@@ -197,7 +192,6 @@ begin
when others =>
v.state := s_idle;
-
end case;
if(dp_rst = '1') then
@@ -223,7 +217,6 @@ begin
end if;
rin <= v;
-
end process;
p_regs : process(dp_clk)
@@ -246,6 +239,4 @@ begin
start_addr.row(c_address_w - c_ddr3_phy.a_col_w - 1 downto 0) <= r.start_addr(c_address_w - 1 downto c_ddr3_phy.a_col_w);
end_addr.row(c_address_w - c_ddr3_phy.a_col_w - 1 downto 0) <= r.end_addr(c_address_w - 1 downto c_ddr3_phy.a_col_w);
end process;
-
end rtl;
-
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
index d3193d40a440531d1fabd5b144f69ce91ec1468a..1c6b86fceee59f6e3323959a2570408782acf5cf 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_transpose.vhd
@@ -84,9 +84,7 @@ entity ddr3_transpose is
);
end ddr3_transpose;
-
architecture str of ddr3_transpose is
-
constant c_min_fifo_size : positive := 256;
constant c_blocksize : positive := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize;
constant c_wr_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
@@ -139,9 +137,7 @@ architecture str of ddr3_transpose is
signal nxt_mon_nof_sop : std_logic_vector(c_cnt_sop_w - 1 downto 0);
signal sync_ok_in : std_logic;
signal sync_ok_out : std_logic;
-
begin
-
g_merge_in_complex : if g_use_complex = true generate
process(snk_in_arr)
begin
@@ -435,7 +431,4 @@ begin
end loop;
end process;
end generate;
-
end str;
-
-
diff --git a/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd b/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd
index 0da9163646e763bf4951248b9c7b133cb792aeb9..7d093d8240745146facb1811b6a369bbb1331649 100644
--- a/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/mms_ddr3.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -92,9 +91,7 @@ entity mms_ddr3 is
);
end mms_ddr3;
-
architecture str of mms_ddr3 is
-
signal i_ctlr_gen_rst : std_logic;
signal i_ctlr_gen_clk : std_logic;
@@ -109,9 +106,7 @@ architecture str of mms_ddr3 is
-- DDR3 controller status
signal ctlr_init_done : std_logic;
signal ctlr_rdy : std_logic;
-
begin
-
ctlr_gen_clk <= i_ctlr_gen_clk;
ctlr_gen_rst <= i_ctlr_gen_rst;
@@ -198,6 +193,4 @@ begin
st_init_done => ctlr_init_done,
st_ctlr_rdy => ctlr_rdy
);
-
end str;
-
diff --git a/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd b/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
index 68837dd3783e9afb7dbd1000d0e42000bd2dc978..a3f76a4de78e12b8cdd0a734f0819b34a3c7bb41 100644
--- a/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
+++ b/libraries/io/ddr3/src/vhdl/mms_ddr3_capture.vhd
@@ -79,9 +79,7 @@ entity mms_ddr3_capture is
);
end mms_ddr3_capture;
-
architecture str of mms_ddr3_capture is
-
signal rd_sosi : t_dp_sosi;
signal rd_siso : t_dp_siso;
@@ -89,9 +87,7 @@ architecture str of mms_ddr3_capture is
signal rd_rst : std_logic;
signal rd_fifo_usedw : std_logic_vector(ceil_log2(g_rd_fifo_depth * (c_ddr3_ctlr_data_w / g_rd_data_w) ) - 1 downto 0);
-
begin
-
u_mms_ddr3: entity work.mms_ddr3
generic map(
g_sim => g_sim,
@@ -162,7 +158,4 @@ begin
rd_usedw => rd_fifo_usedw
);
-
-
end str;
-
diff --git a/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd b/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
index 29aa4cd8a6f834d6c464701c459d63ec2e8b16ab..49cac0f0c209e2375bb3808fb67beb8a86fbc42b 100644
--- a/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
+++ b/libraries/io/ddr3/src/vhdl/seq_ddr3.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -73,9 +72,7 @@ entity seq_ddr3 is
);
end seq_ddr3;
-
architecture str of seq_ddr3 is
-
constant c_min_fifo_size : positive := 256;
constant c_blocksize : positive := g_ddr3_seq.wr_nof_chunks * g_ddr3_seq.wr_chunksize;
constant c_wr_fifo_depth : natural := sel_a_b(c_blocksize > c_min_fifo_size, c_blocksize, c_min_fifo_size); -- c_blocksize * 2;
@@ -96,9 +93,7 @@ architecture str of seq_ddr3 is
signal ctlr_init_done : std_logic;
signal ctlr_rdy : std_logic;
signal init_done_data_start : std_logic;
-
begin
-
ctlr_gen_clk <= i_ctlr_gen_clk;
ctlr_gen_rst <= i_ctlr_gen_rst;
@@ -184,6 +179,4 @@ begin
init_done => init_done_data_start,
ctlr_rdy => ctlr_rdy
);
-
end str;
-
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
index bef13d4b44d1f73cb7f167c8ae7e5d37eaa3f0c6..4c6005a9a84132cd378bb8e1c011ca4bf8ffc0dc 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
@@ -53,7 +53,6 @@ entity tb_ddr3 is
end entity tb_ddr3;
architecture str of tb_ddr3 is
-
constant c_phy : natural := 1; -- 0: ALTMEMPHY 1: UNIPHY_MASTER 2: UNIPHY_SLAVE
constant c_mts : natural := 800; -- Available options: 800 and 1066
@@ -104,9 +103,7 @@ architecture str of tb_ddr3 is
signal we_n : std_logic_vector(0 downto 0);
signal flush_ena : std_logic;
-
begin
-
ctlr_ref_clk <= not(ctlr_ref_clk) or tb_end after c_ctlr_ref_clk_per / 2;
ctlr_rst <= '0' after 100 ns;
@@ -188,7 +185,6 @@ begin
src_val_cnt(0) => src_val_cnt
);
-
gen_uphy_4g_model : if c_phy > 0 generate
u_4gb_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
generic map (
@@ -283,7 +279,4 @@ begin
phy_io => phy_io,
phy_in => phy_in
);
-
end architecture str;
-
-
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
index c24ad21b180648e5f78353de714614737b620be2..a9e1cb53c3872c3e5cddc1c6e95ae51db0e4dfe1 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -59,7 +58,6 @@ entity tb_ddr3_transpose is
end tb_ddr3_transpose;
architecture tb of tb_ddr3_transpose is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -162,7 +160,6 @@ architecture tb of tb_ddr3_transpose is
signal dvr_wr_not_rd : std_logic;
signal dvr_done : std_logic;
-
-- Signals to interface with the DDR3 memory model.
signal phy_in : t_tech_ddr3_phy_in;
signal phy_io : t_tech_ddr3_phy_io;
@@ -171,10 +168,7 @@ architecture tb of tb_ddr3_transpose is
signal ras_n : std_logic_vector(0 downto 0);
signal cas_n : std_logic_vector(0 downto 0);
signal we_n : std_logic_vector(0 downto 0);
-
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -404,5 +398,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
index bd49f696d4b67e1bc337ca9e1b07466ab03f097a..36e13b7c4385aabb52983a03d86ae9f6905b389e 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -50,7 +49,6 @@ entity tb_mms_ddr3 is
end tb_mms_ddr3;
architecture tb of tb_mms_ddr3 is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -146,7 +144,6 @@ architecture tb of tb_mms_ddr3 is
signal dvr_wr_not_rd : std_logic;
signal dvr_done : std_logic;
-
-- Signals to interface with the DDR3 memory model.
signal phy_in : t_tech_ddr3_phy_in;
signal phy_io : t_tech_ddr3_phy_io;
@@ -157,10 +154,7 @@ architecture tb of tb_mms_ddr3 is
signal we_n : std_logic_vector(0 downto 0);
signal flush_ena : std_logic;
-
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -205,7 +199,6 @@ begin
u_mm_file_reg_ddr3_0 : mm_file generic map(mmf_unb_file_prefix(0, 0, "FN") & "REG_DDR3_0")
port map(mm_rst, mm_clk, reg_ddr3_mosi, reg_ddr3_miso );
-
----------------------------------------------------------------------------
-- Source: block generator
----------------------------------------------------------------------------
@@ -339,7 +332,6 @@ begin
ras_n(0) <= phy_ou.ras_n;
cas_n(0) <= phy_ou.cas_n;
we_n(0) <= phy_ou.we_n;
-
end generate;
----------------------------------------------------------------------------
@@ -368,5 +360,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
end tb;
diff --git a/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
index d21afc7544aae58ca20bbbc2adf9097864d1da8f..fc800b38d513edd0b609061c21a99684ed293e9b 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -58,7 +57,6 @@ entity tb_seq_ddr3 is
end tb_seq_ddr3;
architecture tb of tb_seq_ddr3 is
-
constant c_sim : boolean := true;
----------------------------------------------------------------------------
@@ -132,7 +130,6 @@ architecture tb of tb_seq_ddr3 is
constant c_db_buf_use_sync : boolean := false;
constant c_db_data_type : t_diag_data_type_enum := e_data;
-
signal bg_siso_arr : t_dp_siso_arr(1 - 1 downto 0) := (others => c_dp_siso_rdy);
signal bg_sosi_arr : t_dp_sosi_arr(1 - 1 downto 0);
@@ -155,7 +152,6 @@ architecture tb of tb_seq_ddr3 is
signal dvr_wr_not_rd : std_logic;
signal dvr_done : std_logic;
-
-- Signals to interface with the DDR3 memory model.
signal phy_in : t_tech_ddr3_phy_in;
signal phy_io : t_tech_ddr3_phy_io;
@@ -164,10 +160,7 @@ architecture tb of tb_seq_ddr3 is
signal ras_n : std_logic_vector(0 downto 0);
signal cas_n : std_logic_vector(0 downto 0);
signal we_n : std_logic_vector(0 downto 0);
-
-
begin
-
----------------------------------------------------------------------------
-- Clock and reset generation
----------------------------------------------------------------------------
@@ -322,7 +315,6 @@ begin
ras_n(0) <= phy_ou.ras_n;
cas_n(0) <= phy_ou.cas_n;
we_n(0) <= phy_ou.we_n;
-
end generate;
----------------------------------------------------------------------------
@@ -351,6 +343,4 @@ begin
in_sync => OPEN,
in_sosi_arr => out_sosi_arr
);
-
-
end tb;
diff --git a/libraries/io/epcs/src/vhdl/epcs_reg.vhd b/libraries/io/epcs/src/vhdl/epcs_reg.vhd
index 3c7ae0a5eeb72f6d7b2ed8c841ac0e462c692209..ba976cc634c979adf20c371e3f36da0f9351c792 100644
--- a/libraries/io/epcs/src/vhdl/epcs_reg.vhd
+++ b/libraries/io/epcs/src/vhdl/epcs_reg.vhd
@@ -41,7 +41,6 @@
-- Refer to the user guide of Altera's ALTASMI_PARALLEL megafunction for more
-- information.
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -75,13 +74,10 @@ entity epcs_reg is
);
end epcs_reg;
-
architecture rtl of epcs_reg is
-
-- For safety, address range unprotection requires the following word to be written:
constant c_unprotect_passphrase : std_logic_vector(c_word_w - 1 downto 0 ) := x"BEDA221E"; -- "Bedazzle"
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(6),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
@@ -97,9 +93,7 @@ architecture rtl of epcs_reg is
signal mm_busy : std_logic;
signal mm_unprotect_address_range : std_logic := '0';
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -189,6 +183,4 @@ begin
epcs_in_addr <= mm_epcs_in_addr;
epcs_in_rden <= mm_epcs_in_rden;
unprotect_address_range <= mm_unprotect_address_range;
-
end rtl;
-
diff --git a/libraries/io/epcs/src/vhdl/mms_epcs.vhd b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
index 7bd6417c9b729b2c3eaa3c16339e9ec89e191a67..d7c837f85891751e521a4e7b9a3743d6d1db465f 100644
--- a/libraries/io/epcs/src/vhdl/mms_epcs.vhd
+++ b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
@@ -41,7 +41,6 @@
-- table in the data sheet. These constants can be modified for faster simulation, but I've left them
-- as they were as simulating one page write and read is sufficient.
-
library IEEE, common_lib, dp_lib, technology_lib, tech_flash_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -51,7 +50,6 @@ use dp_lib.dp_stream_pkg.all;
use technology_lib.technology_select_pkg.all;
use tech_flash_lib.tech_flash_component_pkg.all;
-
entity mms_epcs is
generic (
g_technology : natural := c_tech_select_default;
@@ -86,9 +84,7 @@ entity mms_epcs is
);
end mms_epcs;
-
architecture str of mms_epcs is
-
-- ASMI_PARALLEL supports page write mode of 256 bytes
constant c_epcs_page_size : natural := 256;
constant c_user_data_w : natural := c_word_w;
@@ -154,9 +150,7 @@ architecture str of mms_epcs is
signal unprotect_address_range : std_logic;
signal addr_in_protected_range : std_logic;
signal allow_write : std_logic;
-
begin
-
u_epcs_reg: entity work.epcs_reg
generic map (
g_epcs_addr_w => c_epcs_addr_w
@@ -370,6 +364,4 @@ begin
clk => epcs_clk,
out_rst => epcs_rst
);
-
end str;
-
diff --git a/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd b/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd
index 74cfc2675c569e8ba95e67503f1c594e8a5418c4..3007341facc88214a23d440573f8f8fc8083ae5b 100644
--- a/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd
+++ b/libraries/io/epcs/tb/vhdl/tb_mms_epcs.vhd
@@ -38,7 +38,6 @@ entity tb_mms_epcs is
end entity tb_mms_epcs;
architecture str of tb_mms_epcs is
-
constant c_sim : boolean := true;
constant c_mm_clk_period : time := 8 ns;
constant c_epcs_clk_period : time := 50 ns;
@@ -74,9 +73,7 @@ architecture str of tb_mms_epcs is
signal tb_rd_usedw : std_logic_vector(c_word_w - 1 downto 0);
signal tb_rd_data : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -93,7 +90,6 @@ begin
p_reg_input_stimuli : process
begin
-
epcs_mosi <= c_mem_mosi_rst;
dpmm_ctrl_mosi <= c_mem_mosi_rst;
@@ -158,9 +154,7 @@ begin
proc_mem_mm_bus_rd_latency(c_mem_reg_rd_latency, mm_clk);
tb_rd_data <= dpmm_data_miso.rddata(c_word_w - 1 downto 0);
-
end loop; -- read usedw words
-
end loop; -- while usedw>0
wait;
@@ -188,7 +182,4 @@ begin
mmdp_data_mosi => mmdp_data_mosi,
mmdp_data_miso => mmdp_data_miso
);
-
-
end architecture str;
-
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
index 45e5c26c4aa4923ac527a6c08ee7065d13d24a41..0e1f4a27346a68a5b3529e6909f6b7425a1c4db6 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/mmm_unb1_eth_10g.vhd
@@ -225,7 +225,6 @@ entity mmm_unb1_eth_10g is
end entity mmm_unb1_eth_10g;
architecture str of mmm_unb1_eth_10g is
-
constant c_sim_node_type : string(1 to 2) := sel_a_b(g_sim_node_nr < 4, "FN", "BN");
constant c_sim_node_nr : natural := sel_a_b(c_sim_node_type = "BN", g_sim_node_nr - 4, g_sim_node_nr);
constant c_sim_eth_src_mac : std_logic_vector(c_network_eth_mac_slv'range) := X"00228608" & TO_UVEC(g_sim_unb_nr, c_byte_w) & TO_UVEC(g_sim_node_nr, c_byte_w);
@@ -414,10 +413,7 @@ architecture str of mmm_unb1_eth_10g is
ram_diag_data_buffer_address_export : out std_logic_vector(13 downto 0)
);
end component qsys_unb1_eth_10g;
-
-
begin
-
----------------------------------------------------------------------------
-- MM <-> file I/O for simulation. The files are created in $HDL_IOFILE_SIM_DIR.
----------------------------------------------------------------------------
@@ -478,6 +474,7 @@ begin
-- 1GbE setup sequence normally performed by unb_os@NIOS
----------------------------------------------------------------------------
eth1g_mm_rst <= '1', '0' after 40 ns;
+
p_eth_setup : process
begin
sim_eth_mm_bus_switch <= '1';
@@ -500,18 +497,18 @@ begin
eth1g_reg_mosi <= i_eth1g_reg_mosi;
end if;
end process;
+
----------------------------------------------------------------------------
-- Procedure that polls a sim control file that can be used to e.g. get
-- the simulation time in ns
----------------------------------------------------------------------------
mmf_poll_sim_ctrl_file(c_mmf_unb_file_path & "sim.ctrl", c_mmf_unb_file_path & "sim.stat");
-
end generate;
+
----------------------------------------------------------------------------
-- SOPC or QSYS for synthesis
----------------------------------------------------------------------------
gen_qsys_unb1_eth_10g : if g_sim = false generate
-
mm_rst_n <= not(mm_rst);
u_qsys_unb1_eth_10g : qsys_unb1_eth_10g
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
index c114651ec5c5665697630ffd3c6880f6d7ad2f74..a607d66323baea9c444ddb34f40d2d2ac0fc8256 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
@@ -100,9 +100,7 @@ entity unb1_eth_10g is
);
end unb1_eth_10g;
-
architecture str of unb1_eth_10g is
-
-- Firmware version x.y
constant c_fw_version : t_unb1_board_fw_version := (1, 0); --
@@ -167,9 +165,6 @@ architecture str of unb1_eth_10g is
( field_name_pad("usr_hdr_field_6" ), " ", 27, field_default(0) ),
( field_name_pad("usr_hdr_word_align" ), " ", 16, field_default(0) ) );
-
-
-
constant c_bypass_rx_filter : boolean := true;
constant c_hdr_field_ovr_init : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := "111" & "111111111111" & "0011" & "001111111" & "0";
@@ -285,7 +280,6 @@ architecture str of unb1_eth_10g is
signal mms_dp_xonoff_src_out_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
signal mms_dp_xonoff_src_in_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0);
-
signal dp_offload_rx_restored_src_out_arr : t_dp_sosi_arr(c_nof_10GbE_streams - 1 downto 0) := (others => c_dp_sosi_rst);
signal dp_offload_rx_snk_in_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0);
@@ -327,9 +321,7 @@ architecture str of unb1_eth_10g is
signal fo_snk_in : t_dp_sosi;
signal fo_src_in : t_dp_siso;
signal fo_src_out : t_dp_sosi;
-
begin
-
-----------------------------------------------------------------------------
-- Interface : 10GbE
-----------------------------------------------------------------------------
@@ -383,7 +375,6 @@ begin
g_nof_macs => c_nof_10GbE_streams,
g_use_mdio => true
)
-
port map (
-- Transceiver PLL reference clock
tr_ref_clk_156 => SA_CLK,
@@ -479,7 +470,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- TX: dp_offload_tx
-----------------------------------------------------------------------------
@@ -887,7 +877,4 @@ begin
reg_mdio_0_miso <= reg_mdio_miso_arr(0);
reg_mdio_1_miso <= reg_mdio_miso_arr(1);
reg_mdio_2_miso <= reg_mdio_miso_arr(2);
-
end str;
-
-
diff --git a/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd
index 6341dbe6cb6a3d8d659576194eb807a46bffd585..c5c71f81fa43ba7a20ca0d14a1c3fa3a97b55141 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -49,7 +48,6 @@ entity tb_unb1_eth_10g is
end tb_unb1_eth_10g;
architecture tb of tb_unb1_eth_10g is
-
constant c_sim : boolean := true;
constant c_unb1_board_nr : natural := 0; -- UniBoard 0
@@ -84,7 +82,6 @@ architecture tb of tb_unb1_eth_10g is
signal ID_lcu : std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0) := c_id_lcu;
signal ID_dut : std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0) := c_id_dut;
begin
-
----------------------------------------------------------------------------
-- Externally generated clocks
----------------------------------------------------------------------------
@@ -159,5 +156,4 @@ begin
SI_FN_2_TX => si_fn_2_lcu_rx,
SI_FN_3_TX => si_fn_3_lcu_rx
);
-
end tb;
diff --git a/libraries/io/eth/src/vhdl/avs2_eth.vhd b/libraries/io/eth/src/vhdl/avs2_eth.vhd
index 72286b281d27b7909a6c94f70a91051f0b41770b..2171c73796e907dd156c99b587f5a5e47e508da5 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth.vhd
+++ b/libraries/io/eth/src/vhdl/avs2_eth.vhd
@@ -28,7 +28,6 @@ use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
use work.eth_pkg.all;
-
entity avs2_eth is
port (
---------------------------------------------------------------------------
@@ -91,9 +90,7 @@ entity avs2_eth is
);
end avs2_eth;
-
architecture wrap of avs2_eth is
-
-- Wrap all records to STD_LOGIC
-- ST UDP interface
@@ -110,9 +107,7 @@ architecture wrap of avs2_eth is
-- LED interface
signal tse_led : t_tech_tse_led;
-
begin
-
-- Run internal ST at MM clock
-- Disable UDP off-load interface
udp_tx_snk_in_arr <= (others => c_dp_sosi_rst); -- default not valid if not used
@@ -186,5 +181,4 @@ begin
-- LED interface
tse_led => tse_led
);
-
end wrap;
diff --git a/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd b/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
index 3c94c1901f613072062b922ea5210533129da04d..d648f26fb1cb1a3e9c804714afad5c500ffa4798 100644
--- a/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
+++ b/libraries/io/eth/src/vhdl/avs2_eth_coe.vhd
@@ -31,7 +31,6 @@ use common_lib.common_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
use work.eth_pkg.all;
-
entity avs2_eth_coe is
port (
----------------------------------------------------------------------------
@@ -100,10 +99,8 @@ entity avs2_eth_coe is
);
end avs2_eth_coe;
-
architecture wrap of avs2_eth_coe is
begin
-
------------------------------------------------------------------------------
-- Wires
@@ -135,5 +132,4 @@ begin
-- Interrupt Sender interface
ins_interrupt_irq <= coe_irq_export;
-
end wrap;
diff --git a/libraries/io/eth/src/vhdl/eth.vhd b/libraries/io/eth/src/vhdl/eth.vhd
index 35a68a8a3b6a72be2b54d06f58fb4de60e381018..1906bdf36dd1c4a233978c6a4135f43b0d0d166b 100644
--- a/libraries/io/eth/src/vhdl/eth.vhd
+++ b/libraries/io/eth/src/vhdl/eth.vhd
@@ -88,9 +88,7 @@ entity eth is
);
end eth;
-
architecture str of eth is
-
------------------------------------------------------------------------------
-- ETH Rx packet buffer and Tx packet buffer
------------------------------------------------------------------------------
@@ -199,9 +197,7 @@ architecture str of eth is
signal tse_rx_siso : t_dp_siso;
-- . MAC specific
signal tse_rx_mac_out : t_tech_tse_rx_mac;
-
begin
-
------------------------------------------------------------------------------
-- MM registers
------------------------------------------------------------------------------
@@ -262,7 +258,6 @@ begin
mem_in_endian <= func_mem_swap_endianess(mem_in, c_word_sz);
mem_out <= func_mem_swap_endianess(mem_out_endian, c_word_sz);
-
------------------------------------------------------------------------------
-- RX : Adapt the TSE RX source ready latency from 2 to 1
------------------------------------------------------------------------------
@@ -327,7 +322,6 @@ begin
rx_crc_siso <= rx_ihl20_siso;
end generate;
-
------------------------------------------------------------------------------
-- RX : For IP verify IP header checksum
------------------------------------------------------------------------------
@@ -385,7 +379,6 @@ begin
frm_discard_val => rx_frm_discard_val
);
-
------------------------------------------------------------------------------
-- Demux the UDP off-load traffic and the keep the other ETH traffic
------------------------------------------------------------------------------
@@ -438,7 +431,6 @@ begin
demux_siso_arr(i) <= udp_rx_src_in_arr(i - 1);
end generate;
-
------------------------------------------------------------------------------
-- ETH RX frame buffer
------------------------------------------------------------------------------
@@ -467,7 +459,6 @@ begin
flushed_frm_cnt => rx_flushed_frm_cnt
);
-
------------------------------------------------------------------------------
-- ETH RX frame monitor
------------------------------------------------------------------------------
@@ -522,7 +513,6 @@ begin
reg_frame => reg_frame
);
-
------------------------------------------------------------------------------
-- ETH Control
------------------------------------------------------------------------------
@@ -557,7 +547,6 @@ begin
mem_out => mem_out
);
-
------------------------------------------------------------------------------
-- TX : Mux UDP
------------------------------------------------------------------------------
@@ -622,7 +611,6 @@ begin
src_out => tx_hdr_sosi
);
-
------------------------------------------------------------------------------
-- TSE MAC
------------------------------------------------------------------------------
@@ -670,5 +658,4 @@ begin
-- LED interface
tse_led => tse_led
);
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_buffer.vhd b/libraries/io/eth/src/vhdl/eth_buffer.vhd
index 75802e20b246e5a4cc5b13574d51addce9cd88a5..957ce8ecae7f891691d35a5ca1caa545338ae70c 100644
--- a/libraries/io/eth/src/vhdl/eth_buffer.vhd
+++ b/libraries/io/eth/src/vhdl/eth_buffer.vhd
@@ -58,9 +58,7 @@ entity eth_buffer is
);
end eth_buffer;
-
architecture str of eth_buffer is
-
constant c_nof_frames : natural := 2; -- support at least 2 max size frames in the FIFO
constant c_fifo_nof_words : natural := 2**(ceil_log2(c_nof_frames * c_eth_frame_nof_words));
constant c_fifo_almost_full : natural := c_fifo_nof_words - 32; -- little margin is sufficient, because flush u_fifo will start immediately
@@ -93,9 +91,7 @@ architecture str of eth_buffer is
signal nxt_state : t_state_enum;
signal nxt_src_ack : std_logic;
signal nxt_src_done : std_logic;
-
begin
-
flushed_frm_cnt <= i_flushed_frm_cnt;
p_reg : process(rst, clk)
@@ -151,7 +147,6 @@ begin
src_out => fifo_rd_sosi
);
-
u_frame_rd : entity dp_lib.dp_frame_rd
generic map (
g_dat_w => c_eth_data_w,
@@ -182,7 +177,6 @@ begin
out_eof => src_out.eop
);
-
------------------------------------------------------------------------------
-- Output state machine
------------------------------------------------------------------------------
@@ -226,5 +220,4 @@ begin
end if;
end case;
end process;
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_checksum.vhd b/libraries/io/eth/src/vhdl/eth_checksum.vhd
index 7f1f0d97ef55dd2bd7124906745f967e67d9cce7..a07bd80977169ec968030a3651ac23e67e7a9d6d 100644
--- a/libraries/io/eth/src/vhdl/eth_checksum.vhd
+++ b/libraries/io/eth/src/vhdl/eth_checksum.vhd
@@ -59,9 +59,7 @@ entity eth_checksum is
);
end eth_checksum;
-
architecture rtl of eth_checksum is
-
signal in_data : std_logic_vector(c_word_w - 1 downto 0);
signal in_valid : std_logic;
signal in_sop : std_logic;
@@ -87,9 +85,7 @@ architecture rtl of eth_checksum is
signal nxt_checksum : std_logic_vector(checksum'range);
signal i_checksum_val : std_logic;
signal nxt_checksum_val : std_logic;
-
begin
-
checksum <= i_checksum;
checksum_val <= i_checksum_val;
@@ -156,5 +152,4 @@ begin
nxt_checksum <= not(std_logic_vector(last_dat)) when prev_in_eop_dly = '1' else i_checksum;
nxt_checksum_val <= '1' when prev_in_eop_dly = '1' else
'0' when in_sop = '1' else i_checksum_val;
-
end rtl;
diff --git a/libraries/io/eth/src/vhdl/eth_control.vhd b/libraries/io/eth/src/vhdl/eth_control.vhd
index 87984bf8b7d7fef4e72cd3b2c5c09ea5a34b57ae..35ea4905fa6aaeaffce2c6b99704b78cbebb6916 100644
--- a/libraries/io/eth/src/vhdl/eth_control.vhd
+++ b/libraries/io/eth/src/vhdl/eth_control.vhd
@@ -61,9 +61,7 @@ entity eth_control is
);
end eth_control;
-
architecture rtl of eth_control is
-
-- Internal source ready latency of this component
constant c_this_src_latency : natural := 1; -- xmt_in, xmt_out
@@ -125,9 +123,7 @@ architecture rtl of eth_control is
-- ST->MM state machine
signal state : t_state_enum;
signal nxt_state : t_state_enum;
-
begin
-
reg_status <= i_reg_status;
mem_in <= i_mem_in;
xmt_out <= i_xmt_out;
@@ -236,7 +232,6 @@ begin
end if;
end process;
-
------------------------------------------------------------------------------
-- Tx frame output control
------------------------------------------------------------------------------
@@ -301,7 +296,6 @@ begin
nxt_tx_nof_words <= reg_control.tx_nof_words(c_eth_frame_nof_words_w - 1 downto 0) when xmt_start = '1' else tx_nof_words;
nxt_tx_empty <= reg_control.tx_empty when xmt_start = '1' else tx_empty;
-
------------------------------------------------------------------------------
-- State machine
------------------------------------------------------------------------------
@@ -364,5 +358,4 @@ begin
end if;
end case;
end process;
-
end rtl;
diff --git a/libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd b/libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd
index faf8952a29a9044e8900fe4cb939997ebe00eb0d..cca9ed98fb289e57e9ecace746e8f0979463b474 100644
--- a/libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd
+++ b/libraries/io/eth/src/vhdl/eth_crc_ctrl.vhd
@@ -36,7 +36,6 @@ use work.eth_pkg.all;
-- . c_this_snk_latency = 1
-- . c_this_src_latency = 1
-
entity eth_crc_ctrl is
port (
rst : in std_logic;
@@ -54,9 +53,7 @@ entity eth_crc_ctrl is
);
end eth_crc_ctrl;
-
architecture rtl of eth_crc_ctrl is
-
constant c_tail_nof_words : natural := 2; -- if empty /=0 then the CRC is straddled over the last two packet words
constant c_tail_high : natural := c_tail_nof_words - 1;
@@ -68,9 +65,7 @@ architecture rtl of eth_crc_ctrl is
signal in_err : std_logic_vector(c_eth_data_w - 1 downto 0);
signal in_err_hold : std_logic_vector(snk_in_err'range);
signal nxt_in_err_hold : std_logic_vector(snk_in_err'range);
-
begin
-
src_out <= i_src_out;
-- Pass on frame level flow control
diff --git a/libraries/io/eth/src/vhdl/eth_crc_word.vhd b/libraries/io/eth/src/vhdl/eth_crc_word.vhd
index 3b94d950f05508394877873e5540c8ceb07ffb6b..b848b5e0b3a7cbb794c679bab9a521210d842814 100644
--- a/libraries/io/eth/src/vhdl/eth_crc_word.vhd
+++ b/libraries/io/eth/src/vhdl/eth_crc_word.vhd
@@ -58,18 +58,14 @@ entity eth_crc_word is
);
end eth_crc_word;
-
architecture rtl of eth_crc_word is
-
signal tail_word : std_logic_vector(c_eth_data_w - 1 downto 0);
signal nxt_tail_word : std_logic_vector(tail_word'range);
signal i_crc_word : std_logic_vector(crc_word'range) := (others => '0');
signal nxt_crc_word : std_logic_vector(crc_word'range);
signal i_crc_word_val : std_logic;
signal nxt_crc_word_val : std_logic;
-
begin
-
-- Direct connection between snk and src to support series connection of this component in a stream
src_out <= snk_in;
snk_out <= src_in; -- default this component is always ready thanks to c_eth_stream_rdy, but the downstream component may overrule this
@@ -113,5 +109,4 @@ begin
end case;
end if;
end process;
-
end rtl;
diff --git a/libraries/io/eth/src/vhdl/eth_frm_discard.vhd b/libraries/io/eth/src/vhdl/eth_frm_discard.vhd
index 416f9076f545b4269a483e18381a71fc6a0e1d14..19b1deed09cc7750f238d67cbb2661ff9a695e1f 100644
--- a/libraries/io/eth/src/vhdl/eth_frm_discard.vhd
+++ b/libraries/io/eth/src/vhdl/eth_frm_discard.vhd
@@ -62,14 +62,10 @@ entity eth_frm_discard is
);
end eth_frm_discard;
-
architecture rtl of eth_frm_discard is
-
signal i_frm_discard : std_logic;
signal nxt_frm_discard : std_logic;
-
begin
-
frm_discard <= i_frm_discard;
p_reg : process(rst, clk)
@@ -120,5 +116,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/libraries/io/eth/src/vhdl/eth_hdr.vhd b/libraries/io/eth/src/vhdl/eth_hdr.vhd
index e183e1a0503660b12b3632df2a8ece638d75bf08..04060bdb252d7277542a5d5e98d6d17ac35f0dee 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr.vhd
@@ -70,9 +70,7 @@ entity eth_hdr is
);
end eth_hdr;
-
architecture str of eth_hdr is
-
-- Internal sink ready latency and source ready latency of this component
constant c_this_snk_latency : natural := 1;
constant c_this_src_latency : natural := 1;
@@ -87,9 +85,7 @@ architecture str of eth_hdr is
signal i_hdr_data : std_logic_vector(c_word_w - 1 downto 0);
signal i_hdr_data_val : std_logic;
signal i_hdr_status : t_eth_hdr_status;
-
begin
-
-- Make all header info available
hdr_words_arr <= i_hdr_words_arr;
hdr_words_arr_val <= i_hdr_words_arr_val;
@@ -173,5 +169,4 @@ begin
hdr_status => i_hdr_status,
hdr_status_complete => hdr_status_complete
);
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd b/libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd
index 70ce4ea30957359dd87f97aedd444fdae419788c..b3b8e2fdde4b328cc9ec3aa0b031363ffb44797b 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr_ctrl.vhd
@@ -57,9 +57,7 @@ entity eth_hdr_ctrl is
);
end eth_hdr_ctrl;
-
architecture rtl of eth_hdr_ctrl is
-
-- Internal sink ready latency and source ready latency of this component
constant c_this_snk_latency : natural := 1;
constant c_this_src_latency : natural := 1;
@@ -86,9 +84,7 @@ architecture rtl of eth_hdr_ctrl is
signal nxt_src_out : t_dp_sosi;
signal src_word_cnt : natural range 0 to c_network_total_header_32b_nof_words;
signal nxt_src_word_cnt : natural;
-
begin
-
src_out <= i_src_out;
p_reg : process(rst, clk)
@@ -106,7 +102,6 @@ begin
end if;
end process;
-
------------------------------------------------------------------------------
-- Hold the sink input for source output
------------------------------------------------------------------------------
@@ -221,5 +216,4 @@ begin
-- Pass on frame level flow control
snk_out.xon <= src_in.xon;
end process;
-
end rtl;
diff --git a/libraries/io/eth/src/vhdl/eth_hdr_status.vhd b/libraries/io/eth/src/vhdl/eth_hdr_status.vhd
index 50d2f4d59fb2b52e67dbe7cf60c1f24902ce6108..469b00c370ed78dc17bce8b3f8d6ad2d9ed342cc 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr_status.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr_status.vhd
@@ -64,9 +64,7 @@ entity eth_hdr_status is
);
end eth_hdr_status;
-
architecture rtl of eth_hdr_status is
-
signal i_hdr_status : t_eth_hdr_status;
signal nxt_hdr_status : t_eth_hdr_status;
@@ -75,9 +73,7 @@ architecture rtl of eth_hdr_status is
signal calc_checksum_val : std_logic;
signal ip_checksum : std_logic_vector(c_halfword_w - 1 downto 0);
signal ip_checksum_val : std_logic;
-
begin
-
hdr_status <= i_hdr_status;
p_clk : process(rst, clk)
@@ -147,5 +143,4 @@ begin
------------------------------------------------------------------------------
-- UDP port number
nxt_hdr_status.udp_port <= hdr_fields.udp.dst_port;
-
end rtl;
diff --git a/libraries/io/eth/src/vhdl/eth_hdr_store.vhd b/libraries/io/eth/src/vhdl/eth_hdr_store.vhd
index f81a6b7d3bbd9c2ec9d15bd02a74bf97890b5906..ab6f7b520206be015a53a58b9202c1794c2d3eeb 100644
--- a/libraries/io/eth/src/vhdl/eth_hdr_store.vhd
+++ b/libraries/io/eth/src/vhdl/eth_hdr_store.vhd
@@ -74,9 +74,7 @@ entity eth_hdr_store is
);
end eth_hdr_store;
-
architecture rtl of eth_hdr_store is
-
signal word_cnt : natural range 0 to c_network_total_header_32b_nof_words;
signal nxt_word_cnt : natural;
@@ -88,9 +86,7 @@ architecture rtl of eth_hdr_store is
signal i_hdr_data : std_logic_vector(c_word_w - 1 downto 0) := (others => '0'); -- init to avoid numeric_std warning, no need to rst
signal nxt_hdr_data : std_logic_vector(c_word_w - 1 downto 0);
signal nxt_hdr_data_val : std_logic;
-
begin
-
snk_in_word_cnt <= word_cnt;
hdr_words_arr <= i_hdr_words_arr;
@@ -152,5 +148,4 @@ begin
hdr_fields.ip <= func_network_total_header_extract_ip( i_hdr_words_arr);
hdr_fields.icmp <= func_network_total_header_extract_icmp(i_hdr_words_arr);
hdr_fields.udp <= func_network_total_header_extract_udp( i_hdr_words_arr);
-
end rtl;
diff --git a/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd b/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd
index 6e3eca5f07b94f2d54a60165c5a7c51f94ff0a83..02b167448fe219cdd3b5f72fb60974a197e074f0 100644
--- a/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd
+++ b/libraries/io/eth/src/vhdl/eth_ihl_to_20.vhd
@@ -57,7 +57,6 @@ use work.eth_pkg.all;
-- | Options ... |
-- |----------------------------------------------------------------------|
-
entity eth_ihl_to_20 is
generic (
incoming_ihl : natural := 20
@@ -76,9 +75,7 @@ entity eth_ihl_to_20 is
);
end eth_ihl_to_20;
-
architecture rtl of eth_ihl_to_20 is
-
signal i_src_out : t_dp_sosi;
signal i_src_in : t_dp_siso;
@@ -86,10 +83,7 @@ architecture rtl of eth_ihl_to_20 is
signal state : state_type;
signal ihl : unsigned(c_network_ip_header_length_w - 1 downto 0);
-
begin
-
-
-- Pass on frame level flow control
snk_out.xon <= i_src_in.xon;
@@ -114,8 +108,6 @@ begin
src_in => src_in
);
-
-
process(clk, rst)
begin
if rst = '1' then
@@ -217,5 +209,4 @@ begin
end case;
end if;
end process;
-
end rtl;
diff --git a/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd b/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
index 14013f5dbe205f45f31ff9f275bb9e2f3ad9cccc..c3c8b74b5e33c147986287a947798270017c919d 100644
--- a/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/src/vhdl/eth_ip_header_checksum.vhd
@@ -28,7 +28,6 @@
-- Remarks:
-- The hdr_fields_slv_in should be valid on the snk_in.sop
-
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -57,7 +56,6 @@ entity eth_ip_header_checksum is
end eth_ip_header_checksum;
architecture rtl of eth_ip_header_checksum is
-
constant c_hdr_len : natural := field_slv_len(g_hdr_field_arr);
constant c_hdr_crc_bit_hi : natural := field_hi(g_hdr_field_arr, "ip_header_checksum");
constant c_hdr_crc_bit_lo : natural := field_lo(g_hdr_field_arr, "ip_header_checksum");
@@ -81,9 +79,7 @@ architecture rtl of eth_ip_header_checksum is
signal dp_pipeline_src_out : t_dp_sosi;
signal reg_done : std_logic := '0';
signal nxt_reg_done : std_logic := '0';
-
begin
-
-- calculate checksum
checksum <= func_network_ip_header_checksum(g_hdr_field_arr, hdr_fields_slv_in) when rising_edge(clk);
@@ -172,5 +168,4 @@ begin
src_in => src_in,
src_out => dp_pipeline_src_out
);
-
end rtl;
diff --git a/libraries/io/eth/src/vhdl/eth_mm_reg_frame.vhd b/libraries/io/eth/src/vhdl/eth_mm_reg_frame.vhd
index e03dff82310d7ce793a1c81e361fa8c9d15d35ff..f7877190291bc43d4f57d53c9160730315108a13 100644
--- a/libraries/io/eth/src/vhdl/eth_mm_reg_frame.vhd
+++ b/libraries/io/eth/src/vhdl/eth_mm_reg_frame.vhd
@@ -44,13 +44,9 @@ entity eth_mm_reg_frame is
);
end eth_mm_reg_frame;
-
architecture str of eth_mm_reg_frame is
-
signal nxt_reg_frame : t_eth_mm_reg_frame;
-
begin
-
p_reg : process(rst, clk)
begin
if rst = '1' then
@@ -70,5 +66,4 @@ begin
nxt_reg_frame.is_arp <= hdr_status.is_arp;
nxt_reg_frame.mac_address_match <= '1' when unsigned(hdr_fields.eth.dst_mac) = unsigned(reg_config.mac_address) else '0';
nxt_reg_frame.eth_mac_error <= erc_word(c_eth_error_w - 1 downto 0);
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_mm_registers.vhd b/libraries/io/eth/src/vhdl/eth_mm_registers.vhd
index 51432f701e95991e72ae6cf55c76888562f5a1d7..f2011b02744ca3320d56d07def554b374d3a27f8 100644
--- a/libraries/io/eth/src/vhdl/eth_mm_registers.vhd
+++ b/libraries/io/eth/src/vhdl/eth_mm_registers.vhd
@@ -28,7 +28,6 @@ use common_lib.common_mem_pkg.all;
use common_lib.common_network_layers_pkg.all;
use work.eth_pkg.all;
-
entity eth_mm_registers is
generic (
g_cross_clock_domain : boolean := true; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
@@ -59,9 +58,7 @@ entity eth_mm_registers is
);
end eth_mm_registers;
-
architecture str of eth_mm_registers is
-
-- Use MM bus data width = c_word_w = 32
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => c_eth_reg_addr_w,
@@ -114,9 +111,7 @@ architecture str of eth_mm_registers is
-- . Information in the status register in the mm_clk domain is used to generate the interrupt
signal mm_reg_status : t_eth_mm_reg_status;
-
begin
-
------------------------------------------------------------------------------
-- Register fields mapping (all wires)
-- . wire the entire register vector to the register field vectors
@@ -138,7 +133,6 @@ begin
mm_vec_rd <= mm_vec_status & mm_vec_frame & mm_vec_control & mm_vec_config & mm_vec_demux;
-
------------------------------------------------------------------------------
-- Register store in MM clock domain
------------------------------------------------------------------------------
@@ -163,7 +157,6 @@ begin
in_reg => mm_vec_rd
);
-
------------------------------------------------------------------------------
-- Detect specific register accesses for handshake control with MM master
------------------------------------------------------------------------------
@@ -187,7 +180,6 @@ begin
nxt_mm_reg_continue_wr <= '1' when sla_in_reg.wr = '1' and unsigned(sla_in_reg.address(c_mm_reg.adr_w - 1 downto 0)) = c_eth_reg_continue_wi else '0';
nxt_mm_reg_status_wr <= '1' when sla_in_reg.wr = '1' and unsigned(sla_in_reg.address(c_mm_reg.adr_w - 1 downto 0)) = c_eth_reg_status_wi else '0';
-
------------------------------------------------------------------------------
-- Interrupt MM master based on status register info
------------------------------------------------------------------------------
@@ -198,7 +190,6 @@ begin
-- Interrupt when there is a new Rx packet in the buffer or to acknowledge Tx instert request
nxt_sla_interrupt <= mm_reg_status.rx_avail or mm_reg_status.tx_avail;
-
no_cross : if g_cross_clock_domain = false generate
-- MM -> ST
st_vec_demux <= mm_vec_demux;
@@ -214,7 +205,6 @@ begin
end generate;
gen_cross : if g_cross_clock_domain = true generate
-
------------------------------------------------------------------------------
-- Cross the register access event between the MM and the ST clock domain
------------------------------------------------------------------------------
@@ -307,7 +297,6 @@ begin
out_clk => mm_clk,
out_dat => mm_vec_status
);
-
end generate;
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_pkg.vhd b/libraries/io/eth/src/vhdl/eth_pkg.vhd
index 5b03a4aa477ca32bace5889ae326787fa245d3dc..d7f2fe2b9b4777d8538e73b6f443a7b0605c8b50 100644
--- a/libraries/io/eth/src/vhdl/eth_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_pkg.vhd
@@ -28,9 +28,7 @@ use common_lib.common_network_layers_pkg.all;
use dp_lib.dp_stream_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
-
package eth_pkg is
-
constant c_eth_data_w : natural := c_tech_tse_data_w; -- = c_word_w
constant c_eth_empty_w : natural := c_tech_tse_empty_w; -- = ceil_log2(c_word_sz) = 2;
constant c_eth_error_w : natural := c_tech_tse_error_w; -- = 6, but no error field, pass error info on via checksum or CRC /= 0 in packet word
@@ -57,7 +55,6 @@ package eth_pkg is
type t_eth_data_arr is array (integer range <>) of std_logic_vector(c_eth_data_w - 1 downto 0);
-
------------------------------------------------------------------------------
-- Definitions for eth header status
------------------------------------------------------------------------------
@@ -223,9 +220,7 @@ package eth_pkg is
end eth_pkg;
-
package body eth_pkg is
-
-- Register mapping functions
function func_eth_mm_reg_demux(mm_reg : std_logic_vector) return t_eth_mm_reg_demux is
variable v_reg : t_eth_mm_reg_demux;
@@ -235,6 +230,7 @@ package body eth_pkg is
v_reg.udp_ports_en(I) := mm_reg(c_network_udp_port_w + (I - 1) * c_word_w); -- [16] = UDP port enable
v_reg.udp_ports(I) := mm_reg(c_network_udp_port_w - 1 + (I - 1) * c_word_w downto (I - 1) * c_word_w); -- [15:0] = UDP port number
end loop;
+
return v_reg;
end func_eth_mm_reg_demux;
@@ -354,4 +350,3 @@ package body eth_pkg is
end func_eth_mm_reg_status;
end eth_pkg;
-
diff --git a/libraries/io/eth/src/vhdl/eth_statistics.vhd b/libraries/io/eth/src/vhdl/eth_statistics.vhd
index ab40c61a8cab0460c1b74dd6da427897a6e7c51e..1282286c2294bc7addafcf80414ee802f8fe5ca3 100644
--- a/libraries/io/eth/src/vhdl/eth_statistics.vhd
+++ b/libraries/io/eth/src/vhdl/eth_statistics.vhd
@@ -62,9 +62,7 @@ entity eth_statistics is
);
end eth_statistics;
-
architecture str of eth_statistics is
-
constant c_eth_word_w : natural := 32;
constant c_eth_clk_period : time := 8 ns;
@@ -74,9 +72,7 @@ architecture str of eth_statistics is
signal tech_tse_rx_src_out : t_dp_sosi;
signal i_tb_end : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- We're using the tb_end output locally
------------------------------------------------------------------------------
@@ -143,5 +139,4 @@ begin
-- Output the received decoded data, to support further external analysis
eth_src_out <= tech_tse_rx_src_out;
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_stream.vhd b/libraries/io/eth/src/vhdl/eth_stream.vhd
index 0bbb8f26f05669fb4324876de3731a00efad058c..4f66bb93cf47bbfd77d74d69500110e20b01490d 100644
--- a/libraries/io/eth/src/vhdl/eth_stream.vhd
+++ b/libraries/io/eth/src/vhdl/eth_stream.vhd
@@ -92,9 +92,7 @@ entity eth_stream is
);
end eth_stream;
-
architecture str of eth_stream is
-
-- Tx UDP offload stream to TSE
signal tse_tx_sosi : t_dp_sosi;
signal tse_tx_siso : t_dp_siso;
@@ -103,9 +101,7 @@ architecture str of eth_stream is
-- network packets)
signal tse_rx_sosi : t_dp_sosi;
signal tse_rx_siso : t_dp_siso;
-
begin
-
u_eth_stream_udp : entity work.eth_stream_udp
generic map (
g_rx_udp_port => g_rx_udp_port
@@ -175,5 +171,4 @@ begin
tse_led => tse_led
);
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_stream_udp.vhd b/libraries/io/eth/src/vhdl/eth_stream_udp.vhd
index 9fe0b835c7f23d903ffaf602ddb837e74aa4217e..d914ff1dc8a3dd1966fc5a4bd59919b646d8a08f 100644
--- a/libraries/io/eth/src/vhdl/eth_stream_udp.vhd
+++ b/libraries/io/eth/src/vhdl/eth_stream_udp.vhd
@@ -70,9 +70,7 @@ entity eth_stream_udp is
);
end eth_stream_udp;
-
architecture str of eth_stream_udp is
-
-- ETH Tx
signal eth_tx_siso : t_dp_siso;
signal eth_tx_sosi : t_dp_sosi;
@@ -86,9 +84,7 @@ architecture str of eth_stream_udp is
signal rx_eth_discard : std_logic;
signal rx_eth_discard_val : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- TX
------------------------------------------------------------------------------
@@ -184,5 +180,4 @@ begin
rx_eth_discard_val <= rx_hdr_status_complete;
end if;
end process;
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_tester.vhd b/libraries/io/eth/src/vhdl/eth_tester.vhd
index 51aeb7a357bd1e5ad8e752464314628293f44e55..932dcfa20c169fc16909bf3ad5eb589ddc3418e4 100644
--- a/libraries/io/eth/src/vhdl/eth_tester.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester.vhd
@@ -93,9 +93,7 @@ entity eth_tester is
);
end eth_tester;
-
architecture str of eth_tester is
-
constant c_dp_split_reg_adr_w : natural := 1; -- 1 for 1 stream in dp_split
signal ref_sync_arr : std_logic_vector(g_nof_streams - 1 downto 0);
@@ -119,9 +117,7 @@ architecture str of eth_tester is
signal reg_bsn_monitor_v2_rx_cipo_arr : t_mem_cipo_arr(g_nof_streams - 1 downto 0) := (others => c_mem_cipo_rst);
signal reg_strobe_total_count_rx_copi_arr : t_mem_copi_arr(g_nof_streams - 1 downto 0) := (others => c_mem_copi_rst);
signal reg_strobe_total_count_rx_cipo_arr : t_mem_cipo_arr(g_nof_streams - 1 downto 0) := (others => c_mem_cipo_rst);
-
begin
-
gen_streams : for I in 0 to g_nof_streams - 1 generate
u_tx : entity work.eth_tester_tx
generic map (
@@ -288,5 +284,4 @@ begin
mosi_arr => reg_strobe_total_count_rx_copi_arr,
miso_arr => reg_strobe_total_count_rx_cipo_arr
);
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
index 233abb3703c1007832f16853f426c2bd7b4de0b4..7d83b02996112591506ca1ff75bae7de8236604e 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_pkg.vhd
@@ -30,7 +30,6 @@ use common_lib.common_field_pkg.all;
use common_lib.common_network_layers_pkg.all;
package eth_tester_pkg is
-
constant c_eth_tester_bg_block_len_max : natural := c_network_eth_payload_jumbo_max; -- 9000 octets
constant c_eth_tester_rx_block_len_max : natural := c_network_eth_payload_jumbo_max + c_network_eth_crc_len; -- 9004 octets
constant c_eth_tester_eth_packet_len_max : natural := c_network_eth_word_align_len + c_network_eth_frame_jumbo_max; -- 9020 octets = 2 word align + 14 header + 9000 + 4 crc
@@ -139,9 +138,7 @@ package eth_tester_pkg is
end eth_tester_pkg;
-
package body eth_tester_pkg is
-
function func_eth_tester_gn_index_to_mac_15_0(gn_index : natural; eth_port_index : natural) return std_logic_vector is
-- Assume gn_index < 256.
-- Use default address for 1GbE II (eth_port_index = 0) and
@@ -159,7 +156,6 @@ package body eth_tester_pkg is
return func_eth_tester_gn_index_to_mac_15_0(gn_index, 0); -- default use 1GbE port I
end func_eth_tester_gn_index_to_mac_15_0;
-
function func_eth_tester_gn_index_to_ip_15_0(gn_index : natural; eth_port_index : natural) return std_logic_vector is
-- Assume gn_index < 256.
-- Use default address for 1GbE II (eth_port_index = 0) and
@@ -177,7 +173,6 @@ package body eth_tester_pkg is
return func_eth_tester_gn_index_to_ip_15_0(gn_index, 0); -- default use 1GbE port I
end func_eth_tester_gn_index_to_ip_15_0;
-
function func_eth_tester_gn_index_to_udp_7_0(gn_index : natural; eth_port_index : natural) return std_logic_vector is
-- Assume gn_index < 128.
-- Use default udp port for 1GbE I (eth_port_index = 0) and
@@ -193,7 +188,6 @@ package body eth_tester_pkg is
return func_eth_tester_gn_index_to_udp_7_0(gn_index, 0); -- default use 1GbE port I
end func_eth_tester_gn_index_to_udp_7_0;
-
function func_eth_tester_map_header(hdr_fields_raw : std_logic_vector) return t_eth_tester_header is
variable v : t_eth_tester_header;
begin
@@ -231,4 +225,3 @@ package body eth_tester_pkg is
end func_eth_tester_map_header;
end eth_tester_pkg;
-
diff --git a/libraries/io/eth/src/vhdl/eth_tester_rx.vhd b/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
index b1baa380950528d3c111ff3db9f7a6ba39cf398f..e64d5c042e51cbb413214b7d26899e1bfe7b6a17 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_rx.vhd
@@ -66,9 +66,7 @@ entity eth_tester_rx is
);
end eth_tester_rx;
-
architecture str of eth_tester_rx is
-
constant c_nof_total_counts : natural := 3; -- 0 = nof_sop, 1 = nof_valid, 2 = nof_crc_corrupt
constant c_empty_w : natural := ceil_log2(g_nof_octet_input);
@@ -104,9 +102,7 @@ architecture str of eth_tester_rx is
signal hdr_fields_raw_slv : std_logic_vector(1023 downto 0);
signal hdr_fields_out_rec : t_eth_tester_header;
signal hdr_fields_raw_rec : t_eth_tester_header;
-
begin
-
-- View sosi.data in Wave Window
rx_udp_data <= rx_udp_sosi.data(c_word_w - 1 downto 0);
rx_offload_data <= rx_offload_sosi.data(c_word_w - 1 downto 0);
@@ -271,5 +267,4 @@ begin
reg_mosi => reg_strobe_total_count_rx_copi,
reg_miso => reg_strobe_total_count_rx_cipo
);
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
index 265db1b7e96ce88606aedce9edbba518c6edd7af..2544df663b6c2ee9ed1d22ab1802262c3c22ed3a 100644
--- a/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_tester_tx.vhd
@@ -90,9 +90,7 @@ entity eth_tester_tx is
);
end eth_tester_tx;
-
architecture str of eth_tester_tx is
-
constant c_empty_w : natural := ceil_log2(g_nof_octet_output);
-- Choose 10% extra margin for FIFO fill level that will result in BG block
@@ -150,9 +148,7 @@ architecture str of eth_tester_tx is
signal hdr_fields_slv_tx : std_logic_vector(1023 downto 0);
signal hdr_fields_rec_in : t_eth_tester_header;
signal hdr_fields_rec_tx : t_eth_tester_header;
-
begin
-
ref_sync <= i_ref_sync;
tx_length <= app_total_length;
tx_fifo_rd_emp <= i_tx_fifo_rd_emp;
@@ -437,7 +433,6 @@ begin
src_out => i_tx_udp_sosi
);
-
-------------------------------------------------------------------------------
-- Tx packet monitors
-------------------------------------------------------------------------------
@@ -485,5 +480,4 @@ begin
reg_mosi => reg_strobe_total_count_tx_copi,
reg_miso => reg_strobe_total_count_tx_cipo
);
-
end str;
diff --git a/libraries/io/eth/src/vhdl/eth_udp_channel.vhd b/libraries/io/eth/src/vhdl/eth_udp_channel.vhd
index 8ba3e3925585acd80ac4721fda405edd46d5867d..76bdc91b615317005d7ef87966cb643d5f6859e8 100644
--- a/libraries/io/eth/src/vhdl/eth_udp_channel.vhd
+++ b/libraries/io/eth/src/vhdl/eth_udp_channel.vhd
@@ -46,15 +46,11 @@ entity eth_udp_channel is
);
end eth_udp_channel;
-
architecture rtl of eth_udp_channel is
-
-- ETH channel number
signal channel : natural range 0 to c_eth_nof_channels - 1;
signal nxt_channel : natural;
-
begin
-
p_reg : process(rst, clk)
begin
if rst = '1' then
@@ -82,5 +78,4 @@ begin
-- Fill in the channel field in the stream t_dp_stream
src_out <= func_dp_stream_channel_set(snk_in, channel);
-
end rtl;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_eth.vhd
index f072da9d92181b3752fd41b54b8f942b4fa9f4f1..9a880edc0917423d26593dff98b1f4c8d74e23e9 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth.vhd
@@ -39,7 +39,6 @@
-- > as 10
-- > run -all
-
library IEEE, common_lib, dp_lib, technology_lib, tech_tse_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -55,7 +54,6 @@ use tech_tse_lib.tech_tse_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
use WORK.eth_pkg.all;
-
entity tb_eth is
-- Test bench control parameters
generic (
@@ -78,9 +76,7 @@ entity tb_eth is
);
end tb_eth;
-
architecture tb of tb_eth is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
constant cable_delay : time := sel_a_b(g_sim_level = 0, 12 ns, 0 ns);
@@ -253,7 +249,6 @@ architecture tb of tb_eth is
signal udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
signal udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
-
-- LCU TSE interface
signal lcu_init : std_logic := '1';
signal lcu_tse_miso : t_mem_miso;
@@ -281,9 +276,7 @@ architecture tb of tb_eth is
signal rx_pkt_cnt : natural := 0;
signal rx_pkt_discarded_cnt: natural := 0;
signal rx_pkt_flushed_cnt : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
-- run 50 us
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
@@ -343,7 +336,6 @@ begin
wait;
end process;
-
p_eth_control : process
variable v_eth_control_word : std_logic_vector(c_word_w - 1 downto 0);
begin
@@ -515,7 +507,6 @@ begin
wait;
end process;
-
p_lcu_receiver : process
begin
-- . Avalon ST
@@ -678,5 +669,4 @@ begin
end if;
wait;
end process;
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd
index 8d6fcbf815c2ebf8c1f4e151b98203cb2a8e314f..60e4727e698b334b8922460be6fc3ffaabce6664 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_checksum.vhd
@@ -20,7 +20,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Testbench for eth_checksum
-- Description:
--
@@ -43,13 +42,10 @@ use common_lib.common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.eth_pkg.all;
-
entity tb_eth_checksum is
end tb_eth_checksum;
-
architecture tb of tb_eth_checksum is
-
constant clk_period : time := 10 ns; -- 100 MHz
constant c_exp_checksum : natural := 16#442E#;
@@ -66,9 +62,7 @@ architecture tb of tb_eth_checksum is
signal checksum : std_logic_vector(c_halfword_w - 1 downto 0);
signal checksum_val : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after 3 * clk_period;
@@ -196,7 +190,6 @@ begin
wait;
end process;
-
p_verify : process
begin
wait until rising_edge(clk);
@@ -218,5 +211,4 @@ begin
checksum => checksum,
checksum_val => checksum_val
);
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd b/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd
index 037db6b9621188908d0bad435e31b9c39f9c0187..115c8f00b04ad1668726e60cc5b2405051553399 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_crc_ctrl.vhd
@@ -36,13 +36,10 @@ use dp_lib.dp_stream_pkg.all;
use dp_lib.tb_dp_pkg.all;
use work.eth_pkg.all;
-
entity tb_eth_crc_ctrl is
end tb_eth_crc_ctrl;
-
architecture tb of tb_eth_crc_ctrl is
-
-- DUT ready latency
constant c_dut_latency : natural := 1; -- fixed 1 for dp_pipeline
constant c_tx_latency : natural := c_dut_latency; -- TX ready latency of TB
@@ -108,9 +105,7 @@ architecture tb of tb_eth_crc_ctrl is
signal src_in : t_dp_siso;
signal src_out : t_dp_sosi;
signal src_out_err : std_logic;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -178,5 +173,4 @@ begin
src_out => src_out,
src_out_err => src_out_err
);
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd b/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd
index aa1b57282276560c09d9ef5fb0c6729523386b7f..2a04c64dcd8cfba247491c8e81bc116f1428e6ac 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_hdr.vhd
@@ -39,9 +39,7 @@ use work.eth_pkg.all;
entity tb_eth_hdr is
end tb_eth_hdr;
-
architecture tb of tb_eth_hdr is
-
-- DUT ready latency
constant c_dut_latency : natural := 1; -- fixed 1 for eth_hdr
constant c_tx_latency : natural := c_dut_latency; -- TX ready latency of TB
@@ -95,9 +93,7 @@ architecture tb of tb_eth_hdr is
signal src_in : t_dp_siso;
signal src_out : t_dp_sosi;
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -160,5 +156,4 @@ begin
src_in => src_in,
src_out => src_out
);
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
index ff27d79426b6278989076d7d3f3e0366f61e418d..22a401dde7a9a6baebb9b51dae8b5ac60456f4f0 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_ihl_to_20.vhd
@@ -34,21 +34,16 @@ use dp_lib.dp_stream_pkg.all;
use common_lib.common_network_layers_pkg.all;
use work.eth_pkg.all;
-
entity tb_eth_IHL_to_20 is
end tb_eth_IHL_to_20;
-
architecture tb of tb_eth_IHL_to_20 is
-
constant clk_period : time := 5 ns; -- 100 MHz
-
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
signal rst : std_logic;
-
signal snk_in : t_dp_sosi := c_dp_sosi_rst;
signal snk_out : t_dp_siso;
@@ -59,7 +54,6 @@ architecture tb of tb_eth_IHL_to_20 is
constant c_IHL_to_test : int_arr(1 to 11) := (5,6,7,8,9,10,11,12,13,14,15);
constant c_len_to_test : int_arr(1 to 5) := (0,1,16,20,3000);
-
procedure gen_eth_frame (constant IHL : natural;
constant UDP_payload_len : natural;
signal clk : in std_logic;
@@ -120,7 +114,6 @@ architecture tb of tb_eth_IHL_to_20 is
signal src_out : in t_dp_sosi) is
constant c_IHL : natural := 5;
begin
-
-- Eth header
wait until falling_edge(clk) and src_out.valid = '1' and src_out.sop = '1';
assert src_out.data(31 downto 0) = X"0000FFFF" report "Wrong word align and Destination MAC" severity FAILURE;
@@ -166,16 +159,11 @@ architecture tb of tb_eth_IHL_to_20 is
-- Eth CRC
wait until falling_edge(clk) and src_out.valid = '1' and src_out.eop <= '1';
assert src_out.data(31 downto 0) = X"CCCCCCCC" report "Wrong Eth CRC" severity FAILURE;
-
end procedure check_eth_frame;
-
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
-
gen_frame: process
begin
wait until rst = '0';
@@ -196,7 +184,6 @@ begin
wait;
end process;
-
dut : entity work.eth_IHL_to_20
generic map (
incoming_IHL => 24
@@ -214,10 +201,8 @@ begin
src_out => src_out
);
-
check_frame: process
begin
-
for len_n in c_len_to_test'range loop
for IHL_n in c_IHL_to_test'range loop
check_eth_frame (c_len_to_test(len_n), clk, src_out);
@@ -229,5 +214,4 @@ begin
assert false report "Simulation tb_eth_IHL_to_20 finished." severity NOTE;
wait;
end process;
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
index 0f7ddc33da0b815d787fd3d9e5633dd9d931caf0..61a076e891c390cf8dccab7f9f23c3dea846daae 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_ip_header_checksum.vhd
@@ -78,9 +78,7 @@ entity tb_eth_ip_header_checksum is
);
end tb_eth_ip_header_checksum;
-
architecture tb of tb_eth_ip_header_checksum is
-
constant c_mm_clk_period : time := 1 ns;
constant c_dp_clk_period : time := 5 ns;
@@ -337,9 +335,7 @@ architecture tb of tb_eth_ip_header_checksum is
signal verify_snk_in : t_dp_sosi;
signal verify_snk_in_data : std_logic_vector(g_data_w - 1 downto 0);
signal prev_verify_snk_in_data : std_logic_vector(g_data_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Clock & reset
------------------------------------------------------------------------------
@@ -386,7 +382,6 @@ begin
tb_end => tb_end -- signal end of tb as far as this dp_stream_stimuli is concerned
);
-
------------------------------------------------------------------------------
-- DATA VERIFICATION
------------------------------------------------------------------------------
@@ -541,7 +536,6 @@ begin
hdr_fields_slv_in => tx_hdr_fields_out_arr(0)
);
-
p_rd_tx_hdr_words : process
variable v_word : std_logic_vector(c_word_w - 1 downto 0);
begin
@@ -566,7 +560,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- offload Rx
------------------------------------------------------------------------------
@@ -609,7 +602,6 @@ begin
dp_offload_rx_src_in_arr <= (others => c_dp_siso_rdy);
dp_offload_rx_src_in_arr(0) <= verify_snk_out;
-
p_rd_rx_hdr_words : process
variable v_word : std_logic_vector(c_word_w - 1 downto 0);
begin
@@ -670,5 +662,4 @@ begin
-- Map to slv to ease monitoring in wave window
stimuli_src_out_data <= stimuli_src_out.data(g_data_w - 1 downto 0);
verify_snk_in_data <= verify_snk_in.data(g_data_w - 1 downto 0);
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd b/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
index 926f3e7069e8d09f5d075a254f09fa7ad1374d40..4f5554d5c58725cdae4ff317350bf1af924c5860 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_stream_udp.vhd
@@ -64,9 +64,7 @@ entity tb_eth_stream_udp is
);
end tb_eth_stream_udp;
-
architecture tb of tb_eth_stream_udp is
-
constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : "; -- use to distinguish logging from tb instances in tb_tb
constant mm_clk_period : time := 10 ns; -- 100 MHz
constant c_nof_st_clk_per_s : natural := 200 * 10**6;
@@ -169,9 +167,7 @@ architecture tb of tb_eth_stream_udp is
signal dbg_c_mon_nof_sop_rx : natural := c_mon_nof_sop_rx;
signal dbg_c_mon_nof_valid_tx : natural := c_mon_nof_valid_tx;
signal dbg_c_mon_nof_valid_rx : natural := c_mon_nof_valid_rx;
-
begin
-
mm_clk <= (not mm_clk) or tb_end after mm_clk_period / 2;
st_clk <= (not st_clk) or tb_end after st_clk_period / 2;
mm_rst <= '1', '0' after mm_clk_period * 5;
@@ -401,7 +397,6 @@ begin
reg_strobe_total_count_rx_cipo => reg_strobe_total_count_rx_cipo
);
-
-- ETH stream
u_dut : entity work.eth_stream_udp
generic map (
@@ -432,5 +427,4 @@ begin
-- Loopback wire Tx to Rx, register to increasy ready latency from 1 to 2
tse_rx_sosi <= tse_tx_sosi when rising_edge(st_clk);
tse_tx_siso <= tse_rx_siso;
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
index 554b3462b74995c0de1cfdc77467016b21fe6194..96ef9afd24438b4c80ca128d7ecca136a433d12f 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester.vhd
@@ -82,9 +82,7 @@ entity tb_eth_tester is
);
end tb_eth_tester;
-
architecture tb of tb_eth_tester is
-
constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : "; -- use to distinguish logging from tb instances in tb_tb
constant eth_clk_period : time := 8 ns; -- 125 MHz
constant mm_clk_period : time := 10 ns; -- 100 MHz
@@ -226,9 +224,7 @@ architecture tb of tb_eth_tester is
signal dbg_c_mon_nof_valid_first_rx : natural := c_mon_nof_valid_first_rx;
signal dbg_c_mon_nof_valid_others_tx : natural := c_mon_nof_valid_others_tx;
signal dbg_c_mon_nof_valid_others_rx : natural := c_mon_nof_valid_others_rx;
-
begin
-
tb_end <= i_tb_end;
eth_clk <= (not eth_clk) or i_tb_end after eth_clk_period / 2;
@@ -603,6 +599,7 @@ begin
eth_rxp <= eth_txp;
tse_init <= '0';
end generate;
+
use_tech_tse : if g_eth_sim_level = 0 generate
p_eth_link : process(eth_txp)
begin
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
index 92a17149255cb38b503cc6d21faf77ad29d705fd..ad83dbe15cc888c3e90ef2a0b07a9270c368fb6e 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_high_bw.vhd
@@ -76,9 +76,7 @@ entity tb_eth_tester_high_bw is
);
end tb_eth_tester_high_bw;
-
architecture tb of tb_eth_tester_high_bw is
-
constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : "; -- use to distinguish logging from tb instances in tb_tb
constant mm_clk_period : time := 10 ns; -- 100 MHz
constant c_nof_st_clk_per_s : natural := 200 * 10**6;
@@ -199,9 +197,7 @@ architecture tb of tb_eth_tester_high_bw is
signal dbg_c_mon_nof_valid_first_rx : natural := c_mon_nof_valid_first_rx;
signal dbg_c_mon_nof_valid_others_tx : natural := c_mon_nof_valid_others_tx;
signal dbg_c_mon_nof_valid_others_rx : natural := c_mon_nof_valid_others_rx;
-
begin
-
tb_end <= i_tb_end;
mm_clk <= (not mm_clk) or i_tb_end after mm_clk_period / 2;
@@ -248,8 +244,6 @@ begin
---------------------------------------------------------------------------
v_udp_dst_port := TO_UINT(c_eth_tester_udp_dst_port);
-
-
for I in g_nof_streams - 1 downto 0 loop
v_offset := I * c_eth_tester_reg_hdr_dat_addr_span;
-- Set destination MAC/IP/UDP port in tx header, increment udp_dst_port per stream
@@ -278,7 +272,6 @@ begin
proc_mem_mm_bus_wr(v_offset + 7, 0, mm_clk, reg_bg_ctrl_copi); -- high part
-- Enable the BG at st_pps pulse.
proc_mem_mm_bus_wr(v_offset + 0, 3, mm_clk, reg_bg_ctrl_copi);
-
end loop;
proc_common_wait_some_cycles(mm_clk, 10);
-- Issue an st_pps pulse to start the enabled BG
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
index b2260a9785c249c5d595ca0de12fdc8bee04ac51..b5075a71f6009c929843d7f520d8e3e41f1d0abf 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_tester_pkg.vhd
@@ -34,7 +34,6 @@ use common_lib.common_network_layers_pkg.all;
use work.eth_tester_pkg.all;
package tb_eth_tester_pkg is
-
constant c_eth_tester_eth_dst_mac : std_logic_vector(47 downto 0) := x"001B217176B9"; -- 001B217176B9 = DOP36-enp2s0
constant c_eth_tester_ip_dst_addr : std_logic_vector(31 downto 0) := x"0A6300FE"; -- 0A6300FE = '10.99.0.254' = DOP36-enp2s0
constant c_eth_tester_udp_dst_port : std_logic_vector(15 downto 0) := c_eth_tester_udp_port;
@@ -44,12 +43,9 @@ package tb_eth_tester_pkg is
-- Ethernet packet lenght on link including c_network_eth_preamble_len and one idle word
function func_eth_tester_eth_packet_on_link_length(block_len : natural) return natural;
-
end tb_eth_tester_pkg;
-
package body tb_eth_tester_pkg is
-
function func_eth_tester_eth_packet_length(block_len : natural) return natural is
constant c_app_len : natural := c_eth_tester_app_hdr_len + block_len;
constant c_udp_len : natural := c_network_udp_header_len + c_app_len;
@@ -65,4 +61,3 @@ package body tb_eth_tester_pkg is
end func_eth_tester_eth_packet_on_link_length;
end tb_eth_tester_pkg;
-
diff --git a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
index 12968aa8fe6aad14a836b1eb7b8b613e087f0f46..14ea6f5af14c79e8bfce4a7af8df7af9d0d532e9 100644
--- a/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_eth_udp_offload.vhd
@@ -46,9 +46,7 @@ entity tb_eth_udp_offload is
);
end tb_eth_udp_offload;
-
architecture tb of tb_eth_udp_offload is
-
-- tb default
constant c_rl : natural := 1;
constant c_pulse_active : natural := 1;
@@ -221,9 +219,7 @@ architecture tb of tb_eth_udp_offload is
signal dut_eth_init : std_logic := '1';
signal dut_tse_init : std_logic := '1';
-
begin
-
mm_clk <= (not mm_clk) or tb_end after c_mm_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * 20;
@@ -268,7 +264,6 @@ begin
wait;
end process;
-
------------------------------------------------------------------------------
-- DATA GENERATION
------------------------------------------------------------------------------
@@ -496,5 +491,4 @@ begin
src_in => udp_rx_siso,
src_out => udp_rx_sosi
);
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
index 7ee620708c377aa1eac014de4711b2ab82ac0261..f0db304df319bc52e955ad8d7fe7bbc449bdcc80 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth.vhd
@@ -33,24 +33,19 @@ use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
-
entity tb_tb_eth is
generic (
g_technology_dut : natural := c_tech_select_default
);
end tb_tb_eth;
-
architecture tb of tb_tb_eth is
-
constant c_technology_lcu : natural := c_tech_select_default;
constant c_tb_end_vec : std_logic_vector(15 downto 0) := (others => '1');
signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
-
begin
-
-- g_technology_dut : NATURAL := c_tech_select_default;
-- g_technology_lcu : NATURAL := c_tech_select_default;
-- g_sim : BOOLEAN := FALSE;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd
index 51931716735b4f0b21decfb7048ffae67d70325f..3c0b451544d7a5bb79d6c094732410bd7867a345 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_ip_header_checksum.vhd
@@ -30,13 +30,9 @@ use dp_lib.tb_dp_pkg.all; -- for t_dp_flow_control_enum
entity tb_tb_eth_ip_header_checksum is
end tb_tb_eth_ip_header_checksum;
-
architecture tb of tb_tb_eth_ip_header_checksum is
-
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
-
begin
-
-- -- general
-- g_flow_control_stimuli : t_dp_flow_control_enum := e_pulse; -- always e_active, e_random or e_pulse flow control
-- g_flow_control_verify : t_dp_flow_control_enum := e_active; -- always e_active, e_random or e_pulse flow control
@@ -60,5 +56,4 @@ begin
u_rnd_act_data_64_symbol_32 : entity work.tb_eth_ip_header_checksum generic map (e_random, e_active, false, 64, 32, 1, 240, 16);
u_rnd_act_data_32_symbol_8 : entity work.tb_eth_ip_header_checksum generic map (e_random, e_active, false, 32, 8, 1, 240, 16);
u_rnd_act_data_32_symbol_16 : entity work.tb_eth_ip_header_checksum generic map (e_random, e_active, false, 32, 16, 1, 240, 16);
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd
index cc880667d1c7d9a59c09a1bcd61d04d36ba6a3ef..6ec8e8ecb7bfe6a025742a7c1deb774f97820fb2 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_stream_udp.vhd
@@ -34,7 +34,6 @@ entity tb_tb_eth_stream_udp is
end tb_tb_eth_stream_udp;
architecture tb of tb_tb_eth_stream_udp is
-
-- Tb
constant c_eth_clk_MHz : natural := 125;
constant c_st_clk_MHz : natural := 200;
@@ -56,9 +55,7 @@ architecture tb of tb_tb_eth_stream_udp is
constant c_high : natural := c_diag_bg_mem_max_adr; -- = 2**24
constant c_bg_ctrl : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_gap_len, 0, c_high, 0); -- for first stream
-
begin
-
-- g_tb_index : NATURAL := 0; -- use to incremental delay logging from tb instances in tb_tb
-- g_nof_sync : NATURAL := 2; -- number of BG sync intervals to set c_run_time
-- g_udp_port_match : BOOLEAN := TRUE;
@@ -76,5 +73,4 @@ begin
u_udp : entity work.tb_eth_stream_udp generic map (0, c_nof_sync, true, c_bg_ctrl);
u_udp_mismatch : entity work.tb_eth_stream_udp generic map (1, c_nof_sync, false, c_bg_ctrl);
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
index 05b5190526f58b65a1f9c98b2afab4087b402297..5d5731ec82e95da17408db28991dd942aa916a9f 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester.vhd
@@ -39,7 +39,6 @@ entity tb_tb_eth_tester is
end tb_tb_eth_tester;
architecture tb of tb_tb_eth_tester is
-
-- Multi tb
constant c_tb_w : natural := 100; -- sufficiently long to fit all tb instances
constant c_tb_end_vec : std_logic_vector(c_tb_w - 1 downto 0) := (others => '1');
@@ -95,9 +94,7 @@ architecture tb of tb_tb_eth_tester is
constant c_bg_ctrl_multiple_first : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0); -- for first stream
constant c_bg_ctrl_multiple_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0); -- for other streams
-
begin
-
-- g_tb_index : NATURAL := 0; -- use to incremental delay logging from tb instances in tb_tb
-- g_nof_sync : NATURAL := 3; -- number of BG sync intervals to set c_run_time
-- g_nof_streams : NATURAL := 2;
@@ -227,5 +224,4 @@ begin
report "Multi tb simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd
index b96f739e0f2453187ae6d7cd3f3eb69468891ca0..b22af44ba50ef79cfff39471a0cb3f0b312ba25a 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_eth_tester_high_bw.vhd
@@ -38,7 +38,6 @@ entity tb_tb_eth_tester_high_bw is
end tb_tb_eth_tester_high_bw;
architecture tb of tb_tb_eth_tester_high_bw is
-
-- Multi tb
constant c_tb_w : natural := 100; -- sufficiently long to fit all tb instances
constant c_tb_end_vec : std_logic_vector(c_tb_w - 1 downto 0) := (others => '1');
@@ -91,9 +90,7 @@ architecture tb of tb_tb_eth_tester_high_bw is
constant c_bg_ctrl_multiple_first : t_diag_block_gen_integer := ('1', '1', c_block_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0); -- for first stream
constant c_bg_ctrl_multiple_others : t_diag_block_gen_integer := ('1', '1', c_others_len, c_nof_blk, c_nof_streams * c_gap_len, 0, c_high, 0); -- for other streams
-
begin
-
-- g_tb_index : NATURAL := 0; -- use to incremental delay logging from tb instances in tb_tb
-- g_nof_sync : NATURAL := 3; -- number of BG sync intervals to set c_run_time
-- g_nof_streams : NATURAL := 2;
@@ -115,7 +112,6 @@ begin
-- Tb instance prefix:
-- . u_st : uses streaming Tx-Rx interface
-
-----------------------------------------------------------------------------
-- Single stream
-----------------------------------------------------------------------------
@@ -136,8 +132,6 @@ begin
c_bg_ctrl_rst)
port map (tb_end_vec(11));
-
-
-- Try small block sizes at 64*8 = 512b bus size
-- . BG supports samples_per_packet >= 2, BG treats samples_per_packet = 1 as 2
-- . ETH MAC pads samples_per_packet <= 6 to 6, to have minimum packet length of 64 octets,
@@ -147,7 +141,6 @@ begin
c_bg_ctrl_rst)
port map (tb_end_vec(20));
-
-- Try different BG block lengths and data widths to verify sosi.empty nof octets in last word and repack.
u_st_bg_len_0 : entity work.tb_eth_tester_high_bw generic map (30, c_nof_sync, 1, 64, 8, c_bg_ctrl_len_0, c_bg_ctrl_rst) port map (tb_end_vec(30));
u_st_bg_len_1 : entity work.tb_eth_tester_high_bw generic map (31, c_nof_sync, 1, 8, 1, c_bg_ctrl_len_1, c_bg_ctrl_rst) port map (tb_end_vec(31));
@@ -163,7 +156,6 @@ begin
c_bg_ctrl_multiple_others)
port map (tb_end_vec(80));
-
tb_end <= '1' when tb_end_vec = c_tb_end_vec else '0';
p_tb_end : process
@@ -173,5 +165,4 @@ begin
report "Multi tb simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/io/eth/tb/vhdl/tb_tb_tb_eth_regression.vhd b/libraries/io/eth/tb/vhdl/tb_tb_tb_eth_regression.vhd
index a4627b1e2cf54d83009ea683a5ae5d28c62ac052..e7a93ddbbe38fcb5426812fe4739be7dbceb4f4a 100644
--- a/libraries/io/eth/tb/vhdl/tb_tb_tb_eth_regression.vhd
+++ b/libraries/io/eth/tb/vhdl/tb_tb_tb_eth_regression.vhd
@@ -34,12 +34,10 @@ end tb_tb_tb_eth_regression;
architecture tb of tb_tb_tb_eth_regression is
begin
-
u_tb_tb_eth : entity work.tb_tb_eth;
u_tb_eth_hdr : entity work.tb_eth_hdr;
u_tb_eth_checksum : entity work.tb_eth_checksum;
u_tb_eth_crc_ctrl : entity work.tb_eth_crc_ctrl;
u_tb_eth_udp_offload : entity work.tb_eth_udp_offload;
u_tb_eth_IHL_to_20 : entity work.tb_eth_IHL_to_20;
-
end tb;
diff --git a/libraries/io/eth1g/src/vhdl/eth1g.vhd b/libraries/io/eth1g/src/vhdl/eth1g.vhd
index 79d3543ff849edc3d8953d38257db12f5ce857de..1e957edd5c04899dd31cbb2919c3f65059aab44a 100644
--- a/libraries/io/eth1g/src/vhdl/eth1g.vhd
+++ b/libraries/io/eth1g/src/vhdl/eth1g.vhd
@@ -86,9 +86,7 @@ entity eth1g is
);
end eth1g;
-
architecture str of eth1g is
-
------------------------------------------------------------------------------
-- ETH Rx packet buffer and Tx packet buffer
------------------------------------------------------------------------------
@@ -197,9 +195,7 @@ architecture str of eth1g is
signal tse_rx_siso : t_dp_siso;
-- . MAC specific
signal tse_rx_mac_out : t_tech_tse_rx_mac;
-
begin
-
------------------------------------------------------------------------------
-- MM registers
------------------------------------------------------------------------------
@@ -260,7 +256,6 @@ begin
mem_in_endian <= func_mem_swap_endianess(mem_in, c_word_sz);
mem_out <= func_mem_swap_endianess(mem_out_endian, c_word_sz);
-
------------------------------------------------------------------------------
-- RX : Adapt the TSE RX source ready latency from 2 to 1
------------------------------------------------------------------------------
@@ -325,7 +320,6 @@ begin
rx_crc_siso <= rx_ihl20_siso;
end generate;
-
------------------------------------------------------------------------------
-- RX : For IP verify IP header checksum
------------------------------------------------------------------------------
@@ -383,7 +377,6 @@ begin
frm_discard_val => rx_frm_discard_val
);
-
------------------------------------------------------------------------------
-- Demux the UDP off-load traffic and the keep the other ETH traffic
------------------------------------------------------------------------------
@@ -436,7 +429,6 @@ begin
demux_siso_arr(i) <= udp_rx_src_in_arr(i - 1);
end generate;
-
------------------------------------------------------------------------------
-- ETH RX frame buffer
------------------------------------------------------------------------------
@@ -465,7 +457,6 @@ begin
flushed_frm_cnt => rx_flushed_frm_cnt
);
-
------------------------------------------------------------------------------
-- ETH RX frame monitor
------------------------------------------------------------------------------
@@ -520,7 +511,6 @@ begin
reg_frame => reg_frame
);
-
------------------------------------------------------------------------------
-- ETH Control
------------------------------------------------------------------------------
@@ -555,7 +545,6 @@ begin
mem_out => mem_out
);
-
------------------------------------------------------------------------------
-- TX : Mux UDP
------------------------------------------------------------------------------
@@ -620,7 +609,6 @@ begin
src_out => tx_hdr_sosi
);
-
------------------------------------------------------------------------------
-- TSE MAC
------------------------------------------------------------------------------
@@ -664,5 +652,4 @@ begin
-- LED interface
tse_led => tse_led
);
-
end str;
diff --git a/libraries/io/eth1g/src/vhdl/eth1g_master.vhd b/libraries/io/eth1g/src/vhdl/eth1g_master.vhd
index 8b090c53b8e30ad58358a382b5f4b1b7043e4d62..e96e339728011ec605ddd33938b177faf9be0984 100644
--- a/libraries/io/eth1g/src/vhdl/eth1g_master.vhd
+++ b/libraries/io/eth1g/src/vhdl/eth1g_master.vhd
@@ -41,7 +41,6 @@ use eth_lib.eth_pkg.all;
use technology_lib.technology_select_pkg.all;
use work.eth1g_mem_pkg.all;
-
entity eth1g_master is
generic (
g_sim : boolean := false -- when true speed up led toggling in simulation
@@ -64,7 +63,6 @@ entity eth1g_master is
end eth1g_master;
architecture rtl of eth1g_master is
-
-- ETH control
constant c_reply_payload : boolean := false; -- TRUE copy rx payload into response payload, else header only (e.g. for ARP)
@@ -148,7 +146,6 @@ architecture rtl of eth1g_master is
signal lat_ram_vec : std_logic_vector(0 to lat_vec_size-1);
signal ram_rd_valid : std_logic;
-
-- Write data to the MM bus
procedure proc_eth1g_mem_mm_bus_wr(constant wr_addr : in natural;
constant wr_data : in integer;
@@ -159,7 +156,6 @@ architecture rtl of eth1g_master is
mm_mosi.wr := '1';
end proc_eth1g_mem_mm_bus_wr;
-
procedure proc_eth1g_mem_mm_bus_wr(constant wr_addr : in natural;
signal wr_data : in std_logic_vector;
variable mm_mosi : out t_mem_mosi) is
@@ -175,9 +171,7 @@ architecture rtl of eth1g_master is
mm_mosi.address := TO_MEM_ADDRESS(wr_addr);
mm_mosi.rd := '1';
end proc_eth1g_mem_mm_bus_rd;
-
begin
-
tse_mosi <= r.tse_mosi;
reg_mosi <= r.reg_mosi;
ram_mosi <= r.ram_mosi;
@@ -198,7 +192,6 @@ begin
--END PROCESS;
mm_init <= '0' when rising_edge(mm_clk) and mm_rst = '0'; -- concurrent statement is equivalent to commented p_mm_init
-
p_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -208,7 +201,6 @@ begin
end if;
end process p_reg;
-
p_rd_latency : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -228,7 +220,6 @@ begin
reg_rd_valid <= lat_reg_vec(c_mem_reg_rd_latency);
ram_rd_valid <= lat_ram_vec(c_mem_ram_rd_latency);
-
p_comb : process (r.state, reg_miso, ram_miso, tse_miso, reg_interrupt, mm_init, reg_rd_valid, ram_rd_valid)
variable v : t_reg;
variable v_eth_control_word : std_logic_vector(c_word_w - 1 downto 0);
@@ -449,12 +440,9 @@ begin
end case;
nxt_r <= v;
-
end process p_comb;
-
end;
-
--ARCHITECTURE beh OF eth1g_master IS
-- -- ETH control
diff --git a/libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd b/libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd
index 5dbb11176fc6fb31f94a918a12232fb36c856b2c..2829040000ac3f5f9a1f81185e1f8140da71b1d8 100644
--- a/libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd
+++ b/libraries/io/eth1g/src/vhdl/eth1g_mem_pkg.vhd
@@ -37,7 +37,6 @@ use common_lib.common_network_layers_pkg.all;
use common_lib.common_network_total_header_pkg.all;
use tech_tse_lib.tech_tse_pkg.all;
-
package eth1g_mem_pkg is
------------------------------------------------------------------------------
-- MM bus access functions
@@ -89,10 +88,8 @@ package eth1g_mem_pkg is
signal mm_clk : in std_logic;
signal mm_miso : in t_mem_miso;
signal mm_mosi : out t_mem_mosi);
-
end eth1g_mem_pkg;
-
package body eth1g_mem_pkg is
------------------------------------------------------------------------------
-- Private functions
@@ -106,8 +103,8 @@ package body eth1g_mem_pkg is
if rising_edge(mm_clk) then
mm_access <= '0';
end if;
- end proc_mm_access;
+ end proc_mm_access;
-- Issues a rd or a wr MM access and wait for it to have finished
procedure proc_mm_access(signal mm_clk : in std_logic;
@@ -123,7 +120,6 @@ package body eth1g_mem_pkg is
end proc_mm_access;
-
function func_map_pcs_addr(pcs_addr : natural) return natural is
begin
return pcs_addr * 2 + c_tech_tse_byte_addr_pcs_offset;
@@ -146,7 +142,6 @@ package body eth1g_mem_pkg is
end proc_mem_mm_bus_wr;
-
procedure proc_mem_mm_bus_wr(constant wr_addr : in integer;
signal wr_data : in std_logic_vector;
signal mm_clk : in std_logic;
@@ -158,7 +153,6 @@ package body eth1g_mem_pkg is
proc_mm_access(mm_clk, mm_miso.waitrequest, mm_mosi.wr);
end proc_mem_mm_bus_wr;
-
-- Read data request to the MM bus
-- Use proc_mem_mm_bus_rd_latency() to wait for the MM MISO rd_data signal
-- to show the data after some read latency
@@ -173,7 +167,6 @@ package body eth1g_mem_pkg is
mm_mosi.rd <= '0';
end proc_mem_mm_bus_rd;
-
-- Wait for read data valid after read latency mm_clk cycles
-- Directly assign mm_miso.rddata to capture the read data
procedure proc_mem_mm_bus_rd_latency(constant c_rd_latency : in natural;
@@ -182,7 +175,6 @@ package body eth1g_mem_pkg is
for I in 0 to c_rd_latency - 1 loop wait until rising_edge(mm_clk); end loop;
end proc_mem_mm_bus_rd_latency;
-
function func_tech_tse_header_size(data_type : natural) return natural is
begin
case data_type is
@@ -193,7 +185,6 @@ package body eth1g_mem_pkg is
return c_network_total_header_32b_nof_words;
end func_tech_tse_header_size;
-
-- . The src_mac[47:0] = 0x123456789ABC for MAC address 12-34-56-78-9A-BC
procedure proc_tech_tse_setup(constant c_promis_en : in boolean;
constant c_tse_tx_fifo_depth : in natural;
diff --git a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
index 6a8a5081ff8de2e8d529a142bac7900470b06cc5..1c7c417a59305b593829531394b9817d3c6799a6 100644
--- a/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
+++ b/libraries/io/eth1g/tb/vhdl/tb_eth1g.vhd
@@ -39,7 +39,6 @@
-- > as 10
-- > run -all
-
library IEEE, common_lib, dp_lib, technology_lib, eth_lib, tech_tse_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -55,7 +54,6 @@ use tech_tse_lib.tech_tse_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
use eth_lib.eth_pkg.all;
-
entity tb_eth1g is
-- Test bench control parameters
generic (
@@ -76,7 +74,6 @@ entity tb_eth1g is
);
end tb_eth1g;
-
architecture tb of tb_eth1g is
constant c_sim : boolean := false; -- TRUE;
constant c_sim_level : natural := 1; -- 0 = use IP; 1 = use fast serdes model;
@@ -253,7 +250,6 @@ architecture tb of tb_eth1g is
signal udp_rx_siso_arr : t_dp_siso_arr(c_eth_nof_udp_ports - 1 downto 0);
signal udp_rx_sosi_arr : t_dp_sosi_arr(c_eth_nof_udp_ports - 1 downto 0);
-
-- LCU TSE interface
signal lcu_init : std_logic := '1';
signal lcu_tse_miso : t_mem_miso;
@@ -279,9 +275,7 @@ architecture tb of tb_eth1g is
signal rx_pkt_cnt : natural := 0;
signal rx_pkt_discarded_cnt: natural := 0;
signal rx_pkt_flushed_cnt : std_logic_vector(c_word_w - 1 downto 0);
-
begin
-
-- run 50 us
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
@@ -341,7 +335,6 @@ begin
wait;
end process;
-
p_eth_control : process
variable v_eth_control_word : std_logic_vector(c_word_w - 1 downto 0);
begin
@@ -508,7 +501,6 @@ begin
wait;
end process;
-
p_lcu_receiver : process
begin
-- . Avalon ST
@@ -666,5 +658,4 @@ begin
end if;
wait;
end process;
-
end tb;
diff --git a/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd b/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd
index 49c109dd9059e53777161e746bc264cb3fc697ae..98f9c0ae048fd7bf6a2ebfe6a8947a6712c1ae93 100644
--- a/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd
+++ b/libraries/io/eth1g/tb/vhdl/tb_tb_eth1g.vhd
@@ -33,24 +33,19 @@ use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
-
entity tb_tb_eth1g is
generic (
g_technology_dut : natural := c_tech_select_default
);
end tb_tb_eth1g;
-
architecture tb of tb_tb_eth1g is
-
constant c_technology_lcu : natural := c_tech_select_default;
constant c_tb_end_vec : std_logic_vector(15 downto 0) := (others => '1');
signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
-
begin
-
-- g_technology_dut : NATURAL := c_tech_select_default;
-- g_technology_lcu : NATURAL := c_tech_select_default;
-- g_frm_discard_en : BOOLEAN := TRUE; -- when TRUE discard frame types that would otherwise have to be discarded by the Nios MM master
diff --git a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
index b986b1dc124060cd80eb27ba20bed73adc9ac738..35261ba170dfffbae5967509bb1e84a9ad4b004c 100644
--- a/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
+++ b/libraries/io/fpga_sense/src/vhdl/fpga_sense.vhd
@@ -26,7 +26,6 @@
-- Which states Temperature = ( (A * C) / 1024 ) - B
-- Where A = 693, B = 265, C = decimal value of tempout[9..0] (unsigned)
-
library IEEE, common_lib, technology_lib, tech_fpga_temp_sens_lib, tech_fpga_voltage_sens_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -36,7 +35,6 @@ use technology_lib.technology_select_pkg.all;
use technology_lib.technology_pkg.all;
--USE tech_temp_sense_lib.tech_temp_sense_component_pkg.ALL;
-
entity fpga_sense is
generic (
g_technology : natural := c_tech_select_default;
@@ -59,9 +57,7 @@ entity fpga_sense is
);
end fpga_sense;
-
architecture str of fpga_sense is
-
-- constants for the temperature sensor
constant c_mem_reg_temp_adr_w : natural := 1;
constant c_mem_reg_temp_dat_w : natural := 32;
@@ -88,11 +84,10 @@ architecture str of fpga_sense is
-- bits 9:8 = "00" select channels 2-7
-- bits 2:1 = "00" select single conversion
-- bit 0 = '1' set the self-clearing run bit
-
begin
-
-- temperature sensor
temp_alarm <= '1' when (unsigned(temp_data) > unsigned(c_temp_high_raw)) else '0';
+
gen_tech_fpga_temp_sens: if g_sim = false generate
u_tech_fpga_temp_sens : entity tech_fpga_temp_sens_lib.tech_fpga_temp_sens
generic map (
@@ -151,7 +146,6 @@ begin
out_reg => open
);
-
-- voltage sensor
no_tech_fpga_voltage_sens: if g_sim = true generate
-- Model the voltage sensor by returning the MM register address of the voltage field
@@ -200,6 +194,4 @@ begin
end generate;
-
-
end str;
diff --git a/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd b/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
index 5330d16ea9fa73adeecae270afba9fdc659d7574..389c96fb2fa8618a86ac1229b8741c4a48083abb 100644
--- a/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
+++ b/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use work.i2c_pkg.all;
-
-- Need to wrap i2c_master with this avs_i2c_master, because the SOPC Component
-- Editor does not support the user defined types from i2c_pkg.
@@ -106,18 +105,13 @@ entity avs_i2c_master is
);
end avs_i2c_master;
-
architecture wrap of avs_i2c_master is
-
constant c_avs_i2c_mm : t_c_i2c_mm := (g_control_adr_w, g_protocol_adr_w, 2**g_protocol_adr_w, g_result_adr_w, 2**g_result_adr_w);
constant c_avs_i2c_phy : t_c_i2c_phy := (g_clk_cnt, g_comma_w);
-
signal cs_sim : boolean;
signal i_avs_control_address : std_logic_vector(0 downto 0);
-
begin
-
-- SOPC Builder does not use BOOLEAN, so use STD_LOGIC and is_true()
cs_sim <= is_true(coe_gs_sim_export);
@@ -167,6 +161,4 @@ begin
scl => coe_i2c_scl_export,
sda => coe_i2c_sda_export
);
-
end wrap;
-
diff --git a/libraries/io/i2c/src/vhdl/i2c_bit.vhd b/libraries/io/i2c/src/vhdl/i2c_bit.vhd
index 5fac1e59711d03422908143caa5a30f04f6f55e9..f2685c2b704c6dcf9c1041f2408041f4e0a0fb7d 100644
--- a/libraries/io/i2c/src/vhdl/i2c_bit.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_bit.vhd
@@ -108,7 +108,6 @@
-- Added headers.
--
-
--
-------------------------------------
-- Bit controller section
@@ -198,7 +197,6 @@ architecture rtl of i2c_bit is
signal ial : std_logic; -- internal arbitration lost signal
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
-
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
@@ -239,7 +237,6 @@ begin
end if;
end process gen_clken;
-
-- generate bus status controller
bus_status_ctrl: block
signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
@@ -307,7 +304,6 @@ begin
end process gen_busy;
busy <= ibusy;
-
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
@@ -335,7 +331,6 @@ begin
-- else
-- ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
-- end if;
-
end if;
end if;
end process gen_al;
@@ -352,7 +347,6 @@ begin
end process gen_dout;
end block bus_status_ctrl;
-
-- generate statemachine
nxt_state_decoder : process (clk, nReset)
begin
@@ -499,18 +493,15 @@ begin
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
-
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture rtl;
-
diff --git a/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd b/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd
index 942246ebefede8eeb01196a57fc952f39b16a24b..81cd7c0a85b7107218a049c38919e9aa1ea2d2c8 100644
--- a/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_bit_scl_sense.vhd
@@ -108,7 +108,6 @@
-- Added headers.
--
-
--
-------------------------------------
-- Bit controller section
@@ -198,7 +197,6 @@ architecture rtl of i2c_bit_scl_sense is
signal ial : std_logic; -- internal arbitration lost signal
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
-
begin
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
-- delay scl_oen
@@ -239,7 +237,6 @@ begin
end if;
end process gen_clken;
-
-- generate bus status controller
bus_status_ctrl: block
signal dSCL, dSDA : std_logic; -- delayes sSCL and sSDA
@@ -307,7 +304,6 @@ begin
end process gen_busy;
busy <= ibusy;
-
-- generate arbitration lost signal
-- aribitration lost when:
-- 1) master drives SDA high, but the i2c bus is low
@@ -335,7 +331,6 @@ begin
else
ial <= (sda_chk and not sSDA and isda_oen) or (sto_condition and not cmd_stop);
end if;
-
end if;
end if;
end process gen_al;
@@ -352,7 +347,6 @@ begin
end process gen_dout;
end block bus_status_ctrl;
-
-- generate statemachine
nxt_state_decoder : process (clk, nReset)
begin
@@ -499,18 +493,15 @@ begin
sda_chk <= '0'; -- don't check SDA (SCL low)
when others =>
-
end case;
end if;
end if;
end if;
end process nxt_state_decoder;
-
-- assign outputs
scl_o <= '0';
scl_oen <= iscl_oen;
sda_o <= '0';
sda_oen <= isda_oen;
end architecture rtl;
-
diff --git a/libraries/io/i2c/src/vhdl/i2c_byte.vhd b/libraries/io/i2c/src/vhdl/i2c_byte.vhd
index 66b08fb84b4e18de03c3f0f797fd95eb37fb1207..1460a8c2728ffc8a2c3af891cf39a1163ddcdffb 100644
--- a/libraries/io/i2c/src/vhdl/i2c_byte.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_byte.vhd
@@ -81,9 +81,6 @@
-- Added headers.
--
-
-
-
--
------------------------------------------
-- Byte controller section
@@ -204,7 +201,6 @@ architecture structural of i2c_byte is
signal go, host_ack : std_logic;
signal dcnt : unsigned(2 downto 0); -- data counter
signal cnt_done : std_logic;
-
begin
-- hookup bit_controller
gen_bit_ctrl : if g_clock_stretch_sense_scl = false generate
@@ -228,6 +224,7 @@ begin
sda_oen => sda_oen
);
end generate;
+
gen_bit_ctrl_scl_sense : if g_clock_stretch_sense_scl = true generate
bit_ctrl_scl_sense: i2c_bit_scl_sense port map(
clk => clk,
@@ -249,6 +246,7 @@ begin
sda_oen => sda_oen
);
end generate;
+
i2c_al <= al;
-- generate host-command-acknowledge
@@ -424,14 +422,9 @@ begin
c_state <= st_idle;
core_cmd <= I2C_CMD_NOP;
report ("Byte controller entered illegal state.");
-
end case;
-
end if;
end if;
end process nxt_state_decoder;
-
end block statemachine;
-
end architecture structural;
-
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander.vhd b/libraries/io/i2c/src/vhdl/i2c_commander.vhd
index 6e48c42a83f2680ac6e0c5cbc1705e6fdb528462..97c57a07b7176f32df7811d3e331de2fd6dff832 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander.vhd
@@ -64,7 +64,6 @@
-- one mask word or they have to occur periodically. This can be achieved
-- by inserting SMBUS_C_NOP in the protocol list.
-
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -110,9 +109,7 @@ entity i2c_commander is
);
end i2c_commander;
-
architecture str of i2c_commander is
-
-- Use MM bus data width = SMBus data width = c_byte_w
constant c_ram_rd_latency : natural := 1; -- instead of c_mem_ram_rd_latency = 2
@@ -161,9 +158,7 @@ architecture str of i2c_commander is
signal smbus_out_ack : std_logic;
signal smbus_st_idle : std_logic;
signal smbus_st_end : std_logic;
-
begin
-
u_commander_reg : entity work.i2c_commander_reg
generic map (
g_i2c_cmdr => g_i2c_cmdr,
@@ -219,7 +214,6 @@ begin
result_ready_evt => result_ready_evt
);
-
-- Activate pending protocol at sync control
u_protocol_activate : entity common_lib.common_request
port map (
@@ -233,7 +227,6 @@ begin
-- Result ready control
result_ready_evt <= smbus_st_end;
-
u_protocol_ctrl : entity work.i2c_list_ctrl
generic map (
g_protocol_adr_w => g_i2c_mm.protocol_adr_w,
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_aduh_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_aduh_pkg.vhd
index 83f489b245ed3f25b09997c5a37d01ed29f7fe7f..befe290e7b1a3a79065a26b9e01bb8c5617d9e8a 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_aduh_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_aduh_pkg.vhd
@@ -28,9 +28,7 @@ use work.i2c_pkg.all;
use work.i2c_commander_pkg.all;
use work.i2c_dev_adu_pkg.all;
-
package i2c_commander_aduh_pkg is
-
------------------------------------------------------------------------------
-- Local constants (with prefix 'k_')
------------------------------------------------------------------------------
@@ -186,7 +184,6 @@ package i2c_commander_aduh_pkg is
constant k_nof_result_data_max : natural := 2; -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init, choose 2 to also suit I2C read word
constant k_result_cnt_w : natural := k_result_adr_w;
-
------------------------------------------------------------------------------
-- Global constants (with prefix 'c_i2c_cmdr_aduh_')
------------------------------------------------------------------------------
@@ -216,8 +213,6 @@ package i2c_commander_aduh_pkg is
k_result_adr_w,
2**k_result_adr_w);
-
-
-- MM register map:
--
-- . c_i2c_cmdr_aduh_protocol_commander.nof_protocols = 16
@@ -272,9 +267,7 @@ package i2c_commander_aduh_pkg is
-- func_i2c_cmdr_mm_reg_nof_dat(c_i2c_cmdr_aduh_protocol_commander) -->
-- 3*nof_protocols + 1 + 1 + nof_result_data_max = 3*16 + 1 + 1 + 2 = 52
-- k_commander_adr_w = ceil_log2(k_commander_nof_dat) = ceil_log2(52) = 6
-
end i2c_commander_aduh_pkg;
-
package body i2c_commander_aduh_pkg is
end i2c_commander_aduh_pkg;
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_ctrl.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_ctrl.vhd
index dd40cfac8e00a7b2b58d01519236d5d672c50afb..549f5ee46e320208c798f647de1ca1531c5bf1d3 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_ctrl.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_ctrl.vhd
@@ -61,9 +61,7 @@ entity i2c_commander_ctrl is
);
end entity;
-
architecture rtl of i2c_commander_ctrl is
-
constant c_expected_bi_w : natural := ceil_log2(c_word_w);
signal state : natural range 0 to c_i2c_cmdr_state_max;
@@ -81,10 +79,7 @@ architecture rtl of i2c_commander_ctrl is
signal nxt_data_cnt : natural;
signal data_arr : t_slv_32_arr(0 to g_i2c_cmdr.nof_result_data_max);
signal nxt_data_arr : t_slv_32_arr(0 to g_i2c_cmdr.nof_result_data_max);
-
-
begin
-
protocol_offset <= i_protocol_offset;
protocol_activate <= i_protocol_activate;
@@ -171,5 +166,4 @@ begin
end if;
end if;
end process;
-
end rtl;
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_pkg.vhd
index 8852bb61ab9319b7dceef579f518f070ed52777f..4048565c321bfbd061cd4e7aa1a76fe0ac0a1058 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_pkg.vhd
@@ -26,7 +26,6 @@ use work.i2c_pkg.all;
use work.i2c_smbus_pkg.all;
package i2c_commander_pkg is
-
-- I2C commander settings
--
constant c_i2c_cmdr_state_idle : natural := 0; -- no protocol active
@@ -86,9 +85,7 @@ package i2c_commander_pkg is
end i2c_commander_pkg;
-
package body i2c_commander_pkg is
-
function func_i2c_cmdr_mm_reg_nof_dat(rec : t_c_i2c_cmdr_commander) return natural is
-- Example MM register map defined for:
-- . c_nof_protocols = 2
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_reg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_reg.vhd
index 84a218bbf425bd9b4aa10016f5f3f3a41c2659b3..818be9fceaae95202943b901972a1ebf7a708c5f 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_reg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_reg.vhd
@@ -59,9 +59,7 @@ entity i2c_commander_reg is
);
end i2c_commander_reg;
-
architecture rtl of i2c_commander_reg is
-
-- Use shorter aliases for some generic constants
constant c_nof_protocols : natural := g_i2c_cmdr.nof_protocols; -- must be <= c_i2c_max_nof_protocols to fit the t_c_i2c_cmdr_commander record
constant c_nof_result_data_max : natural := g_i2c_cmdr.nof_result_data_max;
@@ -98,9 +96,7 @@ architecture rtl of i2c_commander_reg is
-- Commander registers
signal i_protocol_offset_arr : t_natural_arr(0 to c_nof_protocols - 1);
signal i_result_expected_arr : t_slv_32_arr(0 to c_nof_protocols - 1);
-
begin
-
protocol_offset_arr <= i_protocol_offset_arr;
result_expected_arr <= i_result_expected_arr;
@@ -199,5 +195,4 @@ begin
-- Detect read commander status event (has to be combinatorial to avoid missing the c_i2c_state_done state, because the state depends on the this pulse)
protocol_status_rd <= '1' when sla_in.rd = '1' and TO_UINT(sla_in.address(c_mm_reg.adr_w - 1 downto 0)) = 3 * c_nof_protocols else '0';
-
end rtl;
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd
index 21192d9292fd5c2a4552101e085b9ccb047efc8d..e63ef8691cf5705c7fdb97e2a872be4fce61857d 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_unb2_pmbus_pkg.vhd
@@ -32,9 +32,7 @@ use work.i2c_pkg.all;
use work.i2c_commander_pkg.all;
use work.i2c_dev_unb2_pkg.all;
-
package i2c_commander_unb2_pmbus_pkg is
-
------------------------------------------------------------------------------
-- Local constants (with prefix 'k_')
------------------------------------------------------------------------------
@@ -142,7 +140,6 @@ package i2c_commander_unb2_pmbus_pkg is
constant k_nof_result_data_max : natural := 32; -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init
constant k_result_cnt_w : natural := k_result_adr_w;
-
------------------------------------------------------------------------------
-- Global constants (with prefix 'c_i2c_cmdr_unbh_')
------------------------------------------------------------------------------
@@ -161,9 +158,7 @@ package i2c_commander_unb2_pmbus_pkg is
k_expected_mask_arr,
k_result_cnt_w,
k_nof_result_data_max);
-
end i2c_commander_unb2_pmbus_pkg;
-
package body i2c_commander_unb2_pmbus_pkg is
end i2c_commander_unb2_pmbus_pkg;
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_unb2_sens_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_unb2_sens_pkg.vhd
index 0436317df9d7d08db3483f1f1e90abc32a2dc690..0a140460876ec70a9e53f379412f3d3045cc1a42 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_unb2_sens_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_unb2_sens_pkg.vhd
@@ -32,9 +32,7 @@ use work.i2c_pkg.all;
use work.i2c_commander_pkg.all;
use work.i2c_dev_unb2_pkg.all; -- slave addresses and commands for all unb2 i2c interfaces
-
package i2c_commander_unb2_sens_pkg is
-
------------------------------------------------------------------------------
-- Local constants (with prefix 'k_')
------------------------------------------------------------------------------
@@ -85,7 +83,6 @@ package i2c_commander_unb2_sens_pkg is
k_expected_mask_14,
k_expected_mask_15);
-
-- Define the corresponding expected nof read data
constant k_nof_result_data_0 : natural := c_i2c_unb2_sens_max1617_nof_result_data_read_config;
constant k_nof_result_data_1 : natural := c_i2c_unb2_sens_max1617_nof_result_data_read_temp;
@@ -132,7 +129,6 @@ package i2c_commander_unb2_sens_pkg is
k_protocol_ofs_14,
k_protocol_ofs_15);
-
-- RAM sizes
constant k_protocol_ram_nof_dat : natural := ceil_div(k_protocol_ram_init'LENGTH, c_i2c_cmdr_mem_block_sz) * c_i2c_cmdr_mem_block_sz;
constant k_protocol_ram_adr_w : natural := ceil_log2(k_protocol_ram_nof_dat);
@@ -144,7 +140,6 @@ package i2c_commander_unb2_sens_pkg is
constant k_nof_result_data_max : natural := 32; -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init
constant k_result_cnt_w : natural := k_result_adr_w;
-
------------------------------------------------------------------------------
-- Global constants (with prefix 'c_i2c_cmdr_unbh_')
------------------------------------------------------------------------------
@@ -163,9 +158,7 @@ package i2c_commander_unb2_sens_pkg is
k_expected_mask_arr,
k_result_cnt_w,
k_nof_result_data_max);
-
end i2c_commander_unb2_sens_pkg;
-
package body i2c_commander_unb2_sens_pkg is
end i2c_commander_unb2_sens_pkg;
diff --git a/libraries/io/i2c/src/vhdl/i2c_commander_unbh_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_commander_unbh_pkg.vhd
index d7d30880ebe9ea2e070971112aed8d85d45fb791..61a54ef3fd8434061ed2a81bb7ad1c83a75dccd5 100644
--- a/libraries/io/i2c/src/vhdl/i2c_commander_unbh_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_commander_unbh_pkg.vhd
@@ -32,9 +32,7 @@ use work.i2c_pkg.all;
use work.i2c_commander_pkg.all;
use work.i2c_dev_unb_pkg.all;
-
package i2c_commander_unbh_pkg is
-
------------------------------------------------------------------------------
-- Local constants (with prefix 'k_')
------------------------------------------------------------------------------
@@ -190,7 +188,6 @@ package i2c_commander_unbh_pkg is
constant k_nof_result_data_max : natural := 4; -- Must be >= the maximum nof read bytes in any protocol list in k_protocol_ram_init
constant k_result_cnt_w : natural := k_result_adr_w;
-
------------------------------------------------------------------------------
-- Global constants (with prefix 'c_i2c_cmdr_unbh_')
------------------------------------------------------------------------------
@@ -209,9 +206,7 @@ package i2c_commander_unbh_pkg is
k_expected_mask_arr,
k_result_cnt_w,
k_nof_result_data_max);
-
end i2c_commander_unbh_pkg;
-
package body i2c_commander_unbh_pkg is
end i2c_commander_unbh_pkg;
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd
index 2e74afb214aa093bd60fc6c216361af42569118b..ce9c30ba209608e9e1af18b5596e10f3f501216b 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_adu_pkg.vhd
@@ -26,9 +26,7 @@ use work.i2c_smbus_pkg.all;
use work.i2c_dev_max1617_pkg.all;
use work.i2c_commander_pkg.all;
-
package i2c_dev_adu_pkg is
-
-- I2C slave addresses of the devices on the I2C bus on ADU
constant I2C_ADU_MAX1617_ADR : natural := MAX1617_ADR_LOW_LOW; -- temperature sensor, slave address is "0011000"
constant I2C_ADU_PCA9555_ADR : natural := 16#20#; -- IO expander, slave address is "0100" & A[2:0], A[2:0]= "000"
@@ -51,7 +49,6 @@ package i2c_dev_adu_pkg is
SMBUS_C_END
);
-
-- * IO expander:
-- + IO set
-- . c_i2c_adu_pca9555_protocol_list_set_atten_0_0dB
@@ -74,7 +71,6 @@ package i2c_dev_adu_pkg is
SMBUS_C_END
);
-
-- S4002C040P
-- S4002C440P
-- S4002C040P
@@ -2518,5 +2514,4 @@ package i2c_dev_adu_pkg is
SMBUS_WRITE_BYTE, I2C_ADU_PCA9555_ADR, 16#02#, 16#D0#,
SMBUS_C_END
);
-
end package;
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd
index 98020e8807911d2c29d2e1a5b2c0772e29ccf066..1b02b98698c07ce9c2c7e59709df978c441d3c24 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_ltc4260_pkg.vhd
@@ -20,7 +20,6 @@
-------------------------------------------------------------------------------
package i2c_dev_ltc4260_pkg is
-
-- Positive High Voltage Hot Swap Controller with I2C Compatible Monitoring
constant LTC4260_ADR_MW : natural := 2#1011111#; -- Mass write (broadcast)
@@ -47,5 +46,4 @@ package i2c_dev_ltc4260_pkg is
-- & 0 = Overcurrent Autoretry Disabled
-- & 1 = Undervoltage Autoretry Enabled
-- & 1 = Overvoltage Autoretry Enabled
-
end package;
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_max1617_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_max1617_pkg.vhd
index 2cca11b83985f442117b9d1e40ef28c7eaecffaf..9d2fe2b67eb8f669b6ae7edecb9dbabdf235101c 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_max1617_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_max1617_pkg.vhd
@@ -20,7 +20,6 @@
-------------------------------------------------------------------------------
package i2c_dev_max1617_pkg is
-
-- Also applies to MAX1618
-- ADD0_ADD1
constant MAX1617_ADR_LOW_LOW : natural := 2#0011000#;
@@ -82,5 +81,4 @@ package i2c_dev_max1617_pkg is
constant MAX1617_STATUS_RHIGH : natural := 2**MAX1617_STATUS_RHIGH_BI;
constant MAX1617_STATUS_RLOW : natural := 2**MAX1617_STATUS_RLOW_BI;
constant MAX1617_STATUS_DIODE : natural := 2**MAX1617_STATUS_DIODE_BI;
-
end package;
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_max6652_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_max6652_pkg.vhd
index 17a1a17d5b2f5887f40fe9bef465002edd99ba7b..dc6723ba8f5aa78ae8233d0df269d30842c1327a 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_max6652_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_max6652_pkg.vhd
@@ -20,7 +20,6 @@
-------------------------------------------------------------------------------
package i2c_dev_max6652_pkg is
-
constant MAX6652_ADR_GND : natural := 2#0010100#;
constant MAX6652_ADR_VCC : natural := 2#0010101#;
constant MAX6652_ADR_SDA : natural := 2#0010110#;
@@ -55,5 +54,4 @@ package i2c_dev_max6652_pkg is
constant MAX6652_CONFIG_LINE_FREQ_SEL : natural := 16#10#;
constant MAX6652_CONFIG_SHORT_CYCLE : natural := 16#20#;
constant MAX6652_CONFIG_RESET : natural := 16#80#;
-
end package;
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd
index b4152f69cd1de0c27337f3841c34ec3090ce1ec3..d5d2e4237df93e7ff9e5d7de9f99aeb2bff2688c 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_unb2_pkg.vhd
@@ -29,9 +29,7 @@ use work.i2c_dev_max1617_pkg.all;
use work.i2c_dev_max6652_pkg.all;
use work.i2c_commander_pkg.all;
-
package i2c_dev_unb2_pkg is
-
-- I2C slave addresses of the devices on the I2C sens bus on UniBoard2
constant I2C_UNB2_SENS_TEMP_MAX1617_ADR : natural := MAX1617_ADR_MID_LOW; -- temperature sensor, slave address is 0x29
constant I2C_UNB2_SENS_DCDC_BMR456_ADR : natural := 16#2C#; -- dc/dc converter, slave address is 0x2c
@@ -91,7 +89,6 @@ package i2c_dev_unb2_pkg is
SMBUS_C_END
);
-
constant c_i2c_unb2_sens_expected_mask_read_all : std_logic_vector := RESIZE_UVEC("001010101010101010101010101010101010101010101", c_word_w);
constant c_i2c_unb2_sens_nof_result_data_read_all : natural := 22;
constant c_i2c_unb2_sens_protocol_list_read_all : t_nat_natural_arr := (
@@ -120,7 +117,6 @@ package i2c_dev_unb2_pkg is
SMBUS_C_END
);
-
-- Commander protocol lists for UNB2 PMBUS
constant c_i2c_unb2_pmbus_expected_mask_read_all : std_logic_vector := RESIZE_UVEC("0010101010101010101010101010101010101", c_word_w);
@@ -146,5 +142,4 @@ package i2c_dev_unb2_pkg is
SMBUS_READ_BYTE , I2C_UNB2_PMB_FPGAIO_BMR461_ADR, PMBUS_REG_READ_TEMP,
SMBUS_C_END
);
-
end package;
diff --git a/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd
index 39b18838934f29d2442de5b5666c08228fa40883..fd7b8dacf9f1069549faa1b5e7f7eebe9e5cd00d 100644
--- a/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_dev_unb_pkg.vhd
@@ -27,9 +27,7 @@ use work.i2c_dev_max1617_pkg.all;
use work.i2c_dev_max6652_pkg.all;
use work.i2c_commander_pkg.all;
-
package i2c_dev_unb_pkg is
-
-- I2C slave addresses of the devices on the I2C bus on UniBoard
constant I2C_UNB_MAX1617_ADR : natural := MAX1617_ADR_LOW_LOW; -- temperature sensor, slave address is "0011000"
constant I2C_UNB_MAX6652_ADR : natural := MAX6652_ADR_GND; -- temperature-voltage sensor, slave address is "0010100"
@@ -71,5 +69,4 @@ package i2c_dev_unb_pkg is
SMBUS_WRITE_BYTE, I2C_UNB_MAX6652_ADR, MAX6652_REG_CONFIG, MAX6652_CONFIG_LINE_FREQ_SEL + MAX6652_CONFIG_START,
SMBUS_C_END
);
-
end package;
diff --git a/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd b/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd
index 31534bcf36b548d9a547dc42b4c131e3db80738e..79d5aab2f4f54d6b0a7bb6f32036f8c809b7bd28 100644
--- a/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_list_ctrl.vhd
@@ -53,9 +53,7 @@ entity i2c_list_ctrl is
);
end entity;
-
architecture rtl of i2c_list_ctrl is
-
signal i_busy : std_logic;
signal nxt_busy : std_logic;
signal nxt_protocol_rd_en : std_logic;
@@ -75,9 +73,7 @@ architecture rtl of i2c_list_ctrl is
signal prev_list_end : std_logic;
signal i_smbus_out_req : std_logic;
signal nxt_smbus_out_req : std_logic;
-
begin
-
protocol_rd_adr <= i_protocol_rd_adr;
result_wr_en <= i_result_wr_en;
@@ -148,7 +144,6 @@ begin
nxt_smbus_out_req <= '0';
end if;
end process;
-
end_of_protocol_list: process(pend_st_end, prot_done, smbus_st_end)
begin
nxt_pend_st_end <= pend_st_end;
@@ -178,5 +173,4 @@ begin
nxt_result_wr_dat <= smbus_in_dat;
end if;
end process;
-
end rtl;
diff --git a/libraries/io/i2c/src/vhdl/i2c_master.vhd b/libraries/io/i2c/src/vhdl/i2c_master.vhd
index 8ce6d8a387894f1ce08178e1612d915744d252a1..668aea77ac905d5fbf22335b22622944e047bd63 100644
--- a/libraries/io/i2c/src/vhdl/i2c_master.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_master.vhd
@@ -73,7 +73,6 @@ entity i2c_master is
end i2c_master;
architecture str of i2c_master is
-
-- MM - I2C ctrl list
signal protocol_rd_en : std_logic;
signal protocol_rd_adr : std_logic_vector(g_i2c_mm.protocol_adr_w - 1 downto 0);
@@ -96,9 +95,7 @@ architecture str of i2c_master is
signal smbus_out_ack : std_logic;
signal smbus_st_idle : std_logic;
signal smbus_st_end : std_logic;
-
begin
-
result_ready_evt <= smbus_st_end;
u_mm : entity work.i2c_mm
@@ -195,5 +192,4 @@ begin
scl => scl,
sda => sda
);
-
end str;
diff --git a/libraries/io/i2c/src/vhdl/i2c_mm.vhd b/libraries/io/i2c/src/vhdl/i2c_mm.vhd
index 1c88f486a80823be369e97e8485788c933a48924..08e9d24c2ba9351e92e2c16f06c98eb9a60a68ec 100644
--- a/libraries/io/i2c/src/vhdl/i2c_mm.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_mm.vhd
@@ -77,9 +77,7 @@ entity i2c_mm is
);
end i2c_mm;
-
architecture str of i2c_mm is
-
-- Use default MM bus data width = c_word_w
constant c_reg_control : t_c_mem := (latency => 1,
adr_w => 1,
@@ -114,9 +112,7 @@ architecture str of i2c_mm is
signal reg_control_rd : std_logic_vector(reg_control'range);
signal result_ready : std_logic;
-
begin
-
-- Protocol activate control
u_protocol_activate : entity common_lib.common_request
port map (
@@ -215,5 +211,4 @@ begin
rd_dat_b => OPEN,
rd_val_b => open
);
-
end str;
diff --git a/libraries/io/i2c/src/vhdl/i2c_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_pkg.vhd
index 520f3c488904017c8456c96071ddc39af30b843f..12105da3ca31d4726f95e80d4e38b700b81bd2ea 100644
--- a/libraries/io/i2c/src/vhdl/i2c_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_pkg.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package i2c_pkg is
-
-- I2C register size settings
--
constant c_i2c_control_adr_w : natural := 1; -- fixed
@@ -70,7 +69,6 @@ package i2c_pkg is
end i2c_pkg;
package body i2c_pkg is
-
function func_i2c_calculate_clk_cnt(system_clock_freq_in_MHz, bit_rate_in_kHz : natural) return natural is
-- . Adapt c_i2c_clk_freq and c_i2c_bit_rate and c_i2c_clk_cnt will be set appropriately
-- . Default no comma time is needed, it appeared necessary for the uP based I2C slave in the LOFAR HBA client
diff --git a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
index 2b6d0908c5be81f7aa520404db6bf12b379f6386..725394f4f1118906c9393cbb2c6b9e80320b74d2 100644
--- a/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_smbus.vhd
@@ -27,7 +27,6 @@ use common_lib.common_pkg.all;
use work.i2c_pkg.all;
use work.i2c_smbus_pkg.all;
-
entity i2c_smbus is
generic (
g_i2c_phy : t_c_i2c_phy;
@@ -51,9 +50,7 @@ entity i2c_smbus is
);
end entity;
-
architecture rtl of i2c_smbus is
-
constant c_i2c_octet_sz : natural := 9;
-- CONSTANT Signals that depend on GENERIC Signal gs_sim
@@ -144,9 +141,7 @@ architecture rtl of i2c_smbus is
attribute keep: boolean;
attribute keep of scl_o: signal is true;
attribute keep of sda_o: signal is true;
-
begin
-
-- CONSTANT Signals dependent on GENERIC Signal gs_sim
cs_clk_cnt <= conv_unsigned(g_i2c_phy.clk_cnt, cs_clk_cnt'length) when gs_sim = false else
conv_unsigned(c_i2c_clk_cnt_sim, cs_clk_cnt'length);
@@ -348,7 +343,6 @@ begin
op_val, op, in_req, in_dat, sda_i_reg,
i2c_cmd_ack, i2c_ack_out, i2c_dat_out, timeout)
begin
-
nxt_adr <= adr;
nxt_cnt <= cnt;
@@ -544,7 +538,6 @@ begin
end if;
end process;
-
to_cnt_en <= not timeout;
u_timeout : entity common_lib.common_counter
@@ -560,5 +553,4 @@ begin
);
nxt_timeout <= '1' when unsigned(to_cnt) > unsigned(to_value(to_cnt'range)) else '0';
-
end architecture;
diff --git a/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd b/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd
index ba1fc7ab454027f5103ca65e34dc8874409bd2c9..be84b90a3d9b57e42166378ca26f4500b1944099 100644
--- a/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_smbus_pkg.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package i2c_smbus_pkg is
-
-- Opcodes used in protocol definitions
type OPCODE is (
-- I2C opcodes
@@ -203,5 +202,4 @@ package i2c_smbus_pkg is
constant c_smbus_timeout_nof_byte : natural := 4; -- Four byte timeout value set via OP_LD_TIMEOUT
constant c_smbus_timeout_word_w : natural := c_smbus_timeout_nof_byte * 8;
constant c_smbus_timeout_w : natural := 28; -- Only use 28 bits for actual timeout counter, 2^28 > 200M cycles in 1 sec
-
end package;
diff --git a/libraries/io/i2c/src/vhdl/i2cslave.vhd b/libraries/io/i2c/src/vhdl/i2cslave.vhd
index 2de5cdb2c101a5b912996fd53de9f38346e50323..47e65a0c3ec93cb3272c7a7eed7685bbc2065eaf 100644
--- a/libraries/io/i2c/src/vhdl/i2cslave.vhd
+++ b/libraries/io/i2c/src/vhdl/i2cslave.vhd
@@ -34,7 +34,6 @@ entity i2cslave is
g_address : std_logic_vector(6 downto 0) := "0000001"; -- Slave I2C address
g_nof_ctrl_bytes : natural := 3 -- size of control register in bytes
);
-
port(
clk : in std_logic; -- system clock (clk freq >> SCL freq)
SDA : inout std_logic; -- I2C Serial Data Line
@@ -44,9 +43,7 @@ entity i2cslave is
);
end i2cslave;
-
architecture rtl of i2cslave is
-
function strong( sl : in std_logic ) return std_logic is
begin
if sl = 'H'THEN
@@ -117,9 +114,7 @@ architecture rtl of i2cslave is
signal wbitcnt : natural range 0 to 8; -- bitcnt for writing bits
signal wbytecnt : natural range 0 to g_nof_ctrl_bytes - 1; -- bytenct for writing bytes
signal zeroedge_state : state;
-
begin
-
CTRL_REG <= i_ctrl_reg;
no_rx : if g_rx_filter = false generate
@@ -186,7 +181,6 @@ begin
nxt_sda_rx <= '1' when sda_hi = '1' else '0' when sda_lo = '1' else sda_rx;
end generate;
-
startcontrol: process(streset, RST, sda_rx)
begin
if streset = '1' or RST = '1' then
@@ -213,10 +207,8 @@ begin
end if;
end process;
-
control: process(RST, scl_rx) -- i2c slave
begin
-
if RST = '1' then
--reset input connected to bit 17 of CTRL register, hence default for CTRL[17] must be '0' so RST will act as a spike.
--if the spike is strong enough, then this works also in hardware for the rest of the logic connected to RST.
@@ -390,7 +382,6 @@ begin
end case;
end if;
end if;
-
end process;
--control the tri state buffer
diff --git a/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd b/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd
index d661350c4abd169e27c610318cce3d928bad3c7a..923f63a046590863e439fcbab87bf005333c3dde 100644
--- a/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_ltc4260.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use work.i2c_dev_ltc4260_pkg.all;
-
entity dev_ltc4260 is
generic(
g_address : std_logic_vector(c_byte_w - 2 downto 0); -- 7 bit address, so without R/Wn bit
@@ -40,9 +39,7 @@ entity dev_ltc4260 is
);
end dev_ltc4260;
-
architecture beh of dev_ltc4260 is
-
-- Convert V sense into I sense
constant c_I_unit_sense : real := LTC4260_V_UNIT_SENSE / g_R_sense; -- = 0.3 mV / 10 mOhm
@@ -64,9 +61,7 @@ architecture beh of dev_ltc4260 is
-- LTC4260 registers (with power up defaults)
signal control_reg : std_logic_vector(c_byte_w - 1 downto 0) := std_logic_vector(to_unsigned(LTC4260_CONTROL_DEFAULT, c_byte_w));
-
begin
-
-- Digitize the measured current and voltages
dig_current_sense <= integer(ana_current_sense / c_I_unit_sense); -- e.g. 5.0 A / 0.03 = 166
dig_volt_source <= integer(ana_volt_source / LTC4260_V_UNIT_SOURCE); -- e.g. 48.0 V / 0.4 = 120
@@ -124,5 +119,4 @@ begin
end case;
end if;
end process;
-
end beh;
diff --git a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
index 2b75d0527bcbb0b1589a872550c21801d15f16f9..1b7e84b0e8f82a03c95af3a162dea3c0205b92c6 100644
--- a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.i2c_dev_max1617_pkg.all;
-
entity dev_max1618 is
generic(
g_address : std_logic_vector(6 downto 0)
@@ -36,9 +35,7 @@ entity dev_max1618 is
);
end dev_max1618;
-
architecture beh of dev_max1618 is
-
signal enable : std_logic; -- enable
signal stop : std_logic; -- stop
signal wr_dat : std_logic_vector(7 downto 0); -- I2C write data
@@ -53,9 +50,7 @@ architecture beh of dev_max1618 is
signal status_reg : std_logic_vector(7 downto 0) := (others => '0');
signal temp_hi_reg : std_logic_vector(7 downto 0) := "01111111";
signal temp_lo_reg : std_logic_vector(7 downto 0) := "11001001";
-
begin
-
i2c_slv_device : entity work.i2c_slv_device
generic map (
g_address => g_address
@@ -110,5 +105,4 @@ begin
end case;
end if;
end process;
-
end beh;
diff --git a/libraries/io/i2c/tb/vhdl/dev_max6652.vhd b/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
index 859c95f5c9516cf60e6668e7807fb5d189b94bbb..02ddc416d49acd6c94d6e782d873cfe966bb4670 100644
--- a/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_max6652.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity dev_max6652 is
generic(
g_address : std_logic_vector(6 downto 0)
@@ -39,9 +38,7 @@ entity dev_max6652 is
);
end dev_max6652;
-
architecture beh of dev_max6652 is
-
constant c_cmd_read_2v5 : std_logic_vector(7 downto 0) := "00100000";
constant c_cmd_read_12v : std_logic_vector(7 downto 0) := "00100001";
constant c_cmd_read_3v3 : std_logic_vector(7 downto 0) := "00100010";
@@ -59,9 +56,7 @@ architecture beh of dev_max6652 is
signal cmd_en : std_logic := '0';
signal cmd : std_logic_vector(7 downto 0); -- device command
signal config_reg : std_logic_vector(7 downto 0) := "00001000";
-
begin
-
i2c_slv_device : entity work.i2c_slv_device
generic map (
g_address => g_address
@@ -111,5 +106,4 @@ begin
end case;
end if;
end process;
-
end beh;
diff --git a/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd b/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd
index f01d48ca017358be8672d1eb4be238f1763621cf..d80181f2f455acf898bb0af163d696899f32f2f7 100644
--- a/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_pca9555.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity dev_pca9555 is
generic(
g_address : std_logic_vector(6 downto 0) -- PCA9555 slave address is "0100" & A2 & A1 & A0
@@ -37,7 +36,6 @@ entity dev_pca9555 is
end dev_pca9555;
architecture beh of dev_pca9555 is
-
constant c_cmd_input_0 : natural := 0;
constant c_cmd_input_1 : natural := 1;
constant c_cmd_output_0 : natural := 2;
@@ -66,9 +64,7 @@ architecture beh of dev_pca9555 is
signal invert_reg1 : std_logic_vector(7 downto 0) := (others => '0');
signal config_reg0 : std_logic_vector(7 downto 0) := (others => '1');
signal config_reg1 : std_logic_vector(7 downto 0) := (others => '1');
-
begin
-
i2c_slv_device : entity work.i2c_slv_device
generic map (
g_address => g_address
@@ -150,5 +146,4 @@ begin
if config_reg1(I) = '0' then iobank1(I) <= output_reg1(I); else iobank1(I) <= 'Z'; end if;
end loop;
end process;
-
end beh;
diff --git a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
index 37c8bed78756256dc5a141a3d6031db3d6e817e2..65a3f2c7bcfd3786a0b46597a5911e9d03c716a1 100644
--- a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.i2c_dev_unb2_pkg.all;
-
entity dev_pmbus is
generic(
g_address : std_logic_vector(6 downto 0)
@@ -41,9 +40,7 @@ entity dev_pmbus is
);
end dev_pmbus;
-
architecture beh of dev_pmbus is
-
signal enable : std_logic; -- enable
signal stop : std_logic; -- stop
signal wr_dat : std_logic_vector(7 downto 0); -- I2C write data
@@ -58,9 +55,7 @@ architecture beh of dev_pmbus is
signal status_reg : std_logic_vector(7 downto 0) := (others => '0');
signal temp_hi_reg : std_logic_vector(7 downto 0) := "01111111";
signal temp_lo_reg : std_logic_vector(7 downto 0) := "11001001";
-
begin
-
i2c_slv_device : entity work.i2c_slv_device
generic map (
g_address => g_address
@@ -76,7 +71,6 @@ begin
rd_dat => rd_dat
);
-
p_write : process (enable, wr_val) -- first write byte is treated as command
begin
if rising_edge(enable) then
@@ -110,5 +104,4 @@ begin
end case;
end if;
end process;
-
end beh;
diff --git a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
index 3074b1afc02788190e169ead838834e79e52a4e6..89472e640474856072cbbdda960b356f12ff9f69 100644
--- a/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
+++ b/libraries/io/i2c/tb/vhdl/i2c_slv_device.vhd
@@ -39,9 +39,7 @@ entity i2c_slv_device is
);
end i2c_slv_device;
-
architecture beh of i2c_slv_device is
-
-- The code reuses the RTL code of i2cslave(rtl).vhd written by A.W. Gunst.
function strong( sl : in std_logic ) return std_logic is
@@ -96,9 +94,7 @@ architecture beh of i2c_slv_device is
signal wbitcnt : natural range 0 to 8; -- bitcnt for writing bits
signal wbytecnt : natural range 0 to g_nof_ctrl_bytes - 1; -- bytenct for writing bytes
signal zeroedge_state : state;
-
begin
-
-- Mostly behavioral code:
RST <= '0';
@@ -161,7 +157,6 @@ begin
startcontrol:
process(SDA,SCL,streset,RST)
begin
-
if falling_edge(SDA) then
if strong(SCL) = '1' then
start <= '1';
@@ -173,13 +168,11 @@ begin
if streset = '1' or RST = '1' then
start <= '0';
end if;
-
end process;
stopcontrol:
process(SDA,SCL,streset,RST)
begin
-
if rising_edge(SDA) then
if strong(SCL) = '1' then
stop <= '1';
@@ -191,13 +184,11 @@ begin
if streset = '1' or RST = '1' then
stop <= '0';
end if;
-
end process;
control: -- i2c slave
process(SCL,RST)
begin
-
if RST = '1' then
--reset input connected to bit 17 of CTRL register, hence default for CTRL[17] must be '0' so RST will act as a spike.
--if the spike is strong enough, then this works also in hardware for the rest of the logic connected to RST.
@@ -367,7 +358,6 @@ begin
end case;
end if;
end if;
-
end process;
--control the tri state buffer
diff --git a/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd b/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
index 19149291096f15f8c6c8ba47cbcb7bda6ebf3587..10a8d997b3d72b622df0b38e5b167af4011a3dc9 100644
--- a/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
@@ -27,7 +27,6 @@ entity tb_avs_i2c_master is
end tb_avs_i2c_master;
architecture tb of tb_avs_i2c_master is
-
component avs_i2c_master is
generic (
g_control_adr_w : natural := 1;
@@ -69,9 +68,7 @@ architecture tb of tb_avs_i2c_master is
signal i2c_scl : std_logic;
signal i2c_sda : std_logic;
-
begin
-
reset <= '1', '0' after c_clk_period * 10;
clk <= not clk after c_clk_period / 2;
@@ -133,6 +130,4 @@ begin
---------------------------------------------------------------------------
ins_interrupt_irq => open
);
-
end;
-
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
index 3e2ecea62270fd663b6aa40c10f8353d28ae2ee5..9a20f6b1672db7acfcfefa9f48a8943ab46c1def 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander.vhd
@@ -19,7 +19,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Verify the i2c_commander and create a u_protocol_ram init file
--
-- Description:
@@ -53,7 +52,6 @@
-- In the Wave Window view the signal u_commander/protocol_index to observe
-- the progress
-
entity tb_i2c_commander is
generic (
g_board : string := "adu" -- else default to "unb"
@@ -76,9 +74,7 @@ use work.i2c_commander_pkg.all;
use work.i2c_commander_aduh_pkg.all;
use work.i2c_commander_unbh_pkg.all;
-
architecture tb of tb_i2c_commander is
-
constant c_protocol_ram_init_file : string := sel_a_b(g_board = "adu", "data/adu_protocol_ram_init.hex", "data/unb_protocol_ram_init.hex");
--CONSTANT c_protocol_ram_init_file : STRING := "UNUSED";
@@ -164,7 +160,6 @@ architecture tb of tb_i2c_commander is
constant c_result_error_cnt_wi : natural := 3 * c_protocol_commander.nof_protocols + 1;
constant c_result_data_wi : natural := 3 * c_protocol_commander.nof_protocols + 2;
-
-- Test bench PHY
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
@@ -212,9 +207,7 @@ architecture tb of tb_i2c_commander is
signal protocol_status : natural;
signal result_data : natural;
signal result_error_cnt : natural;
-
begin
-
-- run -all
rst <= '0' after 4 * c_clk_period;
@@ -292,7 +285,6 @@ begin
proc_common_wait_some_cycles(clk, 10);
-
----------------------------------------------------------------------------
-- Create the u_protocol_ram_init_file
----------------------------------------------------------------------------
@@ -306,7 +298,6 @@ begin
proc_common_wait_some_cycles(clk, 10);
-
----------------------------------------------------------------------------
-- Try and verify all commander protocols
----------------------------------------------------------------------------
@@ -365,7 +356,6 @@ begin
wait;
end process;
-
-- I2C commander
u_commander : entity work.i2c_commander
generic map (
@@ -454,6 +444,4 @@ begin
adu_ctrl_3_modem_on <= adu_ctrl(3);
adu_atten_ctrl <= iobank1(5 downto 0);
-
end tb;
-
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
index 902e7da21a4f8c4d727c5beb1e683cd8eb218603..352690a6f633776d6c6c86a4e47b101fb9cabcf3 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_pmbus.vhd
@@ -19,7 +19,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Verify the i2c_commander and create a u_protocol_ram init file
--
-- Description:
@@ -56,7 +55,6 @@
-- Uniboard2 version derived from tb_i2c_commander November 2015
-- this version tests the PMBUS bus
-
entity tb_i2c_commander_unb2_pmbus is
generic (
g_board : string := "unb2" -- only works with UniBoard2
@@ -77,9 +75,7 @@ use work.i2c_commander_pkg.all;
use work.i2c_commander_unb2_sens_pkg.all;
use work.i2c_commander_unb2_pmbus_pkg.all; -- in case we can add the PMBUS later
-
architecture tb of tb_i2c_commander_unb2_pmbus is
-
--CONSTANT c_protocol_ram_init_file : STRING := "data/unb2_sens_protocol_ram_init.hex";
--CONSTANT c_protocol_ram_init_file : STRING := "data/unb2_pmbus_protocol_ram_init.hex";
constant c_protocol_ram_init_file : string := "UNUSED"; -- start with this, then make a hex file from the txt file?
@@ -92,7 +88,6 @@ architecture tb of tb_i2c_commander_unb2_pmbus is
constant c_phy_i2c : t_c_i2c_phy := func_i2c_sel_a_b(c_sim, c_i2c_phy_sim, func_i2c_calculate_phy(c_clk_freq_in_MHz));
-
--CONSTANT c_pmbus_temp_address : STD_LOGIC_VECTOR := TO_UVEC(MAX1617_ADR_LOW_LOW, 7); -- use other slave address to force I2C errors
constant c_pmbus_core_address : std_logic_vector := TO_UVEC(I2C_UNB2_PMB_CORE_BMR464_ADR, 7);
constant c_pmbus_vccram_address : std_logic_vector := TO_UVEC(I2C_UNB2_PMB_VCCRAM_BMR461_ADR, 7);
@@ -102,7 +97,6 @@ architecture tb of tb_i2c_commander_unb2_pmbus is
constant c_pmbus_fpgaio_address : std_logic_vector := TO_UVEC(I2C_UNB2_PMB_FPGAIO_BMR461_ADR, 7);
constant c_max1618_temp : integer := 60;
-
-- Select the expected read data arrays for the result data (the read data values are tb dependent, so therefore they are not obtained from a package)
type t_i2c_unb2_natural_arr is array (integer range 0 to 31) of natural; -- needto test some long protocol lists
@@ -129,7 +123,6 @@ architecture tb of tb_i2c_commander_unb2_pmbus is
constant c_result_error_cnt_wi : natural := 3 * c_protocol_commander.nof_protocols + 1;
constant c_result_data_wi : natural := 3 * c_protocol_commander.nof_protocols + 2;
-
-- Test bench PHY
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
@@ -157,9 +150,7 @@ architecture tb of tb_i2c_commander_unb2_pmbus is
signal protocol_status : natural;
signal result_data : natural;
signal result_error_cnt : natural;
-
begin
-
-- run -all
rst <= '0' after 4 * c_clk_period;
@@ -237,7 +228,6 @@ begin
proc_common_wait_some_cycles(clk, 10);
-
----------------------------------------------------------------------------
-- Create the u_protocol_ram_init_file
----------------------------------------------------------------------------
@@ -251,7 +241,6 @@ begin
proc_common_wait_some_cycles(clk, 10);
-
----------------------------------------------------------------------------
-- Try and verify all commander protocols
----------------------------------------------------------------------------
@@ -310,7 +299,6 @@ begin
wait;
end process;
-
-- I2C commander
u_commander : entity work.i2c_commander
generic map (
@@ -431,7 +419,4 @@ begin
vcap => 0,
temp => 39
);
-
-
end tb;
-
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
index 40af119f362c15b39078f1ec3c4f79ff9ad6663c..065b2c384d3845dd74d1fda8abe5455abc792910 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_commander_unb2_sens.vhd
@@ -19,7 +19,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose: Verify the i2c_commander and create a u_protocol_ram init file
--
-- Description:
@@ -56,7 +55,6 @@
-- Uniboard2 version derived from tb_i2c_commander November 2015
-- this version tests the SENS bus
-
entity tb_i2c_commander_unb2_sens is
generic (
g_board : string := "unb2" -- only works with UniBoard2
@@ -77,9 +75,7 @@ use work.i2c_commander_pkg.all;
use work.i2c_commander_unb2_sens_pkg.all;
use work.i2c_commander_unb2_pmbus_pkg.all; -- in case we can add the PMBUS later
-
architecture tb of tb_i2c_commander_unb2_sens is
-
--CONSTANT c_protocol_ram_init_file : STRING := "data/unb2_sens_protocol_ram_init.hex";
--CONSTANT c_protocol_ram_init_file : STRING := "data/unb2_pmbus_protocol_ram_init.hex";
constant c_protocol_ram_init_file : string := "UNUSED"; -- start with this, then make a hex file from the txt file?
@@ -92,7 +88,6 @@ architecture tb of tb_i2c_commander_unb2_sens is
constant c_phy_i2c : t_c_i2c_phy := func_i2c_sel_a_b(c_sim, c_i2c_phy_sim, func_i2c_calculate_phy(c_clk_freq_in_MHz));
-
--CONSTANT c_sens_temp_address : STD_LOGIC_VECTOR := TO_UVEC(MAX1617_ADR_LOW_LOW, 7); -- use other slave address to force I2C errors
constant c_sens_temp_address : std_logic_vector := TO_UVEC(I2C_UNB2_SENS_TEMP_MAX1617_ADR, 7);
constant c_sens_dcdc_address : std_logic_vector := TO_UVEC(I2C_UNB2_SENS_DCDC_BMR456_ADR, 7);
@@ -106,7 +101,6 @@ architecture tb of tb_i2c_commander_unb2_sens is
constant c_sens_temp2_address : std_logic_vector := TO_UVEC(I2C_UNB2_SENS_TEMP_TMP451_ADR, 7);
constant c_max1618_temp : integer := 60;
-
-- Select the expected read data arrays for the result data (the read data values are tb dependent, so therefore they are not obtained from a package)
type t_i2c_unb2_natural_arr is array (integer range 0 to 31) of natural; -- needto test some long protocol lists
@@ -134,7 +128,6 @@ architecture tb of tb_i2c_commander_unb2_sens is
constant c_result_error_cnt_wi : natural := 3 * c_protocol_commander.nof_protocols + 1;
constant c_result_data_wi : natural := 3 * c_protocol_commander.nof_protocols + 2;
-
-- Test bench PHY
signal tb_end : std_logic := '0';
signal clk : std_logic := '0';
@@ -162,9 +155,7 @@ architecture tb of tb_i2c_commander_unb2_sens is
signal protocol_status : natural;
signal result_data : natural;
signal result_error_cnt : natural;
-
begin
-
-- run -all
rst <= '0' after 4 * c_clk_period;
@@ -242,7 +233,6 @@ begin
proc_common_wait_some_cycles(clk, 10);
-
----------------------------------------------------------------------------
-- Create the u_protocol_ram_init_file
----------------------------------------------------------------------------
@@ -256,7 +246,6 @@ begin
proc_common_wait_some_cycles(clk, 10);
-
----------------------------------------------------------------------------
-- Try and verify all commander protocols
----------------------------------------------------------------------------
@@ -315,7 +304,6 @@ begin
wait;
end process;
-
-- I2C commander
u_commander : entity work.i2c_commander
generic map (
@@ -451,7 +439,6 @@ begin
temp => 40
);
-
u_sens_temp : entity work.dev_max1618 -- both on "unb" and on "adu"
generic map (
g_address => c_sens_temp_address
@@ -461,7 +448,4 @@ begin
sda => sda,
temp => c_max1618_temp
);
-
-
end tb;
-
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
index 4d93569fc29938b900a3d7fb098ca59cc6c45957..436888b8d3a79181214f690079912fd20ddede55 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2c_master.vhd
@@ -33,9 +33,7 @@ use work.i2c_dev_max1617_pkg.all;
use work.i2c_dev_max6652_pkg.all;
use work.i2c_pkg.all;
-
architecture tb of tb_i2c_master is
-
constant c_sim : boolean := true; -- FALSE
constant c_clk_freq_in_MHz : natural := 100; -- 100 MHz
constant c_clk_period : time := (10**3 / c_clk_freq_in_MHz) * 1 ns;
@@ -168,9 +166,7 @@ architecture tb of tb_i2c_master is
signal expected_ctrl : natural;
signal expected_data : natural;
signal expected_cnt : natural := c_expected_data'length;
-
begin
-
-- run -all
rst <= '0' after 4 * c_clk_period;
@@ -189,7 +185,6 @@ begin
end if;
end process;
-
p_mm_stimuli : process
begin
-- Wait for reset release
@@ -265,7 +260,6 @@ begin
end if;
end process;
-
-- I2C master
u_i2c_master : entity work.i2c_master
generic map (
@@ -375,6 +369,4 @@ begin
volt_vcc => c_volt_3v3,
temp => c_temp_pcb
);
-
end tb;
-
diff --git a/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd b/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
index 80969c5f5e2b153b539c9a57306f44029214bb9e..1307590caddc8ce3bc549c28c6640277698e9711 100644
--- a/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_i2cslave.vhd
@@ -33,7 +33,6 @@ entity tb_i2cslave is
end tb_i2cslave;
architecture tb of tb_i2cslave is
-
constant c_period : time := 25 ns;
constant c_address : std_logic_vector(6 downto 0) := "0000001"; -- Slave I2C address
constant c_nof_ctrl_bytes : integer := 3;
@@ -57,9 +56,7 @@ architecture tb of tb_i2cslave is
signal SCL : std_logic; -- I2C Serial Clock Line
signal RST : std_logic; -- optional reset bit
signal CTRL_REG : std_logic_vector(8 * c_nof_ctrl_bytes - 1 downto 0); -- ctrl for RCU control
-
begin
-
uut: i2cslave
generic map (
g_rx_filter => false,
@@ -173,6 +170,4 @@ tbsda : process
SDA <= '0'; -- stop
wait for 20 ns; -- to get in line with falling clk edge
end process;
-
end;
-
diff --git a/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd b/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd
index d1215aff99cd8b56e14e4b1c5f0fd940fe4d1929..8bc60ed08ef6fdd173441a26974a2c22bb42137d 100644
--- a/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_tb_i2c_commander.vhd
@@ -33,14 +33,11 @@ use IEEE.std_logic_1164.all;
entity tb_tb_i2c_commander is
end tb_tb_i2c_commander;
-
architecture tb of tb_tb_i2c_commander is
signal tb_end : std_logic := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
begin
-
-- g_board : STRING := "adu" -- else default to "unb"
u_adu : entity work.tb_i2c_commander generic map ("adu");
u_unb : entity work.tb_i2c_commander generic map ("unb");
-
end tb;
diff --git a/libraries/io/mac_10g/io_mac_10g.vhd b/libraries/io/mac_10g/io_mac_10g.vhd
index a22e115c947a257f04d291d8b574045b42ccd95c..0327504a1c3626098ff08be39735eaa5f895b0dc 100644
--- a/libraries/io/mac_10g/io_mac_10g.vhd
+++ b/libraries/io/mac_10g/io_mac_10g.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: MAC for 10 Gigabit Ethernet via XGMII
-- Description:
-- See description of tech_mac_10g.
@@ -77,11 +76,8 @@ entity io_mac_10g is
);
end io_mac_10g;
-
architecture str of io_mac_10g is
-
begin
-
u_tech_mac_10g : entity tech_mac_10g_lib.tech_mac_10g
generic map (
g_technology => g_technology,
@@ -112,6 +108,4 @@ begin
xgmii_tx_data => xgmii_tx_data,
xgmii_rx_data => xgmii_rx_data
);
-
end str;
-
diff --git a/libraries/io/mdio/src/vhdl/avs_mdio.vhd b/libraries/io/mdio/src/vhdl/avs_mdio.vhd
index b4945619dea21cdd022daf4eb174d1acce1ac1b1..c5885093709a02dbdf0642becd49cb030566d2c7 100644
--- a/libraries/io/mdio/src/vhdl/avs_mdio.vhd
+++ b/libraries/io/mdio/src/vhdl/avs_mdio.vhd
@@ -92,17 +92,13 @@ entity avs_mdio is
);
end avs_mdio;
-
architecture wrap of avs_mdio is
-
constant c_avs_mdio_phy : t_c_mdio_phy := (g_mdc_period, g_hold_time, g_setup_time);
signal cs_sim : boolean;
signal i_avs_header_address : std_logic_vector(0 downto 0);
signal i_avs_data_address : std_logic_vector(0 downto 0);
-
begin
-
-- SOPC Builder does not use BOOLEAN, so use STD_LOGIC and is_true()
cs_sim <= is_true(coe_gs_sim_export);
@@ -142,6 +138,4 @@ begin
mdat_in => coe_mdio_phy_mdat_in_export,
mdat_oen => coe_mdio_phy_mdat_oen_export
);
-
end wrap;
-
diff --git a/libraries/io/mdio/src/vhdl/mdio.vhd b/libraries/io/mdio/src/vhdl/mdio.vhd
index b62c19d2ccaac7b3d5eda253ac499e77bca2f156..3414cf531d03ac76bac8adb305702acd8de47e42 100644
--- a/libraries/io/mdio/src/vhdl/mdio.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use work.mdio_pkg.all;
-
entity mdio is
generic (
g_mdio_phy : t_c_mdio_phy := c_mdio_phy
@@ -63,17 +62,13 @@ entity mdio is
);
end mdio;
-
architecture str of mdio is
-
signal mdio_en_evt : std_logic;
signal mdio_done_evt : std_logic;
signal mdio_hdr : std_logic_vector(c_halfword_w - 1 downto 0);
signal mdio_tx_dat : std_logic_vector(c_halfword_w - 1 downto 0);
signal mdio_rx_dat : std_logic_vector(c_halfword_w - 1 downto 0);
-
begin
-
u_mm : entity work.mdio_mm
port map (
clk => clk,
@@ -122,5 +117,4 @@ begin
mdat_in => mdat_in,
mdat_oen => mdat_oen
);
-
end str;
diff --git a/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd b/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
index 70bca908f61984a05ec5dc84487c81e332515e87..4c9e5def3024890c445e8b8da1f2ea674fdf18f6 100644
--- a/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_ctlr.vhd
@@ -50,7 +50,6 @@ entity mdio_ctlr is
end mdio_ctlr;
architecture rtl of mdio_ctlr is
-
type t_state_enum is (s_init_rst, s_init_post_rst, s_idle, s_write_adr, s_write_dat, s_ackdone, s_exec_complete);
type t_reg is record
@@ -67,9 +66,7 @@ architecture rtl of mdio_ctlr is
end record;
signal r , nxt_r : t_reg;
-
begin
-
p_comb : process(rst, r, mdio_done)
variable v : t_reg;
begin
@@ -136,7 +133,6 @@ begin
end if;
when s_exec_complete => v.exec_complete := '1';
-
end case;
if rst = '1' then
@@ -165,6 +161,4 @@ begin
hdr <= r.hdr;
tx_dat <= r.tx_dat;
exec_complete <= r.exec_complete;
-
end rtl;
-
diff --git a/libraries/io/mdio/src/vhdl/mdio_mm.vhd b/libraries/io/mdio/src/vhdl/mdio_mm.vhd
index 873015a036bc0abb53e5ed679d11a79670fbc137..676c286d001db22c91d0610c8ec06fa56e4e74ca 100644
--- a/libraries/io/mdio/src/vhdl/mdio_mm.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_mm.vhd
@@ -61,9 +61,7 @@ entity mdio_mm is
);
end mdio_mm;
-
architecture str of mdio_mm is
-
-- Use MM bus data width = c_halfword_w
constant c_reg_mdio : t_c_mem := (latency => 1,
adr_w => 1,
@@ -77,10 +75,7 @@ architecture str of mdio_mm is
signal reg_header : std_logic_vector(c_halfword_w - 1 downto 0);
signal reg_data : std_logic_vector(c_halfword_w - 1 downto 0);
signal reg_data_rd : std_logic_vector(reg_data'range);
-
-
begin
-
-- MDIO access enable when the MDIO header register is written.
-- Hence for a MDIO write the MDIO data register needs to have been written first.
header_write <= mms_header_write; -- only one reg, so no need to check mms_header_address
@@ -151,5 +146,4 @@ begin
out_reg => reg_data,
in_reg => reg_data_rd
);
-
end str;
diff --git a/libraries/io/mdio/src/vhdl/mdio_phy.vhd b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
index 594d6d69306bc6af10be351132c873aebf7e212d..3f6b278be998fd3fde9f34dfe3bd4a9797ee1c95 100644
--- a/libraries/io/mdio/src/vhdl/mdio_phy.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_phy.vhd
@@ -25,7 +25,6 @@ use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
use work.mdio_pkg.all;
-
-- MDIO = Management Data Input Output
-- MMD = MDIO Manageable Device
-- MDC = Management Data Clock
@@ -58,9 +57,7 @@ entity mdio_phy is
);
end mdio_phy;
-
architecture rtl of mdio_phy is
-
-- Simulation constants for when gs_sim=TRUE
constant c_sim_mdc_period : natural := 8; -- must be a power of 2 and <= g_mdio_phy.mdc_period
constant c_sim_mdc_cnt_high : natural := ceil_log2(c_sim_mdc_period) - 1;
@@ -112,9 +109,7 @@ architecture rtl of mdio_phy is
signal nxt_mdc_oen : std_logic;
signal i_mdat_oen : std_logic;
signal nxt_mdat_oen : std_logic;
-
begin
-
mdat_oen <= i_mdat_oen;
rx_dat <= i_rx_dat;
mdio_done_evt <= i_mdio_done_evt;
@@ -186,7 +181,6 @@ begin
end if;
end process;
-
p_state : process (state, mdio_en_revt, bit_cnt, hdr, tx_en, mdc_oen)
begin
nxt_state <= state;
@@ -250,11 +244,9 @@ begin
when others =>
assert false report "Uknown state." severity Failure;
nxt_state <= s_idle;
-
end case;
end process;
-
p_bit_counter : process (bit_cnt, bit_cnt_rst, tx_en, state)
begin
nxt_bit_cnt <= bit_cnt;
@@ -274,7 +266,6 @@ begin
tx_en <= '1' when unsigned(mdc_cnt) = cs_tx_en_cnt else '0';
rx_en <= '1' when unsigned(mdc_cnt) = cs_rx_en_cnt and state = s_receive else '0';
-
p_transmitter : process (msg_reg, state, mdio_en_revt, hdr, tx_dat, tx_en, mdc_oen, i_mdat_oen)
begin
nxt_mdc_oen <= mdc_oen;
@@ -302,7 +293,6 @@ begin
end if;
end process;
-
p_receiver : process (mdio_en_revt, i_rx_dat, rx_en, mdat_in, state, bit_cnt)
begin
nxt_rx_dat <= i_rx_dat;
@@ -319,5 +309,4 @@ begin
end loop;
end if;
end process;
-
end rtl;
diff --git a/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd b/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd
index d8f5e2748122ed0543fff96ab73e6e1c685bbfbe..c516148bc7f820b7664493eb4b56fa3ca918420a 100644
--- a/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_phy_reg.vhd
@@ -48,9 +48,7 @@ entity mdio_phy_reg is
);
end mdio_phy_reg;
-
architecture rtl of mdio_phy_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(5),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
@@ -64,9 +62,7 @@ architecture rtl of mdio_phy_reg is
signal mm_hdr : std_logic_vector(c_halfword_w - 1 downto 0);
signal mm_tx_dat : std_logic_vector(c_halfword_w - 1 downto 0);
signal mm_rx_dat : std_logic_vector(c_halfword_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -177,6 +173,4 @@ begin
din => mdio_done,
dout => mm_done
);
-
end rtl;
-
diff --git a/libraries/io/mdio/src/vhdl/mdio_pkg.vhd b/libraries/io/mdio/src/vhdl/mdio_pkg.vhd
index 1c662bf53a5dec02fa89f6e1c8dc0391e12c6063..a684ac0bb7adce068edd1c8b81d954b1fc308f97 100644
--- a/libraries/io/mdio/src/vhdl/mdio_pkg.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_pkg.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
--USE common_lib.common_pkg.ALL;
package mdio_pkg is
-
constant c_mdio_phy_data_width : natural := 16;
constant c_mdio_phy_hdr_st_len : natural := 2;
@@ -87,7 +86,6 @@ package mdio_pkg is
end mdio_pkg;
package body mdio_pkg is
-
function mdio_hdr_adr(prtad: std_logic_vector(c_mdio_phy_hdr_prtad_len - 1 downto 0); devad: std_logic_vector(c_mdio_phy_hdr_devad_len - 1 downto 0) ) return std_logic_vector is
-- Return a full address header based on port address and device address.
begin
diff --git a/libraries/io/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd b/libraries/io/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
index 3228fc60e09a6ab6524705d6c5858607a5199187..5bbe7c3651be99d0c9826334efb10331bd00f11d 100644
--- a/libraries/io/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_vitesse_vsc8486_pkg.vhd
@@ -31,7 +31,6 @@ use work.mdio_pkg.all;
-- contents with the target bit(s) set or unset.
package mdio_vitesse_vsc8486_pkg is
-
constant c_mdio_vsc8486_prtad : std_logic_vector(c_mdio_phy_hdr_prtad_len - 1 downto 0) := "00000";
-- XAUI loopbacks, closest to XAUI side first: B, C, E. G, J
@@ -143,8 +142,6 @@ package mdio_vitesse_vsc8486_pkg is
-- Set RX equalization.
('1', TO_UVEC(1, c_mdio_phy_hdr_devad_len), c_mdio_vsc8486_rx_eq_dev1, c_mdio_vsc8486_rx_eq_dev1_set)
);
-
-
end mdio_vitesse_vsc8486_pkg;
package body mdio_vitesse_vsc8486_pkg is
diff --git a/libraries/io/mdio/tb/vhdl/mmd_slave.vhd b/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
index 213d7c88f20af113e7007ec6e4b17beb2c79df44..9f0b403713febb4ed344527953ee6221177e5d2f 100644
--- a/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
+++ b/libraries/io/mdio/tb/vhdl/mmd_slave.vhd
@@ -23,7 +23,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-
entity mmd_slave is
generic (
g_st : std_logic_vector(1 downto 0) := "00";
@@ -42,9 +41,7 @@ entity mmd_slave is
);
end mmd_slave;
-
architecture beh of mmd_slave is
-
constant c_preamble_len : natural := 32;
constant c_preamble_timeout : natural := 1; -- >= 0
constant c_header_st_len : natural := 2;
@@ -70,9 +67,7 @@ architecture beh of mmd_slave is
signal i_addr : std_logic_vector(g_reg_w - 1 downto 0) := (others => '1');
signal i_reg_dat : std_logic_vector(g_reg_w - 1 downto 0) := std_logic_vector(to_unsigned(g_reg_dat, g_reg_w));
-
begin
-
addr <= i_addr;
reg_dat <= i_reg_dat;
@@ -219,7 +214,6 @@ begin
when others => -- can not occur
assert false report "Unknown MDIO state." severity FAILURE;
-
end case;
if v_match = false then
@@ -228,5 +222,4 @@ begin
mdio <= v_mdout;
end if;
end process;
-
end beh;
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
index abd4972f5522eb3180084457c5548e4facfbe682..1822ffda1130061ed60360d7d5af3f48ce1bd347 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio.vhd
@@ -28,9 +28,7 @@ use work.mdio_pkg.all;
entity tb_mdio is
end tb_mdio;
-
architecture tb of tb_mdio is
-
constant c_sim : boolean := true;
constant clk_period : time := 10 ns;
@@ -84,9 +82,7 @@ architecture tb of tb_mdio is
signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- MDIO access address
signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register address
signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register data value
-
begin
-
-- run 50 us
clk <= not clk or tb_end after clk_period / 2;
@@ -185,7 +181,6 @@ begin
phy_readdata <= mms_data_readdata; -- capture read PHY data
-
-- MDIO master
u_mdio : entity work.mdio
port map (
@@ -223,7 +218,6 @@ begin
dat_out_en => mdat_oen -- pull low when mdat_oen (so implicitely mdat_out='0')
);
-
-- MDIO slave
u_slave : entity work.mmd_slave
generic map (
@@ -242,5 +236,4 @@ begin
);
slave_reg_addr <= std_logic_vector(to_unsigned(c_slave_reg_addr, c_halfword_w));
-
end tb;
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
index 42c9f8a8afe930184a7aee3cce346c56bbc1c96b..f6974791671f9991419df444531bc808879e0ba2 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy.vhd
@@ -28,9 +28,7 @@ use work.mdio_pkg.all;
entity tb_mdio_phy is
end tb_mdio_phy;
-
architecture tb of tb_mdio_phy is
-
constant c_sim : boolean := true;
constant clk_period : time := 10 ns;
@@ -74,9 +72,7 @@ architecture tb of tb_mdio_phy is
signal slave_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- MDIO access address
signal slave_reg_addr : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register address
signal slave_reg_dat : std_logic_vector(c_halfword_w - 1 downto 0); -- the one data register data value
-
begin
-
-- run 50 us
clk <= not clk or tb_end after clk_period / 2;
@@ -226,5 +222,4 @@ begin
);
slave_reg_addr <= std_logic_vector(to_unsigned(c_slave_reg_addr, c_halfword_w));
-
end tb;
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
index 181f50ab018e5a10943596d68dbf613a6308400a..9b5a2bcdd29f38359e869f3fe86dd780455a5e49 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_ctlr.vhd
@@ -28,9 +28,7 @@ use work.mdio_pkg.all;
entity tb_mdio_phy_ctlr is
end tb_mdio_phy_ctlr;
-
architecture tb of tb_mdio_phy_ctlr is
-
constant c_sim : boolean := true;
constant clk_period : time := 10 ns;
@@ -85,9 +83,7 @@ architecture tb of tb_mdio_phy_ctlr is
-- Read MMD
('0', c_devad, TO_UVEC(c_slave_reg_addr, c_mdio_phy_data_width), (others => '0'))
);
-
begin
-
clk <= not clk or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 3;
@@ -181,5 +177,4 @@ begin
);
slave_reg_addr <= std_logic_vector(to_unsigned(c_slave_reg_addr, c_halfword_w));
-
end tb;
diff --git a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
index 2f8aa8d5829cb9d6094d3de28aff339909dbb128..0ce05943aca1e8e0aa2376752ac60b358be77e7d 100644
--- a/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
+++ b/libraries/io/mdio/tb/vhdl/tb_mdio_phy_reg.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009
@@ -32,9 +31,7 @@ use work.mdio_pkg.all;
entity tb_mdio_phy_reg is
end tb_mdio_phy_reg;
-
architecture tb of tb_mdio_phy_reg is
-
constant c_sim : boolean := true;
constant clk_period : time := 10 ns;
@@ -92,9 +89,7 @@ architecture tb of tb_mdio_phy_reg is
signal en_evt : std_logic;
signal done : std_logic;
signal done_ack_evt : std_logic;
-
begin
-
-- Run 25us
clk <= not clk or tb_end after clk_period / 2;
@@ -249,5 +244,4 @@ begin
);
slave_reg_addr <= std_logic_vector(to_unsigned(c_slave_reg_addr, c_halfword_w));
-
end tb;
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
index cf592d5003018013b89fe89cb40e4213a11c46ba..0eabcfe6ead66301f0a9e626b85ca3ab4fcebf96 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_10GbE.vhd
@@ -115,7 +115,6 @@ entity nw_10GbE is
end nw_10GbE;
architecture str of nw_10GbE is
-
constant c_nof_mux_streams : natural := 3;
signal nw_arp_request_src_out_arr : t_dp_sosi_arr(g_nof_macs - 1 downto 0) := (others => c_dp_sosi_rst);
@@ -135,14 +134,11 @@ architecture str of nw_10GbE is
signal eth_src_mac_arr : t_slv_48_arr(g_nof_macs - 1 downto 0);
signal ip_src_addr_arr : t_slv_32_arr(g_nof_macs - 1 downto 0);
signal ip_dst_addr_arr : t_slv_32_arr(g_nof_macs - 1 downto 0);
-
begin
-
src_out_arr <= tr_10GbE_src_out_arr;
tr_10GbE_src_in_arr <= src_in_arr;
gen_nof_macs : for I in 0 to g_nof_macs - 1 generate
-
-- Wire hdr_fields_in_arr
eth_src_mac_arr(I) <= hdr_fields_in_arr(I)(field_hi(g_ip_hdr_field_arr, "eth_src_mac") downto field_lo(g_ip_hdr_field_arr, "eth_src_mac"));
ip_src_addr_arr(I) <= hdr_fields_in_arr(I)(field_hi(g_ip_hdr_field_arr, "ip_src_addr") downto field_lo(g_ip_hdr_field_arr, "ip_src_addr"));
@@ -215,7 +211,6 @@ begin
src_out => tr_10GbE_snk_in_arr(I),
src_in => tr_10GbE_snk_out_arr(I)
);
-
end generate;
-------------
@@ -289,5 +284,4 @@ begin
mdio_mdat_in_arr => mdio_mdat_in_arr,
mdio_mdat_oen_arr => mdio_mdat_oen_arr
);
-
end str;
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd
index 1584384970cd2319ae29e970e76e516c326057e0..b1bad94e019bbed9e4d77718826f53d766893275 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_arp_request.vhd
@@ -55,7 +55,6 @@ entity nw_arp_request is
end nw_arp_request;
architecture rtl of nw_arp_request is
-
constant c_data_w : natural := c_xgmii_data_w;
constant c_nof_hdr_fields : natural := 12;
constant c_hdr_field_sel : std_logic_vector(c_nof_hdr_fields - 1 downto 0) := (others => '0');
@@ -85,9 +84,7 @@ architecture rtl of nw_arp_request is
signal dp_field_blk_snk_in : t_dp_sosi := c_dp_sosi_rst;
signal nxt_dp_field_blk_snk_in : t_dp_sosi := c_dp_sosi_rst;
signal dp_field_blk_snk_out : t_dp_siso := c_dp_siso_rdy;
-
begin
-
p_field_wires : process (arp_sha, arp_spa, arp_tpa)
begin
-- Set defaults
@@ -167,6 +164,4 @@ begin
src_in => src_in
);
-
-
end rtl;
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
index 0d57d18c18b901ec6c296e7929e5925f15e28310..8ac3fed9ca7866758fa272180339a59b80b0e779 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
@@ -91,9 +91,7 @@ architecture rtl of nw_ping_response is
signal dp_pipeline_src_out : t_dp_sosi;
signal dp_fifo_sc_src_out : t_dp_sosi;
signal dp_fifo_sc_rd_emp : std_logic;
-
begin
-
-- Combinational Process
p_comb : process(r, rst, snk_in, dp_pipeline_src_out, dp_fifo_sc_rd_emp, eth_src_mac)
variable v : t_reg;
@@ -146,7 +144,6 @@ begin
+ unsigned(r.hdr_response(3)(c_halfword_w - 1 downto 0)) -- ip_dst_addr(1/2)
+ unsigned(r.hdr_response(4)(c_halfword_w * 4 - 1 downto c_halfword_w * 3)); -- ip_dst_addr(2/2)
-
when s_output => -- Send out ICMP response
v.src_out := dp_pipeline_src_out;
if dp_pipeline_src_out.valid = '1' then
@@ -184,7 +181,6 @@ begin
if dp_fifo_sc_rd_emp = '1' then -- Wait until ping response has left the fifo
v := c_r_rst;
end if;
-
end case;
if rst = '1' then
@@ -236,5 +232,4 @@ begin
src_out => dp_fifo_sc_src_out
);
src_out <= dp_fifo_sc_src_out;
-
end rtl;
diff --git a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd
index b6fe67a14d8a40f5b96a4f26ee947ab1a547ccf2..544e1970373f10f97e8f45b3cd56b52a8b5e2a2b 100644
--- a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_10GbE.vhd
@@ -80,7 +80,6 @@ entity tb_nw_10GbE is
end tb_nw_10GbE;
architecture tb of tb_nw_10GbE is
-
constant c_sim : boolean := true; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
constant cal_clk_period : time := 25 ns; -- 40 MHz
@@ -177,9 +176,7 @@ architecture tb of tb_nw_10GbE is
signal tx_pkt_cnt_arr : t_natural_arr(g_nof_channels - 1 downto 0) := (others => 0);
signal rx_pkt_cnt_arr : t_natural_arr(g_nof_channels - 1 downto 0) := (others => 0);
signal rx_toggle_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0'); -- toggle after every received packet
-
begin
-
cal_clk <= not cal_clk after cal_clk_period / 2; -- Calibration clock
dp_clk <= not dp_clk after g_dp_clk_period / 2; -- DP clock
@@ -407,5 +404,4 @@ begin
rx_end => rx_end,
tb_end => tb_end
);
-
end tb;
diff --git a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_arp_request.vhd b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_arp_request.vhd
index b553fe461783be6f4f4659c6f530768c9459f226..b2e120b04ffa428ea1708de56dcbdd221dddfa9e 100644
--- a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_arp_request.vhd
+++ b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_arp_request.vhd
@@ -44,7 +44,6 @@ generic (
end tb_nw_arp_request;
architecture tb of tb_nw_arp_request is
-
-- Use c_tb_timeout to raise ERROR if there is no result
constant c_tb_timeout : natural := 100;
@@ -59,9 +58,7 @@ architecture tb of tb_nw_arp_request is
signal arp_sha : std_logic_vector(c_network_eth_mac_addr_w - 1 downto 0) := x"AABBCCDDEEFF";
signal arp_spa : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := x"A1A2A3A4";
signal arp_tpa : std_logic_vector(c_network_ip_addr_w - 1 downto 0) := x"B1B2B3B4";
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
src_in.xon <= '1';
@@ -103,5 +100,4 @@ begin
arp_spa => arp_spa,
arp_tpa => arp_tpa
);
-
end tb;
diff --git a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd
index 3fd06e13ed327ea4b428da22bbc667c4593b6cb9..16170a8737161877fb706e22b2448cdf55542c8a 100644
--- a/libraries/io/nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd
+++ b/libraries/io/nw_10GbE/tb/vhdl/tb_nw_ping_response.vhd
@@ -41,7 +41,6 @@ entity tb_nw_ping_response is
end tb_nw_ping_response;
architecture tb of tb_nw_ping_response is
-
-- Use c_tb_timeout to raise ERROR if there is no result
constant c_tb_timeout : natural := 100;
@@ -72,7 +71,6 @@ architecture tb of tb_nw_ping_response is
( field_name_pad("icmp_seq_number" ), "RW", 16, field_default(x"0001") ),
( field_name_pad("icmp_payload" ), "RW", 160, field_default(x"123456789ABCDEF01234123456789ABCDEF01234") ) );
-
constant c_udp_packet : t_common_field_arr(c_nof_udp_packet_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"00074306C700") ),
( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
@@ -123,9 +121,7 @@ architecture tb of tb_nw_ping_response is
signal nw_ping_response_src_out : t_dp_sosi;
signal cnt : natural := 0;
-
begin
-
clk <= (not clk) or tb_end after clk_period / 2;
rst <= '1', '0' after clk_period * 7;
@@ -142,7 +138,6 @@ begin
udp_dp_field_blk_snk_in.valid <= udp_dp_field_blk_snk_out.ready;
udp_dp_field_blk_snk_in.sop <= udp_dp_field_blk_snk_out.ready;
udp_dp_field_blk_snk_in.eop <= udp_dp_field_blk_snk_out.ready;
-
end if;
end process;
diff --git a/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd b/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd
index 3215edd2d99e148697e8c29a4647eeec1db1399a..f5af904d95c524dcb02aaea3a81634c9d43fc988 100644
--- a/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd
+++ b/libraries/io/nw_10GbE/tb/vhdl/tb_tb_nw_10GbE.vhd
@@ -47,7 +47,6 @@ architecture tb of tb_tb_nw_10GbE is
signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
begin
-
-- g_technology : NATURAL := c_tech_select_default;
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
@@ -65,13 +64,16 @@ begin
u_nw_10GbE_tx_only : entity work.tb_nw_10GbE generic map (c_tech_select_default, false, false, 5 ns, 0, 1, "TX_ONLY", c_644, c_156, c_data_type, true) port map (tb_end_vec(2));
u_nw_10GbE_rx_only : entity work.tb_nw_10GbE generic map (c_tech_select_default, false, false, 5 ns, 0, 1, "RX_ONLY", c_644, c_156, c_data_type, true) port map (tb_end_vec(3));
u_nw_10GbE_dp_clk_6_5ns : entity work.tb_nw_10GbE generic map (c_tech_select_default, false, false, 6.5 ns, 0, 1, "TX_RX", c_644, c_156, c_data_type, true) port map (tb_end_vec(4));
+
gen_2_channels : if c_tech_select_default = c_tech_stratixiv generate
u_nw_10GbE_nof_channels_is_2 : entity work.tb_nw_10GbE generic map (c_tech_select_default, false, false, 5 ns, 0, 2, "TX_RX", c_644, c_156, c_data_type, true) port map (tb_end_vec(5));
end generate;
+
-- For arria10, nof_channels need to be 1, 4, 12, 24, 48.
gen_24_channels : if c_tech_select_default /= c_tech_stratixiv generate
u_nw_10GbE_nof_channels_is_24 : entity work.tb_nw_10GbE generic map (c_tech_select_default, false, false, 5 ns, 0, 24, "TX_RX", c_644, c_156, c_data_type, true) port map (tb_end_vec(5));
end generate;
+
u_nw_10GbE_sim_level_is_1 : entity work.tb_nw_10GbE generic map (c_tech_select_default, false, false, 5 ns, 1, 1, "TX_RX", c_644, c_156, c_data_type, true) port map (tb_end_vec(6));
tb_end <= '1' when tb_end_vec = c_tb_end_vec else '0';
diff --git a/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
index b97ddded7882bb5e1eea4b08b38fd9f6dfe696c9..4fb564836913db5c44b2b99ff2ab5c8696025b06 100644
--- a/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mm_ppsh.vhd
@@ -49,9 +49,7 @@ entity mm_ppsh is
);
end mm_ppsh;
-
architecture str of mm_ppsh is
-
-- ext_clk domain
signal i_pps_pulse : std_logic;
signal i_pps_toggle : std_logic;
@@ -63,9 +61,7 @@ architecture str of mm_ppsh is
signal nxt_mm_pps_toggle : std_logic;
signal i_mm_pps_capture_cnt : std_logic_vector(ceil_log2(g_ext_clk_freq) - 1 downto 0);
signal nxt_mm_pps_capture_cnt : std_logic_vector(ceil_log2(g_ext_clk_freq) - 1 downto 0);
-
begin
-
pps_pulse <= i_pps_pulse;
pps_toggle <= i_pps_toggle;
@@ -115,6 +111,4 @@ begin
nxt_mm_pps_toggle <= i_pps_toggle when i_mm_pps_pulse = '1' else i_mm_pps_toggle;
nxt_mm_pps_capture_cnt <= pps_capture_cnt when i_mm_pps_pulse = '1' else i_mm_pps_capture_cnt;
-
end str;
-
diff --git a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
index 3bd213f47087feff7c3948c511f6e0cc38a29f6a..8844056f9e0fc6cbef3df452e5116b1c39236eef 100644
--- a/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/mms_ppsh.vhd
@@ -55,9 +55,7 @@ entity mms_ppsh is
);
end mms_ppsh;
-
architecture str of mms_ppsh is
-
signal st_pps_sys : std_logic;
signal mm_pps_sys : std_logic;
@@ -77,9 +75,7 @@ architecture str of mms_ppsh is
signal nxt_mm_pps_toggle : std_logic;
signal mm_capture_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
signal nxt_mm_capture_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
-
begin
-
pps_sys <= st_pps_sys;
u_ppsh : entity work.ppsh
@@ -164,6 +160,4 @@ begin
nxt_mm_capture_cnt <= st_capture_cnt when mm_pps_sys = '1' else mm_capture_cnt;
pin_pps <= mm_pps_toggle & '0' & RESIZE_UVEC(mm_capture_cnt, 30); -- pin_pps did not support pps_stable yet
-
end str;
-
diff --git a/libraries/io/ppsh/src/vhdl/ppsh.vhd b/libraries/io/ppsh/src/vhdl/ppsh.vhd
index ebc760809e61b80d04cdf563e52615b123184c53..ce1c41eb55f0b5b36d91965001012d1a26ea35c1 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh.vhd
@@ -75,9 +75,7 @@ entity ppsh is
);
end ppsh;
-
architecture rtl of ppsh is
-
constant c_pipeline_output : natural := 100;
signal pps_ext_delayed : std_logic_vector(0 downto 0);
@@ -99,9 +97,7 @@ architecture rtl of ppsh is
signal pps_locked : std_logic;
signal nxt_pps_locked : std_logic;
-
begin
-
capture_cnt <= i_capture_cnt;
pps_toggle <= i_pps_toggle;
@@ -207,6 +203,4 @@ begin
r_stable => pps_stable,
r_stable_ack => pps_stable_ack
);
-
end rtl;
-
diff --git a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
index 6fee943ec51ecdd17b19fcc3f92ba295e6ebeda1..b7d28c187909e180a4cd529b2ad5486d3d16389d 100644
--- a/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
+++ b/libraries/io/ppsh/src/vhdl/ppsh_reg.vhd
@@ -34,7 +34,6 @@
-- | xxx offset_cnt = [n:0]| 2
-- |-----------------------------------------------------------------------|
-
-- Info from L2SDP-78 ticket.
-- Add a new offset_cnt field to the PPSH register that reports the current capture_cnt value at the moment that this MM read access occurs.
-- The offset_cnt reports the time since last PPSH in units of the dp_clk, so 5 ns (at 200MHz). The host can use this offset_cnt value to
@@ -48,7 +47,6 @@
--
-- Also prepare unb2c_minimal by updating the PPSH register span there.
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -83,9 +81,7 @@ entity ppsh_reg is
);
end ppsh_reg;
-
architecture rtl of ppsh_reg is
-
-- Define the actual size of the MM slave register
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(4),
@@ -104,9 +100,7 @@ architecture rtl of ppsh_reg is
signal mm_capture_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
signal mm_expected_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
signal mm_offset_cnt : std_logic_vector(ceil_log2(g_st_clk_freq) - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- MM register access in the mm_clk domain
-- . Hardcode the shared MM slave register directly in RTL instead of using
@@ -278,8 +272,6 @@ begin
out_dat => st_expected_cnt,
out_new => open
);
-
end generate; -- gen_cross
end rtl;
-
diff --git a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
index ea7035f5586b94a8c0b4b3383e2945870030c274..65be3c0f2ff972aef51dbcd77cd42b9984e8a098 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_mms_ppsh.vhd
@@ -31,7 +31,6 @@ entity tb_mms_ppsh is
end tb_mms_ppsh;
architecture tb of tb_mms_ppsh is
-
constant c_st_clk_freq : natural := 1000; -- clock frequency in Hz
constant c_st_clk_period : time := 1000000 us / c_st_clk_freq;
constant c_mm_clk_period : time := c_st_clk_period * 3; -- somewhat slower mm_clk
@@ -59,9 +58,7 @@ architecture tb of tb_mms_ppsh is
signal capture_cnt : natural;
signal offset_cnt : natural;
signal last_offset_cnt : natural;
-
begin
-
-- Usage:
-- > as 10
-- > run -all
@@ -109,7 +106,6 @@ begin
-- expected_cnt = c_pps_period = 1000
proc_mem_mm_bus_wr(1, v_word, mm_clk, reg_mosi);
-
-- Simulate reading PPS status every 10 PPS periods
proc_common_wait_some_cycles(st_clk, 10);
for I in 0 to 9 loop
@@ -188,7 +184,6 @@ begin
wait;
end process;
-
-----------------------------------------------------------------------------
-- DUT: PPSH
-----------------------------------------------------------------------------
@@ -212,5 +207,4 @@ begin
-- Streaming clock domain
pps_sys => pps_sys
);
-
end tb;
diff --git a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
index f9d316579eb1390b9a4ac8b3a746f4b24299dc2d..e54dd7851d3a0e0063223c87b278837e48f7cfa0 100644
--- a/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
+++ b/libraries/io/ppsh/tb/vhdl/tb_ppsh.vhd
@@ -28,7 +28,6 @@ entity tb_ppsh is
end tb_ppsh;
architecture tb of tb_ppsh is
-
constant c_clk_freq : natural := 1000; -- clock frequency in Hz
constant c_clk_period : time := 1000000 us / c_clk_freq;
constant c_pps_default_period : natural := c_clk_freq; -- 1 s takes c_clk_freq clk cycles
@@ -64,9 +63,7 @@ architecture tb of tb_ppsh is
-- Verify
signal verify_s : real := 0.0; -- provides time line marker for p_verify in Wave Window
-
begin
-
-- Usage: 'run -all', observe unsigned capture_cnt, there should occur no
-- REPORT errors.
@@ -177,7 +174,6 @@ begin
-- Apply some PPS to CLK skew
pps_ext <= transport pps after c_pps_skew;
-
-----------------------------------------------------------------------------
-- DUT: PPSH
-----------------------------------------------------------------------------
@@ -307,5 +303,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/io/remu/src/vhdl/mms_remu.vhd b/libraries/io/remu/src/vhdl/mms_remu.vhd
index 3000f356bc564bb737ebe41b8bf32cdc67801a7f..59087e30d34f83baf0b2dfbd448b2f6823eb6101 100644
--- a/libraries/io/remu/src/vhdl/mms_remu.vhd
+++ b/libraries/io/remu/src/vhdl/mms_remu.vhd
@@ -42,9 +42,7 @@ entity mms_remu is
);
end mms_remu;
-
architecture str of mms_remu is
-
constant c_param_w : natural := 3;
constant c_data_w : natural := tech_flash_data_w(g_technology);
@@ -64,9 +62,7 @@ architecture str of mms_remu is
signal nxt_fall_remu_write_param : std_logic;
signal nxt_fall_remu_param : std_logic_vector(c_param_w - 1 downto 0);
signal nxt_fall_remu_data_in : std_logic_vector(c_data_w - 1 downto 0);
-
begin
-
u_remu: entity tech_flash_lib.tech_flash_remote_update
generic map (
g_technology => g_technology
@@ -144,6 +140,4 @@ begin
clk => epcs_clk,
out_rst => epcs_rst
);
-
end str;
-
diff --git a/libraries/io/remu/src/vhdl/remu_reg.vhd b/libraries/io/remu/src/vhdl/remu_reg.vhd
index 0df4a3a49a12e9367dc12fee865f5df68080fcaa..6080750d1d68b0b606aa7436aa4a1429d1d9867a 100644
--- a/libraries/io/remu/src/vhdl/remu_reg.vhd
+++ b/libraries/io/remu/src/vhdl/remu_reg.vhd
@@ -70,9 +70,7 @@ entity remu_reg is
);
end remu_reg;
-
architecture rtl of remu_reg is
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(7),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
@@ -89,9 +87,7 @@ architecture rtl of remu_reg is
signal mm_busy : std_logic;
signal mm_data_out : std_logic_vector(g_data_w - 1 downto 0);
signal mm_data_in : std_logic_vector(g_data_w - 1 downto 0);
-
begin
-
p_mm_reg : process (mm_rst, mm_clk)
begin
if mm_rst = '1' then
@@ -226,6 +222,4 @@ begin
out_dat => mm_data_out,
out_new => open
);
-
end rtl;
-
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
index 491ffac9c0e340831fafa7f5227b1bbb3fadc83f..85c4d7da1208fa90f8b00c5271a66f1b4bd6054a 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE.vhd
@@ -142,9 +142,7 @@ entity tr_10GbE is
);
end tr_10GbE;
-
architecture str of tr_10GbE is
-
signal tx_rst_arr_out : std_logic_vector(g_nof_macs - 1 downto 0);
signal rx_clk_arr_out : std_logic_vector(g_nof_macs - 1 downto 0);
signal rx_rst_arr_out : std_logic_vector(g_nof_macs - 1 downto 0);
@@ -172,7 +170,6 @@ architecture str of tr_10GbE is
signal dp_fifo_dc_rx_src_out_arr : t_dp_sosi_arr(g_nof_macs - 1 downto 0);
signal dp_fifo_dc_rx_src_in_arr : t_dp_siso_arr(g_nof_macs - 1 downto 0);
-
component tr_xaui_mdio is
generic (
g_sim : boolean := false;
@@ -199,11 +196,7 @@ architecture str of tr_10GbE is
mdio_mdat_oen_arr : out std_logic_vector(g_nof_xaui - 1 downto 0)
);
end component;
-
-
-
begin
-
---------------------------------------------------------------------------------------
-- Clocks and reset
---------------------------------------------------------------------------------------
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
index 1b485b10e3a864278bebf79e69e8e2cbab0732aa..b2627f65513f6f29b508d2c955a5481241cb0755 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
@@ -49,7 +49,6 @@ entity tr_10GbE_ip_checksum is
end tr_10GbE_ip_checksum;
architecture rtl of tr_10GbE_ip_checksum is
-
constant c_cin_w : natural := 4; -- bit width of carry
constant c_pipeline_delay : natural := 2;
@@ -59,7 +58,6 @@ architecture rtl of tr_10GbE_ip_checksum is
signal cnt_en, cnt_p_en : std_logic;
signal count, count_p : std_logic_vector(31 downto 0);
signal dp_pipeline_src_out : t_dp_sosi;
-
begin
-------------------------------------------------
-- process to calculate the ip_header_checksum --
@@ -153,5 +151,4 @@ begin
src_in => src_in,
src_out => dp_pipeline_src_out
);
-
end rtl;
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd
index 2a43dc775b06b49823c9fe25c1b1fa8f8fa744ee..3d6158d99a0124a171b73dbd9ca66a2a329a2020 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_statistics.vhd
@@ -51,9 +51,7 @@ entity tr_10GbE_statistics is
);
end tr_10GbE_statistics;
-
architecture str of tr_10GbE_statistics is
-
constant c_eth_clk_freq_khz : natural := 156250; -- not used, because dp_statistics operates in dp_clk domain
constant c_eth_word_w : natural := 64;
constant c_dp_word_w : natural := c_eth_word_w;
@@ -84,9 +82,7 @@ architecture str of tr_10GbE_statistics is
signal tr_10GbE_src_out : t_dp_sosi;
signal i_tb_end : std_logic;
-
begin
-
------------------------------------------------------------------------------
-- We're using the tb_end output locally
------------------------------------------------------------------------------
@@ -99,7 +95,6 @@ begin
dp_rst <= '1', '0' after c_dp_clk_period * 2;
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
-
----------------------------------------------------------------------------
-- We're generating a reference clock locally, just like the sim model in
-- tr_10GbE
@@ -135,11 +130,9 @@ begin
src_out_arr(0) => tr_10GbE_src_out
);
-
end generate;
gen_ip_arria10 : if g_technology /= c_tech_stratixiv generate
-
mm_clk <= not mm_clk or i_tb_end after c_mm_clk_period / 2;
mm_rst <= '1', '0' after c_mm_clk_period * 2;
sa_clk <= not sa_clk or i_tb_end after c_sa_clk_period / 2;
@@ -185,7 +178,6 @@ begin
src_out_arr(0) => tr_10GbE_src_out
);
-
end generate;
------------------------------------------------------------------------------
@@ -207,5 +199,4 @@ begin
tb_end => i_tb_end
);
-
end str;
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
index 5da8f7f240c421cb5c98516426c086dffc4ef1b3..a07ba8b66f4684549c70e186a354e8400878bdff 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tb_tr_10GbE.vhd
@@ -33,11 +33,9 @@ use technology_lib.technology_select_pkg.all;
use tech_mac_10g_lib.tb_tech_mac_10g_pkg.all;
use tech_pll_lib.tech_pll_component_pkg.all;
-
entity tb_tb_tr_10GbE is
end tb_tb_tr_10GbE;
-
architecture tb of tb_tb_tr_10GbE is
constant c_644 : time := tech_pll_clk_644_period;
constant c_156 : time := 6.4 ns;
@@ -47,7 +45,6 @@ architecture tb of tb_tb_tr_10GbE is
signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
begin
-
-- g_technology : NATURAL := c_tech_select_default;
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
@@ -65,13 +62,16 @@ begin
u_tr_10GbE_tx_only : entity work.tb_tr_10GbE generic map (c_tech_select_default, false, false, 5 ns, 0, 1, "TX_ONLY", c_644, c_156, c_data_type, true) port map (tb_end_vec(2));
u_tr_10GbE_rx_only : entity work.tb_tr_10GbE generic map (c_tech_select_default, false, false, 5 ns, 0, 1, "RX_ONLY", c_644, c_156, c_data_type, true) port map (tb_end_vec(3));
u_tr_10GbE_dp_clk_6_5ns : entity work.tb_tr_10GbE generic map (c_tech_select_default, false, false, 6.5 ns, 0, 1, "TX_RX", c_644, c_156, c_data_type, true) port map (tb_end_vec(4));
+
gen_2_channels : if c_tech_select_default = c_tech_stratixiv generate
u_tr_10GbE_nof_channels_is_2 : entity work.tb_tr_10GbE generic map (c_tech_select_default, false, false, 5 ns, 0, 2, "TX_RX", c_644, c_156, c_data_type, true) port map (tb_end_vec(5));
end generate;
+
-- For arria10, nof_channels need to be 1, 4, 12, 24, 48.
gen_24_channels : if c_tech_select_default /= c_tech_stratixiv generate
u_tr_10GbE_nof_channels_is_24 : entity work.tb_tr_10GbE generic map (c_tech_select_default, false, false, 5 ns, 0, 24, "TX_RX", c_644, c_156, c_data_type, true) port map (tb_end_vec(5));
end generate;
+
u_tr_10GbE_sim_level_is_1 : entity work.tb_tr_10GbE generic map (c_tech_select_default, false, false, 5 ns, 1, 1, "TX_RX", c_644, c_156, c_data_type, true) port map (tb_end_vec(6));
tb_end <= '1' when tb_end_vec = c_tb_end_vec else '0';
diff --git a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
index add50b13027685ce12e43c88c02ce9f25eafd3ed..aa75e5580c6018356571b6bff4da345dce33218c 100644
--- a/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
+++ b/libraries/io/tr_10GbE/tb/vhdl/tb_tr_10GbE.vhd
@@ -76,9 +76,7 @@ entity tb_tr_10GbE is
);
end tb_tr_10GbE;
-
architecture tb of tb_tr_10GbE is
-
constant c_sim : boolean := true; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
constant cal_clk_period : time := 25 ns; -- 40 MHz
@@ -159,9 +157,7 @@ architecture tb of tb_tr_10GbE is
signal tx_pkt_cnt_arr : t_natural_arr(g_nof_channels - 1 downto 0) := (others => 0);
signal rx_pkt_cnt_arr : t_natural_arr(g_nof_channels - 1 downto 0) := (others => 0);
signal rx_toggle_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0'); -- toggle after every received packet
-
begin
-
cal_clk <= not cal_clk after cal_clk_period / 2; -- Calibration clock
dp_clk <= not dp_clk after g_dp_clk_period / 2; -- DP clock
@@ -385,5 +381,4 @@ begin
rx_end => rx_end,
tb_end => tb_end
);
-
end tb;
diff --git a/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
index 3ac1def2398c8c06c41ad377e092dc0f8d74c30a..080b2833fc184981953ff0dd67fafe0751ad2331 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/mms_tr_nonbonded.vhd
@@ -82,9 +82,7 @@ entity mms_tr_nonbonded is
);
end mms_tr_nonbonded;
-
architecture str of mms_tr_nonbonded is
-
constant c_nof_select : natural := 2;
constant c_nof_select_w : natural := ceil_log2(c_nof_select);
constant c_sel_user : natural := 0;
@@ -139,9 +137,7 @@ architecture str of mms_tr_nonbonded is
signal demux_select_arr : t_select_arr(g_nof_gx - 1 downto 0) := (others => (others => '0'));
signal nxt_demux_select_arr : t_select_arr(g_nof_gx - 1 downto 0);
-
begin
-
u_tr_nonbonded : entity work.tr_nonbonded
generic map (
g_sim => g_sim,
@@ -247,7 +243,6 @@ begin
);
gen_select : for i in 0 to g_nof_gx - 1 generate
-
-- 0 = user data,
snk_out_arr(i) <= mux_in_siso_2arr(i)(c_sel_user);
mux_in_sosi_2arr(i)(c_sel_user) <= snk_in_arr(i);
@@ -316,7 +311,6 @@ begin
src_in_arr => demux_out_siso_2arr(i),
src_out_arr => demux_out_sosi_2arr(i)
);
-
end generate;
p_st_clk : process(st_rst, st_clk)
diff --git a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
index 1ef1211278908711de6ef45e05a1a3fc43591e1e..f148977a494aeecd11b2aa63765cca5aec5dbdc2 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded.vhd
@@ -99,9 +99,7 @@ entity tr_nonbonded is
);
end tr_nonbonded;
-
architecture str of tr_nonbonded is
-
signal i_rx_clk : std_logic_vector(g_nof_gx - 1 downto 0);
signal i_rx_rst : std_logic_vector(g_nof_gx - 1 downto 0);
@@ -116,9 +114,7 @@ architecture str of tr_nonbonded is
signal gp_out_tx : std_logic_vector(g_nof_gx - 1 downto 0) := (others => '0');
signal gp_out_rx : std_logic_vector(g_nof_gx - 1 downto 0) := (others => '0');
-
begin
-
-- FIFO monitoring
gp_out <= gp_out_tx & gp_out_rx;
@@ -196,12 +192,10 @@ begin
-- === TX === TX === TX === TX === TX === TX === TX === TX === TX === TX === TX === TX === TX === TX === TX === TX
gen_tx : if g_tx = true generate
-
tx_rst <= i_tx_rst;
tx_clk <= i_tx_clk;
gen_i : for i in 0 to g_nof_gx - 1 generate
-
no_tx_fifo : if g_fifos = false generate
tx_fifo_sosi_arr(i) <= tx_sosi_arr(i); -- for tx_fifo_sosi_arr it is needed to select between tx_sosi_arr and dp_tx_sosi_arr
tx_siso_arr(i) <= tx_fifo_siso_arr(i); -- could default connect tx_siso_arr, but for clarity only connect tx_siso_arr when g_fifos = FALSE, else leave it 'X'
@@ -237,15 +231,12 @@ begin
end generate; -- gen_i
end generate; -- gen_tx
-
-- === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX === RX
gen_rx : if g_rx = true generate
-
rx_rst <= i_rx_rst;
rx_clk <= i_rx_clk;
gen_i : for i in 0 to g_nof_gx - 1 generate
-
rx_dataout(i)(g_data_w - 1 downto 0) <= rx_fifo_sosi_arr(i).data(g_data_w - 1 downto 0);
no_rx_fifo : if g_fifos = false generate
@@ -282,6 +273,4 @@ begin
end generate; -- gen_rx_fifo
end generate; -- gen_i
end generate; -- gen_rx
-
end str;
-
diff --git a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
index b7732b1c32fc02c7d6eebde947a61d1089245e0b..62aa54ca01956ace978f341f0ebf9d4a24e6c864 100644
--- a/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
+++ b/libraries/io/tr_nonbonded/src/vhdl/tr_nonbonded_reg.vhd
@@ -54,13 +54,10 @@ entity tr_nonbonded_reg is
);
end tr_nonbonded_reg;
-
architecture rtl of tr_nonbonded_reg is
-
constant c_nof_addr : natural := 16;
constant c_max_nof_gx : natural := 12;
-
constant c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(c_nof_addr),
dat_w => c_word_w,
@@ -74,9 +71,7 @@ architecture rtl of tr_nonbonded_reg is
signal mm_rx_align_en : std_logic_vector(c_word_w - 1 downto 0);
signal mm_rx_dataout : t_slv_32_arr(c_max_nof_gx - 1 downto 0);
-
begin
-
gen_wires : for i in 0 to g_nof_gx - 1 generate
mm_rx_dataout(i) <= rx_dataout(i);
end generate;
@@ -153,7 +148,6 @@ begin
mm_rx_state(2 * g_nof_gx - 1 downto 0) <= rx_state;
gen_asyncs: for i in 0 to g_nof_gx - 1 generate
-
u_async_tx_align_en: entity common_lib.common_async
generic map(
g_rst_level => '0'
@@ -175,8 +169,6 @@ begin
din => mm_rx_align_en(i),
dout => rx_align_en(i)
);
-
end generate;
end rtl;
-
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
index d20b660dd88b1e41f9ff45160dc5b92b8f4a950d..1f7f9a16d2eb452ff541299741fd04fb9190c103 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tb_tr_nonbonded.vhd
@@ -30,17 +30,14 @@ use IEEE.std_logic_1164.all;
use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_tb_tr_nonbonded is
end tb_tb_tr_nonbonded;
-
architecture tb of tb_tb_tr_nonbonded is
constant c_tb_end_vec : std_logic_vector(7 downto 0) := (others => '1');
signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
begin
-
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_data_w : NATURAL := 32;
-- g_sim_level : NATURAL := 1
@@ -58,5 +55,4 @@ begin
report "Multi tb simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
index a2db82ef499fcee6fd2c3bb43f10e9efa2ab16b7..623b6e66aafb742a6ce6e74d63837c9d56a8c4c1 100644
--- a/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
+++ b/libraries/io/tr_nonbonded/tb/vhdl/tb_tr_nonbonded.vhd
@@ -60,7 +60,6 @@
-- due to the link error.
--
-
library IEEE, tr_nonbonded_lib, common_lib, dp_lib, diagnostics_lib;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
@@ -81,7 +80,6 @@ entity tb_tr_nonbonded is
end entity tb_tr_nonbonded;
architecture str of tb_tr_nonbonded is
-
constant c_sim : boolean := true;
constant c_nof_gx : natural := 1;
constant c_mbps : natural := 6250;
@@ -128,9 +126,7 @@ architecture str of tb_tr_nonbonded is
signal bn_snk_val_cnt : t_slv_32_arr(c_nof_gx - 1 downto 0);
signal bn_clk_en : std_logic := '0';
-
begin
-
fn_tr_clk <= not fn_tr_clk after tr_clk_period / 2;
bn_tr_clk <= not bn_tr_clk after tr_clk_period / 2 when bn_clk_en = '1' else '0';
@@ -306,7 +302,4 @@ begin
end if;
wait;
end process;
-
end architecture str;
-
-
diff --git a/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
index 7af2f247875d33f08322295987d5cc5aa6ecd5f9..a2423241e25de40ef94f81bf2aebc7ade5021cb6 100644
--- a/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/mms_tr_xaui.vhd
@@ -83,9 +83,7 @@ entity mms_tr_xaui is
);
end mms_tr_xaui;
-
architecture wrap of mms_tr_xaui is
-
constant c_nof_select : natural := 2;
constant c_nof_select_w : natural := ceil_log2(c_nof_select);
constant c_sel_user : natural := 0;
@@ -125,9 +123,7 @@ architecture wrap of mms_tr_xaui is
signal demux_select_arr : t_select_arr(g_nof_xaui - 1 downto 0);
signal nxt_demux_select_arr : t_select_arr(g_nof_xaui - 1 downto 0);
-
begin
-
tx_rst_arr <= i_tx_rst_arr;
rx_rst_arr <= i_rx_rst_arr;
@@ -206,7 +202,6 @@ begin
);
gen_select : for i in 0 to g_nof_xaui - 1 generate
-
-- 0 = user data,
tx_siso_arr(i) <= mux_in_siso_2arr(i)(c_sel_user);
mux_in_sosi_2arr(i)(c_sel_user) <= tx_sosi_arr(i);
@@ -296,4 +291,3 @@ begin
end generate;
end wrap;
-
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
index f4ce31195805479dada360dad2b3b9abf50f2329..b93a840b0650b4fabb4d6344b09ba86f568ee5b6 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui.vhd
@@ -87,9 +87,7 @@ entity tr_xaui is
);
end tr_xaui;
-
architecture str of tr_xaui is
-
signal i_tx_rst_arr : std_logic_vector(g_nof_xaui - 1 downto 0);
signal i_rx_rst_arr : std_logic_vector(g_nof_xaui - 1 downto 0);
@@ -111,9 +109,7 @@ architecture str of tr_xaui is
signal tx_framer_siso_arr : t_dp_siso_arr(g_nof_xaui - 1 downto 0);
signal tx_framer_sosi_arr : t_dp_sosi_arr(g_nof_xaui - 1 downto 0);
-
begin
-
tx_rst_arr <= i_tx_rst_arr;
rx_rst_arr <= i_rx_rst_arr;
@@ -163,7 +159,6 @@ begin
-----------------------------------------------------------------------------
gen_sosi_io: if g_use_xgmii = false generate
gen_nof_user : for i in g_nof_xaui - 1 downto 0 generate
-
xgmii_tx_dc_in_arr(i) <= func_xgmii_dc(xgmii_tx_d_arr(i), xgmii_tx_c_arr(i));
xgmii_rx_d_arr(i) <= func_xgmii_d(xgmii_rx_dc_out_arr(i));
@@ -243,4 +238,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
index 30ce21748bc5ad7010b98790b0012789a92aac71..75a6f90acaba2e7c023fb842b76b06a15dc0f850 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui_deframer.vhd
@@ -39,7 +39,6 @@ entity tr_xaui_deframer is
end tr_xaui_deframer;
architecture rtl of tr_xaui_deframer is
-
constant c_xgmii_c_start_lo : std_logic_vector(c_xgmii_nof_lanes / 2 - 1 downto 0) := c_xgmii_c_start(c_xgmii_nof_lanes / 2 - 1 downto 0); -- 0x1
constant c_xgmii_c_term_lo : std_logic_vector(c_xgmii_nof_lanes / 2 - 1 downto 0) := c_xgmii_c_term (c_xgmii_nof_lanes / 2 - 1 downto 0); -- 0x8
@@ -70,9 +69,7 @@ architecture rtl of tr_xaui_deframer is
signal nxt_rx_data_hi : std_logic_vector(c_xgmii_data_w / 2 - 1 downto 0);
signal nxt_rx_data_lo : std_logic_vector(c_xgmii_data_w / 2 - 1 downto 0);
signal nxt_rx_data_val : std_logic;
-
begin
-
src_out.data(c_xgmii_data_w - 1 downto 0) <= rx_data_hi & rx_data_lo;
src_out.valid <= rx_data_val;
@@ -89,7 +86,6 @@ begin
-- nxt_rx_sosi: G G G D0 D1 D2 D3 G G G G G D4 D5
-- State : G G G D D D D G G G G G D D
-
-- FSM function, word boundary is 32b, tx_data_lo aligned to rx_data_lo:
-- =====================================================================
-- nxt_rx_sosi_hi = xgmii_rx_d_hi (during s_data)
@@ -106,7 +102,6 @@ begin
-- | nxt_rx_data<=DATA during all s_data cycles but the last
-- START(LS portion) detected on xgmii_rx_d_lo: nxt_state <= s_data
-
-- FSM function, word boundary is 32b, tx_data_lo aligned to rx_data_hi:
-- =====================================================================
-- We need to use the previous rx_data_hi:
@@ -125,7 +120,6 @@ begin
-- | nxt_rx_data<=GAP during first s_data_misaligned cycle (prev_state=s_gap)
-- START(LS portion) detected on xgmii_rx_d_hi: nxt_state <= s_data_misaligned
-
p_clk : process(rx_clk, rx_rst)
begin
if rx_rst = '1' then
@@ -203,10 +197,6 @@ begin
nxt_rx_data_hi <= (others => '0');
nxt_rx_data_lo <= (others => '0');
nxt_rx_data_val <= '0';
-
end case;
end process;
-
end rtl;
-
-
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd
index 30cda903e9621e5191b8672886dd9c28c91a94a1..5b678cd51c515fb4be7b4098e4573d7bd8887d2e 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui_framer.vhd
@@ -1,4 +1,3 @@
-
-------------------------------------------------------------------------------
--
-- Copyright (C) 2012
@@ -46,7 +45,6 @@ entity tr_xaui_framer is
end tr_xaui_framer;
architecture rtl of tr_xaui_framer is
-
type t_state_enum is (s_init, s_gap, s_data);
signal prev_state : t_state_enum;
@@ -63,9 +61,7 @@ architecture rtl of tr_xaui_framer is
signal gap_sosi : t_dp_sosi;
signal prev_gap_sosi : t_dp_sosi;
-
begin
-
xgmii_tx_d <= i_xgmii_tx_d;
xgmii_tx_c <= i_xgmii_tx_c;
@@ -152,10 +148,6 @@ begin
nxt_state <= s_gap;
nxt_xgmii_tx_d <= c_xgmii_d_idle;
nxt_xgmii_tx_c <= c_xgmii_c_idle;
-
end case;
end process;
-
end rtl;
-
-
diff --git a/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd b/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd
index 9ce36997513ba5bc1e1b647ebf7b991aa3042d48..532e735e4bd768c56a538e47e9303b511071db8c 100644
--- a/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd
+++ b/libraries/io/tr_xaui/src/vhdl/tr_xaui_mdio.vhd
@@ -54,9 +54,7 @@ entity tr_xaui_mdio is
);
end tr_xaui_mdio;
-
architecture str of tr_xaui_mdio is
-
constant c_mdio_xaui_phy_mdc_period : natural := 256; -- must be a power of 2
constant c_mdio_xaui_phy_hold_time : natural := 10;
constant c_mdio_xaui_phy_setup_time : natural := 2;
@@ -86,14 +84,11 @@ architecture str of tr_xaui_mdio is
signal ctlr_mdio_done_ack_evt : std_logic_vector(g_nof_xaui - 1 downto 0);
signal ctlr_exec_complete : std_logic_vector(g_nof_xaui - 1 downto 0);
-
begin
-
-- UniBoard FN resets 4 Vitesse chips using one output.
mdio_rst <= ctlr_mdio_rst(0);
gen_nof_xaui : for i in g_nof_xaui - 1 downto 0 generate
-
-- PHY core
u_mdio_phy : entity mdio_lib.mdio_phy
generic map(
@@ -204,8 +199,5 @@ begin
ctlr_mdio_done(i) <= mdio_done(i) when ctlr_exec_complete(i) = '0' else '0';
reg_mdio_done(i) <= mdio_done(i) when ctlr_exec_complete(i) = '1' else '0';
reg_mdio_rx_dat(i) <= mdio_rx_dat(i) when ctlr_exec_complete(i) = '1' else (others => '0');
-
end generate;
-
end str;
-
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
index 95bfa9185e9cd640358c7118bc8f4d647e9ddf9e..efe6772df5f67cf30c86aa0602ef24e64bafc3d3 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tb_tr_xaui.vhd
@@ -30,17 +30,14 @@ library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
use technology_lib.technology_select_pkg.all;
-
entity tb_tb_tr_xaui is
end tb_tb_tr_xaui;
-
architecture tb of tb_tb_tr_xaui is
constant c_tb_end_vec : std_logic_vector(31 downto 0) := (others => '1');
signal tb_end_vec : std_logic_vector(31 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
begin
-
-- g_technology : NATURAL := c_tech_stratixiv;
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_sim_level : NATURAL := 0; -- 0 = use IP; 1 = use fast serdes model
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
index 0beb2527ccd47d3136942024d9fa2ec2efb730d9..ba35ff1c89f7487e8c49996137ac0ec24b9fbe47 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui.vhd
@@ -48,7 +48,6 @@ entity tb_tr_xaui is
end entity tb_tr_xaui;
architecture str of tb_tr_xaui is
-
constant c_sim : boolean := true; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
constant tr_clk_period : time := 6.4 ns; -- 156.25 MHz
@@ -96,9 +95,7 @@ architecture str of tb_tr_xaui is
signal link_fault : std_logic;
signal verify_en : std_logic;
-
begin
-
-- Duration
p_tb_end : process
begin
@@ -227,7 +224,4 @@ begin
src_diag_md => (others => '1'),
src_val_cnt => src_val_cnt
);
-
end architecture str;
-
-
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd
index e2377f7b581f1b58f1b9598e819dd6613b835457..f2b093acaba633a484992bc7c1e47f5bc2a4a17f 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_deframer.vhd
@@ -39,7 +39,6 @@ entity tb_tr_xaui_deframer is
end tb_tr_xaui_deframer;
architecture tb of tb_tr_xaui_deframer is
-
constant c_clk_period : time := 10 ns;
constant c_rl : natural := 1;
constant c_tx_init : natural := 0;
@@ -85,9 +84,7 @@ architecture tb of tb_tr_xaui_deframer is
signal xgmii_rx_c_lo : std_logic_vector(c_xgmii_nof_lanes / 2 - 1 downto 0);
signal misalign : std_logic;
-
begin
-
rst <= '1', '0' after c_clk_period * 7;
clk <= not clk or tb_end after c_clk_period / 2;
@@ -210,5 +207,4 @@ begin
-- Verify DUT output incrementing data, prev_data is an auxiliary signal needed by the proc
proc_common_verify_data(c_rl, clk, verify_en, deframer_siso.ready, deframer_sosi.valid, deframer_sosi.data(c_xgmii_data_w - 1 downto 0), prev_data1);
proc_dp_verify_data("data", c_rl, clk, verify_en, deframer_siso.ready, deframer_sosi.valid, deframer_sosi.data(c_xgmii_data_w - 1 downto 0), prev_data2);
-
end tb;
diff --git a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_framer.vhd b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_framer.vhd
index e7d299f65aaf1d8a769607d63548baf7f7421dd0..d79c5274f8800f0835cb8ab499d2ec9b42107063 100644
--- a/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_framer.vhd
+++ b/libraries/io/tr_xaui/tb/vhdl/tb_tr_xaui_framer.vhd
@@ -32,7 +32,6 @@ entity tb_tr_xaui_framer is
end tb_tr_xaui_framer;
architecture tb of tb_tr_xaui_framer is
-
constant c_clk_period : time := 10 ns;
constant c_rl : natural := 1;
constant c_tx_init : natural := 0;
@@ -50,9 +49,7 @@ architecture tb of tb_tr_xaui_framer is
signal xgmii_tx_d : std_logic_vector(c_xgmii_data_w - 1 downto 0);
signal xgmii_tx_c : std_logic_vector(c_xgmii_nof_lanes - 1 downto 0);
-
begin
-
rst <= '1', '0' after c_clk_period * 7;
clk <= not clk after c_clk_period / 2;
@@ -102,5 +99,4 @@ begin
xgmii_tx_c => xgmii_tx_c
);
-
end tb;
diff --git a/libraries/technology/10gbase_r/sim_10gbase_r.vhd b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
index 0ac49c2ed6de09d77712418c87b3ea21b925691e..2c3e4959cf2e0cdf4860e3b5d384005d80a1e5b9 100644
--- a/libraries/technology/10gbase_r/sim_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/sim_10gbase_r.vhd
@@ -59,9 +59,7 @@ entity sim_10gbase_r is
);
end sim_10gbase_r;
-
architecture str of sim_10gbase_r is
-
constant c_tr_clk_period : time := tech_pll_clk_156_period; -- 6.400020 ns ~= 156.25 MHz --> model line rate : 156.25 MHz * 10/8 (encoding) * 64b (data width) = 12500 Mbps / lane
constant c_serdes_data_w : natural := c_xgmii_data_w; -- 64 b
@@ -74,11 +72,8 @@ architecture str of sim_10gbase_r is
-- XGMII data
signal xgmii_tx_d_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
signal xgmii_rx_d_arr : t_xgmii_d_arr(g_nof_channels - 1 downto 0);
-
begin
-
gen_nof_10gbase_r : for i in g_nof_channels - 1 downto 0 generate
-
-- Rewire XGMII
xgmii_tx_d_arr(i) <= func_xgmii_d(xgmii_tx_dc_arr(i));
xgmii_tx_c_arr(i) <= func_xgmii_c(xgmii_tx_dc_arr(i));
@@ -138,8 +133,6 @@ begin
rx_serial_in => rx_serial_arr(i)
);
-
end generate;
end str;
-
diff --git a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
index d49ed0cee30ec95747f77ef78f127a410d70992b..1ca8d66bf7b673cfa60b1c624cea621ff52cc2b8 100644
--- a/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tb_tech_10gbase_r.vhd
@@ -44,7 +44,6 @@ use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
use tech_pll_lib.tech_pll_component_pkg.all;
-
entity tb_tech_10gbase_r is
-- Test bench control parameters
generic (
@@ -53,9 +52,7 @@ entity tb_tech_10gbase_r is
);
end tb_tech_10gbase_r;
-
architecture tb of tb_tech_10gbase_r is
-
constant c_sim : boolean := true;
constant c_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model (not useful here, because no proper xgmii_tx_dc_arr stimuli)
constant phy_loopback_delay : time := sel_a_b(c_sim_level = 0, 1 ns, 0 ns);
@@ -77,9 +74,7 @@ architecture tb of tb_tech_10gbase_r is
signal tx_serial_arr : std_logic_vector(g_nof_channels - 1 downto 0);
signal tx_serial_arr_dly : std_logic_vector(g_nof_channels - 1 downto 0);
signal rx_serial_arr : std_logic_vector(g_nof_channels - 1 downto 0);
-
begin
-
tr_ref_clk_644 <= not tr_ref_clk_644 after tech_pll_clk_644_period / 2;
p_stimuli : process
@@ -161,5 +156,4 @@ begin
rx_serial_arr(0) <= '0'; -- model link fault only for channel 0
end if;
end process;
-
end tb;
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r.vhd b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
index 5ecde61bb2a16d58899e409376be8802c6472c2f..f2bfdc6e44ad7c9b00f26661875840ce34eee2d6 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r.vhd
@@ -64,14 +64,10 @@ entity tech_10gbase_r is
);
end tech_10gbase_r;
-
architecture str of tech_10gbase_r is
-
constant c_use_technology : boolean := g_sim = false or g_sim_level = 0;
constant c_use_sim_model : boolean := not c_use_technology;
-
begin
-
gen_ip_arria10 : if c_use_technology = true and g_technology = c_tech_arria10_proto generate
u0 : entity work.tech_10gbase_r_arria10
generic map (g_sim, g_nof_channels)
@@ -127,4 +123,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
index b1c48d128a0d331090c5eff00dc666fe91a18f3e..f106ec2d00a625f32cd321a3bdd7d2c41fde0a25 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10.vhd
@@ -65,16 +65,13 @@ entity tech_10gbase_r_arria10 is
);
end tech_10gbase_r_arria10;
-
architecture str of tech_10gbase_r_arria10 is
-
-- FIXME check selection of g_nof_channels to be 1,4,12 or 24
--CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 12
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
constant c_nof_channels_per_ip : natural := g_nof_channels;
-
constant IP_SIZE : natural := c_nof_channels_per_ip; -- short constant name alias to improve index readability
constant IP_SIZE_DATA : natural := IP_SIZE * c_xgmii_data_w;
constant IP_SIZE_CONTROL : natural := IP_SIZE * c_xgmii_nof_lanes;
@@ -112,9 +109,7 @@ architecture str of tech_10gbase_r_arria10 is
signal atx_pll_locked_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0');
signal atx_pll_locked : std_logic;
signal atx_pll_cal_busy : std_logic;
-
begin
-
-- Clocks
tr_coreclkin(0) <= clk_156;
@@ -126,6 +121,7 @@ begin
gen_hw : if g_sim = false generate
atx_pll_locked_arr(I) <= atx_pll_locked;
end generate;
+
gen_sim : if g_sim = true generate
atx_pll_locked_arr(I) <= transport atx_pll_locked after tech_pll_clk_156_period * I;
end generate;
@@ -137,7 +133,6 @@ begin
xgmii_rx_dc_arr(I) <= func_xgmii_dc(rx_parallel_data_arr(I), rx_control_arr(I));
end generate;
-
gen_phy_1 : if c_nof_channels_per_ip = 1 generate
gen_channels : for I in 0 to g_nof_channels - 1 generate
u_ip_arria10_phy_10gbase_r : ip_arria10_phy_10gbase_r
@@ -206,8 +201,6 @@ begin
end generate;
end generate;
-
-
gen_phy_4 : if c_nof_channels_per_ip = 4 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -289,9 +282,6 @@ begin
);
end generate;
-
-
-
gen_phy_12 : if c_nof_channels_per_ip = 12 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -373,9 +363,6 @@ begin
);
end generate;
-
-
-
gen_phy_24 : if c_nof_channels_per_ip = 24 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -457,9 +444,6 @@ begin
);
end generate;
-
-
-
gen_phy_48 : if c_nof_channels_per_ip = 48 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -541,7 +525,6 @@ begin
);
end generate;
-
-- ATX PLL
u_ip_arria10_transceiver_pll_10g : ip_arria10_transceiver_pll_10g
port map (
@@ -552,5 +535,4 @@ begin
mcgb_rst => atx_pll_powerdown_arr(0),
mcgb_serial_clk => tx_serial_clk(0)
);
-
end str;
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
index a8003b6bf82fd9b6bcb78afd1ae7cfdf1d47830d..b69ecf769b7f83c1c57ffa17e339b5e6fdc9b0f8 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e1sg.vhd
@@ -54,7 +54,6 @@ entity tech_10gbase_r_arria10_e1sg is
reg_ip_arria10_e1sg_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e1sg_phy_10gbase_r_24_miso : out t_mem_miso;
-
-- Transceiver ATX PLL reference clock
tr_ref_clk_644 : in std_logic; -- 644.531250 MHz
@@ -74,16 +73,13 @@ entity tech_10gbase_r_arria10_e1sg is
);
end tech_10gbase_r_arria10_e1sg;
-
architecture str of tech_10gbase_r_arria10_e1sg is
-
-- FIXME check selection of g_nof_channels to be 1,4,12 or 24
--CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 12
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
constant c_nof_channels_per_ip : natural := g_nof_channels;
-
constant IP_SIZE : natural := c_nof_channels_per_ip; -- short constant name alias to improve index readability
constant IP_SIZE_DATA : natural := IP_SIZE * c_xgmii_data_w;
constant IP_SIZE_CONTROL : natural := IP_SIZE * c_xgmii_nof_lanes;
@@ -121,9 +117,7 @@ architecture str of tech_10gbase_r_arria10_e1sg is
signal atx_pll_locked_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0');
signal atx_pll_locked : std_logic;
signal atx_pll_cal_busy : std_logic;
-
begin
-
-- Clocks
tr_coreclkin(0) <= clk_156;
@@ -135,6 +129,7 @@ begin
gen_hw : if g_sim = false generate
atx_pll_locked_arr(I) <= atx_pll_locked;
end generate;
+
gen_sim : if g_sim = true generate
atx_pll_locked_arr(I) <= transport atx_pll_locked after tech_pll_clk_156_period * I;
end generate;
@@ -146,7 +141,6 @@ begin
xgmii_rx_dc_arr(I) <= func_xgmii_dc(rx_parallel_data_arr(I), rx_control_arr(I));
end generate;
-
gen_phy_1 : if c_nof_channels_per_ip = 1 generate
gen_channels : for I in 0 to g_nof_channels - 1 generate
u_ip_arria10_e1sg_phy_10gbase_r : ip_arria10_e1sg_phy_10gbase_r
@@ -377,9 +371,6 @@ begin
);
end generate;
-
-
-
gen_phy_12 : if c_nof_channels_per_ip = 12 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -461,9 +452,6 @@ begin
);
end generate;
-
-
-
gen_phy_24 : if c_nof_channels_per_ip = 24 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -554,9 +542,6 @@ begin
);
end generate;
-
-
-
gen_phy_48 : if c_nof_channels_per_ip = 48 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -638,7 +623,6 @@ begin
);
end generate;
-
-- ATX PLL
u_ip_arria10_e1sg_transceiver_pll_10g : ip_arria10_e1sg_transceiver_pll_10g
port map (
@@ -649,5 +633,4 @@ begin
mcgb_rst => atx_pll_powerdown_arr(0),
mcgb_serial_clk => tx_serial_clk(0)
);
-
end str;
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
index 858251d6dd9c0e18260a795bf5d30d0b6a2929a5..2b3c08f784ffb676f6e66d4392cef61e9bcb4224 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e2sg.vhd
@@ -54,7 +54,6 @@ entity tech_10gbase_r_arria10_e2sg is
reg_ip_arria10_e2sg_phy_10gbase_r_24_mosi : in t_mem_mosi := c_mem_mosi_rst;
reg_ip_arria10_e2sg_phy_10gbase_r_24_miso : out t_mem_miso;
-
-- Transceiver ATX PLL reference clock
tr_ref_clk_644 : in std_logic; -- 644.531250 MHz
@@ -74,16 +73,13 @@ entity tech_10gbase_r_arria10_e2sg is
);
end tech_10gbase_r_arria10_e2sg;
-
architecture str of tech_10gbase_r_arria10_e2sg is
-
-- FIXME check selection of g_nof_channels to be 1,4,12 or 24
--CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 12
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
constant c_nof_channels_per_ip : natural := g_nof_channels;
-
constant IP_SIZE : natural := c_nof_channels_per_ip; -- short constant name alias to improve index readability
constant IP_SIZE_DATA : natural := IP_SIZE * c_xgmii_data_w;
constant IP_SIZE_CONTROL : natural := IP_SIZE * c_xgmii_nof_lanes;
@@ -121,9 +117,7 @@ architecture str of tech_10gbase_r_arria10_e2sg is
signal atx_pll_locked_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0');
signal atx_pll_locked : std_logic;
signal atx_pll_cal_busy : std_logic;
-
begin
-
-- Clocks
tr_coreclkin(0) <= clk_156;
@@ -135,6 +129,7 @@ begin
gen_hw : if g_sim = false generate
atx_pll_locked_arr(I) <= atx_pll_locked;
end generate;
+
gen_sim : if g_sim = true generate
atx_pll_locked_arr(I) <= transport atx_pll_locked after tech_pll_clk_156_period * I;
end generate;
@@ -146,7 +141,6 @@ begin
xgmii_rx_dc_arr(I) <= func_xgmii_dc(rx_parallel_data_arr(I), rx_control_arr(I));
end generate;
-
gen_phy_1 : if c_nof_channels_per_ip = 1 generate
gen_channels : for I in 0 to g_nof_channels - 1 generate
u_ip_arria10_e2sg_phy_10gbase_r : ip_arria10_e2sg_phy_10gbase_r
@@ -377,9 +371,6 @@ begin
);
end generate;
-
-
-
gen_phy_12 : if c_nof_channels_per_ip = 12 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -461,9 +452,6 @@ begin
);
end generate;
-
-
-
gen_phy_24 : if c_nof_channels_per_ip = 24 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -554,9 +542,6 @@ begin
);
end generate;
-
-
-
gen_phy_48 : if c_nof_channels_per_ip = 48 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -638,7 +623,6 @@ begin
);
end generate;
-
-- ATX PLL
u_ip_arria10_e2sg_transceiver_pll_10g : ip_arria10_e2sg_transceiver_pll_10g
port map (
@@ -649,5 +633,4 @@ begin
mcgb_rst => atx_pll_powerdown_arr(0),
mcgb_serial_clk => tx_serial_clk(0)
);
-
end str;
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd
index c736f5453e0e9e8cfdba7b7cc152a3fef3e0d6f4..6881254db1d2fecacccb4b246ad305ac09155046 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_arria10_e3sge3.vhd
@@ -72,16 +72,13 @@ entity tech_10gbase_r_arria10_e3sge3 is
);
end tech_10gbase_r_arria10_e3sge3;
-
architecture str of tech_10gbase_r_arria10_e3sge3 is
-
-- FIXME check selection of g_nof_channels to be 1,4,12 or 24
--CONSTANT c_nof_channels_per_ip : NATURAL := sel_a_b(g_nof_channels=24, 24, 1); -- only support single 1 or block of 12
--CONSTANT c_nof_channels_per_ip : NATURAL := 24 WHEN g_nof_channels=24 ELSE 12 WHEN g_nof_channels=12 ELSE 1;
constant c_nof_channels_per_ip : natural := g_nof_channels;
-
constant IP_SIZE : natural := c_nof_channels_per_ip; -- short constant name alias to improve index readability
constant IP_SIZE_DATA : natural := IP_SIZE * c_xgmii_data_w;
constant IP_SIZE_CONTROL : natural := IP_SIZE * c_xgmii_nof_lanes;
@@ -119,9 +116,7 @@ architecture str of tech_10gbase_r_arria10_e3sge3 is
signal atx_pll_locked_arr : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '0');
signal atx_pll_locked : std_logic;
signal atx_pll_cal_busy : std_logic;
-
begin
-
-- Clocks
tr_coreclkin(0) <= clk_156;
@@ -133,6 +128,7 @@ begin
gen_hw : if g_sim = false generate
atx_pll_locked_arr(I) <= atx_pll_locked;
end generate;
+
gen_sim : if g_sim = true generate
atx_pll_locked_arr(I) <= transport atx_pll_locked after tech_pll_clk_156_period * I;
end generate;
@@ -144,7 +140,6 @@ begin
xgmii_rx_dc_arr(I) <= func_xgmii_dc(rx_parallel_data_arr(I), rx_control_arr(I));
end generate;
-
gen_phy_1 : if c_nof_channels_per_ip = 1 generate
gen_channels : for I in 0 to g_nof_channels - 1 generate
u_ip_arria10_e3sge3_phy_10gbase_r : ip_arria10_e3sge3_phy_10gbase_r
@@ -213,8 +208,6 @@ begin
end generate;
end generate;
-
-
gen_phy_4 : if c_nof_channels_per_ip = 4 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -296,9 +289,6 @@ begin
);
end generate;
-
-
-
gen_phy_12 : if c_nof_channels_per_ip = 12 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -380,9 +370,6 @@ begin
);
end generate;
-
-
-
gen_phy_24 : if c_nof_channels_per_ip = 24 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -473,9 +460,6 @@ begin
);
end generate;
-
-
-
gen_phy_48 : if c_nof_channels_per_ip = 48 generate
tx_serial_clk_slv <= (others => tx_serial_clk(0));
tr_coreclkin_slv <= (others => tr_coreclkin(0));
@@ -557,7 +541,6 @@ begin
);
end generate;
-
-- ATX PLL
u_ip_arria10_e3sge3_transceiver_pll_10g : ip_arria10_e3sge3_transceiver_pll_10g
port map (
@@ -568,5 +551,4 @@ begin
mcgb_rst => atx_pll_powerdown_arr(0),
mcgb_serial_clk => tx_serial_clk(0)
);
-
end str;
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
index 7c8da07f3df305691f7fb82388df9deccf100c48..a8c8d20b50041cc02ac6832370421b749e0361bb 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
@@ -25,7 +25,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_10gbase_r_component_pkg is
-
------------------------------------------------------------------------------
-- ip_arria10
------------------------------------------------------------------------------
@@ -898,7 +897,6 @@ package tech_10gbase_r_component_pkg is
);
end component ip_arria10_e1sg_phy_10gbase_r_3;
-
component ip_arria10_e1sg_phy_10gbase_r_4
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
@@ -1359,7 +1357,6 @@ package tech_10gbase_r_component_pkg is
);
end component;
-
component ip_arria10_e2sg_phy_10gbase_r_4
port (
reconfig_write : in std_logic_vector(0 downto 0) := (others => '0'); -- reconfig_avmm.write
diff --git a/libraries/technology/clkbuf/tech_clkbuf.vhd b/libraries/technology/clkbuf/tech_clkbuf.vhd
index d4de3e9e56c963b524f8bf2ca11ae88af4d40ce1..ccb8eb551dc32f6bac7d4f5cac5e8c6d4fb6a6c4 100644
--- a/libraries/technology/clkbuf/tech_clkbuf.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf.vhd
@@ -43,9 +43,7 @@ entity tech_clkbuf is
end tech_clkbuf;
architecture str of tech_clkbuf is
-
begin
-
-----------------------------------------------------------------------------
-- ip_arria10
-----------------------------------------------------------------------------
diff --git a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
index c071028b4f21131c0cd407abdeba8da25244c42d..11debb90e497181403d8842d5c1f5978c4337665 100644
--- a/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
+++ b/libraries/technology/clkbuf/tech_clkbuf_component_pkg.vhd
@@ -25,7 +25,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_clkbuf_component_pkg is
-
-----------------------------------------------------------------------------
-- ip_arria10
-----------------------------------------------------------------------------
@@ -37,7 +36,6 @@ package tech_clkbuf_component_pkg is
);
end component;
-
-----------------------------------------------------------------------------
-- ip_arria10_e3sge3
-----------------------------------------------------------------------------
@@ -72,4 +70,3 @@ package tech_clkbuf_component_pkg is
end component;
end tech_clkbuf_component_pkg;
-
diff --git a/libraries/technology/ddr/sim_ddr.vhd b/libraries/technology/ddr/sim_ddr.vhd
index 5c7aeaa1225be135271bad253c37611cfe3be827..5d719ed9d9f770ec3def88939edfe9088297ccf5 100644
--- a/libraries/technology/ddr/sim_ddr.vhd
+++ b/libraries/technology/ddr/sim_ddr.vhd
@@ -63,7 +63,6 @@
-- application such that the fixed size sim_ddr memory is as small as
-- possible.
-
library IEEE, common_lib, technology_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -92,9 +91,7 @@ entity sim_ddr is
);
end sim_ddr;
-
architecture str of sim_ddr is
-
-- DDR size and controller data width
constant c_nof_addr : natural := 2**func_tech_ddr_ctlr_address_w(g_tech_ddr); -- 8192;
constant c_dat_w : natural := func_tech_ddr_ctlr_data_w(g_tech_ddr); -- 256;
@@ -122,9 +119,7 @@ architecture str of sim_ddr is
signal dbg_c_nof_addr : natural;
signal dbg_c_dat_w : natural;
signal mem_state : t_mem_state;
-
begin
-
dbg_g_tech_ddr <= g_tech_ddr;
dbg_c_nof_addr <= c_nof_addr;
dbg_c_dat_w <= c_dat_w;
@@ -143,9 +138,7 @@ begin
-- Process variables get initalized once and then they keep their state
variable v_mem_arr : t_mem_arr := (others => (others => '0'));
variable v : t_mem_state := (0, 0, 0, false, false, false, false, 0, 0);
-
begin
-
if rising_edge(sim_clk) then
-- Burst begin
@@ -225,8 +218,5 @@ begin
-- Show DDR memory state in wave window
mem_state <= v;
end if;
-
end process;
-
end str;
-
diff --git a/libraries/technology/ddr/tech_ddr.vhd b/libraries/technology/ddr/tech_ddr.vhd
index 81b8142546dfd39718e7b41755332bab11f88c87..e15ba40ef64495f7c64b282e72a75875e96aea95 100644
--- a/libraries/technology/ddr/tech_ddr.vhd
+++ b/libraries/technology/ddr/tech_ddr.vhd
@@ -68,11 +68,8 @@ entity tech_ddr is
);
end tech_ddr;
-
architecture str of tech_ddr is
-
begin
-
-----------------------------------------------------------------------------
-- Technology IP cores
-----------------------------------------------------------------------------
@@ -149,4 +146,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/ddr/tech_ddr_arria10.vhd b/libraries/technology/ddr/tech_ddr_arria10.vhd
index 1273503b6ce8a815bbff2ed71ee09974df03d807..0bf13a950e7a03dd6332747af1d46a9a58d0580c 100644
--- a/libraries/technology/ddr/tech_ddr_arria10.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: DDR4 memory access component for Arria10.
-- Description:
-- Remarks:
@@ -68,9 +67,7 @@ entity tech_ddr_arria10 is
);
end tech_ddr_arria10;
-
architecture str of tech_ddr_arria10 is
-
constant c_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
constant c_ctlr_address_w : natural := 26; -- func_tech_ddr_ctlr_address_w(g_tech_ddr);
@@ -82,16 +79,13 @@ architecture str of tech_ddr_arria10 is
signal local_cal_success : std_logic;
signal local_cal_fail : std_logic;
-
begin
-
ctlr_gen_clk <= i_ctlr_gen_clk;
ref_rst_n <= not ref_rst;
ctlr_gen_rst <= not ctlr_gen_rst_n;
gen_ip_arria10_ddr4_4g_2000 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 4 and g_tech_ddr.mts = 2000 generate
-
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
phy_ou.odt(1) <= '0';
@@ -144,11 +138,9 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
gen_ip_arria10_ddr4_4g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 4 and g_tech_ddr.mts = 1600 generate
-
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
phy_ou.odt(1) <= '0';
@@ -201,7 +193,6 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
end str;
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
index 3bbe8bdb32d184bd2b1decd6bea156bb6de274a7..ab1bb6058ef7ddbfa90f8021c2947b5a8cdbc81e 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e1sg.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: DDR4 memory access component for Arria10.
-- Description:
-- Remarks:
@@ -71,9 +70,7 @@ entity tech_ddr_arria10_e1sg is
);
end tech_ddr_arria10_e1sg;
-
architecture str of tech_ddr_arria10_e1sg is
-
constant c_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
constant c_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr);
@@ -85,16 +82,13 @@ architecture str of tech_ddr_arria10_e1sg is
signal local_cal_success : std_logic;
signal local_cal_fail : std_logic;
-
begin
-
ctlr_gen_clk <= i_ctlr_gen_clk;
ref_rst_n <= not ref_rst;
ctlr_gen_rst <= not ctlr_gen_rst_n;
gen_ip_arria10_e1sg_ddr4_4g_2000 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 4 and g_tech_ddr.mts = 2000 generate
-
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
phy_ou.odt(1) <= '0';
@@ -147,11 +141,9 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
gen_ip_arria10_e1sg_ddr4_4g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 4 and g_tech_ddr.mts = 1600 generate
-
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
phy_ou.odt(1) <= '0';
@@ -204,11 +196,9 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
gen_ip_arria10_e1sg_ddr4_8g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
-
u_ip_arria10_e1sg_ddr4_8g_1600 : ip_arria10_e1sg_ddr4_8g_1600
port map (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -257,11 +247,9 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
gen_ip_arria10_e1sg_ddr4_16g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 16 and g_tech_ddr.mts = 1600 generate
-
u_ip_arria10_e1sg_ddr4_16g_1600 : ip_arria10_e1sg_ddr4_16g_1600
port map (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -310,8 +298,6 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
-
end str;
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
index de086516b57d14d53ded4f07e4b3ba904120d930..0f98ab5202f0e934d570596b80d1b31c68050b95 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e2sg.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: DDR4 memory access component for Arria10.
-- Description:
-- Remarks:
@@ -70,9 +69,7 @@ entity tech_ddr_arria10_e2sg is
);
end tech_ddr_arria10_e2sg;
-
architecture str of tech_ddr_arria10_e2sg is
-
constant c_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
constant c_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr);
@@ -88,18 +85,13 @@ architecture str of tech_ddr_arria10_e2sg is
signal amm_readdata : std_logic_vector(c_ctlr_ip_data_w - 1 downto 0) := (others => '0');
signal amm_writedata : std_logic_vector(c_ctlr_ip_data_w - 1 downto 0) := (others => '0');
-
-
begin
-
ctlr_gen_clk <= i_ctlr_gen_clk;
ref_rst_n <= not ref_rst;
ctlr_gen_rst <= not ctlr_gen_rst_n;
-
gen_ip_arria10_e2sg_ddr4_8g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
-
u_ip_arria10_e2sg_ddr4_8g_1600 : ip_arria10_e2sg_ddr4_8g_1600
port map (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -148,12 +140,9 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
-
gen_ip_arria10_e2sg_ddr4_8g_2400 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 8 and g_tech_ddr.mts = 2400 generate
-
u_ip_arria10_e2sg_ddr4_8g_2400 : ip_arria10_e2sg_ddr4_8g_2400
port map (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -202,12 +191,9 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
-
gen_ip_arria10_e2sg_ddr4_16g_1600_64b : if g_tech_ddr.name = "DDR4" and c_gigabytes = 16 and g_tech_ddr.mts = 1600 and g_tech_ddr.dq_w = 64 generate
-
u_ip_arria10_e2sg_ddr4_16g_1600_64b : ip_arria10_e2sg_ddr4_16g_1600_64b
port map (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -256,12 +242,9 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
-
gen_ip_arria10_e2sg_ddr4_16g_1600_72b : if g_tech_ddr.name = "DDR4" and c_gigabytes = 16 and g_tech_ddr.mts = 1600 and g_tech_ddr.dq_w = 72 generate
-
u_ip_arria10_e2sg_ddr4_16g_1600_72b : ip_arria10_e2sg_ddr4_16g_1600_72b
port map (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -316,7 +299,6 @@ begin
ctlr_miso.cal_fail <= '0';
end generate;
-
gen_no_rewire_data : if g_tech_ddr.mem_dq_w = g_tech_ddr.dq_w generate
ctlr_miso.rddata(c_ctlr_ip_data_w - 1 downto 0) <= amm_readdata;
amm_writedata <= ctlr_mosi.wrdata(c_ctlr_ip_data_w - 1 downto 0);
@@ -327,5 +309,4 @@ begin
end generate;
end generate;
-
end str;
diff --git a/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd b/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd
index cbd50202b66c01ce63d8b7af70ea214c2004fb26..c7dd3c97dc1b666a02f87466c5419cf782b4140f 100644
--- a/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd
+++ b/libraries/technology/ddr/tech_ddr_arria10_e3sge3.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: DDR4 memory access component for Arria10.
-- Description:
-- Remarks:
@@ -70,9 +69,7 @@ entity tech_ddr_arria10_e3sge3 is
);
end tech_ddr_arria10_e3sge3;
-
architecture str of tech_ddr_arria10_e3sge3 is
-
constant c_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
constant c_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr);
@@ -84,16 +81,13 @@ architecture str of tech_ddr_arria10_e3sge3 is
signal local_cal_success : std_logic;
signal local_cal_fail : std_logic;
-
begin
-
ctlr_gen_clk <= i_ctlr_gen_clk;
ref_rst_n <= not ref_rst;
ctlr_gen_rst <= not ctlr_gen_rst_n;
gen_ip_arria10_e3sge3_ddr4_4g_2000 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 4 and g_tech_ddr.mts = 2000 generate
-
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
phy_ou.odt(1) <= '0';
@@ -146,11 +140,9 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
gen_ip_arria10_e3sge3_ddr4_4g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 4 and g_tech_ddr.mts = 1600 generate
-
phy_ou.cs_n(1) <= '1';
phy_ou.cke(1) <= '0';
phy_ou.odt(1) <= '0';
@@ -203,11 +195,9 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
gen_ip_arria10_e3sge3_ddr4_8g_1600 : if g_tech_ddr.name = "DDR4" and c_gigabytes = 8 and g_tech_ddr.mts = 1600 generate
-
u_ip_arria10_e3sge3_ddr4_8g_1600 : ip_arria10_e3sge3_ddr4_8g_1600
port map (
amm_ready_0 => ctlr_miso.waitrequest_n, -- ctrl_amm_avalon_slave_0.waitrequest_n
@@ -256,7 +246,6 @@ begin
ctlr_miso.done <= local_cal_success and not local_cal_fail when rising_edge(i_ctlr_gen_clk);
ctlr_miso.cal_ok <= local_cal_success;
ctlr_miso.cal_fail <= local_cal_fail;
-
end generate;
end str;
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index db101fb47e5336df39db227e663f6a5e80b444e0..fb1f0bf99002831f2659b41cd0d0a6d60291c365 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -26,7 +26,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_ddr_component_pkg is
-
------------------------------------------------------------------------------
-- ip_stratixiv
------------------------------------------------------------------------------
diff --git a/libraries/technology/ddr/tech_ddr_mem_model.vhd b/libraries/technology/ddr/tech_ddr_mem_model.vhd
index 379aca836f9f2a2f3a457edba0048f2bd026ba05..dcdb187b78702ac100ebc6c233ac2b8e71ddddea 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model.vhd
@@ -33,7 +33,6 @@
library ip_stratixiv_ddr3_mem_model_lib;
library ed_sim_altera_emif_mem_model_core_ddr4_141;
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -56,16 +55,12 @@ entity tech_ddr_memory_model is
);
end tech_ddr_memory_model;
-
architecture str of tech_ddr_memory_model is
-
constant c_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
signal dbg_g_tech_ddr : t_c_tech_ddr := g_tech_ddr;
signal dbg_c_gigabytes : integer := c_gigabytes;
-
begin
-
gen_ip_stratixiv_ddr_memory_model : if g_tech_ddr.name = "DDR3" generate
u_ip_stratixiv_ddr_memory_model : alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
generic map (
@@ -137,4 +132,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index 7e537fc95fdb5bf91a55ae90dfc553463bb89605..65a8e2493f0a0351fde3803f1cfe973e43c56c9b 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -26,7 +26,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_ddr_mem_model_component_pkg is
-
------------------------------------------------------------------------------
-- ip_stratixiv
------------------------------------------------------------------------------
@@ -108,7 +107,6 @@ package tech_ddr_mem_model_component_pkg is
);
end component ed_sim_altera_emif_mem_model_141_z3tvrmq;
-
end tech_ddr_mem_model_component_pkg;
package body tech_ddr_mem_model_component_pkg is
diff --git a/libraries/technology/ddr/tech_ddr_pkg.vhd b/libraries/technology/ddr/tech_ddr_pkg.vhd
index bf49e25c72aa3acbd8ae4e237fe2616e015f5aa7..8dd9f402e491b7f46abe85d2ab5bbd657fd64677 100644
--- a/libraries/technology/ddr/tech_ddr_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_pkg.vhd
@@ -26,7 +26,6 @@ use common_lib.common_pkg.all;
use technology_lib.technology_pkg.all;
package tech_ddr_pkg is
-
-- Gather all DDR parameters in one record
type t_c_tech_ddr is record
-- PHY variant within a technology
@@ -204,7 +203,6 @@ package tech_ddr_pkg is
end tech_ddr_pkg;
package body tech_ddr_pkg is
-
function func_tech_sel_ddr(g_technology : natural; g_ddr3, g_ddr4 : t_c_tech_ddr) return t_c_tech_ddr is
begin
case g_technology is
@@ -215,6 +213,7 @@ package body tech_ddr_pkg is
when c_tech_arria10_e2sg => return g_ddr4; -- unb2c
when others => return g_ddr3;
end case;
+
end;
function func_tech_sel_ddr(g_sel : boolean; a, b : t_c_tech_ddr) return t_c_tech_ddr is
@@ -298,4 +297,3 @@ package body tech_ddr_pkg is
end;
end tech_ddr_pkg;
-
diff --git a/libraries/technology/ddr/tech_ddr_stratixiv.vhd b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
index 679ece657275027e3a8507cebf95e0408ddb8fb8..b4713542562502c913ebef831a4cc0883e35ecf5 100644
--- a/libraries/technology/ddr/tech_ddr_stratixiv.vhd
+++ b/libraries/technology/ddr/tech_ddr_stratixiv.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: DDR3 memory access component for Stratix IV.
-- Description:
-- Remarks:
@@ -72,9 +71,7 @@ entity tech_ddr_stratixiv is
);
end tech_ddr_stratixiv;
-
architecture str of tech_ddr_stratixiv is
-
constant c_gigabytes : integer := func_tech_ddr_module_gigabytes(g_tech_ddr);
constant c_ctlr_address_w : natural := func_tech_ddr_ctlr_address_w(g_tech_ddr);
@@ -90,9 +87,7 @@ architecture str of tech_ddr_stratixiv is
signal i_mem_cke : std_logic;
signal i_mem_cs_n : std_logic;
signal i_mem_odt : std_logic;
-
begin
-
ref_rst_n <= not ref_rst;
gen_ip_stratixiv_ddr3_uphy_4g_800_master : if g_tech_ddr.name = "DDR3" and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = true and g_tech_ddr.rank = "DUAL " generate
@@ -251,7 +246,6 @@ begin
phy_ou.cke(0) <= i_mem_cke;
phy_ou.cs_n(0) <= i_mem_cs_n;
phy_ou.odt(0) <= i_mem_odt;
-
end generate;
gen_ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave : if g_tech_ddr.name = "DDR3" and c_gigabytes = 4 and g_tech_ddr.mts = 800 and g_tech_ddr.master = false and g_tech_ddr.rank = "SINGLE" generate
@@ -306,7 +300,6 @@ begin
phy_ou.cke(0) <= i_mem_cke;
phy_ou.cs_n(0) <= i_mem_cs_n;
phy_ou.odt(0) <= i_mem_odt;
-
end generate;
gen_ip_stratixiv_ddr3_uphy_16g_dual_rank_800 : if g_tech_ddr.name = "DDR3" and c_gigabytes = 16 and g_tech_ddr.mts = 800 and g_tech_ddr.master = true and g_tech_ddr.rank = "DUAL " generate
@@ -359,9 +352,6 @@ begin
pll_config_clk => OPEN, -- .pll_config_clk
dll_delayctrl => open -- dll_sharing.dll_delayctrl
);
-
-
-
end generate;
i_ctlr_gen_rst <= not ctlr_gen_rst_n;
@@ -379,5 +369,4 @@ begin
ctlr_gen_rst <= i_ctlr_gen_rst;
ctlr_gen_clk_2x <= i_ctlr_gen_clk_2x;
-
end str;
diff --git a/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
index f8adbe53e85c4f1f8c7e8fed6ad0c13e398862d7..5922075d48a3726aa8ab93702d41d22114c58a0f 100644
--- a/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tb_tech_eth_10g.vhd
@@ -36,9 +36,7 @@ use common_lib.tb_common_pkg.all;
entity tb_tb_tech_eth_10g is
end tb_tb_tech_eth_10g;
-
architecture tb of tb_tb_tech_eth_10g is
-
constant c_644 : time := tech_pll_clk_644_period;
constant c_156 : time := 6.4 ns;
constant c_data_type : natural := c_tb_tech_mac_10g_data_type_symbols;
@@ -46,9 +44,7 @@ architecture tb of tb_tb_tech_eth_10g is
constant c_tb_end_vec : std_logic_vector(7 downto 0) := (others => '1');
signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
-
begin
-
-- g_technology : NATURAL := c_tech_select_default;
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
@@ -68,5 +64,4 @@ begin
proc_common_stop_simulation(tb_end);
proc_common_timeout_failure(1 ms, tb_end);
-
end tb;
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
index 013033493adb156f3c6dd76893478dd2456c0457..7cd775e11e755268a9a5bc733621e67ec0412c12 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g.vhd
@@ -67,9 +67,7 @@ entity tb_tech_eth_10g is
);
end tb_tech_eth_10g;
-
architecture tb of tb_tech_eth_10g is
-
constant c_sim : boolean := true; -- tr_xaui_align_dly has time delay ~ 1 sec, so not suitable for simulation
constant c_nof_channels : natural := 1; -- fixed in this tb
@@ -163,9 +161,7 @@ architecture tb of tb_tech_eth_10g is
signal tx_pkt_cnt : natural := 0;
signal rx_pkt_cnt : natural := 0;
signal rx_toggle : std_logic; -- toggle after every received packet
-
begin
-
cal_clk <= not cal_clk after cal_clk_period / 2; -- Calibration clock
-- debug signals to ease monitoring in wave window
@@ -404,5 +400,4 @@ begin
rx_end => rx_end,
tb_end => tb_end
);
-
end tb;
diff --git a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
index 895b8123fd0cab96f3edcab7480dfc3e7d192ad5..2f83f74fcb89b1743949f3a015763b7090746e38 100644
--- a/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
+++ b/libraries/technology/eth_10g/tb_tech_eth_10g_ppm.vhd
@@ -48,7 +48,6 @@ entity tb_tech_eth_10g_ppm is
end tb_tech_eth_10g_ppm;
architecture tb of tb_tech_eth_10g_ppm is
-
-- PHY 10gbase_r
signal serial_tx_0 : std_logic; -- 1 lane
signal serial_tx_1 : std_logic;
@@ -56,9 +55,7 @@ architecture tb of tb_tech_eth_10g_ppm is
-- PHY XAUI
signal xaui_tx_0 : std_logic_vector(c_nof_xaui_lanes - 1 downto 0); -- 4 lanes
signal xaui_tx_1 : std_logic_vector(c_nof_xaui_lanes - 1 downto 0);
-
begin
-
u_tb_tech_eth_10g_0 : entity work.tb_tech_eth_10g
generic map (
g_technology => g_technology,
@@ -94,5 +91,4 @@ begin
xaui_tx_out => xaui_tx_1,
xaui_rx_in => xaui_tx_0
);
-
end tb;
diff --git a/libraries/technology/eth_10g/tech_eth_10g.vhd b/libraries/technology/eth_10g/tech_eth_10g.vhd
index 4a8677a591f14752d36cd958bc48e7d06e232eb8..fa7502cef39091424edc574eb00964e5bb9a20d0 100644
--- a/libraries/technology/eth_10g/tech_eth_10g.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and 10gbase_r
-- Description:
-- . For c_tech_stratixiv:
@@ -130,10 +129,8 @@ entity tech_eth_10g is
);
end tech_eth_10g;
-
architecture str of tech_eth_10g is
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : entity work.tech_eth_10g_stratixiv
generic map (
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
index 20eac55b10b876342b3de9efbc66ca3076badf57..e24a5253edfcd33d3c2feda336b69c23ac56c335 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10
-- Description
--
@@ -133,9 +132,7 @@ entity tech_eth_10g_arria10 is
);
end tech_eth_10g_arria10;
-
architecture str of tech_eth_10g_arria10 is
-
begin
u_ip_arria10_eth_10g : ip_arria10_eth_10g
generic map(
@@ -175,5 +172,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
index e8a019b6d6c9d428a2a5d725094e6dc1f84fad4f..2d23b34659fa8b9172bcf05a6038670d365e1a03 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e1sg.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e1sg
-- Description
--
@@ -137,9 +136,7 @@ entity tech_eth_10g_arria10_e1sg is
);
end tech_eth_10g_arria10_e1sg;
-
architecture str of tech_eth_10g_arria10_e1sg is
-
begin
u_ip_arria10_e1sg_eth_10g : ip_arria10_e1sg_eth_10g
generic map(
@@ -183,5 +180,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd
index cf3feb45f4074676189260fff8934f60462fba61..e9d80d791d33f9c0d1964840b07eaf1c793acdf4 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e2sg.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e2sg
-- Description
--
@@ -137,9 +136,7 @@ entity tech_eth_10g_arria10_e2sg is
);
end tech_eth_10g_arria10_e2sg;
-
architecture str of tech_eth_10g_arria10_e2sg is
-
begin
u_ip_arria10_e2sg_eth_10g : ip_arria10_e2sg_eth_10g
generic map(
@@ -183,5 +180,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd b/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
index 9315697fd555beefa74a1fea8673813bd8df6186..fea1119601766b539b77af28bee4134d539762fc 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_arria10_e3sge3.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e3sge3
-- Description
--
@@ -136,9 +135,7 @@ entity tech_eth_10g_arria10_e3sge3 is
);
end tech_eth_10g_arria10_e3sge3;
-
architecture str of tech_eth_10g_arria10_e3sge3 is
-
begin
u_ip_arria10_e3sge3_eth_10g : ip_arria10_e3sge3_eth_10g
generic map(
@@ -181,5 +178,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
index e276bedeedef0067e6c5ca28daef5e14183f6d06..0ccadb8a9b19a1b39a6393eee4b73d708e1bbe21 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_clocks.vhd
@@ -26,7 +26,6 @@
-- are also reassigned to preserve same delta-cycle phase as for the data
-- clocks.
-
library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
use technology_lib.technology_pkg.all;
@@ -66,10 +65,8 @@ entity tech_eth_10g_clocks is
);
end tech_eth_10g_clocks;
-
architecture str of tech_eth_10g_clocks is
begin
-
-- Reference
eth_ref_clk_644 <= tr_ref_clk_644;
eth_ref_clk_312 <= tr_ref_clk_312;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd b/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
index 71006e4562268c23c73554ae6d7dfa7186774d44..072c427e9cf4ec454f820899105722cf5889ecdc 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_component_pkg.vhd
@@ -31,8 +31,6 @@ use technology_lib.technology_pkg.all;
use dp_lib.dp_stream_pkg.all;
package tech_eth_10g_component_pkg is
-
-
------------------------------------------------------------------------------
-- ip_stratixiv
------------------------------------------------------------------------------
@@ -82,7 +80,6 @@ package tech_eth_10g_component_pkg is
);
end component;
-
------------------------------------------------------------------------------
-- ip_arria10
------------------------------------------------------------------------------
@@ -272,5 +269,4 @@ package tech_eth_10g_component_pkg is
end tech_eth_10g_component_pkg;
package body tech_eth_10g_component_pkg is
-
end tech_eth_10g_component_pkg;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
index 6daed47bbd4faa31bf9013eb92cfcdd4754246b3..39d77831af1a00069b3c41ab43095fbe2941f305 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and xaui for c_tech_stratixiv
-- Description:
--
@@ -131,11 +130,8 @@ entity tech_eth_10g_stratixiv is
);
end tech_eth_10g_stratixiv;
-
architecture str of tech_eth_10g_stratixiv is
-
begin
-
u_ip_stratixiv_eth_10g : ip_stratixiv_eth_10g
generic map(
g_sim => g_sim,
@@ -180,5 +176,4 @@ begin
xaui_tx_arr => xaui_tx_arr,
xaui_rx_arr => xaui_rx_arr
);
-
end str;
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index 4c46bf4f7c7ab8c785ee7281f2675b13ee3782ee..d57f837edd08425727af72d22f2bdb0465058844 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -26,7 +26,6 @@ use IEEE.std_logic_1164.all;
use technology_lib.technology_pkg.all;
package tech_fifo_component_pkg is
-
-----------------------------------------------------------------------------
-- ip_stratixiv
-----------------------------------------------------------------------------
@@ -91,7 +90,6 @@ package tech_fifo_component_pkg is
);
end component;
-
-----------------------------------------------------------------------------
-- ip_arria10
-----------------------------------------------------------------------------
diff --git a/libraries/technology/fifo/tech_fifo_dc.vhd b/libraries/technology/fifo/tech_fifo_dc.vhd
index db5ca404fbda0172ff7be43ee8a48c20d3158239..c2f8207953d00f34d9bb8b740b9f8fa6d0e65302 100644
--- a/libraries/technology/fifo/tech_fifo_dc.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc.vhd
@@ -55,11 +55,8 @@ entity tech_fifo_dc is
);
end tech_fifo_dc;
-
architecture str of tech_fifo_dc is
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_fifo_dc
generic map (g_dat_w, g_nof_words)
diff --git a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
index 3f17a2415e9ba1df4f7ab53ca0c6e9de666cbc51..502fb8bb3928f4cd7d919eb00534df44cfbe993b 100644
--- a/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/fifo/tech_fifo_dc_mixed_widths.vhd
@@ -55,11 +55,8 @@ entity tech_fifo_dc_mixed_widths is
);
end tech_fifo_dc_mixed_widths;
-
architecture str of tech_fifo_dc_mixed_widths is
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_fifo_dc_mixed_widths
generic map (g_nof_words, g_wrdat_w, g_rddat_w)
diff --git a/libraries/technology/fifo/tech_fifo_sc.vhd b/libraries/technology/fifo/tech_fifo_sc.vhd
index 502722f065da7a64dcd1706da52eaabe838995ce..53f9427bb11f059bb4a9ae6a7cbb8a57c895804b 100644
--- a/libraries/technology/fifo/tech_fifo_sc.vhd
+++ b/libraries/technology/fifo/tech_fifo_sc.vhd
@@ -53,11 +53,8 @@ entity tech_fifo_sc is
);
end tech_fifo_sc;
-
architecture str of tech_fifo_sc is
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_fifo_sc
generic map (g_use_eab, g_dat_w, g_nof_words)
diff --git a/libraries/technology/flash/tech_flash_asmi_parallel.vhd b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
index aa8214345c49de70a66cebd8e556feda16a15f9c..536e905748ee3a8ac8173529ba3da7ddb303e307 100644
--- a/libraries/technology/flash/tech_flash_asmi_parallel.vhd
+++ b/libraries/technology/flash/tech_flash_asmi_parallel.vhd
@@ -61,11 +61,8 @@ entity tech_flash_asmi_parallel is
);
end tech_flash_asmi_parallel;
-
architecture str of tech_flash_asmi_parallel is
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_asmi_parallel
generic map (g_sim_flash_model)
@@ -95,5 +92,4 @@ begin
port map (addr, clkin, datain, rden, read, sector_erase, shift_bytes, wren, write, busy, data_valid, dataout, illegal_erase, illegal_write, reset, sce, en4b_addr);
end generate;
-
end architecture;
diff --git a/libraries/technology/flash/tech_flash_component_pkg.vhd b/libraries/technology/flash/tech_flash_component_pkg.vhd
index ebedb81c75aaf7e1dd86937697a95e3efd1db379..2ae3ba18dbba83644989aa88f27adfe249e88579 100644
--- a/libraries/technology/flash/tech_flash_component_pkg.vhd
+++ b/libraries/technology/flash/tech_flash_component_pkg.vhd
@@ -26,7 +26,6 @@ use IEEE.std_logic_1164.all;
use technology_lib.technology_pkg.all;
package tech_flash_component_pkg is
-
-----------------------------------------------------------------------------
-- ip_stratixiv
-----------------------------------------------------------------------------
@@ -112,7 +111,6 @@ package tech_flash_component_pkg is
);
end component ip_arria10_remote_update;
-
-----------------------------------------------------------------------------
-- ip_arria10_e3sge3
-----------------------------------------------------------------------------
@@ -242,12 +240,12 @@ package tech_flash_component_pkg is
end tech_flash_component_pkg;
package body tech_flash_component_pkg is
-
function tech_flash_addr_w( technology : in integer ) return integer is
begin
if technology = c_tech_stratixiv then
return 24;
end if;
+
if technology = c_tech_arria10_proto then
return 32;
end if;
@@ -269,5 +267,4 @@ package body tech_flash_component_pkg is
end if;
end;
-
end tech_flash_component_pkg;
diff --git a/libraries/technology/flash/tech_flash_remote_update.vhd b/libraries/technology/flash/tech_flash_remote_update.vhd
index f312a5f4ea20debf1fbc49f71278d76d95a984b0..cb345589769a77d1665d534a8bec5ff17114c686 100644
--- a/libraries/technology/flash/tech_flash_remote_update.vhd
+++ b/libraries/technology/flash/tech_flash_remote_update.vhd
@@ -52,11 +52,8 @@ entity tech_flash_remote_update is
);
end tech_flash_remote_update;
-
architecture str of tech_flash_remote_update is
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_remote_update
port map (clock, data_in, param, read_param, reconfig, reset, reset_timer, write_param, busy, data_out);
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index fc52633eee89a7b2775a763b5ecd666c5754e536..c1a0615bb10603daafbcbbfceecb5cd6c38bed4d 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -32,7 +32,6 @@ library ip_arria10_e3sge3_temp_sense_altera_temp_sense_151;
library ip_arria10_e1sg_temp_sense_altera_temp_sense_180;
library ip_arria10_e2sg_temp_sense_altera_temp_sense_1910;
-
entity tech_fpga_temp_sens is
generic (
g_technology : natural := c_tech_select_default
@@ -46,9 +45,7 @@ entity tech_fpga_temp_sens is
end tech_fpga_temp_sens;
architecture str of tech_fpga_temp_sens is
-
begin
-
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_temp_sense
port map (
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
index 0f7d7b625676ffbd548428d23ec5408a23cde193..8cf7fbc8d139f4031a7e20e0bf621e8509bb59a5 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
@@ -25,7 +25,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_fpga_temp_sens_component_pkg is
-
component ip_arria10_temp_sense is
port (
corectl : in std_logic := '0'; -- corectl.corectl
@@ -63,4 +62,3 @@ package tech_fpga_temp_sens_component_pkg is
end component;
end tech_fpga_temp_sens_component_pkg;
-
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
index 0eff6ac0249671ef753862e785341cd70bc32406..c7c5df214a4dcd570ca7887ba7af404795ec42ad 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens.vhd
@@ -31,7 +31,6 @@ library ip_arria10_e3sge3_voltage_sense_altera_voltage_sense_151;
library ip_arria10_e1sg_voltage_sense_altera_voltage_sense_180;
library ip_arria10_e2sg_voltage_sense_altera_voltage_sense_1910;
-
entity tech_fpga_voltage_sens is
generic (
g_technology : natural := c_tech_select_default
@@ -54,9 +53,7 @@ entity tech_fpga_voltage_sens is
end tech_fpga_voltage_sens;
architecture str of tech_fpga_voltage_sens is
-
begin
-
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_voltage_sense
port map (
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
index 0835ef84144b64742749b24e69f69181ea7aef64..89cee1b2e3083c976ceca56174b523e8db084bf9 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
@@ -25,7 +25,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_fpga_voltage_sens_component_pkg is
-
component ip_arria10_voltage_sense is
port (
clock_clk : in std_logic := '0';
@@ -99,4 +98,3 @@ package tech_fpga_voltage_sens_component_pkg is
end component;
end tech_fpga_voltage_sens_component_pkg;
-
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index b88b4653d2273563300031cdb28134a3903e099e..8b567885cdfd462038e41c4239fe8803077fec6a 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -47,9 +47,7 @@ entity tech_fractional_pll_clk125 is
end tech_fractional_pll_clk125;
architecture str of tech_fractional_pll_clk125 is
-
begin
-
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_fractional_pll_clk125
port map (
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index 5b69f99ecdaf9072cf9b64330fd3e508e1a5c968..dde0319d8e1db86fb08217328ba7b05a5af32528 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -46,9 +46,7 @@ entity tech_fractional_pll_clk200 is
end tech_fractional_pll_clk200;
architecture str of tech_fractional_pll_clk200 is
-
begin
-
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_fractional_pll_clk200
port map (
@@ -102,4 +100,3 @@ begin
end generate;
end architecture;
-
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
index 1d280232bc4d3a7d67525a4f8ccdca3e173e03f8..15097276103c9e7b4003b2bc2111875d6f194cac 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_component_pkg.vhd
@@ -25,7 +25,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_fractional_pll_component_pkg is
-
-----------------------------------------------------------------------------
-- ip_arria10
-----------------------------------------------------------------------------
@@ -151,4 +150,3 @@ package tech_fractional_pll_component_pkg is
end component;
end tech_fractional_pll_component_pkg;
-
diff --git a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
index 09b9b36dcd0c9906591addf2aa074515d8d21185..fdae4b1c7207d6c56ef46ff17fc12afbfdc773df 100644
--- a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
@@ -25,7 +25,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_iobuf_component_pkg is
-
-----------------------------------------------------------------------------
-- ip_stratixiv
-----------------------------------------------------------------------------
@@ -60,7 +59,6 @@ package tech_iobuf_component_pkg is
);
end component;
-
-----------------------------------------------------------------------------
-- ip_arria10
-----------------------------------------------------------------------------
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
index 930a614e4d382536f786776fe33f52f3b8bf1f13..4b040c6d309134506607e1277df22735c077f5da 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_in.vhd
@@ -47,11 +47,8 @@ entity tech_iobuf_ddio_in is
);
end tech_iobuf_ddio_in;
-
architecture str of tech_iobuf_ddio_in is
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_ddio_in
generic map ("Stratix IV", g_width)
diff --git a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
index 98087c04d39ad10b99000513115e020c6e24c11a..70be9d84f95f395882d2e4b06163f1f0fd533abc 100644
--- a/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_ddio_out.vhd
@@ -47,11 +47,8 @@ entity tech_iobuf_ddio_out is
);
end tech_iobuf_ddio_out;
-
architecture str of tech_iobuf_ddio_out is
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_ddio_out
generic map ("Stratix IV", g_width)
diff --git a/libraries/technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd b/libraries/technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd
index 246560b179dfccfbe3f719cff30e099584497e20..3cbb1f5c3d425824b1e1195c4a9f560f30e51eab 100644
--- a/libraries/technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd
+++ b/libraries/technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd
@@ -62,7 +62,6 @@ entity ip_arria10_complex_mult_rtl is
end ip_arria10_complex_mult_rtl;
architecture str of ip_arria10_complex_mult_rtl is
-
function RESIZE_NUM(s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
@@ -118,9 +117,7 @@ architecture str of ip_arria10_complex_mult_rtl is
signal prod_ar_bi : signed(c_prod_w - 1 downto 0);
signal sum_re : signed(c_sum_w - 1 downto 0);
signal sum_im : signed(c_sum_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -183,7 +180,6 @@ begin
bi <= reg_bi;
end generate;
-
------------------------------------------------------------------------------
-- Products
------------------------------------------------------------------------------
@@ -206,7 +202,6 @@ begin
prod_ar_bi <= reg_prod_ar_bi;
end generate;
-
------------------------------------------------------------------------------
-- Sum
------------------------------------------------------------------------------
@@ -217,6 +212,7 @@ begin
gen_re_add : if g_conjugate_b generate
nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) + prod_ai_bi;
end generate;
+
gen_re_sub : if not g_conjugate_b generate
nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) - prod_ai_bi;
end generate;
@@ -227,11 +223,11 @@ begin
gen_im_add : if not g_conjugate_b generate
nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) + prod_ar_bi;
end generate;
+
gen_im_sub : if g_conjugate_b generate
nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) - prod_ar_bi;
end generate;
-
no_adder_reg : if g_pipeline_adder = 0 generate -- wired
sum_re <= nxt_sum_re;
sum_im <= nxt_sum_im;
@@ -256,5 +252,4 @@ begin
result_re <= std_logic_vector(reg_result_re);
result_im <= std_logic_vector(reg_result_im);
end generate;
-
end architecture;
diff --git a/libraries/technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd b/libraries/technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd
index 95463e94dda1e3a1ed5295f52b1ef517df87ec77..81d2df2351204a3c4006e3d91db51042707bf0c7 100644
--- a/libraries/technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd
+++ b/libraries/technology/ip_arria10/complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical.vhd
@@ -58,7 +58,6 @@ entity ip_arria10_complex_mult_rtl_canonical is
end ip_arria10_complex_mult_rtl_canonical;
architecture str of ip_arria10_complex_mult_rtl_canonical is
-
function RESIZE_NUM(s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
@@ -144,9 +143,7 @@ architecture str of ip_arria10_complex_mult_rtl_canonical is
signal reg_result_re : signed(g_out_p_w - 1 downto 0);
signal reg_result_im : signed(g_out_p_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -247,7 +244,6 @@ begin
prod_ar_bi <= nxt_prod_ar_bi;
prod_ai_br <= nxt_prod_ai_br;
prod_sum_ar_ai_sum_br_bi <= nxt_prod_sum_ar_ai_sum_br_bi;
-
end generate;
gen_product_reg : if g_pipeline_product > 0 generate -- register
prod_ar_bi <= reg_prod_ar_bi;
@@ -270,5 +266,4 @@ begin
result_re <= std_logic_vector(reg_result_re);
result_im <= std_logic_vector(reg_result_im);
end generate;
-
end architecture;
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd
index 0d25901272998c8c9221805c32fabb9b5d751e1d..7f7d4131f30810e479145aed1676b67f10987f72 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_in.vhd
@@ -38,9 +38,7 @@ entity ip_arria10_ddio_in is
);
end ip_arria10_ddio_in;
-
architecture str of ip_arria10_ddio_in is
-
component ip_arria10_ddio_in_1 is
port (
datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
@@ -50,11 +48,8 @@ architecture str of ip_arria10_ddio_in is
dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
);
end component;
-
begin
-
gen_w : for I in g_width - 1 downto 0 generate
-
u_ip_arria10_ddio_in_1 : ip_arria10_ddio_in_1
port map (
datain => in_dat(I downto I),
@@ -63,7 +58,6 @@ begin
dataout_h => out_dat_hi(I downto I),
dataout_l => out_dat_lo(I downto I)
);
-
end generate;
end str;
diff --git a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd
index 0bf866591da28d96fea41172f15d79a40ad4646f..6b0f88ced42c69b1fe45b016ebcc85730ac237f1 100644
--- a/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd
+++ b/libraries/technology/ip_arria10/ddio/ip_arria10_ddio_out.vhd
@@ -38,9 +38,7 @@ entity ip_arria10_ddio_out is
);
end ip_arria10_ddio_out;
-
architecture str of ip_arria10_ddio_out is
-
component ip_arria10_ddio_out_1 is
port (
dataout : out std_logic_vector(0 downto 0); -- pad_out.export
@@ -50,9 +48,7 @@ architecture str of ip_arria10_ddio_out is
datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
);
end component;
-
begin
-
gen_w : for I in g_width - 1 downto 0 generate
u_ip_arria10_ddio_out_1 : ip_arria10_ddio_out_1
port map (
diff --git a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd
index ca313f2411aa1fda83cedc2026268163530f3a6f..ec1bc006bcf15dd0a3b8352b76460be6ce88febb 100644
--- a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd
+++ b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd
@@ -48,18 +48,13 @@ entity ip_arria10_ddio_in_1 is
);
end ip_arria10_ddio_in_1;
-
architecture beh of ip_arria10_ddio_in_1 is
-
signal in_dat_r : std_logic;
signal in_dat_f : std_logic;
-
begin
-
in_dat_r <= datain(0) when rising_edge(inclock);
in_dat_f <= datain(0) when falling_edge(inclock);
dataout_h <= (others => in_dat_r);
dataout_l <= (others => in_dat_f) when rising_edge(inclock);
-
end beh;
diff --git a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd
index 805178d4f834d31e9a87a0779dfa1cac09cb751d..99ad1519d6ec0abe1d1920c480b0c0a88e1880cc 100644
--- a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd
+++ b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd
@@ -45,15 +45,10 @@ entity ip_arria10_ddio_out_1 is
);
end ip_arria10_ddio_out_1;
-
architecture beh of ip_arria10_ddio_out_1 is
-
signal out_dat_r : std_logic;
signal out_dat_f : std_logic;
-
begin
-
dataout <= datain_l when falling_edge(outclock) else
datain_h when rising_edge(outclock);
-
end beh;
diff --git a/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd b/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
index 7c7eb78696073189afab7755355ab10ac2be83d7..0c619c5edbcfd63986e20d6fa9c37c32c066c7fe 100644
--- a/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
+++ b/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
@@ -41,9 +41,7 @@ use IEEE.std_logic_1164.all;
entity tb_ip_arria10_ddio_1 is
end tb_ip_arria10_ddio_1;
-
architecture tb of tb_ip_arria10_ddio_1 is
-
constant c_clk_period : time := 10 ns;
signal tb_end : std_logic := '0';
@@ -55,9 +53,7 @@ architecture tb of tb_ip_arria10_ddio_1 is
signal out_data : std_logic_vector(0 downto 0);
signal out_dat : std_logic;
signal out_dat_exp : std_logic;
-
begin
-
tb_end <= '0', '1' after 100 * c_clk_period;
clk <= not clk or tb_end after c_clk_period / 2;
@@ -122,5 +118,4 @@ begin
assert out_dat = out_dat_exp report "tb_ip_arria10_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
index a802d7a64bd37bb68c3c7250a2fa68e85083076f..fc6617c765cf6177599a987ff14b82b243b2e408 100644
--- a/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
+++ b/libraries/technology/ip_arria10/eth_10g/ip_arria10_eth_10g.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_proto
-- Description
--
@@ -132,9 +131,7 @@ entity ip_arria10_eth_10g is
);
end ip_arria10_eth_10g;
-
architecture str of ip_arria10_eth_10g is
-
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
constant c_check_link_status : boolean := g_direction /= "TX_ONLY";
constant c_check_xgmii_tx_ready : boolean := g_direction /= "RX_ONLY";
@@ -165,12 +162,10 @@ architecture str of ip_arria10_eth_10g is
signal reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels - 1 downto 0);
signal mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels - 1 downto 0);
-
begin
tx_snk_out_arr <= i_tx_snk_out_arr;
gen_mac : for I in 0 to g_nof_channels - 1 generate
-
i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
p_xon_flow_control : process(clk_156)
@@ -251,7 +246,6 @@ begin
rx_serial_arr => serial_rx_arr
);
-
gen_reg_eth10g : for I in 0 to g_nof_channels - 1 generate
mm_reg_eth10g_arr(I) <= RESIZE_UVEC(xgmii_link_status_arr(I) & xgmii_tx_ready_arr(I) & i_tx_snk_out_arr(I).xon, c_mem_reg_eth10g_dat_w);
@@ -283,7 +277,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- MM bus mux
-----------------------------------------------------------------------------
@@ -310,5 +303,4 @@ begin
mosi_arr => reg_eth10g_mosi_arr,
miso_arr => reg_eth10g_miso_arr
);
-
end str;
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
index 9122cd03336fc1de04d1d1c74f5f018db4426c85..87fa2a1ca29a55f2fdd98663d1e887fd6aabdf6b 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_fifo_dc is
);
end ip_arria10_fifo_dc;
-
architecture SYN of ip_arria10_fifo_dc is
-
component dcfifo
generic (
intended_device_family : string;
@@ -86,9 +84,7 @@ architecture SYN of ip_arria10_fifo_dc is
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
-
begin
-
u_dcfifo : dcfifo
generic map (
intended_device_family => "Arria 10",
@@ -118,5 +114,4 @@ begin
wrfull => wrfull,
wrusedw => wrusedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
index ef461ee1e18d0d12b2f9d7b0faa1d807dbc43671..89f1521773138d3276a043bf90a8fb37c02c9d54 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_dc_mixed_widths.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_fifo_dc_mixed_widths is
);
end ip_arria10_fifo_dc_mixed_widths;
-
architecture SYN of ip_arria10_fifo_dc_mixed_widths is
-
component dcfifo_mixed_widths
generic (
intended_device_family : string;
@@ -88,9 +86,7 @@ architecture SYN of ip_arria10_fifo_dc_mixed_widths is
wrusedw : out std_logic_vector(wrusedw'range)
);
end component;
-
begin
-
dcfifo_mixed_widths_component : dcfifo_mixed_widths
generic map (
intended_device_family => "Arria 10",
@@ -122,5 +118,4 @@ begin
wrfull => wrfull,
wrusedw => wrusedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
index 8cce1d7ec76076ae9dc5bbc8b1cb038daf09a4a0..0581d4fca8755641c763222291f199e7975bff49 100644
--- a/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
+++ b/libraries/technology/ip_arria10/fifo/ip_arria10_fifo_sc.vhd
@@ -51,9 +51,7 @@ entity ip_arria10_fifo_sc is
);
end ip_arria10_fifo_sc;
-
architecture SYN of ip_arria10_fifo_sc is
-
component scfifo
generic (
add_ram_output_register : string;
@@ -79,9 +77,7 @@ architecture SYN of ip_arria10_fifo_sc is
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
-
begin
-
u_scfifo : scfifo
generic map (
add_ram_output_register => "ON",
@@ -106,5 +102,4 @@ begin
q => q,
usedw => usedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10/mult/ip_arria10_mult.vhd b/libraries/technology/ip_arria10/mult/ip_arria10_mult.vhd
index e64232a2d05b5450f0a9960c50edfe65e69b5483..51fe57d1d22f8ee5d49ce21bd958de4068ffffcf 100644
--- a/libraries/technology/ip_arria10/mult/ip_arria10_mult.vhd
+++ b/libraries/technology/ip_arria10/mult/ip_arria10_mult.vhd
@@ -32,9 +32,7 @@ use lpm.lpm_components.all;
);
end ip_arria10_mult;
-
architecture str of ip_arria10_mult is
-
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_output;
-- When g_out_p_w < g_in_a_w+g_in_b_w then the LPM_MULT truncates the LSbits of the product. Therefore
@@ -42,9 +40,7 @@ architecture str of ip_arria10_mult is
constant c_prod_w : natural := g_in_a_w + g_in_b_w;
signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
-
begin
-
gen_mult : for I in 0 to g_nof_mult - 1 generate
m : lpm_mult
generic map (
@@ -67,7 +63,6 @@ begin
result => prod((I + 1) * c_prod_w - 1 downto I * c_prod_w)
);
-
out_p <= prod;
---- Truncate MSbits, also for signed (common_pkg.vhd for explanation of RESIZE_SVEC)
-- out_p((I+1)*g_out_p_w-1 DOWNTO I*g_out_p_w) <= RESIZE_SVEC(prod((I+1)*c_prod_w-1 DOWNTO I*c_prod_w), g_out_p_w) WHEN g_representation="SIGNED" ELSE
diff --git a/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd b/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
index 6ea2d197f823210879685ea0913a9498b926a80a..d8ed3b0ed990455a47ea2eb759de52af74d8a52e 100644
--- a/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
+++ b/libraries/technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
@@ -45,9 +45,7 @@ use IEEE.numeric_std.all;
);
end ip_arria10_mult_rtl;
-
architecture str of ip_arria10_mult_rtl is
-
constant c_prod_w : natural := g_in_a_w + g_in_b_w;
-- registers
@@ -67,9 +65,7 @@ architecture str of ip_arria10_mult_rtl is
signal inp_b : std_logic_vector(in_b'range);
signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0); -- stage dependent on g_pipeline_product being 0 or 1
signal result : std_logic_vector(out_p'range); -- stage dependent on g_pipeline_output being 0 or 1
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -140,5 +136,4 @@ begin
end generate;
out_p <= result;
-
end str;
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
index bab5e8d17f6488f0778577a264dc3d91f670a956..4b51cd15a06847f7c216cc4588813715153dd7f4 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_cr_cw.vhd
@@ -50,9 +50,7 @@ entity ip_arria10_ram_cr_cw is
);
end ip_arria10_ram_cr_cw;
-
architecture SYN of ip_arria10_ram_cr_cw is
-
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -93,9 +91,7 @@ architecture SYN of ip_arria10_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
index a101a09dbf75b2c8eda11ab2a59ca24012b22e8d..2b65b1aa03ad78063c79c7caac67c07e644cd29f 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crw_crw.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_ram_crw_crw is
);
end ip_arria10_ram_crw_crw;
-
architecture SYN of ip_arria10_ram_crw_crw is
-
constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
@@ -109,9 +107,7 @@ architecture SYN of ip_arria10_ram_crw_crw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
index ec4a9e6a1b847342c2c6a47e9971794e8ebd5fd7..48d8ca9c1122a36bbcf0930cb67116b249c7f532 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_crwk_crw.vhd
@@ -10,7 +10,6 @@
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-
library ieee, technology_lib;
use ieee.std_logic_1164.all;
use technology_lib.technology_pkg.all;
@@ -44,9 +43,7 @@ entity ip_arria10_ram_crwk_crw is
);
end ip_arria10_ram_crwk_crw;
-
architecture SYN of ip_arria10_ram_crwk_crw is
-
constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
@@ -92,9 +89,7 @@ architecture SYN of ip_arria10_ram_crwk_crw is
q_b : out std_logic_vector(g_dat_b_w - 1 downto 0)
);
end component;
-
begin
-
-- Copied from ip_arria10_ram_crwk_crw/ram_2port_140/sim/ip_arria10_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
generic map (
@@ -137,6 +132,4 @@ begin
q_a => q_a,
q_b => q_b
);
-
end SYN;
-
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
index 4084447a41613387d22341219a7d86c3c51f526e..0880d2e81bb6bf8a208c46adf00d3cd7c222fab5 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_ram_r_w.vhd
@@ -48,9 +48,7 @@ entity ip_arria10_ram_r_w is
);
end ip_arria10_ram_r_w;
-
architecture SYN of ip_arria10_ram_r_w is
-
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -90,9 +88,7 @@ architecture SYN of ip_arria10_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_dual_clock.vhd
index 87643e24e157d5b922247b3ef4f648cc50d3c9ec..08efdd6ec30c17f098d4d7a3c12e9bdd13d6d10f 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_dual_clock.vhd
@@ -30,13 +30,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_simple_dual_port_ram_dual_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
rclk : in std_logic;
@@ -47,20 +45,16 @@ entity ip_arria10_simple_dual_port_ram_dual_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_simple_dual_port_ram_dual_clock;
architecture rtl of ip_arria10_simple_dual_port_ram_dual_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-
begin
-
process(wclk)
begin
if(rising_edge(wclk)) then
@@ -76,5 +70,4 @@ begin
q <= ram(raddr);
end if;
end process;
-
end rtl;
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd
index a3d536b1ddd615cdd5562ea09c7958da655885ab..206e76f7b0ee7f1aeed0b974688519c8090c2a21 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_simple_dual_port_ram_single_clock.vhd
@@ -29,13 +29,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_simple_dual_port_ram_single_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
clk : in std_logic;
@@ -45,20 +43,16 @@ entity ip_arria10_simple_dual_port_ram_single_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_simple_dual_port_ram_single_clock;
architecture rtl of ip_arria10_simple_dual_port_ram_single_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-
begin
-
process(clk)
begin
if(rising_edge(clk)) then
@@ -71,6 +65,4 @@ begin
q <= ram(raddr);
end if;
end process;
-
end rtl;
-
diff --git a/libraries/technology/ip_arria10/ram/ip_arria10_true_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10/ram/ip_arria10_true_dual_port_ram_dual_clock.vhd
index ef8d0552b1e67719e7a6f4ff24342d9129d01b05..f34b91bf853910200e9f81e96da2e0dc12964893 100644
--- a/libraries/technology/ip_arria10/ram/ip_arria10_true_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_arria10/ram/ip_arria10_true_dual_port_ram_dual_clock.vhd
@@ -33,13 +33,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_true_dual_port_ram_dual_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
clk_a : in std_logic;
@@ -53,20 +51,16 @@ entity ip_arria10_true_dual_port_ram_dual_clock is
q_a : out std_logic_vector((DATA_WIDTH - 1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_true_dual_port_ram_dual_clock;
architecture rtl of ip_arria10_true_dual_port_ram_dual_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM
shared variable ram : memory_t;
-
begin
-
-- Port A
process(clk_a)
begin
@@ -88,5 +82,4 @@ begin
q_b <= ram(addr_b);
end if;
end process;
-
end rtl;
diff --git a/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
index e7de9d13e4615d8a49b6fed3ce12a0e719dc70b9..cd1d8282ea9efc49c1ff24907b92285f04c5aafa 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10/tse_sgmii_gx/tb_ip_arria10_tse_sgmii_gx.vhd
@@ -32,13 +32,10 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_ip_arria10_tse_sgmii_gx is
end tb_ip_arria10_tse_sgmii_gx;
-
architecture tb of tb_ip_arria10_tse_sgmii_gx is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
constant serial_clk_period : time := 800 ps; -- 1250 MHz ????
@@ -402,7 +399,6 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
end if;
end proc_rx_packet;
-
-- Clocks and reset
signal tb_end : std_logic := '0';
signal eth_clk : std_logic := '0';
@@ -459,9 +455,7 @@ architecture tb of tb_ip_arria10_tse_sgmii_gx is
signal dbg_mm : t_mm_bus;
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -744,5 +738,4 @@ begin
assert false report "Simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
index d363fb2759fe6e3490d035b180560b52aa6cfdf1..e5ad6682c9cd45a25d65ab62bbe391ccf2d6d96a 100644
--- a/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10/tse_sgmii_lvds/tb_ip_arria10_tse_sgmii_lvds.vhd
@@ -37,13 +37,10 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_ip_arria10_tse_sgmii_lvds is
end tb_ip_arria10_tse_sgmii_lvds;
-
architecture tb of tb_ip_arria10_tse_sgmii_lvds is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
@@ -405,7 +402,6 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
end if;
end proc_rx_packet;
-
-- Clocks and reset
signal tb_end : std_logic := '0';
signal eth_clk : std_logic := '0';
@@ -458,9 +454,7 @@ architecture tb of tb_ip_arria10_tse_sgmii_lvds is
signal dbg_mm : t_mm_bus;
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -726,5 +720,4 @@ begin
assert false report "Simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd
index 4c268e8c721fa002dac86a1f58ea7120126184ec..dcccc9b1c8b2e9b990741414a491ff0cacdf2be9 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_in.vhd
@@ -38,9 +38,7 @@ entity ip_arria10_e1sg_ddio_in is
);
end ip_arria10_e1sg_ddio_in;
-
architecture str of ip_arria10_e1sg_ddio_in is
-
component ip_arria10_e1sg_ddio_in_1 is
port (
datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
@@ -50,11 +48,8 @@ architecture str of ip_arria10_e1sg_ddio_in is
dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
);
end component;
-
begin
-
gen_w : for I in g_width - 1 downto 0 generate
-
u_ip_arria10_e1sg_ddio_in_1 : ip_arria10_e1sg_ddio_in_1
port map (
datain => in_dat(I downto I),
@@ -63,7 +58,6 @@ begin
dataout_h => out_dat_hi(I downto I),
dataout_l => out_dat_lo(I downto I)
);
-
end generate;
end str;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd
index 16aceb1933871b7c113af80acc1893bd1e6e44e4..5d100fa091dc2e36c91b349f0b7fc3572882febb 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/ip_arria10_e1sg_ddio_out.vhd
@@ -38,9 +38,7 @@ entity ip_arria10_e1sg_ddio_out is
);
end ip_arria10_e1sg_ddio_out;
-
architecture str of ip_arria10_e1sg_ddio_out is
-
component ip_arria10_e1sg_ddio_out_1 is
port (
dataout : out std_logic_vector(0 downto 0); -- pad_out.export
@@ -50,9 +48,7 @@ architecture str of ip_arria10_e1sg_ddio_out is
datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
);
end component;
-
begin
-
gen_w : for I in g_width - 1 downto 0 generate
u_ip_arria10_e1sg_ddio_out_1 : ip_arria10_e1sg_ddio_out_1
port map (
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
index 59ab7dc28e843ff98668ee71766b1331f9f4ea20..1fa58c09df658fe769799e9d15fe9a03b353fbbe 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
@@ -48,18 +48,13 @@ entity ip_arria10_e1sg_ddio_in_1 is
);
end ip_arria10_e1sg_ddio_in_1;
-
architecture beh of ip_arria10_e1sg_ddio_in_1 is
-
signal in_dat_r : std_logic;
signal in_dat_f : std_logic;
-
begin
-
in_dat_r <= datain(0) when rising_edge(inclock);
in_dat_f <= datain(0) when falling_edge(inclock);
dataout_h <= (others => in_dat_r);
dataout_l <= (others => in_dat_f) when rising_edge(inclock);
-
end beh;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
index 074f64c5f394047a12da7091c0e398f87cda6888..fc28a379d95e90944401bb65cc1a92a91cb00a23 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
@@ -45,15 +45,10 @@ entity ip_arria10_e1sg_ddio_out_1 is
);
end ip_arria10_e1sg_ddio_out_1;
-
architecture beh of ip_arria10_e1sg_ddio_out_1 is
-
signal out_dat_r : std_logic;
signal out_dat_f : std_logic;
-
begin
-
dataout <= datain_l when falling_edge(outclock) else
datain_h when rising_edge(outclock);
-
end beh;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
index dda238e0f75dcc24976fd10e3981e5846303d930..7521516fe76bbbe872297649543d9b6dd6cec6d0 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
@@ -41,9 +41,7 @@ use IEEE.std_logic_1164.all;
entity tb_ip_arria10_e1sg_ddio_1 is
end tb_ip_arria10_e1sg_ddio_1;
-
architecture tb of tb_ip_arria10_e1sg_ddio_1 is
-
constant c_clk_period : time := 10 ns;
signal tb_end : std_logic := '0';
@@ -55,9 +53,7 @@ architecture tb of tb_ip_arria10_e1sg_ddio_1 is
signal out_data : std_logic_vector(0 downto 0);
signal out_dat : std_logic;
signal out_dat_exp : std_logic;
-
begin
-
tb_end <= '0', '1' after 100 * c_clk_period;
clk <= not clk or tb_end after c_clk_period / 2;
@@ -122,5 +118,4 @@ begin
assert out_dat = out_dat_exp report "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd
index 1d307b837f8a98feb54aabd325409edd13b76f23..1bf4433f98fc3c36b0ca1bf16619ce0c2bc75be2 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_170/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -49,7 +48,6 @@ entity ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy is
);
end entity ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy;
-
architecture europa of ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_170_yroldmy is
component altsyncram is
generic (
@@ -80,9 +78,7 @@ generic (
signal clocken0 : std_logic;
signal internal_readdata : std_logic_vector(31 downto 0);
signal wren : std_logic;
-
begin
-
wren <= (chipselect and write) and debugaccess;
clocken0 <= clken and not reset_req;
the_altsyncram : altsyncram
@@ -115,6 +111,4 @@ begin
--s2, which is an e_avalon_slave
--vhdl renameroo for output signals
readdata <= internal_readdata;
-
end europa;
-
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd
index 85d463e5907fabf63a89bf96d3912e15e3f0f364..5705a0515ac01eef868368909c04a5089e4a7bc3 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_avalon_onchip_memory2_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za.vhd
@@ -10,7 +10,6 @@
--or its authorized distributors. Please refer to the applicable
--agreement for further details.
-
-- turn off superfluous VHDL processor warnings
-- altera message_level Level1
-- altera message_off 10034 10035 10036 10037 10230 10240 10030 13469 16735 16788
@@ -49,7 +48,6 @@ entity ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za is
);
end entity ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za;
-
architecture europa of ip_arria10_e1sg_ddr4_8g_2400_altera_avalon_onchip_memory2_180_xymx6za is
component altsyncram is
generic (
@@ -80,9 +78,7 @@ generic (
signal clocken0 : std_logic;
signal internal_readdata : std_logic_vector(31 downto 0);
signal wren : std_logic;
-
begin
-
wren <= (chipselect and write) and debugaccess;
clocken0 <= clken and not reset_req;
the_altsyncram : altsyncram
@@ -115,6 +111,4 @@ begin
--s2, which is an e_avalon_slave
--vhdl renameroo for output signals
readdata <= internal_readdata;
-
end europa;
-
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i.vhd b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i.vhd
index 21033b94a3ac26faabf022b164a2c1b8d0532e05..84681266c2fe800c87d88762aa0217fe39ea3c21 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/altera_emif_arch_nf_180/sim/ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i.vhd
@@ -3583,7 +3583,6 @@ architecture rtl of ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i
dft_core_clk_locked : out std_logic_vector(1 downto 0)
);
end component ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top;
-
begin
arch_inst : component ip_arria10_e1sg_ddr4_8g_2400_altera_emif_arch_nf_180_e37lt4i_top
generic map (
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
index 575461e0a84dfd7132a7fe5386441c06e022533a..cc07d963c90b7fffc61cfd21e35ddc6887ae124b 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
@@ -70,4 +70,3 @@
local_cal_success => CONNECTED_TO_local_cal_success, -- status_conduit_end.local_cal_success
local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
);
-
diff --git a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
index 5e1bfb862ca6faf96768e9dc99d0a8ab2e6c3f59..647e77e35d41dd54ac94d3a24f3570e455abb9a0 100644
--- a/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e1sg/eth_10g/ip_arria10_e1sg_eth_10g.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e1sg
-- Description
--
@@ -136,9 +135,7 @@ entity ip_arria10_e1sg_eth_10g is
);
end ip_arria10_e1sg_eth_10g;
-
architecture str of ip_arria10_e1sg_eth_10g is
-
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
constant c_check_link_status : boolean := true; -- g_direction/="TX_ONLY";
constant c_check_xgmii_tx_ready : boolean := true; -- g_direction/="RX_ONLY";
@@ -171,12 +168,10 @@ architecture str of ip_arria10_e1sg_eth_10g is
signal reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels - 1 downto 0);
signal mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels - 1 downto 0);
-
begin
tx_snk_out_arr <= i_tx_snk_out_arr;
gen_mac : for I in 0 to g_nof_channels - 1 generate
-
i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
p_xon_flow_control : process(clk_156)
@@ -303,7 +298,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- MM bus mux
-----------------------------------------------------------------------------
@@ -330,5 +324,4 @@ begin
mosi_arr => reg_eth10g_mosi_arr,
miso_arr => reg_eth10g_miso_arr
);
-
end str;
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd
index 2a91090a955731c3cc06ca71289e45e6146814f1..37904a397a5c971c52f7c081d129ffd7d0c32e70 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_e1sg_fifo_dc is
);
end ip_arria10_e1sg_fifo_dc;
-
architecture SYN of ip_arria10_e1sg_fifo_dc is
-
component dcfifo
generic (
intended_device_family : string;
@@ -86,9 +84,7 @@ architecture SYN of ip_arria10_e1sg_fifo_dc is
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
-
begin
-
u_dcfifo : dcfifo
generic map (
intended_device_family => "Arria 10",
@@ -118,5 +114,4 @@ begin
wrfull => wrfull,
wrusedw => wrusedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
index b5ff1184fd69b9e0f90a478370919b5cf353cbae..ecea76e2bd81fe1af9db7e6cc7dd3381f0db988d 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_dc_mixed_widths.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_e1sg_fifo_dc_mixed_widths is
);
end ip_arria10_e1sg_fifo_dc_mixed_widths;
-
architecture SYN of ip_arria10_e1sg_fifo_dc_mixed_widths is
-
component dcfifo_mixed_widths
generic (
intended_device_family : string;
@@ -88,9 +86,7 @@ architecture SYN of ip_arria10_e1sg_fifo_dc_mixed_widths is
wrusedw : out std_logic_vector(wrusedw'range)
);
end component;
-
begin
-
dcfifo_mixed_widths_component : dcfifo_mixed_widths
generic map (
intended_device_family => "Arria 10",
@@ -122,5 +118,4 @@ begin
wrfull => wrfull,
wrusedw => wrusedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd
index 79fd98df704b58d3b686c3e0977c7c4770c42a20..3ed039dacbdadabafda05e56c696b38a1ea61ecc 100644
--- a/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd
+++ b/libraries/technology/ip_arria10_e1sg/fifo/ip_arria10_e1sg_fifo_sc.vhd
@@ -51,9 +51,7 @@ entity ip_arria10_e1sg_fifo_sc is
);
end ip_arria10_e1sg_fifo_sc;
-
architecture SYN of ip_arria10_e1sg_fifo_sc is
-
component scfifo
generic (
add_ram_output_register : string;
@@ -79,9 +77,7 @@ architecture SYN of ip_arria10_e1sg_fifo_sc is
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
-
begin
-
u_scfifo : scfifo
generic map (
add_ram_output_register => "ON",
@@ -106,5 +102,4 @@ begin
q => q,
usedw => usedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
index 68580136f74737f349e528d9f966e8ea7f696cd6..554b93b24765987e6d81470ada650b9804adf087 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b.vhd
@@ -71,7 +71,6 @@ entity ip_arria10_e1sg_jesd204b is
end ip_arria10_e1sg_jesd204b;
architecture str of ip_arria10_e1sg_jesd204b is
-
-- JESD IP constants
-- . JESD204B MM has 256 bytes = 64 words, so mm_addr_w = 6 would be enough,
-- but using mm_addr_w = 8 and span = 256 words is fine too.
@@ -231,7 +230,6 @@ architecture str of ip_arria10_e1sg_jesd204b is
rx_ready : out std_logic_vector(11 downto 0) -- rx_ready
);
end component ip_arria10_e1sg_jesd204b_rx_xcvr_reset_control_12;
-
begin
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e1sg_jesd204b and causes a reset on the rx_rst output.
@@ -251,7 +249,6 @@ begin
gen_jesd204b_rx : if g_direction = "RX_ONLY" generate
gen_jesd204b_rx_channels : for I in 0 to g_nof_streams - 1 generate
-
-----------------------------------------------------------------------------
-- The JESD204 IP (rx only)
-----------------------------------------------------------------------------
@@ -410,7 +407,6 @@ begin
end if;
end if;
end process;
-
end generate; -- gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
-----------------------------------------------------------------------------
@@ -491,7 +487,6 @@ begin
rx_is_lockedtodata => rx_islockedtodata_arr, -- input from PHY
rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver
);
-
end generate; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_enable_sync_n : for i in 0 to g_nof_streams - 1 generate
@@ -525,7 +520,4 @@ begin
mosi_arr => jesd204b_mosi_arr,
miso_arr => jesd204b_miso_arr
);
-
end str;
-
-
diff --git a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_component_pkg.vhd b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_component_pkg.vhd
index 841080d30fe1e8d990757b9b2a49b3b0d7513272..34caad0fcfcdf69e98583acd436695420caaca11 100644
--- a/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_component_pkg.vhd
+++ b/libraries/technology/ip_arria10_e1sg/jesd204b/ip_arria10_e1sg_jesd204b_component_pkg.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Component declarations for jesd204b ip blocks
library IEEE, technology_lib, common_lib, dp_lib;
@@ -31,7 +30,6 @@ use technology_lib.technology_pkg.all;
use dp_lib.dp_stream_pkg.all;
package ip_arria10_e1sg_jesd204b_component_pkg is
-
------------------------------------------------------------------------------
-- Main IP, TX ONLY, 1 channel
------------------------------------------------------------------------------
@@ -88,8 +86,6 @@ package ip_arria10_e1sg_jesd204b_component_pkg is
);
end component ip_arria10_e1sg_jesd204b_tx;
-
-
end ip_arria10_e1sg_jesd204b_component_pkg;
package body ip_arria10_e1sg_jesd204b_component_pkg is
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add2/ip_arria10_e1sg_mult_add2_rtl.vhd b/libraries/technology/ip_arria10_e1sg/mult_add2/ip_arria10_e1sg_mult_add2_rtl.vhd
index 5484808364a32bb044d8d57a2585d0209f00c86d..fc7268d3e9c444cc2de06541c8ccabbc64ffcc05 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add2/ip_arria10_e1sg_mult_add2_rtl.vhd
+++ b/libraries/technology/ip_arria10_e1sg/mult_add2/ip_arria10_e1sg_mult_add2_rtl.vhd
@@ -26,7 +26,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
------------------------------------------------------------------------------
-- Function:
-- . res = a0 * b0 + a1 * b1
@@ -56,9 +55,7 @@ entity ip_arria10_e1sg_mult_add2_rtl is
);
end ip_arria10_e1sg_mult_add2_rtl;
-
architecture str of ip_arria10_e1sg_mult_add2_rtl is
-
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
@@ -94,9 +91,7 @@ architecture str of ip_arria10_e1sg_mult_add2_rtl is
signal prod1 : signed(c_prod_w - 1 downto 0);
signal sum : signed(c_sum_w - 1 downto 0);
signal result : signed(g_res_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -173,6 +168,7 @@ begin
gen_add : if g_add_sub = "ADD" generate
nxt_sum <= RESIZE_NUM(prod0, c_sum_w) + prod1;
end generate;
+
gen_sub : if g_add_sub = "SUB" generate
nxt_sum <= RESIZE_NUM(prod0, c_sum_w) - prod1;
end generate;
@@ -184,7 +180,6 @@ begin
sum <= reg_sum;
end generate;
-
------------------------------------------------------------------------------
-- Result sum after optional rounding
------------------------------------------------------------------------------
@@ -199,5 +194,4 @@ begin
end generate;
res <= std_logic_vector(result);
-
end str;
diff --git a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd
index 04a0950450f76a73db82924bf5dd4389e9f75306..15194254d6fa8d95428031c115878884d44f36cc 100644
--- a/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd
+++ b/libraries/technology/ip_arria10_e1sg/mult_add4/ip_arria10_e1sg_mult_add4_rtl.vhd
@@ -53,7 +53,6 @@ entity ip_arria10_e1sg_mult_add4_rtl is
end ip_arria10_e1sg_mult_add4_rtl;
architecture str of ip_arria10_e1sg_mult_add4_rtl is
-
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
@@ -108,9 +107,7 @@ architecture str of ip_arria10_e1sg_mult_add4_rtl is
signal sum1 : signed(g_in_a_w + g_in_b_w downto 0);
signal sum : signed(g_in_a_w + g_in_b_w + 1 downto 0);
signal result : signed(res'range);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -219,6 +216,7 @@ begin
gen_add0 : if g_add_sub0 = "ADD" generate
nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) + prod1;
end generate;
+
gen_sub0 : if g_add_sub0 = "SUB" generate
nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) - prod1;
end generate;
@@ -226,6 +224,7 @@ begin
gen_add1 : if g_add_sub1 = "ADD" generate
nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) + prod3;
end generate;
+
gen_sub1 : if g_add_sub1 = "SUB" generate
nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) - prod3;
end generate;
@@ -240,7 +239,6 @@ begin
sum1 <= reg_sum1;
end generate;
-
------------------------------------------------------------------------------
-- Second sum
------------------------------------------------------------------------------
@@ -249,11 +247,11 @@ begin
gen_add : if g_add_sub = "ADD" generate
sum <= RESIZE_NUM(sum0, sum'length) + sum1;
end generate;
+
gen_sub : if g_add_sub = "SUB" generate
sum <= RESIZE_NUM(sum0, sum'length) - sum1;
end generate;
-
------------------------------------------------------------------------------
-- Result sum after optional rounding
------------------------------------------------------------------------------
@@ -268,5 +266,4 @@ begin
end generate;
res <= std_logic_vector(result);
-
end str;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
index dd02bff6f8b3d9478c3f05416de3b2acf793c20d..604b4da043e9b3dc2ff0ee6a7e54bc19fbb53a16 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_cr_cw.vhd
@@ -50,9 +50,7 @@ entity ip_arria10_e1sg_ram_cr_cw is
);
end ip_arria10_e1sg_ram_cr_cw;
-
architecture SYN of ip_arria10_e1sg_ram_cr_cw is
-
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -93,9 +91,7 @@ architecture SYN of ip_arria10_e1sg_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e1sg_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
index f1ee7e7f67aac89af4eaa4d00e7a0383cf592ac6..3335b480bba324a51cde55b65c2248a71afe36b9 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crw_crw.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_e1sg_ram_crw_crw is
);
end ip_arria10_e1sg_ram_crw_crw;
-
architecture SYN of ip_arria10_e1sg_ram_crw_crw is
-
constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
@@ -109,9 +107,7 @@ architecture SYN of ip_arria10_e1sg_ram_crw_crw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e1sg_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
index 76e942f71d84f652d374203dc9e57d7cd855b923..8adae627db1858f16fa621d56a95bd906f97e783 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw.vhd
@@ -10,7 +10,6 @@
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-
library ieee, technology_lib;
use ieee.std_logic_1164.all;
use technology_lib.technology_pkg.all;
@@ -44,9 +43,7 @@ entity ip_arria10_e1sg_ram_crwk_crw is
);
end ip_arria10_e1sg_ram_crwk_crw;
-
architecture SYN of ip_arria10_e1sg_ram_crwk_crw is
-
constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
@@ -92,9 +89,7 @@ architecture SYN of ip_arria10_e1sg_ram_crwk_crw is
q_b : out std_logic_vector(g_dat_b_w - 1 downto 0)
);
end component;
-
begin
-
-- Copied from ip_arria10_e1sg_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
generic map (
@@ -137,6 +132,4 @@ begin
q_a => q_a,
q_b => q_b
);
-
end SYN;
-
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
index 9fc7face073e8f3312f232accc281d3944716b46..d6f8e5d7c4e426f455ee85725d61eb4b9ceeebe8 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
@@ -30,4 +30,3 @@
q_a => CONNECTED_TO_q_a, -- ram_output.dataout_a
q_b => CONNECTED_TO_q_b -- .dataout_b
);
-
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ram_2port_170/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ram_2port_170/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd
index 91b2fc14c3290952272f8cf0dfa79a0860927955..2a6c542231cf49a463262f234152ee500e7e1a8d 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ram_2port_170/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ram_2port_170/sim/ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri.vhd
@@ -10,9 +10,6 @@
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-
-
-
library ieee;
use ieee.std_logic_1164.all;
@@ -37,12 +34,9 @@ entity ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri is
);
end ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri;
-
architecture SYN of ip_arria10_e1sg_ram_crwk_crw_ram_2port_170_qaianri is
-
signal sub_wire0 : std_logic_vector(31 downto 0);
signal sub_wire1 : std_logic_vector(7 downto 0);
-
begin
q_a <= sub_wire0 (31 downto 0);
q_b <= sub_wire1 (7 downto 0);
@@ -92,8 +86,4 @@ begin
q_a => sub_wire0,
q_b => sub_wire1
);
-
-
-
end SYN;
-
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
index 630c226802e9f66c72f0bea57c3412c257418aa3..6cf10c4b343c813eda054b30486357a231fe740c 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_r_w.vhd
@@ -48,9 +48,7 @@ entity ip_arria10_e1sg_ram_r_w is
);
end ip_arria10_e1sg_ram_r_w;
-
architecture SYN of ip_arria10_e1sg_ram_r_w is
-
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -90,9 +88,7 @@ architecture SYN of ip_arria10_e1sg_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e1sg_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_dual_clock.vhd
index 2892d46f234e8ed3bdf88ec9d749a58477efe4b1..a7b355b3d26ec3d78b61841c6507e4588d223a5f 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_dual_clock.vhd
@@ -30,13 +30,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_e1sg_simple_dual_port_ram_dual_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
rclk : in std_logic;
@@ -47,20 +45,16 @@ entity ip_arria10_e1sg_simple_dual_port_ram_dual_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_e1sg_simple_dual_port_ram_dual_clock;
architecture rtl of ip_arria10_e1sg_simple_dual_port_ram_dual_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-
begin
-
process(wclk)
begin
if(rising_edge(wclk)) then
@@ -76,5 +70,4 @@ begin
q <= ram(raddr);
end if;
end process;
-
end rtl;
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
index c3d96b837436a11d30e8407aabc819b63ac6c581..dba8bb6afd3284259464514303daa65516b3dc09 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_simple_dual_port_ram_single_clock.vhd
@@ -29,13 +29,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_e1sg_simple_dual_port_ram_single_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
clk : in std_logic;
@@ -45,20 +43,16 @@ entity ip_arria10_e1sg_simple_dual_port_ram_single_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_e1sg_simple_dual_port_ram_single_clock;
architecture rtl of ip_arria10_e1sg_simple_dual_port_ram_single_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-
begin
-
process(clk)
begin
if(rising_edge(clk)) then
@@ -71,6 +65,4 @@ begin
q <= ram(raddr);
end if;
end process;
-
end rtl;
-
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_true_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_true_dual_port_ram_dual_clock.vhd
index 1ab7f7db0f497e918f31f86da70336a1f5c4671e..c6754c0e4b057421b419156f6ecff70a538c420b 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_true_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_true_dual_port_ram_dual_clock.vhd
@@ -33,13 +33,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_e1sg_true_dual_port_ram_dual_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
clk_a : in std_logic;
@@ -53,20 +51,16 @@ entity ip_arria10_e1sg_true_dual_port_ram_dual_clock is
q_a : out std_logic_vector((DATA_WIDTH - 1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_e1sg_true_dual_port_ram_dual_clock;
architecture rtl of ip_arria10_e1sg_true_dual_port_ram_dual_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM
shared variable ram : memory_t;
-
begin
-
-- Port A
process(clk_a)
begin
@@ -88,5 +82,4 @@ begin
q_b <= ram(addr_b);
end if;
end process;
-
end rtl;
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
index 3bb76e2262bb41b791e5acac0087638f481e73bf..340470c1754886571c8d2ec237c9c2b81c18873f 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
@@ -34,4 +34,3 @@
tx_digitalreset => CONNECTED_TO_tx_digitalreset, -- tx_digitalreset.tx_digitalreset
tx_ready => CONNECTED_TO_tx_ready -- tx_ready.tx_ready
);
-
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
index d40b3b22345ccc01dfac7bf9a5b9dfe2d992c2fb..5a53d30972078b5c9e7e765fcf201319dd6c4631 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_gx/tb_ip_arria10_e1sg_tse_sgmii_gx.vhd
@@ -32,13 +32,10 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_ip_arria10_e1sg_tse_sgmii_gx is
end tb_ip_arria10_e1sg_tse_sgmii_gx;
-
architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
constant serial_clk_period : time := 800 ps; -- 1250 MHz ????
@@ -402,7 +399,6 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
end if;
end proc_rx_packet;
-
-- Clocks and reset
signal tb_end : std_logic := '0';
signal eth_clk : std_logic := '0';
@@ -459,9 +455,7 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_gx is
signal dbg_mm : t_mm_bus;
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -744,5 +738,4 @@ begin
assert false report "Simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
index b5c9baa9506feee002e5212cb765e5a64af1f796..1fcf8f332f9d5ddeff782899d653acf38d1e976d 100644
--- a/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10_e1sg/tse_sgmii_lvds/tb_ip_arria10_e1sg_tse_sgmii_lvds.vhd
@@ -37,13 +37,10 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_ip_arria10_e1sg_tse_sgmii_lvds is
end tb_ip_arria10_e1sg_tse_sgmii_lvds;
-
architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
@@ -405,7 +402,6 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
end if;
end proc_rx_packet;
-
-- Clocks and reset
signal tb_end : std_logic := '0';
signal eth_clk : std_logic := '0';
@@ -458,9 +454,7 @@ architecture tb of tb_ip_arria10_e1sg_tse_sgmii_lvds is
signal dbg_mm : t_mm_bus;
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -726,5 +720,4 @@ begin
assert false report "Simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
index 2de8bcf036e06b2b2ace6941819d95f5471de4e5..e5221f4af8d1f1a4de5c5f9dd520ad10a5b50ebf 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_in.vhd
@@ -38,9 +38,7 @@ entity ip_arria10_e2sg_ddio_in is
);
end ip_arria10_e2sg_ddio_in;
-
architecture str of ip_arria10_e2sg_ddio_in is
-
component ip_arria10_e2sg_ddio_in_1 is
port (
datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
@@ -50,11 +48,8 @@ architecture str of ip_arria10_e2sg_ddio_in is
dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
);
end component;
-
begin
-
gen_w : for I in g_width - 1 downto 0 generate
-
u_ip_arria10_e2sg_ddio_in_1 : ip_arria10_e2sg_ddio_in_1
port map (
datain => in_dat(I downto I),
@@ -63,7 +58,6 @@ begin
dataout_h => out_dat_hi(I downto I),
dataout_l => out_dat_lo(I downto I)
);
-
end generate;
end str;
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd
index 98d2e24af553e6b00ca35254a9d4c81bfa34eb18..6fcc0779f8b6de6735a491fd3990500c4f82ca38 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/ip_arria10_e2sg_ddio_out.vhd
@@ -38,9 +38,7 @@ entity ip_arria10_e2sg_ddio_out is
);
end ip_arria10_e2sg_ddio_out;
-
architecture str of ip_arria10_e2sg_ddio_out is
-
component ip_arria10_e2sg_ddio_out_1 is
port (
dataout : out std_logic_vector(0 downto 0); -- pad_out.export
@@ -50,9 +48,7 @@ architecture str of ip_arria10_e2sg_ddio_out is
datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
);
end component;
-
begin
-
gen_w : for I in g_width - 1 downto 0 generate
u_ip_arria10_e2sg_ddio_out_1 : ip_arria10_e2sg_ddio_out_1
port map (
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd
index 6292230bbaf3d7ec2fd48a683143fcd7ba5c09e1..6422bbee2dcf6b681ebe79cb5815e383b5834c7b 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd
@@ -48,18 +48,13 @@ entity ip_arria10_e2sg_ddio_in_1 is
);
end ip_arria10_e2sg_ddio_in_1;
-
architecture beh of ip_arria10_e2sg_ddio_in_1 is
-
signal in_dat_r : std_logic;
signal in_dat_f : std_logic;
-
begin
-
in_dat_r <= datain(0) when rising_edge(ck);
in_dat_f <= datain(0) when falling_edge(ck);
dataout_h <= (others => in_dat_r);
dataout_l <= (others => in_dat_f) when rising_edge(ck);
-
end beh;
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd
index c31b29396835f1b54c8af90043608b12bc75e4b3..b27ef2ac7fc403b6862f8a9cc25ece49c39dfd12 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd
@@ -45,15 +45,10 @@ entity ip_arria10_e2sg_ddio_out_1 is
);
end ip_arria10_e2sg_ddio_out_1;
-
architecture beh of ip_arria10_e2sg_ddio_out_1 is
-
signal out_dat_r : std_logic;
signal out_dat_f : std_logic;
-
begin
-
dataout <= datain_l when falling_edge(outclock) else
datain_h when rising_edge(outclock);
-
end beh;
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
index 9d90c65ae0ed54c248450495426e7fdd01e187da..4f443703ccb3ece5a38e50d11c63fef1dfd1f819 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
@@ -41,9 +41,7 @@ use IEEE.std_logic_1164.all;
entity tb_ip_arria10_e2sg_ddio_1 is
end tb_ip_arria10_e2sg_ddio_1;
-
architecture tb of tb_ip_arria10_e2sg_ddio_1 is
-
constant c_clk_period : time := 10 ns;
signal tb_end : std_logic := '0';
@@ -55,9 +53,7 @@ architecture tb of tb_ip_arria10_e2sg_ddio_1 is
signal out_data : std_logic_vector(0 downto 0);
signal out_dat : std_logic;
signal out_dat_exp : std_logic;
-
begin
-
tb_end <= '0', '1' after 100 * c_clk_period;
clk <= not clk or tb_end after c_clk_period / 2;
@@ -122,5 +118,4 @@ begin
assert out_dat = out_dat_exp report "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
index 07b01b50284f92c140cb2182346714b748b659e2..03062d9b02f9e011238dfc6b4cd39b0bc78ac2bc 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
@@ -88,4 +88,3 @@
mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0 -- .readdatavalid
);
-
diff --git a/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
index 78f3cc42a91174ab8fa67a82bddcabd509d7fbf5..9c31185e837f0babb2f7bf4b5f57a1342dc319d2 100644
--- a/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e2sg/eth_10g/ip_arria10_e2sg_eth_10g.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e2sg
-- Description
--
@@ -136,9 +135,7 @@ entity ip_arria10_e2sg_eth_10g is
);
end ip_arria10_e2sg_eth_10g;
-
architecture str of ip_arria10_e2sg_eth_10g is
-
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
constant c_check_link_status : boolean := true; -- g_direction/="TX_ONLY";
constant c_check_xgmii_tx_ready : boolean := true; -- g_direction/="RX_ONLY";
@@ -171,12 +168,10 @@ architecture str of ip_arria10_e2sg_eth_10g is
signal reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels - 1 downto 0);
signal mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels - 1 downto 0);
-
begin
tx_snk_out_arr <= i_tx_snk_out_arr;
gen_mac : for I in 0 to g_nof_channels - 1 generate
-
i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
p_xon_flow_control : process(clk_156)
@@ -303,7 +298,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- MM bus mux
-----------------------------------------------------------------------------
@@ -330,5 +324,4 @@ begin
mosi_arr => reg_eth10g_mosi_arr,
miso_arr => reg_eth10g_miso_arr
);
-
end str;
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd
index 887841ab6d0bf29ae443abb062ba8bc12196ad23..bc3d268f9315585a6e39b34d36a99c8814d5664a 100644
--- a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_e2sg_fifo_dc is
);
end ip_arria10_e2sg_fifo_dc;
-
architecture SYN of ip_arria10_e2sg_fifo_dc is
-
component dcfifo
generic (
intended_device_family : string;
@@ -86,9 +84,7 @@ architecture SYN of ip_arria10_e2sg_fifo_dc is
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
-
begin
-
u_dcfifo : dcfifo
generic map (
intended_device_family => "Arria 10",
@@ -118,5 +114,4 @@ begin
wrfull => wrfull,
wrusedw => wrusedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd
index 49fbe8a0b6d40bf6955c5169089601d7fe7f3db6..48398c9f48726d736d940ea47624f17dc01218da 100644
--- a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_dc_mixed_widths.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_e2sg_fifo_dc_mixed_widths is
);
end ip_arria10_e2sg_fifo_dc_mixed_widths;
-
architecture SYN of ip_arria10_e2sg_fifo_dc_mixed_widths is
-
component dcfifo_mixed_widths
generic (
intended_device_family : string;
@@ -88,9 +86,7 @@ architecture SYN of ip_arria10_e2sg_fifo_dc_mixed_widths is
wrusedw : out std_logic_vector(wrusedw'range)
);
end component;
-
begin
-
dcfifo_mixed_widths_component : dcfifo_mixed_widths
generic map (
intended_device_family => "Arria 10",
@@ -122,5 +118,4 @@ begin
wrfull => wrfull,
wrusedw => wrusedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd
index f5dffa5e60479b29bc503e2da81af5e27361e2eb..2ead8f74d3c14207fbb357693af1a0095bda22ea 100644
--- a/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd
+++ b/libraries/technology/ip_arria10_e2sg/fifo/ip_arria10_e2sg_fifo_sc.vhd
@@ -51,9 +51,7 @@ entity ip_arria10_e2sg_fifo_sc is
);
end ip_arria10_e2sg_fifo_sc;
-
architecture SYN of ip_arria10_e2sg_fifo_sc is
-
component scfifo
generic (
add_ram_output_register : string;
@@ -79,9 +77,7 @@ architecture SYN of ip_arria10_e2sg_fifo_sc is
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
-
begin
-
u_scfifo : scfifo
generic map (
add_ram_output_register => "ON",
@@ -106,5 +102,4 @@ begin
q => q,
usedw => usedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
index f6fc3853dfa66587f2ead5b9a61444eda5b99545..87a34d3c9c97e45cb0e42637a452552975a2ac17 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b.vhd
@@ -71,7 +71,6 @@ entity ip_arria10_e2sg_jesd204b is
end ip_arria10_e2sg_jesd204b;
architecture str of ip_arria10_e2sg_jesd204b is
-
-- JESD IP constants
-- . JESD204B MM has 256 bytes = 64 words, so mm_addr_w = 6 would be enough,
-- but using mm_addr_w = 8 and span = 256 words is fine too.
@@ -231,7 +230,6 @@ architecture str of ip_arria10_e2sg_jesd204b is
rx_ready : out std_logic_vector(11 downto 0) -- rx_ready
);
end component ip_arria10_e2sg_jesd204b_rx_xcvr_reset_control_12;
-
begin
-- The mm_rst resets the MM interface, but is also used to reset the JESD IP reset sequencer.
-- Therefore a reset of mm_rst effectively resets the entire ip_arria10_e2sg_jesd204b and causes a reset on the rx_rst output.
@@ -251,7 +249,6 @@ begin
gen_jesd204b_rx : if g_direction = "RX_ONLY" generate
gen_jesd204b_rx_channels : for I in 0 to g_nof_streams - 1 generate
-
-----------------------------------------------------------------------------
-- The JESD204 IP (rx only)
-----------------------------------------------------------------------------
@@ -410,7 +407,6 @@ begin
end if;
end if;
end process;
-
end generate; -- gen_jesd204b_rx_channels : FOR I IN 0 TO g_nof_streams-1 GENERATE
-----------------------------------------------------------------------------
@@ -491,7 +487,6 @@ begin
rx_is_lockedtodata => rx_islockedtodata_arr, -- input from PHY
rx_ready => xcvr_rst_ctrl_rx_ready_arr -- From example design: gate with rx_csr_lane_powerdown to reset transceiver
);
-
end generate; -- gen_jesd204b_rx : IF g_direction = "RX_ONLY" GENERATE
gen_enable_sync_n : for i in 0 to g_nof_streams - 1 generate
@@ -525,7 +520,4 @@ begin
mosi_arr => jesd204b_mosi_arr,
miso_arr => jesd204b_miso_arr
);
-
end str;
-
-
diff --git a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_component_pkg.vhd b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_component_pkg.vhd
index cd83730b5a82193fff6305e5645db1b9b5c89ffb..7cff7179c570eee9a3373af297e7003d5bc394e6 100644
--- a/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_component_pkg.vhd
+++ b/libraries/technology/ip_arria10_e2sg/jesd204b/ip_arria10_e2sg_jesd204b_component_pkg.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Component declarations for jesd204b ip blocks
library IEEE, technology_lib, common_lib, dp_lib;
@@ -31,7 +30,6 @@ use technology_lib.technology_pkg.all;
use dp_lib.dp_stream_pkg.all;
package ip_arria10_e2sg_jesd204b_component_pkg is
-
------------------------------------------------------------------------------
-- Main IP, TX ONLY, 1 channel
------------------------------------------------------------------------------
@@ -88,8 +86,6 @@ package ip_arria10_e2sg_jesd204b_component_pkg is
);
end component ip_arria10_e2sg_jesd204b_tx;
-
-
end ip_arria10_e2sg_jesd204b_component_pkg;
package body ip_arria10_e2sg_jesd204b_component_pkg is
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2_rtl.vhd b/libraries/technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2_rtl.vhd
index bfc7e19a94b2a3278cbdc0f755dc1c15e5569c52..7c4a0bd71e9fa861d0ae64cc2b246fb813ceeb53 100644
--- a/libraries/technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2_rtl.vhd
+++ b/libraries/technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2_rtl.vhd
@@ -26,7 +26,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
------------------------------------------------------------------------------
-- Function:
-- . res = a0 * b0 + a1 * b1
@@ -56,9 +55,7 @@ entity ip_arria10_e2sg_mult_add2_rtl is
);
end ip_arria10_e2sg_mult_add2_rtl;
-
architecture str of ip_arria10_e2sg_mult_add2_rtl is
-
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
@@ -94,9 +91,7 @@ architecture str of ip_arria10_e2sg_mult_add2_rtl is
signal prod1 : signed(c_prod_w - 1 downto 0);
signal sum : signed(c_sum_w - 1 downto 0);
signal result : signed(g_res_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -173,6 +168,7 @@ begin
gen_add : if g_add_sub = "ADD" generate
nxt_sum <= RESIZE_NUM(prod0, c_sum_w) + prod1;
end generate;
+
gen_sub : if g_add_sub = "SUB" generate
nxt_sum <= RESIZE_NUM(prod0, c_sum_w) - prod1;
end generate;
@@ -184,7 +180,6 @@ begin
sum <= reg_sum;
end generate;
-
------------------------------------------------------------------------------
-- Result sum after optional rounding
------------------------------------------------------------------------------
@@ -199,5 +194,4 @@ begin
end generate;
res <= std_logic_vector(result);
-
end str;
diff --git a/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4_rtl.vhd b/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4_rtl.vhd
index f1dd51e590b6c8b50d16d89cb84dcf181a13d3c7..a0b94f67e6db91d9ad5b94f86dc5cf0e55932682 100644
--- a/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4_rtl.vhd
+++ b/libraries/technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add4_rtl.vhd
@@ -53,7 +53,6 @@ entity ip_arria10_e2sg_mult_add4_rtl is
end ip_arria10_e2sg_mult_add4_rtl;
architecture str of ip_arria10_e2sg_mult_add4_rtl is
-
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
@@ -108,9 +107,7 @@ architecture str of ip_arria10_e2sg_mult_add4_rtl is
signal sum1 : signed(g_in_a_w + g_in_b_w downto 0);
signal sum : signed(g_in_a_w + g_in_b_w + 1 downto 0);
signal result : signed(res'range);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -219,6 +216,7 @@ begin
gen_add0 : if g_add_sub0 = "ADD" generate
nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) + prod1;
end generate;
+
gen_sub0 : if g_add_sub0 = "SUB" generate
nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) - prod1;
end generate;
@@ -226,6 +224,7 @@ begin
gen_add1 : if g_add_sub1 = "ADD" generate
nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) + prod3;
end generate;
+
gen_sub1 : if g_add_sub1 = "SUB" generate
nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) - prod3;
end generate;
@@ -240,7 +239,6 @@ begin
sum1 <= reg_sum1;
end generate;
-
------------------------------------------------------------------------------
-- Second sum
------------------------------------------------------------------------------
@@ -249,11 +247,11 @@ begin
gen_add : if g_add_sub = "ADD" generate
sum <= RESIZE_NUM(sum0, sum'length) + sum1;
end generate;
+
gen_sub : if g_add_sub = "SUB" generate
sum <= RESIZE_NUM(sum0, sum'length) - sum1;
end generate;
-
------------------------------------------------------------------------------
-- Result sum after optional rounding
------------------------------------------------------------------------------
@@ -268,5 +266,4 @@ begin
end generate;
res <= std_logic_vector(result);
-
end str;
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
index 3c87928c117a85e66cacae601b3ceb51092c0014..97ef59ff32d6bb06cbe140797d6c6a00ab97af80 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_cr_cw.vhd
@@ -50,9 +50,7 @@ entity ip_arria10_e2sg_ram_cr_cw is
);
end ip_arria10_e2sg_ram_cr_cw;
-
architecture SYN of ip_arria10_e2sg_ram_cr_cw is
-
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -94,9 +92,7 @@ architecture SYN of ip_arria10_e2sg_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e2sg_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
index e1fcb2365289c8093c1cee71512d19765dab2249..5502afa475a153460709d9dfa1e94450eef141d1 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_e2sg_ram_crw_crw is
);
end ip_arria10_e2sg_ram_crw_crw;
-
architecture SYN of ip_arria10_e2sg_ram_crw_crw is
-
constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
@@ -110,9 +108,7 @@ architecture SYN of ip_arria10_e2sg_ram_crw_crw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e2sg_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
index 22d39efa268811c4acc42dd177c303b96e4f688c..9c6b139903684980cc8b5d8d919c29f563d62219 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
@@ -26,4 +26,3 @@
clock_a => CONNECTED_TO_clock_a, -- clock_a.clk
clock_b => CONNECTED_TO_clock_b -- clock_b.clk
);
-
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
index ce0317d19c164eeb0d043eda009c38335a760719..56433ca33692fb62192341201b74240c139049d6 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ram_2port_2000/sim/ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey.vhd
@@ -10,9 +10,6 @@
-- Intel or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-
-
-
library ieee;
use ieee.std_logic_1164.all;
@@ -35,12 +32,9 @@ entity ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey is
);
end ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey;
-
architecture SYN of ip_arria10_e2sg_ram_crw_crw_ram_2port_2000_zxnv4ey is
-
signal sub_wire0 : std_logic_vector(7 downto 0);
signal sub_wire1 : std_logic_vector(7 downto 0);
-
begin
q_a <= sub_wire0 (7 downto 0);
q_b <= sub_wire1 (7 downto 0);
@@ -87,8 +81,4 @@ begin
q_a => sub_wire0,
q_b => sub_wire1
);
-
-
-
end SYN;
-
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
index 26326f34b0713c57aebf77ca1178fc88c01b507a..fec15d4bc1b9161b9d9da5bf28cb3c83f314b9a6 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crwk_crw.vhd
@@ -10,7 +10,6 @@
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-
library ieee, technology_lib;
use ieee.std_logic_1164.all;
use technology_lib.technology_pkg.all;
@@ -44,9 +43,7 @@ entity ip_arria10_e2sg_ram_crwk_crw is
);
end ip_arria10_e2sg_ram_crwk_crw;
-
architecture SYN of ip_arria10_e2sg_ram_crwk_crw is
-
constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
@@ -92,9 +89,7 @@ architecture SYN of ip_arria10_e2sg_ram_crwk_crw is
q_b : out std_logic_vector(g_dat_b_w - 1 downto 0)
);
end component;
-
begin
-
-- Copied from ip_arria10_e2sg_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e2sg_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
generic map (
@@ -137,6 +132,4 @@ begin
q_a => q_a,
q_b => q_b
);
-
end SYN;
-
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd
index e050e0acc00b2487ad2506d73b6f2463ff8ab73e..1f3461d27e7cba48f93cdf56f82b1f979a01b8ca 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_r_w.vhd
@@ -48,9 +48,7 @@ entity ip_arria10_e2sg_ram_r_w is
);
end ip_arria10_e2sg_ram_r_w;
-
architecture SYN of ip_arria10_e2sg_ram_r_w is
-
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -90,9 +88,7 @@ architecture SYN of ip_arria10_e2sg_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e2sg_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd
index c531ec3a44ad4831df5ffdd78942cbe176cbd7ac..0da6475c1efd0b3f38465141b3dc92393f6d803e 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd
@@ -30,13 +30,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_e2sg_simple_dual_port_ram_dual_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
rclk : in std_logic;
@@ -47,20 +45,16 @@ entity ip_arria10_e2sg_simple_dual_port_ram_dual_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_e2sg_simple_dual_port_ram_dual_clock;
architecture rtl of ip_arria10_e2sg_simple_dual_port_ram_dual_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-
begin
-
process(wclk)
begin
if(rising_edge(wclk)) then
@@ -76,5 +70,4 @@ begin
q <= ram(raddr);
end if;
end process;
-
end rtl;
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
index 66c69a401e746a99a0cc02f165e84db00bea783c..6e789dafdc078d91f84cd714ae2a693aa8bd76b2 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_simple_dual_port_ram_single_clock.vhd
@@ -29,13 +29,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_e2sg_simple_dual_port_ram_single_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
clk : in std_logic;
@@ -45,20 +43,16 @@ entity ip_arria10_e2sg_simple_dual_port_ram_single_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_e2sg_simple_dual_port_ram_single_clock;
architecture rtl of ip_arria10_e2sg_simple_dual_port_ram_single_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-
begin
-
process(clk)
begin
if(rising_edge(clk)) then
@@ -71,6 +65,4 @@ begin
q <= ram(raddr);
end if;
end process;
-
end rtl;
-
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd
index d8d11b395f5d1d175717df14db83e97171d870d4..179c89a7741282186b7be122732e548b7ad82efd 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd
@@ -33,13 +33,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_e2sg_true_dual_port_ram_dual_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
clk_a : in std_logic;
@@ -53,20 +51,16 @@ entity ip_arria10_e2sg_true_dual_port_ram_dual_clock is
q_a : out std_logic_vector((DATA_WIDTH - 1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_e2sg_true_dual_port_ram_dual_clock;
architecture rtl of ip_arria10_e2sg_true_dual_port_ram_dual_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM
shared variable ram : memory_t;
-
begin
-
-- Port A
process(clk_a)
begin
@@ -88,5 +82,4 @@ begin
q_b <= ram(addr_b);
end if;
end process;
-
end rtl;
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd
index fc66ededbfee6305bcf271078ec00d5fa789ec50..d4639eafa14804f16ff22e7678aad54cbf2719bf 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_gx/tb_ip_arria10_e2sg_tse_sgmii_gx.vhd
@@ -32,13 +32,10 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_ip_arria10_e2sg_tse_sgmii_gx is
end tb_ip_arria10_e2sg_tse_sgmii_gx;
-
architecture tb of tb_ip_arria10_e2sg_tse_sgmii_gx is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
constant serial_clk_period : time := 800 ps; -- 1250 MHz ????
@@ -402,7 +399,6 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_gx is
end if;
end proc_rx_packet;
-
-- Clocks and reset
signal tb_end : std_logic := '0';
signal eth_clk : std_logic := '0';
@@ -459,9 +455,7 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_gx is
signal dbg_mm : t_mm_bus;
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -744,5 +738,4 @@ begin
assert false report "Simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd
index 6b5bcc45c325210c6863da18889c8d78d57d400c..7ee9e483be661c075782000c9fd63f2e4abf679e 100644
--- a/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10_e2sg/tse_sgmii_lvds/tb_ip_arria10_e2sg_tse_sgmii_lvds.vhd
@@ -37,13 +37,10 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_ip_arria10_e2sg_tse_sgmii_lvds is
end tb_ip_arria10_e2sg_tse_sgmii_lvds;
-
architecture tb of tb_ip_arria10_e2sg_tse_sgmii_lvds is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
@@ -405,7 +402,6 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_lvds is
end if;
end proc_rx_packet;
-
-- Clocks and reset
signal tb_end : std_logic := '0';
signal eth_clk : std_logic := '0';
@@ -458,9 +454,7 @@ architecture tb of tb_ip_arria10_e2sg_tse_sgmii_lvds is
signal dbg_mm : t_mm_bus;
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -726,5 +720,4 @@ begin
assert false report "Simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/ip_arria10_e3sge3_ddio_in.vhd b/libraries/technology/ip_arria10_e3sge3/ddio/ip_arria10_e3sge3_ddio_in.vhd
index 38c7962560bf14a503223a8eebdebb97f8efab83..f28811cdb53a00b52c1056293cc42397e45e42ea 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/ip_arria10_e3sge3_ddio_in.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/ip_arria10_e3sge3_ddio_in.vhd
@@ -38,9 +38,7 @@ entity ip_arria10_e3sge3_ddio_in is
);
end ip_arria10_e3sge3_ddio_in;
-
architecture str of ip_arria10_e3sge3_ddio_in is
-
component ip_arria10_e3sge3_ddio_in_1 is
port (
datain : in std_logic_vector(0 downto 0) := (others => '0'); -- pad_in.export
@@ -50,11 +48,8 @@ architecture str of ip_arria10_e3sge3_ddio_in is
dataout_l : out std_logic_vector(0 downto 0) -- dataout_l.fragment
);
end component;
-
begin
-
gen_w : for I in g_width - 1 downto 0 generate
-
u_ip_arria10_e3sge3_ddio_in_1 : ip_arria10_e3sge3_ddio_in_1
port map (
datain => in_dat(I downto I),
@@ -63,7 +58,6 @@ begin
dataout_h => out_dat_hi(I downto I),
dataout_l => out_dat_lo(I downto I)
);
-
end generate;
end str;
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/ip_arria10_e3sge3_ddio_out.vhd b/libraries/technology/ip_arria10_e3sge3/ddio/ip_arria10_e3sge3_ddio_out.vhd
index a881d0eee17b73784c250344be0be19af02288de..867d32d4f7268ac8cd433f0d1ce0e9a2d0682ded 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/ip_arria10_e3sge3_ddio_out.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/ip_arria10_e3sge3_ddio_out.vhd
@@ -38,9 +38,7 @@ entity ip_arria10_e3sge3_ddio_out is
);
end ip_arria10_e3sge3_ddio_out;
-
architecture str of ip_arria10_e3sge3_ddio_out is
-
component ip_arria10_e3sge3_ddio_out_1 is
port (
dataout : out std_logic_vector(0 downto 0); -- pad_out.export
@@ -50,9 +48,7 @@ architecture str of ip_arria10_e3sge3_ddio_out is
datain_l : in std_logic_vector(0 downto 0) := (others => '0') -- datain_l.fragment
);
end component;
-
begin
-
gen_w : for I in g_width - 1 downto 0 generate
u_ip_arria10_e3sge3_ddio_out_1 : ip_arria10_e3sge3_ddio_out_1
port map (
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd b/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd
index 1dbd875bf4fa4ce608117a25767a15873846989d..757284ef4804d4cc036d4f22098de65c6ad987da 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd
@@ -48,18 +48,13 @@ entity ip_arria10_e3sge3_ddio_in_1 is
);
end ip_arria10_e3sge3_ddio_in_1;
-
architecture beh of ip_arria10_e3sge3_ddio_in_1 is
-
signal in_dat_r : std_logic;
signal in_dat_f : std_logic;
-
begin
-
in_dat_r <= datain(0) when rising_edge(inclock);
in_dat_f <= datain(0) when falling_edge(inclock);
dataout_h <= (others => in_dat_r);
dataout_l <= (others => in_dat_f) when rising_edge(inclock);
-
end beh;
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd b/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd
index 985a341c55c02b2efdb90f262c631d53e55ba7a0..d18787b4fba26a3765f03a99b6f605c442b2f7db 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd
@@ -45,15 +45,10 @@ entity ip_arria10_e3sge3_ddio_out_1 is
);
end ip_arria10_e3sge3_ddio_out_1;
-
architecture beh of ip_arria10_e3sge3_ddio_out_1 is
-
signal out_dat_r : std_logic;
signal out_dat_f : std_logic;
-
begin
-
dataout <= datain_l when falling_edge(outclock) else
datain_h when rising_edge(outclock);
-
end beh;
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd b/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd
index d95dccc22d29b5bede680bc415c61543faf96ed6..c90e97ad924996ffee42ab1717ee503d844c9533 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd
@@ -41,9 +41,7 @@ use IEEE.std_logic_1164.all;
entity tb_ip_arria10_e3sge3_ddio_1 is
end tb_ip_arria10_e3sge3_ddio_1;
-
architecture tb of tb_ip_arria10_e3sge3_ddio_1 is
-
constant c_clk_period : time := 10 ns;
signal tb_end : std_logic := '0';
@@ -55,9 +53,7 @@ architecture tb of tb_ip_arria10_e3sge3_ddio_1 is
signal out_data : std_logic_vector(0 downto 0);
signal out_dat : std_logic;
signal out_dat_exp : std_logic;
-
begin
-
tb_end <= '0', '1' after 100 * c_clk_period;
clk <= not clk or tb_end after c_clk_period / 2;
@@ -122,5 +118,4 @@ begin
assert out_dat = out_dat_exp report "tb_ip_arria10_e3sge3_ddio_1: Error, unexpeced data at rising edge";
end if;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd b/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
index 4826d2d46aef6c5f165122725c42afa6ad64d970..45ca9acdf0dae35089a7dfcbd9176212350b850c 100644
--- a/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/eth_10g/ip_arria10_e3sge3_eth_10g.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and 10gbase_r for c_tech_arria10_e3sge3
-- Description
--
@@ -92,7 +91,6 @@ use common_lib.common_interface_layers_pkg.all;
use dp_lib.dp_stream_pkg.all;
use tech_mac_10g_lib.tech_mac_10g_component_pkg.all;
-
entity ip_arria10_e3sge3_eth_10g is
generic (
g_sim : boolean := false;
@@ -136,9 +134,7 @@ entity ip_arria10_e3sge3_eth_10g is
);
end ip_arria10_e3sge3_eth_10g;
-
architecture str of ip_arria10_e3sge3_eth_10g is
-
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
constant c_check_link_status : boolean := g_direction /= "TX_ONLY";
constant c_check_xgmii_tx_ready : boolean := g_direction /= "RX_ONLY";
@@ -169,12 +165,10 @@ architecture str of ip_arria10_e3sge3_eth_10g is
signal reg_eth10g_miso_arr : t_mem_miso_arr(g_nof_channels - 1 downto 0);
signal mm_reg_eth10g_arr : t_slv_32_arr(g_nof_channels - 1 downto 0);
-
begin
tx_snk_out_arr <= i_tx_snk_out_arr;
gen_mac : for I in 0 to g_nof_channels - 1 generate
-
i_tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
p_xon_flow_control : process(clk_156)
@@ -261,7 +255,6 @@ begin
rx_serial_arr => serial_rx_arr
);
-
gen_reg_eth10g : for I in 0 to g_nof_channels - 1 generate
mm_reg_eth10g_arr(I) <= RESIZE_UVEC(xgmii_link_status_arr(I) & xgmii_tx_ready_arr(I) & i_tx_snk_out_arr(I).xon, c_mem_reg_eth10g_dat_w);
@@ -293,7 +286,6 @@ begin
);
end generate;
-
-----------------------------------------------------------------------------
-- MM bus mux
-----------------------------------------------------------------------------
@@ -320,5 +312,4 @@ begin
mosi_arr => reg_eth10g_mosi_arr,
miso_arr => reg_eth10g_miso_arr
);
-
end str;
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd
index 7231923dd6f3686fd9a525a397a1f88181c6c5f0..c83b39884c33e1cf8807807aa7fe8da27e10aa87 100644
--- a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_e3sge3_fifo_dc is
);
end ip_arria10_e3sge3_fifo_dc;
-
architecture SYN of ip_arria10_e3sge3_fifo_dc is
-
component dcfifo
generic (
intended_device_family : string;
@@ -86,9 +84,7 @@ architecture SYN of ip_arria10_e3sge3_fifo_dc is
wrusedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
-
begin
-
u_dcfifo : dcfifo
generic map (
intended_device_family => "Arria 10",
@@ -118,5 +114,4 @@ begin
wrfull => wrfull,
wrusedw => wrusedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd
index 8eaf5ceb56ddc0fd576ca2066f864fc0b12c2cd7..09df0fc59d5a163186cbfffa7a5b6e181a2a8c78 100644
--- a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_dc_mixed_widths.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_e3sge3_fifo_dc_mixed_widths is
);
end ip_arria10_e3sge3_fifo_dc_mixed_widths;
-
architecture SYN of ip_arria10_e3sge3_fifo_dc_mixed_widths is
-
component dcfifo_mixed_widths
generic (
intended_device_family : string;
@@ -88,9 +86,7 @@ architecture SYN of ip_arria10_e3sge3_fifo_dc_mixed_widths is
wrusedw : out std_logic_vector(wrusedw'range)
);
end component;
-
begin
-
dcfifo_mixed_widths_component : dcfifo_mixed_widths
generic map (
intended_device_family => "Arria 10",
@@ -122,5 +118,4 @@ begin
wrfull => wrfull,
wrusedw => wrusedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd
index 4e233325fe29bea8dedb91d59fddf9c4fd49fbd1..1ec53513552cf144eeec03fc8e1457d07898e58e 100644
--- a/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/fifo/ip_arria10_e3sge3_fifo_sc.vhd
@@ -51,9 +51,7 @@ entity ip_arria10_e3sge3_fifo_sc is
);
end ip_arria10_e3sge3_fifo_sc;
-
architecture SYN of ip_arria10_e3sge3_fifo_sc is
-
component scfifo
generic (
add_ram_output_register : string;
@@ -79,9 +77,7 @@ architecture SYN of ip_arria10_e3sge3_fifo_sc is
usedw : out std_logic_vector(tech_ceil_log2(g_nof_words) - 1 downto 0)
);
end component;
-
begin
-
u_scfifo : scfifo
generic map (
add_ram_output_register => "ON",
@@ -106,5 +102,4 @@ begin
q => q,
usedw => usedw
);
-
end SYN;
diff --git a/libraries/technology/ip_arria10_e3sge3/mult_add4/ip_arria10_e3sge3_mult_add4_rtl.vhd b/libraries/technology/ip_arria10_e3sge3/mult_add4/ip_arria10_e3sge3_mult_add4_rtl.vhd
index bfdb7d51634384a84815f302ab000ef71a3ac294..fc50b7118460c8f4b1800064273f2466819a705f 100644
--- a/libraries/technology/ip_arria10_e3sge3/mult_add4/ip_arria10_e3sge3_mult_add4_rtl.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/mult_add4/ip_arria10_e3sge3_mult_add4_rtl.vhd
@@ -53,7 +53,6 @@ entity ip_arria10_e3sge3_mult_add4_rtl is
end ip_arria10_e3sge3_mult_add4_rtl;
architecture str of ip_arria10_e3sge3_mult_add4_rtl is
-
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
@@ -108,9 +107,7 @@ architecture str of ip_arria10_e3sge3_mult_add4_rtl is
signal sum1 : signed(g_in_a_w + g_in_b_w downto 0);
signal sum : signed(g_in_a_w + g_in_b_w + 1 downto 0);
signal result : signed(res'range);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -219,6 +216,7 @@ begin
gen_add0 : if g_add_sub0 = "ADD" generate
nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) + prod1;
end generate;
+
gen_sub0 : if g_add_sub0 = "SUB" generate
nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) - prod1;
end generate;
@@ -226,6 +224,7 @@ begin
gen_add1 : if g_add_sub1 = "ADD" generate
nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) + prod3;
end generate;
+
gen_sub1 : if g_add_sub1 = "SUB" generate
nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) - prod3;
end generate;
@@ -240,7 +239,6 @@ begin
sum1 <= reg_sum1;
end generate;
-
------------------------------------------------------------------------------
-- Second sum
------------------------------------------------------------------------------
@@ -249,11 +247,11 @@ begin
gen_add : if g_add_sub = "ADD" generate
sum <= RESIZE_NUM(sum0, sum'length) + sum1;
end generate;
+
gen_sub : if g_add_sub = "SUB" generate
sum <= RESIZE_NUM(sum0, sum'length) - sum1;
end generate;
-
------------------------------------------------------------------------------
-- Result sum after optional rounding
------------------------------------------------------------------------------
@@ -268,5 +266,4 @@ begin
end generate;
res <= std_logic_vector(result);
-
end str;
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
index 51682fa2f82e91e249a8151575adae6555e5fa8b..a3684875767a374adc20889cefc77a92b7058c6c 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_cr_cw.vhd
@@ -50,9 +50,7 @@ entity ip_arria10_e3sge3_ram_cr_cw is
);
end ip_arria10_e3sge3_ram_cr_cw;
-
architecture SYN of ip_arria10_e3sge3_ram_cr_cw is
-
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -93,9 +91,7 @@ architecture SYN of ip_arria10_e3sge3_ram_cr_cw is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e3sge3_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
index 013e8f634c39da4e79b79eefe2bb803e7ec984ff..4b5fe63107fdb859fb3cc22f4191d6659cebf02a 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crw_crw.vhd
@@ -53,9 +53,7 @@ entity ip_arria10_e3sge3_ram_crw_crw is
);
end ip_arria10_e3sge3_ram_crw_crw;
-
architecture SYN of ip_arria10_e3sge3_ram_crw_crw is
-
constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
@@ -109,9 +107,7 @@ architecture SYN of ip_arria10_e3sge3_ram_crw_crw is
signal reg_a : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e3sge3_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
index c9f32b64aa37bf120dc6c5020705e89f9850ed7b..9d6fa597760bc1766e68c565c062d91186fb9d85 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_crwk_crw.vhd
@@ -10,7 +10,6 @@
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-
library ieee, technology_lib;
use ieee.std_logic_1164.all;
use technology_lib.technology_pkg.all;
@@ -44,9 +43,7 @@ entity ip_arria10_e3sge3_ram_crwk_crw is
);
end ip_arria10_e3sge3_ram_crwk_crw;
-
architecture SYN of ip_arria10_e3sge3_ram_crwk_crw is
-
constant c_outdata_reg_a : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
@@ -92,9 +89,7 @@ architecture SYN of ip_arria10_e3sge3_ram_crwk_crw is
q_b : out std_logic_vector(g_dat_b_w - 1 downto 0)
);
end component;
-
begin
-
-- Copied from ip_arria10_e3sge3_ram_crwk_crw/ram_2port_140/sim/ip_arria10_e3sge3_ram_crwk_crw_ram_2port_140_iyfl3wi.vhd
u_altera_syncram : altera_syncram
generic map (
@@ -137,6 +132,4 @@ begin
q_a => q_a,
q_b => q_b
);
-
end SYN;
-
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
index 370948437c051bb7d8a5f82b0b593519371b4db0..7df895809eb9e800570223916242b0d0dbfbc65c 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_ram_r_w.vhd
@@ -48,9 +48,7 @@ entity ip_arria10_e3sge3_ram_r_w is
);
end ip_arria10_e3sge3_ram_r_w;
-
architecture SYN of ip_arria10_e3sge3_ram_r_w is
-
constant c_outdata_reg_b : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK1");
component altera_syncram
@@ -90,9 +88,7 @@ architecture SYN of ip_arria10_e3sge3_ram_r_w is
signal out_q : std_logic_vector(g_dat_w - 1 downto 0);
signal reg_q : std_logic_vector(g_dat_w - 1 downto 0);
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_arria10_e3sge3_ram_r_w : read latency must be 1 (default) or 2" severity FAILURE;
gen_ip : if g_inferred = false generate
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_dual_clock.vhd
index 2fa000bb9539cb601cdb0d4c71cbebb8a41b298f..dd923d0142d8d6290b45e23b44c6954b1fe76336 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_dual_clock.vhd
@@ -30,13 +30,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_e3sge3_simple_dual_port_ram_dual_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
rclk : in std_logic;
@@ -47,20 +45,16 @@ entity ip_arria10_e3sge3_simple_dual_port_ram_dual_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_e3sge3_simple_dual_port_ram_dual_clock;
architecture rtl of ip_arria10_e3sge3_simple_dual_port_ram_dual_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-
begin
-
process(wclk)
begin
if(rising_edge(wclk)) then
@@ -76,5 +70,4 @@ begin
q <= ram(raddr);
end if;
end process;
-
end rtl;
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd
index 0edf5e2d7ac1b2ff0896f8490167e18ef22fa94b..237904b7e18740cb2154dd70e6a0b31b58da1598 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_simple_dual_port_ram_single_clock.vhd
@@ -29,13 +29,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_e3sge3_simple_dual_port_ram_single_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
clk : in std_logic;
@@ -45,20 +43,16 @@ entity ip_arria10_e3sge3_simple_dual_port_ram_single_clock is
we : in std_logic := '1';
q : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_e3sge3_simple_dual_port_ram_single_clock;
architecture rtl of ip_arria10_e3sge3_simple_dual_port_ram_single_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM signal.
signal ram : memory_t;
-
begin
-
process(clk)
begin
if(rising_edge(clk)) then
@@ -71,6 +65,4 @@ begin
q <= ram(raddr);
end if;
end process;
-
end rtl;
-
diff --git a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_true_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_true_dual_port_ram_dual_clock.vhd
index bbb68a7fe36ed48dbb3bbbd7a818abe0f29647da..1a8e2b66ab3ad3c506c679b6c37971ea63c504c3 100644
--- a/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_true_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ram/ip_arria10_e3sge3_true_dual_port_ram_dual_clock.vhd
@@ -33,13 +33,11 @@ library ieee;
use ieee.std_logic_1164.all;
entity ip_arria10_e3sge3_true_dual_port_ram_dual_clock is
-
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 6
);
-
port
(
clk_a : in std_logic;
@@ -53,20 +51,16 @@ entity ip_arria10_e3sge3_true_dual_port_ram_dual_clock is
q_a : out std_logic_vector((DATA_WIDTH - 1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH - 1) downto 0)
);
-
end ip_arria10_e3sge3_true_dual_port_ram_dual_clock;
architecture rtl of ip_arria10_e3sge3_true_dual_port_ram_dual_clock is
-
-- Build a 2-D array type for the RAM
subtype word_t is std_logic_vector((DATA_WIDTH - 1) downto 0);
type memory_t is array(2**ADDR_WIDTH - 1 downto 0) of word_t;
-- Declare the RAM
shared variable ram : memory_t;
-
begin
-
-- Port A
process(clk_a)
begin
@@ -88,5 +82,4 @@ begin
q_b <= ram(addr_b);
end if;
end process;
-
end rtl;
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd
index 9bbf206d02e9ea635a501e20279fbb1cd7cd89d2..b95e10bb59c9e31735b4c4e9036ca1a8668526d5 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_gx/tb_ip_arria10_e3sge3_tse_sgmii_gx.vhd
@@ -32,13 +32,10 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_ip_arria10_e3sge3_tse_sgmii_gx is
end tb_ip_arria10_e3sge3_tse_sgmii_gx;
-
architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_gx is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
constant serial_clk_period : time := 800 ps; -- 1250 MHz ????
@@ -402,7 +399,6 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_gx is
end if;
end proc_rx_packet;
-
-- Clocks and reset
signal tb_end : std_logic := '0';
signal eth_clk : std_logic := '0';
@@ -459,9 +455,7 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_gx is
signal dbg_mm : t_mm_bus;
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -744,5 +738,4 @@ begin
assert false report "Simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd
index bdd20b686a087eee9e62f63ca5bf2524ce1bc271..f5617ba27ad817fa690a21e25af3d900c768d6bd 100644
--- a/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/tse_sgmii_lvds/tb_ip_arria10_e3sge3_tse_sgmii_lvds.vhd
@@ -37,13 +37,10 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_ip_arria10_e3sge3_tse_sgmii_lvds is
end tb_ip_arria10_e3sge3_tse_sgmii_lvds;
-
architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_lvds is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
@@ -405,7 +402,6 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_lvds is
end if;
end proc_rx_packet;
-
-- Clocks and reset
signal tb_end : std_logic := '0';
signal eth_clk : std_logic := '0';
@@ -458,9 +454,7 @@ architecture tb of tb_ip_arria10_e3sge3_tse_sgmii_lvds is
signal dbg_mm : t_mm_bus;
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -726,5 +720,4 @@ begin
assert false report "Simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_in.vhd b/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_in.vhd
index 9440b884ae1661ebe4418167c81e87d60f72bcb4..c5e2a79a2f8c231a4a966952fb4f62fd664458c0 100644
--- a/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_in.vhd
+++ b/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_in.vhd
@@ -70,11 +70,8 @@ entity ip_stratixiv_ddio_in is
);
end ip_stratixiv_ddio_in;
-
architecture str of ip_stratixiv_ddio_in is
-
begin
-
ddio: altddio_in
generic map (
intended_device_family => g_device_family,
@@ -92,5 +89,4 @@ begin
dataout_h => out_dat_hi,
dataout_l => out_dat_lo
);
-
end str;
diff --git a/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_out.vhd b/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_out.vhd
index bc7ac67cdb30d0d60ce14a2f981b6d0451f018d1..13c171d62c6cd0706d8998b29034a9400a6a6855 100644
--- a/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_out.vhd
+++ b/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_out.vhd
@@ -75,9 +75,7 @@ entity ip_stratixiv_ddio_out is
end ip_stratixiv_ddio_out;
architecture str of ip_stratixiv_ddio_out is
-
begin
-
ddio : ALTDDIO_OUT
generic map (
extend_oe_disable => "OFF",
@@ -97,5 +95,4 @@ begin
outclocken => in_clk_en,
dataout => out_dat
);
-
end str;
diff --git a/libraries/technology/ip_stratixiv/eth_10g/ip_stratixiv_eth_10g.vhd b/libraries/technology/ip_stratixiv/eth_10g/ip_stratixiv_eth_10g.vhd
index 5681a2e7c161ae62d5af86a8f6ce63b6ac334e3c..72b14be2c6bb98da356bfac081af077eda306d96 100644
--- a/libraries/technology/ip_stratixiv/eth_10g/ip_stratixiv_eth_10g.vhd
+++ b/libraries/technology/ip_stratixiv/eth_10g/ip_stratixiv_eth_10g.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Combine mac_10g and xaui for c_tech_stratixiv
-- Description:
--
@@ -130,9 +129,7 @@ entity ip_stratixiv_eth_10g is
);
end ip_stratixiv_eth_10g;
-
architecture str of ip_stratixiv_eth_10g is
-
-- Enable or disable the conditions that must be ok to release tx_snk_out_arr xon
constant c_check_link_status : boolean := g_direction /= "TX_ONLY";
constant c_check_rx_channelaligned : boolean := g_direction /= "TX_ONLY";
@@ -161,9 +158,7 @@ architecture str of ip_stratixiv_eth_10g is
signal xgmii_tx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
signal xgmii_rx_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
signal xgmii_internal_dc_arr : t_xgmii_dc_arr(g_nof_channels - 1 downto 0); -- 72 bit
-
begin
-
-- Clocks and reset
tx_rst_arr_out <= i_tx_rst_arr_out;
rx_rst_arr_out <= i_rx_rst_arr_out;
@@ -174,7 +169,6 @@ begin
xgmii_tx_ready_arr <= txc_tx_ready_arr;
gen_mac : for I in 0 to g_nof_channels - 1 generate
-
tx_snk_out_arr(I).ready <= mac_snk_out_arr(I).ready; -- pass on MAC cycle accurate backpressure
p_xon_flow_control : process(tx_clk_arr_in)
@@ -283,5 +277,4 @@ begin
mosi_arr => mac_mosi_arr,
miso_arr => mac_miso_arr
);
-
end str;
diff --git a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_complex_mult_rtl.vhd b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_complex_mult_rtl.vhd
index 61095b3caf63cc4c4980fb016adbd4c3ab31e4fb..9224483e08b4557a8db99f3b6b49dd9e8d261511 100644
--- a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_complex_mult_rtl.vhd
+++ b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_complex_mult_rtl.vhd
@@ -68,7 +68,6 @@ entity ip_stratixiv_complex_mult_rtl is
end ip_stratixiv_complex_mult_rtl;
architecture str of ip_stratixiv_complex_mult_rtl is
-
function RESIZE_NUM(s : signed; w : natural) return signed is
begin
-- extend sign bit or keep LS part
@@ -124,9 +123,7 @@ architecture str of ip_stratixiv_complex_mult_rtl is
signal prod_ar_bi : signed(c_prod_w - 1 downto 0);
signal sum_re : signed(c_sum_w - 1 downto 0);
signal sum_im : signed(c_sum_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -189,7 +186,6 @@ begin
bi <= reg_bi;
end generate;
-
------------------------------------------------------------------------------
-- Products
------------------------------------------------------------------------------
@@ -212,7 +208,6 @@ begin
prod_ar_bi <= reg_prod_ar_bi;
end generate;
-
------------------------------------------------------------------------------
-- Sum
------------------------------------------------------------------------------
@@ -223,6 +218,7 @@ begin
gen_re_add : if g_conjugate_b generate
nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) + prod_ai_bi;
end generate;
+
gen_re_sub : if not g_conjugate_b generate
nxt_sum_re <= RESIZE_NUM(prod_ar_br, c_sum_w) - prod_ai_bi;
end generate;
@@ -233,11 +229,11 @@ begin
gen_im_add : if not g_conjugate_b generate
nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) + prod_ar_bi;
end generate;
+
gen_im_sub : if g_conjugate_b generate
nxt_sum_im <= RESIZE_NUM(prod_ai_br, c_sum_w) - prod_ar_bi;
end generate;
-
no_adder_reg : if g_pipeline_adder = 0 generate -- wired
sum_re <= nxt_sum_re;
sum_im <= nxt_sum_im;
@@ -262,5 +258,4 @@ begin
result_re <= std_logic_vector(reg_result_re);
result_im <= std_logic_vector(reg_result_im);
end generate;
-
end architecture;
diff --git a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult.vhd b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult.vhd
index d2ec41bf286d142a595e7f4552318332528e1cda..973b6aa1e3c2213a331bf6a582e8958b03047d8e 100644
--- a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult.vhd
+++ b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult.vhd
@@ -29,9 +29,7 @@ use lpm.lpm_components.all;
);
end ip_stratixiv_mult;
-
architecture str of ip_stratixiv_mult is
-
constant c_pipeline : natural := g_pipeline_input + g_pipeline_product + g_pipeline_output;
-- When g_out_p_w < g_in_a_w+g_in_b_w then the LPM_MULT truncates the LSbits of the product. Therefore
@@ -39,9 +37,7 @@ architecture str of ip_stratixiv_mult is
constant c_prod_w : natural := g_in_a_w + g_in_b_w;
signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
-
begin
-
gen_mult : for I in 0 to g_nof_mult - 1 generate
m : lpm_mult
generic map (
@@ -61,7 +57,6 @@ begin
result => prod((I + 1) * c_prod_w - 1 downto I * c_prod_w)
);
-
out_p <= prod;
---- Truncate MSbits, also for signed (common_pkg.vhd for explanation of RESIZE_SVEC)
-- out_p((I+1)*g_out_p_w-1 DOWNTO I*g_out_p_w) <= RESIZE_SVEC(prod((I+1)*c_prod_w-1 DOWNTO I*c_prod_w), g_out_p_w) WHEN g_representation="SIGNED" ELSE
diff --git a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_add2_rtl.vhd b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_add2_rtl.vhd
index e9dd4892edd04546ea71d505bb0576a271704feb..bacfeb3185dee6667baa1fc6054f6dd722d8b7fd 100644
--- a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_add2_rtl.vhd
+++ b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_add2_rtl.vhd
@@ -24,7 +24,6 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
------------------------------------------------------------------------------
-- Function:
-- . res = a0 * b0 + a1 * b1
@@ -54,9 +53,7 @@ entity ip_stratixiv_mult_add2_rtl is
);
end ip_stratixiv_mult_add2_rtl;
-
architecture str of ip_stratixiv_mult_add2_rtl is
-
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
@@ -92,9 +89,7 @@ architecture str of ip_stratixiv_mult_add2_rtl is
signal prod1 : signed(c_prod_w - 1 downto 0);
signal sum : signed(c_sum_w - 1 downto 0);
signal result : signed(g_res_w - 1 downto 0);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -171,6 +166,7 @@ begin
gen_add : if g_add_sub = "ADD" generate
nxt_sum <= RESIZE_NUM(prod0, c_sum_w) + prod1;
end generate;
+
gen_sub : if g_add_sub = "SUB" generate
nxt_sum <= RESIZE_NUM(prod0, c_sum_w) - prod1;
end generate;
@@ -182,7 +178,6 @@ begin
sum <= reg_sum;
end generate;
-
------------------------------------------------------------------------------
-- Result sum after optional rounding
------------------------------------------------------------------------------
@@ -197,5 +192,4 @@ begin
end generate;
res <= std_logic_vector(result);
-
end str;
diff --git a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_add4_rtl.vhd b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_add4_rtl.vhd
index 969613737d0d059a789578d744745a620ffe42b4..462ff543817d516c43fc956c032339c577f062d9 100644
--- a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_add4_rtl.vhd
+++ b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_add4_rtl.vhd
@@ -53,7 +53,6 @@ entity ip_stratixiv_mult_add4_rtl is
end ip_stratixiv_mult_add4_rtl;
architecture str of ip_stratixiv_mult_add4_rtl is
-
-- Extra output pipelining is only needed when g_pipeline_output > 1
constant c_pipeline_output : natural := sel_a_b(g_pipeline_output > 0, g_pipeline_output - 1, 0);
@@ -108,9 +107,7 @@ architecture str of ip_stratixiv_mult_add4_rtl is
signal sum1 : signed(g_in_a_w + g_in_b_w downto 0);
signal sum : signed(g_in_a_w + g_in_b_w + 1 downto 0);
signal result : signed(res'range);
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -219,6 +216,7 @@ begin
gen_add0 : if g_add_sub0 = "ADD" generate
nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) + prod1;
end generate;
+
gen_sub0 : if g_add_sub0 = "SUB" generate
nxt_sum0 <= RESIZE_NUM(prod0, sum0'length) - prod1;
end generate;
@@ -226,6 +224,7 @@ begin
gen_add1 : if g_add_sub1 = "ADD" generate
nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) + prod3;
end generate;
+
gen_sub1 : if g_add_sub1 = "SUB" generate
nxt_sum1 <= RESIZE_NUM(prod2, sum1'length) - prod3;
end generate;
@@ -240,7 +239,6 @@ begin
sum1 <= reg_sum1;
end generate;
-
------------------------------------------------------------------------------
-- Second sum
------------------------------------------------------------------------------
@@ -249,11 +247,11 @@ begin
gen_add : if g_add_sub = "ADD" generate
sum <= RESIZE_NUM(sum0, sum'length) + sum1;
end generate;
+
gen_sub : if g_add_sub = "SUB" generate
sum <= RESIZE_NUM(sum0, sum'length) - sum1;
end generate;
-
------------------------------------------------------------------------------
-- Result sum after optional rounding
------------------------------------------------------------------------------
@@ -268,5 +266,4 @@ begin
end generate;
res <= std_logic_vector(result);
-
end str;
diff --git a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_rtl.vhd b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_rtl.vhd
index 42a4acbaf07ffb1b8170037a3c643056d0f373fb..0d2c165e3e21c8f1ea33e507be75b1fdb3c52e53 100644
--- a/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_rtl.vhd
+++ b/libraries/technology/ip_stratixiv/mult/ip_stratixiv_mult_rtl.vhd
@@ -45,9 +45,7 @@ use IEEE.numeric_std.all;
);
end ip_stratixiv_mult_rtl;
-
architecture str of ip_stratixiv_mult_rtl is
-
constant c_prod_w : natural := g_in_a_w + g_in_b_w;
-- registers
@@ -67,9 +65,7 @@ architecture str of ip_stratixiv_mult_rtl is
signal inp_b : std_logic_vector(in_b'range);
signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0); -- stage dependent on g_pipeline_product being 0 or 1
signal result : std_logic_vector(out_p'range); -- stage dependent on g_pipeline_output being 0 or 1
-
begin
-
------------------------------------------------------------------------------
-- Registers
------------------------------------------------------------------------------
@@ -140,5 +136,4 @@ begin
end generate;
out_p <= result;
-
end str;
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
index e13bd7757495bdb0e09a098c2af22d3a267dfc66..017f5c0a0319f09a43a40a62c4b5b491ab9ad038 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
@@ -82,7 +82,6 @@ entity tb_ip_stratixiv_phy_xaui is
end entity tb_ip_stratixiv_phy_xaui;
architecture str of tb_ip_stratixiv_phy_xaui is
-
constant c_phy_loopback : boolean := not g_use_xaui_rx_serial_in;
constant c_mm_clk_period : time := 25 ns; -- 40 MHz
@@ -116,9 +115,7 @@ architecture str of tb_ip_stratixiv_phy_xaui is
-- Important status signal: only send user data after you know the receiver's channel_aligned='1'.
signal rx_channelaligned : std_logic;
-
begin
-
tr_clk <= not tr_clk after g_tr_clk_156_period / 2;
tx_clk <= not tx_clk after g_tr_clk_156_period / 2;
mm_clk <= not mm_clk after c_mm_clk_period / 2;
@@ -230,6 +227,4 @@ begin
xaui_rx_serial <= (others => '0');
end if;
end process;
-
end architecture str;
-
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui_ppm.vhd b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui_ppm.vhd
index 20abdd622db100ecf4f281c7d327b6687754ed72..9e2e65a8adc97b3b891fabb543dd962080dd8660 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui_ppm.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui_ppm.vhd
@@ -47,15 +47,12 @@ entity tb_ip_stratixiv_phy_xaui_ppm is
end tb_ip_stratixiv_phy_xaui_ppm;
architecture tb of tb_ip_stratixiv_phy_xaui_ppm is
-
constant tr_clk_156_period : time := 6.4 ns;
constant tr_clk_156_10ppm : time := 64 fs;
signal xaui_tx_serial_0 : std_logic_vector(c_nof_xaui_lanes - 1 downto 0);
signal xaui_tx_serial_1 : std_logic_vector(c_nof_xaui_lanes - 1 downto 0);
-
begin
-
u_tb_ip_stratixiv_phy_xaui_0 : entity work.tb_ip_stratixiv_phy_xaui
generic map (
g_sim_time => g_sim_time,
@@ -79,5 +76,4 @@ begin
xaui_tx_serial_out => xaui_tx_serial_1,
xaui_rx_serial_in => xaui_tx_serial_0
);
-
end tb;
diff --git a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v101.vhd b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v101.vhd
index 718480a2435e10d11ef21175e1a8d069cdb24b2a..5f8e3b1467a997570365527a7998450c5d970131 100644
--- a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v101.vhd
+++ b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v101.vhd
@@ -19,10 +19,8 @@
--
-------------------------------------------------------------------------------
-
-- Purpose : Create one gxb_reconfig module for all ALTGX instances.
-
library ieee, technology_lib;
use ieee.std_logic_1164.all;
use technology_lib.technology_pkg.all;
@@ -41,10 +39,8 @@ entity ip_stratixiv_gxb_reconfig_v101 is
);
end ip_stratixiv_gxb_reconfig_v101;
-
architecture str of ip_stratixiv_gxb_reconfig_v101 is
begin
-
gen_gx_reconfig_4 : if g_nof_gx <= 4 generate
u_gx_reconfig_4 : entity work.ip_stratixiv_gxb_reconfig_v101_4
port map (
@@ -76,4 +72,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v111.vhd b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v111.vhd
index 984a09a5bd4aa9153716ddc492502a5a931e4bf1..29a174453d2f6ab0e850d17e4ff0e13d5f8caf3b 100644
--- a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v111.vhd
+++ b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v111.vhd
@@ -19,10 +19,8 @@
--
-------------------------------------------------------------------------------
-
-- Purpose : Create one gxb_reconfig module for all ALTGX instances.
-
library ieee, technology_lib;
use ieee.std_logic_1164.all;
use technology_lib.technology_pkg.all;
@@ -41,10 +39,8 @@ entity ip_stratixiv_gxb_reconfig_v111 is
);
end ip_stratixiv_gxb_reconfig_v111;
-
architecture str of ip_stratixiv_gxb_reconfig_v111 is
begin
-
gen_gxb_reconfig_4 : if g_nof_gx <= 4 generate
u_gxb_reconfig_4 : entity work.ip_stratixiv_gxb_reconfig_v111_4
port map (
@@ -66,4 +62,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v91.vhd b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v91.vhd
index 8452807c1c31b3e1e3fc80da21aa292eacb5f13d..e89b3a2ad5a6c7045a2e45566120df2a1b1d36b8 100644
--- a/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v91.vhd
+++ b/libraries/technology/ip_stratixiv/transceiver/ip_stratixiv_gxb_reconfig_v91.vhd
@@ -19,7 +19,6 @@
--
-------------------------------------------------------------------------------
-
-- Purpose : Create one gxb_reconfig module for all ALTGX instances.
library ieee;
@@ -39,10 +38,8 @@ entity ip_stratixiv_gxb_reconfig_v91 is
);
end ip_stratixiv_gxb_reconfig_v91;
-
architecture str of ip_stratixiv_gxb_reconfig_v91 is
begin
-
gen_gxb_reconfig_2 : if g_nof_gx = 2 generate
u_gxb_reconfig_2 : entity work.ip_stratixiv_gxb_reconfig_v91_2
port map (
@@ -84,4 +81,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
index d5ee6f496de1086ca0ea56fbe77265fc6a747a04..e39939d794c30f37354857adcf494ab5f51ebd00 100644
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
@@ -37,13 +37,10 @@ use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use common_lib.common_pkg.all;
-
entity tb_ip_stratixiv_tse_sgmii_lvds is
end tb_ip_stratixiv_tse_sgmii_lvds;
-
architecture tb of tb_ip_stratixiv_tse_sgmii_lvds is
-
constant sys_clk_period : time := 10 ns; -- 100 MHz
constant eth_clk_period : time := 8 ns; -- 125 MHz
@@ -405,7 +402,6 @@ architecture tb of tb_ip_stratixiv_tse_sgmii_lvds is
end if;
end proc_rx_packet;
-
-- Clocks and reset
signal tb_end : std_logic := '0';
signal eth_clk : std_logic := '0';
@@ -458,9 +454,7 @@ architecture tb of tb_ip_stratixiv_tse_sgmii_lvds is
signal dbg_mm : t_mm_bus;
signal dbg_ff_tx : t_tse_stream;
signal dbg_ff_rx : t_tse_stream;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -719,5 +713,4 @@ begin
assert false report "Simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd
index 4ce755cacd0125441b2811ba29abe3ba5664d2ba..99eec71a572ded0024b43ee6c1084748ea49fd14 100644
--- a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd
+++ b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc.vhd
@@ -51,7 +51,6 @@ entity ip_ultrascale_fifo_dc is
end ip_ultrascale_fifo_dc;
architecture SYN of ip_ultrascale_fifo_dc is
-
begin
-- xpm_fifo_async: Asynchronous FIFO
-- Xilinx Parameterized Macro, version 2022.1
diff --git a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd
index bb3116ad9880e2968ea4bb9615de0367de2ff988..8da966009927cc15c1ec0bdf6849f7999862a626 100644
--- a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_dc_mixed_widths.vhd
@@ -52,7 +52,6 @@ entity ip_ultrascale_fifo_dc_mixed_widths is
end ip_ultrascale_fifo_dc_mixed_widths;
architecture SYN of ip_ultrascale_fifo_dc_mixed_widths is
-
begin
-- xpm_fifo_async: Asynchronous FIFO
-- Xilinx Parameterized Macro, version 2022.1
@@ -174,5 +173,4 @@ begin
);
-- End of xpm_fifo_async_inst instantiation
-
end SYN;
diff --git a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd
index 5dc90782278f3e6ede7fe1b58cab7aaf0cd58ca1..49e6db1a52ef36d830da26bbc55096cbbe648608 100644
--- a/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd
+++ b/libraries/technology/ip_ultrascale/fifo/ip_ultrascale_fifo_sc.vhd
@@ -49,7 +49,6 @@ entity ip_ultrascale_fifo_sc is
end ip_ultrascale_fifo_sc;
architecture SYN of ip_ultrascale_fifo_sc is
-
begin
-- xpm_fifo_sync: Synchronous FIFO
-- Xilinx Parameterized Macro, version 2022.1
@@ -167,5 +166,4 @@ begin
);
-- End of xpm_fifo_async_inst instantiation
-
end SYN;
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
index 76a9db04b24b503f65b21b886f9e090a0418bceb..2fc9f11faac791db8e62dea699bac0c62fffe226 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_cr_cw.vhd
@@ -49,11 +49,8 @@ entity ip_ultrascale_ram_cr_cw is
);
end ip_ultrascale_ram_cr_cw;
-
architecture SYN of ip_ultrascale_ram_cr_cw is
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_ultrascale_ram_cr_cw : read latency must be 1 (default) or 2" severity FAILURE;
assert g_inferred = false report "ip_ultrascale_ram_crw_crw : cannot infer RAM" severity FAILURE;
@@ -144,6 +141,4 @@ begin
);
-- End of xpm_memory_sdpram_inst instantiation
-
-
end SYN;
diff --git a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
index f1cbab189c4a8ddc704f4de11f81e989ccffb84a..9f9d96612e276b3484ee93e9ef1b0a94883581c1 100644
--- a/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
+++ b/libraries/technology/ip_ultrascale/ram/ip_ultrascale_ram_crw_crw.vhd
@@ -52,11 +52,8 @@ entity ip_ultrascale_ram_crw_crw is
);
end ip_ultrascale_ram_crw_crw;
-
architecture SYN of ip_ultrascale_ram_crw_crw is
-
begin
-
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_ultrascale_ram_crw_crw : read latency must be 1 (default) or 2" severity FAILURE;
assert g_inferred = false report "ip_ultrascale_ram_crw_crw : cannot infer RAM" severity FAILURE;
@@ -180,5 +177,4 @@ begin
);
-- End of xpm_memory_tdpram_inst instantiation
-
end SYN;
diff --git a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
index a9c7b306ee89034b18354037a7d7d563c77e1501..47421d3e5d0aa7645b04034943f9126d892dc5bf 100644
--- a/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tb_tech_jesd204b.vhd
@@ -48,7 +48,6 @@ entity tb_tech_jesd204b is
end tb_tech_jesd204b;
architecture tb of tb_tech_jesd204b is
-
-- FALSE is use mm_clk in JESD IP, TRUE is use rxlink_clk as mm_clk in JESD IP
constant c_sim : boolean := false; -- use FALSE as on HW, to verify jesd204b_rddata
@@ -169,9 +168,7 @@ architecture tb of tb_tech_jesd204b is
signal avs_address : t_slv_8_arr(c_nof_streams_jesd204b - 1 downto 0);
signal jesd204b_disable_arr : std_logic_vector(c_nof_streams_jesd204b - 1 downto 0);
-
begin
-
----------------------------------------------------------------------------
-- System setup
----------------------------------------------------------------------------
@@ -356,7 +353,6 @@ begin
end generate;
-
-----------------------------------------------------------------------------
-- Stimulii
-----------------------------------------------------------------------------
@@ -368,7 +364,6 @@ begin
txlink_rst_n <= '0', '1' after 25500 ns;
pll_locked(0) <= '0', '1' after 1000 ns;
-
-- Create bonding clocks
-- The clock periods and offsets are copied from the JESD TX sample design
-- They are created directly to simplifiy the test bench
@@ -395,7 +390,6 @@ begin
tx_bonding_clocks(1) <= transport bonding_clock_1 after 7490 ps;
tx_bonding_clocks(0) <= transport bonding_clock_0 after 4000 ps;
-
-- clock source process
-- generate the sysref pulses
proc_sysref : process (jesd204b_sampclk, mm_rst)
@@ -532,5 +526,4 @@ begin
proc_common_timeout_failure(200 us, tb_timeout); -- ERROR: end simulation if it fails to end in time
proc_common_stop_simulation(tb_end); -- OK: end simulation
-
end tb;
diff --git a/libraries/technology/jesd204b/tech_jesd204b.vhd b/libraries/technology/jesd204b/tech_jesd204b.vhd
index f65d1271722ed257bc1d4021c08b4657dac66988..391c8cae96844576fb80c13ca83e902e985bbf06 100644
--- a/libraries/technology/jesd204b/tech_jesd204b.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Author : J Hargreaves
-- Purpose: Technology selection wrapper to instantiate
-- JESD204b interface for ADCs and DACs
@@ -91,10 +90,8 @@ entity tech_jesd204b is
);
end tech_jesd204b;
-
architecture str of tech_jesd204b is
begin
-
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
u0 : entity work.tech_jesd204b_arria10_e1sg
generic map(
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
index 5d69fa11528af58995c4b69264a81fd27fb43166..d2b68e47b3cb32c83de835f596e15971b4d17c79 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e1sg.vhd
@@ -69,9 +69,7 @@ entity tech_jesd204b_arria10_e1sg is
);
end tech_jesd204b_arria10_e1sg;
-
architecture str of tech_jesd204b_arria10_e1sg is
-
begin
u_ip_arria10_e1sg_jesd204b : ip_arria10_e1sg_jesd204b
generic map(
@@ -104,5 +102,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
index cea8bc8428d05c9ae7a97d854f89087d2c00b5d5..ba0645b0f0eda0aaf3dafa7cafbf36c3d034635f 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_arria10_e2sg.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose: Wrapper for the Intel Arria 10 e2sg (unb2b, unb2c) tecnology version of the
-- JESD204b interface for ADCs and DACs
-- Description
@@ -70,9 +69,7 @@ entity tech_jesd204b_arria10_e2sg is
);
end tech_jesd204b_arria10_e2sg;
-
architecture str of tech_jesd204b_arria10_e2sg is
-
begin
u_ip_arria10_e2sg_jesd204b : ip_arria10_e2sg_jesd204b
generic map(
@@ -105,5 +102,4 @@ begin
serial_tx_arr => serial_tx_arr,
serial_rx_arr => serial_rx_arr
);
-
end str;
diff --git a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
index 7259f51fe6e071c792fb6a3c28916c071f71ee17..3661f25e565078f9cf693c7d68946687b9285f4a 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_component_pkg.vhd
@@ -30,7 +30,6 @@ use technology_lib.technology_pkg.all;
use dp_lib.dp_stream_pkg.all;
package tech_jesd204b_component_pkg is
-
------------------------------------------------------------------------------
-- ip_arria10_e1sg
------------------------------------------------------------------------------
@@ -128,7 +127,6 @@ package tech_jesd204b_component_pkg is
);
end component;
-
------------------------------------------------------------------------------
-- ip_arria10_e2sg
------------------------------------------------------------------------------
diff --git a/libraries/technology/jesd204b/tech_jesd204b_pkg.vhd b/libraries/technology/jesd204b/tech_jesd204b_pkg.vhd
index 12f1856b5b07a22d0c04840c6c4824d719f725c6..b2df39a9d64be866f18ef2adabb53221be04ee53 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_pkg.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_pkg.vhd
@@ -32,7 +32,6 @@ library IEEE, technology_lib;
use IEEE.std_logic_1164.all;
package tech_jesd204b_pkg is
-
-- Intel ARRIA10 IP MM interface
-- . JESD204B MM has 256 bytes = 64 words, so span_w = 6 would be enough,
-- but using span_w = 8 and span = 256 words is fine too.
@@ -66,7 +65,6 @@ package tech_jesd204b_pkg is
constant tech_jesd204b_field_csr_dev_syncn_w : natural := 1;
constant tech_jesd204b_field_csr_dev_syncn_lo : natural := 0;
constant tech_jesd204b_field_csr_dev_syncn_hi : natural := tech_jesd204b_field_csr_dev_syncn_w - 1 + tech_jesd204b_field_csr_dev_syncn_lo;
-
end tech_jesd204b_pkg;
package body tech_jesd204b_pkg is
diff --git a/libraries/technology/jesd204b/tech_jesd204b_tx.vhd b/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
index 2f124953b16bc3fe6a4294c84041abcf3e76def3..49102c574510dc19a240ba94dece777249f3069d 100644
--- a/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
+++ b/libraries/technology/jesd204b/tech_jesd204b_tx.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Author : E. Kooistra
-- Purpose: Technology selection wrapper to instantiate
-- Provide JESD204b TX_ONLY interface for DAC to provide stimuli for ADC in a
@@ -97,10 +96,8 @@ entity tech_jesd204b_tx is
);
end tech_jesd204b_tx;
-
architecture str of tech_jesd204b_tx is
begin
-
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
u0 : ip_arria10_e1sg_jesd204b_tx
port map(
diff --git a/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd b/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
index 0c7fc0f189760c22a40444f91fb3dbf4d5a3e2b1..bedceebc639f606f19cab9617ec858ceab012e49 100644
--- a/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tb_tb_tech_mac_10g.vhd
@@ -31,17 +31,14 @@ use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
use work.tb_tech_mac_10g_pkg.all;
-
entity tb_tb_tech_mac_10g is
end tb_tb_tech_mac_10g;
-
architecture tb of tb_tb_tech_mac_10g is
constant c_tb_end_vec : std_logic_vector(7 downto 0) := (others => '1');
signal tb_end_vec : std_logic_vector(7 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
begin
-
-- g_technology : NATURAL := c_tech_select_default;
-- g_tb_end : BOOLEAN := TRUE; -- when TRUE then tb_end ends this simulation, else a higher multi-testbench will end the simulation
-- g_no_dut : BOOLEAN := FALSE; -- default FALSE to verify the DUT, else use TRUE to verify the tb itself without the DUT
@@ -63,5 +60,4 @@ begin
report "Multi tb simulation finished." severity FAILURE;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g.vhd
index 1053b125d9c11d9dae8e9be337e9846df153e15f..9e2423ea0d74cba3545d30ae535c96d926e89ba6 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g.vhd
@@ -43,7 +43,6 @@ use technology_lib.technology_select_pkg.all;
use WORK.tech_mac_10g_component_pkg.all;
use WORK.tb_tech_mac_10g_pkg.all;
-
entity tb_tech_mac_10g is
-- Test bench control parameters
generic (
@@ -59,9 +58,7 @@ entity tb_tech_mac_10g is
);
end tb_tech_mac_10g;
-
architecture tb of tb_tech_mac_10g is
-
constant clk_156_period : time := 6.4 ns; -- 156.25 MHz
constant phy_delay : time := 0 ns;
@@ -125,9 +122,7 @@ architecture tb of tb_tech_mac_10g is
signal tx_pkt_cnt : natural := 0;
signal rx_pkt_cnt : natural := 0;
signal rx_toggle : std_logic; -- toggle after every received packet
-
begin
-
clk_156 <= not clk_156 after clk_156_period / 2;
clk_312 <= not clk_312 after clk_156_period / 4;
tx_ref_clk_156 <= clk_156; -- mac_10g tx reference clock
@@ -283,5 +278,4 @@ begin
rx_end => rx_end,
tb_end => tb_end
);
-
end tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_link_connect.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_link_connect.vhd
index d1018af855b8ed256f58968e0e7df5b988e2e35a..3b2e1fb9e07fef611ef780a298f82e127f27edcc 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_link_connect.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_link_connect.vhd
@@ -30,7 +30,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use common_lib.common_interface_layers_pkg.all;
-
entity tb_tech_mac_10g_link_connect is
generic (
g_loopback : boolean := true; -- default TRUE for loopback tx to rx, else use FALSE to connect tx-tx, rx-rx between two tb devices
@@ -57,12 +56,9 @@ entity tb_tech_mac_10g_link_connect is
);
end tb_tech_mac_10g_link_connect;
-
architecture tb of tb_tech_mac_10g_link_connect is
-
signal serial_tx_dly : std_logic;
signal xaui_tx_dly : std_logic_vector(c_nof_xaui_lanes - 1 downto 0);
-
begin
-----------------------------------------------------------------------------
-- XGMII layer link
@@ -104,5 +100,4 @@ begin
xaui_rx <= (others => '0');
end if;
end process;
-
end tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
index 5cea811f837fce026840a4783d2dcf489a1ceb49..9ce4e0458687c4de0ad2b485f51e8880b110bb32 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_pkg.vhd
@@ -34,9 +34,7 @@ use dp_lib.tb_dp_pkg.all;
use technology_lib.technology_pkg.all;
use work.tech_mac_10g_component_pkg.all;
-
package tb_tech_mac_10g_pkg is
-
-- Test bench supported packet data types
constant c_tb_tech_mac_10g_data_type_symbols : natural := 0;
constant c_tb_tech_mac_10g_data_type_counter : natural := 1;
@@ -88,12 +86,9 @@ package tb_tech_mac_10g_pkg is
signal ff_clk : in std_logic;
signal ff_snk_in : in t_dp_sosi;
signal ff_snk_out : out t_dp_siso);
-
end tb_tech_mac_10g_pkg;
-
package body tb_tech_mac_10g_pkg is
-
------------------------------------------------------------------------------
-- LOCAL ITEMS
------------------------------------------------------------------------------
@@ -101,7 +96,6 @@ package body tb_tech_mac_10g_pkg is
constant c_nof_eth_beats : natural := c_network_total_header_64b_eth_nof_words; -- = 3 (2.5), nof words in eth part of the header
constant c_nof_hdr_beats : natural := c_network_total_header_64b_nof_words; -- = 6, nof words in the total header
-
------------------------------------------------------------------------------
-- GLOBAL ITEMS
------------------------------------------------------------------------------
@@ -113,10 +107,10 @@ package body tb_tech_mac_10g_pkg is
when c_tb_tech_mac_10g_data_type_counter => return c_network_total_header_64b_eth_nof_words;
when others => null;
end case;
+
return c_network_total_header_64b_nof_words;
end func_tech_mac_10g_header_size;
-
-- Configure the 10G MAC
procedure proc_tech_mac_10g_setup(constant c_technology : in natural;
constant src_mac : in std_logic_vector(c_network_eth_mac_slv'range);
@@ -141,7 +135,6 @@ package body tb_tech_mac_10g_pkg is
proc_tech_mac_10g_setup(c_technology, src_mac, 0, mm_clk, mm_miso, mm_mosi);
end proc_tech_mac_10g_setup;
-
-- . The src_mac[47:0] = 0x123456789ABC for MAC address 12-34-56-78-9A-BC
procedure proc_tech_mac_10g_setup_stratixiv(constant src_mac : in std_logic_vector(c_network_eth_mac_slv'range);
constant mm_offset : in natural;
@@ -313,7 +306,6 @@ package body tb_tech_mac_10g_pkg is
end if;
end proc_tech_mac_10g_tx_packet;
-
-- Receive packet
-- . Use word aligned payload data, so with padding inserted before the 14 byte header
-- . Packets can be always be received, assume the user application is always ready
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_receiver.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_receiver.vhd
index 4ce2b7b3b979e9d8c5be9d2642629efd34c4644d..d77204f03b0bf812d6317f3f93f9202bbdebc92f 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_receiver.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_receiver.vhd
@@ -30,7 +30,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use WORK.tb_tech_mac_10g_pkg.all;
-
entity tb_tech_mac_10_receiver is
generic (
-- g_data_type = c_tb_tech_mac_10g_data_type_symbols = 0
@@ -47,7 +46,6 @@ entity tb_tech_mac_10_receiver is
);
end tb_tech_mac_10_receiver;
-
architecture tb of tb_tech_mac_10_receiver is
signal i_rx_toggle : std_logic := '0';
begin
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_setup.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_setup.vhd
index 5767012d23f26abbcdbab20c36a6505a62a9aa12..4c807adf5650cb30233eb4fbf9b827383346301c 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_setup.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_setup.vhd
@@ -33,7 +33,6 @@ use technology_lib.technology_select_pkg.all;
use work.tb_tech_mac_10g_pkg.all;
use work.tech_mac_10g_component_pkg.all;
-
entity tb_tech_mac_10g_setup is
generic (
g_technology : natural := c_tech_select_default;
@@ -50,17 +49,13 @@ entity tb_tech_mac_10g_setup is
);
end tb_tech_mac_10g_setup;
-
architecture tb of tb_tech_mac_10g_setup is
-
constant mm_clk_period : time := 20 ns; -- 50 MHz
-- Clocks and reset
signal i_mm_clk : std_logic := '0'; -- memory-mapped bus clock
signal i_mm_rst : std_logic; -- reset synchronous with mm_clk
-
begin
-
mm_clk <= i_mm_clk;
mm_rst <= i_mm_rst;
@@ -88,5 +83,4 @@ begin
mm_init <= '0';
wait;
end process;
-
end tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
index 6a915545671853bf849d0fbb9ebab6fde16a92b2..7563515c0aaa6e6de51933d1c5c1ebe70f4e23b9 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_simulation_end.vhd
@@ -29,7 +29,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
use common_lib.tb_common_pkg.all;
-
entity tb_tech_mac_10g_simulation_end is
generic (
g_tb_end : boolean := true;
@@ -45,7 +44,6 @@ end tb_tech_mac_10g_simulation_end;
architecture tb of tb_tech_mac_10g_simulation_end is
begin
-
p_tb_end : process
begin
tb_end <= '0';
@@ -65,5 +63,4 @@ begin
end if;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_transmitter.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_transmitter.vhd
index f9c51c0fc1a9e6f9c85b253764cd9c366d029bc0..b92e4f7a3b80621a8d7bcaecaf2af7667fbe2077 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_transmitter.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_transmitter.vhd
@@ -43,7 +43,6 @@ use dp_lib.dp_stream_pkg.all;
use WORK.tech_mac_10g_component_pkg.all;
use WORK.tb_tech_mac_10g_pkg.all;
-
entity tb_tech_mac_10g_transmitter is
generic (
-- g_data_type = c_tb_tech_mac_10g_data_type_symbols = 0
@@ -65,9 +64,7 @@ entity tb_tech_mac_10g_transmitter is
);
end tb_tech_mac_10g_transmitter;
-
architecture tb of tb_tech_mac_10g_transmitter is
-
constant c_rl : natural := 1;
constant c_nof_tx_not_valid : natural := 0; -- when > 0 then pull tx valid low for c_nof_tx_not_valid beats during tx
@@ -75,9 +72,7 @@ architecture tb of tb_tech_mac_10g_transmitter is
constant c_nof_pkt2 : natural := g_pkt_length_arr2'length;
signal tx_en : std_logic := '1';
-
begin
-
p_ff_transmitter : process
begin
tx_end <= '0';
@@ -122,5 +117,4 @@ begin
tx_end <= '1';
wait;
end process;
-
end tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd
index a6ef18cc650d874b35cc8adb14de964c07343e32..edddc9a01f74ce2d4a2b6f797e322d5b214889e0 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_at_eop.vhd
@@ -31,7 +31,6 @@ use common_lib.tb_common_pkg.all;
use dp_lib.dp_stream_pkg.all;
use WORK.tb_tech_mac_10g_pkg.all;
-
entity tb_tech_mac_10_verify_rx_at_eop is
generic (
g_no_padding : boolean := false; -- default FALSE to verify the data from MAC that is padded to minimal length, else use TRUE to verify the data of any length
@@ -46,14 +45,11 @@ entity tb_tech_mac_10_verify_rx_at_eop is
end tb_tech_mac_10_verify_rx_at_eop;
architecture tb of tb_tech_mac_10_verify_rx_at_eop is
-
constant c_nof_pkt : natural := g_pkt_length_arr'length;
signal expected_sosi_arr : t_dp_sosi_arr(0 to c_nof_pkt - 1);
signal rx_sosi_reg : t_dp_sosi;
-
begin
-
p_ff_store_tx_at_eop : process(tx_clk)
variable vI : natural := 0;
begin
@@ -89,5 +85,4 @@ begin
end if;
end if;
end process;
-
end tb;
diff --git a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
index 83a647e1d056f155735403aac7540cb021771a71..369325f4767a04c182b070973d09b22ccdbd1711 100644
--- a/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
+++ b/libraries/technology/mac_10g/tb_tech_mac_10g_verify_rx_pkt_cnt.vhd
@@ -23,12 +23,10 @@
-- Description:
-- . Verify that > 0 packets were transmitted and that all were received
-
library IEEE, dp_lib;
use IEEE.std_logic_1164.all;
use dp_lib.dp_stream_pkg.all;
-
entity tb_tech_mac_10g_verify_rx_pkt_cnt is
generic (
g_nof_pkt : natural
@@ -44,14 +42,10 @@ entity tb_tech_mac_10g_verify_rx_pkt_cnt is
);
end tb_tech_mac_10g_verify_rx_pkt_cnt;
-
architecture tb of tb_tech_mac_10g_verify_rx_pkt_cnt is
-
signal i_tx_pkt_cnt : natural := 0;
signal i_rx_pkt_cnt : natural := 0;
-
begin
-
tx_pkt_cnt <= i_tx_pkt_cnt;
rx_pkt_cnt <= i_rx_pkt_cnt;
@@ -76,5 +70,4 @@ begin
wait;
end process;
-
end tb;
diff --git a/libraries/technology/mac_10g/tech_mac_10g.vhd b/libraries/technology/mac_10g/tech_mac_10g.vhd
index 39d9bb0db78ab70f6d3c240db391b9a2e8155460..a7c3f4dd4d43dc03336152a0f9d9d814e75824ee 100644
--- a/libraries/technology/mac_10g/tech_mac_10g.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g.vhd
@@ -20,7 +20,6 @@
--
--------------------------------------------------------------------------------
-
-- Purpose:
-- Description:
-- . Block diagram:
@@ -114,9 +113,7 @@ entity tech_mac_10g is
);
end tech_mac_10g;
-
architecture str of tech_mac_10g is
-
-- Adapt ST ready latency 1 to IP ready latency
constant c_ip_tx_ready_latency : natural := sel_a_b(g_technology = c_tech_stratixiv or g_technology = c_tech_arria10_proto or g_technology = c_tech_arria10_e3sge3 or g_technology = c_tech_arria10_e1sg or g_technology = c_tech_arria10_e2sg, 0, 1);
constant c_ip_rx_ready_latency : natural := sel_a_b(g_technology = c_tech_stratixiv or g_technology = c_tech_arria10_proto or g_technology = c_tech_arria10_e3sge3 or g_technology = c_tech_arria10_e1sg or g_technology = c_tech_arria10_e2sg, 0, 1);
@@ -142,9 +139,7 @@ architecture str of tech_mac_10g is
signal fifo_usedw : std_logic_vector(ceil_log2(3 + c_fifo_size) - 1 downto 0); -- +3 to match dp_latency_fifo usedw width
signal fifo_ful : std_logic;
signal fifo_emp : std_logic;
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : entity work.tech_mac_10g_stratixiv
port map (mm_clk, mm_rst, csr_mosi, csr_miso,
@@ -192,7 +187,6 @@ begin
tx_mac_snk_in_data <= tx_mac_snk_in.data(c_tech_mac_10g_data_w - 1 downto 0);
rx_mac_src_out_data <= rx_mac_src_out.data(c_tech_mac_10g_data_w - 1 downto 0);
-
-----------------------------------------------------------------------------
-- Tx
-----------------------------------------------------------------------------
@@ -220,7 +214,6 @@ begin
tx_remove_snk_in <= tx_snk_in;
end generate;
-
u_tx_dp_latency_adapter : entity dp_lib.dp_latency_adapter
generic map (
g_in_latency => 1,
@@ -235,7 +228,6 @@ begin
src_out => tx_mac_snk_in
);
-
-----------------------------------------------------------------------------
-- Rx
-----------------------------------------------------------------------------
@@ -298,4 +290,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
index dfc7d3ed6a19093f2900007cb59688e27f5f5b57..8f9cb93809e8e94a7d00af9993e61828aa49c2ef 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10.vhd
@@ -60,9 +60,7 @@ entity tech_mac_10g_arria10 is
);
end tech_mac_10g_arria10;
-
architecture str of tech_mac_10g_arria10 is
-
constant c_mac_10g_csr_addr_w : natural := func_tech_mac_10g_csr_addr_w(c_tech_arria10_proto); -- = 13
signal mm_rst_n : std_logic;
@@ -70,9 +68,7 @@ architecture str of tech_mac_10g_arria10 is
signal rx_rst_n : std_logic;
signal avalon_rx_src_out : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
mm_rst_n <= not mm_rst;
tx_rst_n <= not tx_rst;
rx_rst_n <= not rx_rst;
@@ -141,5 +137,4 @@ begin
unidirectional_en => OPEN,
unidirectional_remote_fault_dis => open
);
-
end str;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
index 16e0c62c8e47182ac55e855f48961c4d6cbe0823..f41c69073aef9bcf8da5e9a01f61a7ffc62b4b4b 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e1sg.vhd
@@ -60,9 +60,7 @@ entity tech_mac_10g_arria10_e1sg is
);
end tech_mac_10g_arria10_e1sg;
-
architecture str of tech_mac_10g_arria10_e1sg is
-
constant c_mac_10g_csr_addr_w : natural := func_tech_mac_10g_csr_addr_w(c_tech_arria10_e1sg); -- = 13
signal mm_rst_n : std_logic;
@@ -70,9 +68,7 @@ architecture str of tech_mac_10g_arria10_e1sg is
signal rx_rst_n : std_logic;
signal avalon_rx_src_out : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
mm_rst_n <= not mm_rst;
tx_rst_n <= not tx_rst;
rx_rst_n <= not rx_rst;
@@ -141,5 +137,4 @@ begin
unidirectional_en => OPEN,
unidirectional_remote_fault_dis => open
);
-
end str;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
index 3d3750d4114dc8aa5fbe7715e313e5623bb7eada..9de848b6e5c7319e4f690c9eb126c54f98388199 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e2sg.vhd
@@ -60,9 +60,7 @@ entity tech_mac_10g_arria10_e2sg is
);
end tech_mac_10g_arria10_e2sg;
-
architecture str of tech_mac_10g_arria10_e2sg is
-
constant c_mac_10g_csr_addr_w : natural := func_tech_mac_10g_csr_addr_w(c_tech_arria10_e2sg); -- = 13
signal mm_rst_n : std_logic;
@@ -70,9 +68,7 @@ architecture str of tech_mac_10g_arria10_e2sg is
signal rx_rst_n : std_logic;
signal avalon_rx_src_out : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
mm_rst_n <= not mm_rst;
tx_rst_n <= not tx_rst;
rx_rst_n <= not rx_rst;
@@ -141,5 +137,4 @@ begin
unidirectional_en => OPEN,
unidirectional_remote_fault_dis => open
);
-
end str;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_arria10_e3sge3.vhd b/libraries/technology/mac_10g/tech_mac_10g_arria10_e3sge3.vhd
index a2378fe317913a6778ac58a32f57d104796592e1..90c0dcdbb28ef605f719b395e948d13959899d53 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_arria10_e3sge3.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_arria10_e3sge3.vhd
@@ -60,9 +60,7 @@ entity tech_mac_10g_arria10_e3sge3 is
);
end tech_mac_10g_arria10_e3sge3;
-
architecture str of tech_mac_10g_arria10_e3sge3 is
-
constant c_mac_10g_csr_addr_w : natural := func_tech_mac_10g_csr_addr_w(c_tech_arria10_e3sge3); -- = 13
signal mm_rst_n : std_logic;
@@ -70,9 +68,7 @@ architecture str of tech_mac_10g_arria10_e3sge3 is
signal rx_rst_n : std_logic;
signal avalon_rx_src_out : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
mm_rst_n <= not mm_rst;
tx_rst_n <= not tx_rst;
rx_rst_n <= not rx_rst;
@@ -141,5 +137,4 @@ begin
unidirectional_en => OPEN,
unidirectional_remote_fault_dis => open
);
-
end str;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
index a8559db9228e9f0cd1e4272e1c3657e512b5779c..ecb02ffc505fe2a9b837aa83e3f21d5bbde2c538 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_component_pkg.vhd
@@ -29,7 +29,6 @@ use common_lib.common_interface_layers_pkg.all;
use technology_lib.technology_pkg.all;
package tech_mac_10g_component_pkg is
-
function func_tech_mac_10g_csr_addr_w(c_technology : natural) return natural;
constant c_tech_mac_10g_link_status_w : natural := 2;
@@ -94,7 +93,6 @@ package tech_mac_10g_component_pkg is
);
end component;
-
------------------------------------------------------------------------------
-- ip_arria10
------------------------------------------------------------------------------
@@ -294,7 +292,6 @@ package tech_mac_10g_component_pkg is
end tech_mac_10g_component_pkg;
package body tech_mac_10g_component_pkg is
-
function func_tech_mac_10g_csr_addr_w(c_technology : natural) return natural is
variable v_csr_addr_w : natural;
begin
@@ -306,6 +303,7 @@ package body tech_mac_10g_component_pkg is
when c_tech_arria10_e2sg => v_csr_addr_w := 13; -- 13 with INSERT_CSR_ADAPTOR=1 in ip_arria10_e1sg_mac_10g.qsys, 10 without
when others => v_csr_addr_w := 13; -- default to c_tech_stratixiv
end case;
+
return v_csr_addr_w;
end func_tech_mac_10g_csr_addr_w;
diff --git a/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd b/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd
index 13c1c420ce731c0d048a25d341c6124b1c0b671c..5d3e9f7833ab315fdb6b852841713ab4c359979e 100644
--- a/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd
+++ b/libraries/technology/mac_10g/tech_mac_10g_stratixiv.vhd
@@ -58,17 +58,13 @@ entity tech_mac_10g_stratixiv is
);
end tech_mac_10g_stratixiv;
-
architecture str of tech_mac_10g_stratixiv is
-
constant c_mac_10g_csr_addr_w : natural := func_tech_mac_10g_csr_addr_w(c_tech_stratixiv); -- = 13
signal mm_rst_n : std_logic;
signal tx_rst_n : std_logic;
signal rx_rst_n : std_logic;
-
begin
-
mm_rst_n <= not mm_rst;
tx_rst_n <= not tx_rst;
rx_rst_n <= not rx_rst;
@@ -124,5 +120,4 @@ begin
link_fault_status_xgmii_rx_data => xgmii_link_status -- 0=ok, 1=local fault, 2=remote fault
);
-
end str;
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index 15a6bcc7e438575ffc4ff42ee88c3f37e006fcc2..a2de0b573e79790ebdd1d71961f46a410dd4a776 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -25,7 +25,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_memory_component_pkg is
-
-----------------------------------------------------------------------------
-- ip_stratixiv
-----------------------------------------------------------------------------
@@ -139,7 +138,6 @@ package tech_memory_component_pkg is
);
end component;
-
-----------------------------------------------------------------------------
-- ip_arria10
-----------------------------------------------------------------------------
diff --git a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
index 6028d8a490ef914dc5561a0d4d50bff1a2f9ded4..2fd68899ece51f43682353bea2de033a4cc93344 100644
--- a/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_cr_cw.vhd
@@ -58,7 +58,6 @@ end tech_memory_ram_cr_cw;
architecture str of tech_memory_ram_cr_cw is
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_ram_cr_cw
generic map (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index defe84f9eed8af1ca9a469211de17818d59f84b6..2707c1f2c1eaafb54bac3bb7dcc3ffb6c1c4c016 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -61,11 +61,8 @@ entity tech_memory_ram_crw_crw is
);
end tech_memory_ram_crw_crw;
-
architecture str of tech_memory_ram_crw_crw is
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_ram_crw_crw
generic map (g_adr_w, g_dat_w, g_nof_words, g_rd_latency, g_init_file)
@@ -102,5 +99,4 @@ begin
port map (address_a, address_b, clock_a, clock_b, data_a, data_b, wren_a, wren_b, q_a, q_b);
end generate;
-
end architecture;
diff --git a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
index ae952e2d3014d1990c49cbde3d76796665128069..e226457910ea323fc3019f5c79ccf17244913736 100644
--- a/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crwk_crw.vhd
@@ -63,10 +63,8 @@ entity tech_memory_ram_crwk_crw is -- support different port data widths and co
);
end tech_memory_ram_crwk_crw;
-
architecture str of tech_memory_ram_crwk_crw is
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_ram_crwk_crw
generic map (g_adr_a_w, g_dat_a_w, g_adr_b_w, g_dat_b_w, g_nof_words_a, g_nof_words_b, g_rd_latency, g_init_file)
diff --git a/libraries/technology/memory/tech_memory_ram_r_w.vhd b/libraries/technology/memory/tech_memory_ram_r_w.vhd
index 57be4c4db67a976921a28223cdf850240db09301..7bf868a390b42ebb1a0cb8f91b030a0c90e3a7b1 100644
--- a/libraries/technology/memory/tech_memory_ram_r_w.vhd
+++ b/libraries/technology/memory/tech_memory_ram_r_w.vhd
@@ -51,10 +51,8 @@ entity tech_memory_ram_r_w is
);
end tech_memory_ram_r_w;
-
architecture str of tech_memory_ram_r_w is
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_ram_r_w
generic map (g_adr_w, g_dat_w, g_nof_words, g_init_file)
diff --git a/libraries/technology/memory/tech_memory_rom_r.vhd b/libraries/technology/memory/tech_memory_rom_r.vhd
index c66f651d84ad1e0d6aa6a5c249a4de71faa69e04..792942f7619813a6d5e3d35c6f38ca7c9ebcd02d 100644
--- a/libraries/technology/memory/tech_memory_rom_r.vhd
+++ b/libraries/technology/memory/tech_memory_rom_r.vhd
@@ -50,7 +50,6 @@ end tech_memory_rom_r;
architecture str of tech_memory_rom_r is
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_rom_r
generic map (g_adr_w, g_dat_w, g_nof_words, g_init_file)
diff --git a/libraries/technology/mult/tech_complex_mult.vhd b/libraries/technology/mult/tech_complex_mult.vhd
index d895f83f36e86d489f1fa7289b9f78d49ab35ef5..d11e36bb05a80b51423d6641bf2b06f5d2859735 100644
--- a/libraries/technology/mult/tech_complex_mult.vhd
+++ b/libraries/technology/mult/tech_complex_mult.vhd
@@ -98,7 +98,6 @@ entity tech_complex_mult is
end tech_complex_mult;
architecture str of tech_complex_mult is
-
constant c_dsp_dat_w : natural := sel_a_b(g_in_a_w <= c_dsp_mult_18_w and g_in_b_w <= c_dsp_mult_18_w, c_dsp_mult_18_w, c_dsp_mult_27_w); -- g_in_a_w = g_in_b_w
constant c_dsp_prod_w : natural := 2 * c_dsp_dat_w;
@@ -108,9 +107,7 @@ architecture str of tech_complex_mult is
signal bi : std_logic_vector(c_dsp_dat_w - 1 downto 0);
signal mult_re : std_logic_vector(c_dsp_prod_w - 1 downto 0);
signal mult_im : std_logic_vector(c_dsp_prod_w - 1 downto 0);
-
begin
-
-----------------------------------------------------------------------------
-- IP variants for <= 18 bit
-----------------------------------------------------------------------------
@@ -215,7 +212,6 @@ begin
result_im <= RESIZE_SVEC(mult_im, g_out_p_w);
end generate;
-
-----------------------------------------------------------------------------
-- IP variants for > 18 bit and <= 27 bit
-----------------------------------------------------------------------------
@@ -302,6 +298,7 @@ begin
gen_ip_arria10_rtl : if g_variant = "RTL" and (g_technology = c_tech_arria10_proto or
g_technology = c_tech_arria10_e3sge3 or
g_technology = c_tech_arria10_e1sg or
+
g_technology = c_tech_arria10_e2sg) generate
u0 : ip_arria10_complex_mult_rtl
generic map (
@@ -331,6 +328,7 @@ begin
gen_ip_arria10_rtl_canonical : if g_variant = "RTL_C" and (g_technology = c_tech_arria10_proto or
g_technology = c_tech_arria10_e3sge3 or
g_technology = c_tech_arria10_e1sg or
+
g_technology = c_tech_arria10_e2sg) generate
-- support g_conjugate_b
bi <= in_bi when g_conjugate_b = false else TO_SVEC(-TO_SINT(in_bi), g_in_b_w);
@@ -359,4 +357,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/mult/tech_mult.vhd b/libraries/technology/mult/tech_mult.vhd
index 17d31e2435ee53f382c17437be2a10e625b60688..02302d50192a9aa4cdf39b42eb9214238e82a9e8 100644
--- a/libraries/technology/mult/tech_mult.vhd
+++ b/libraries/technology/mult/tech_mult.vhd
@@ -30,7 +30,6 @@ use work.tech_mult_component_pkg.all;
library ip_stratixiv_mult_lib;
library ip_arria10_mult_lib;
-
entity tech_mult is
generic (
g_technology : natural := c_tech_select_default;
@@ -55,15 +54,12 @@ entity tech_mult is
end tech_mult;
architecture str of tech_mult is
-
-- When g_out_p_w < g_in_a_w+g_in_b_w then the LPM_MULT truncates the LSbits of the product. Therefore
-- define c_prod_w to be able to let common_mult truncate the LSBits of the product.
constant c_prod_w : natural := g_in_a_w + g_in_b_w;
signal prod : std_logic_vector(g_nof_mult * c_prod_w - 1 downto 0);
-
begin
-
gen_ip_stratixiv_ip : if (g_technology = c_tech_stratixiv and g_variant = "IP") generate
u0 : ip_stratixiv_mult
generic map(
@@ -157,4 +153,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/mult/tech_mult_add2.vhd b/libraries/technology/mult/tech_mult_add2.vhd
index aaa54dd91a661ece197427f61ba374a29965b27e..59504b2139122a8bcd6ea3fc182460d1b59b3df7 100644
--- a/libraries/technology/mult/tech_mult_add2.vhd
+++ b/libraries/technology/mult/tech_mult_add2.vhd
@@ -57,9 +57,7 @@ entity tech_mult_add2 is
end tech_mult_add2;
architecture str of tech_mult_add2 is
-
begin
-
gen_ip_stratixiv_rtl : if (g_technology = c_tech_stratixiv and g_variant = "RTL") generate
u0 : ip_stratixiv_mult_add2_rtl
generic map(
@@ -133,4 +131,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/mult/tech_mult_add4.vhd b/libraries/technology/mult/tech_mult_add4.vhd
index eff6254e42c1eed9391bac0c8e593699f25759c3..bc2e5da25b59eb3e1acbb873bf9617eecea20c3b 100644
--- a/libraries/technology/mult/tech_mult_add4.vhd
+++ b/libraries/technology/mult/tech_mult_add4.vhd
@@ -60,9 +60,7 @@ entity tech_mult_add4 is
end tech_mult_add4;
architecture str of tech_mult_add4 is
-
begin
-
gen_ip_stratixiv_rtl : if (g_technology = c_tech_stratixiv and g_variant = "RTL") generate
u0 : ip_stratixiv_mult_add4_rtl
generic map(
@@ -168,4 +166,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index 448746885e969fe68c1f07ec7c9db6692976a0c7..8d9668897ba9d69109eff6079f39ab095adb39d1 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -25,7 +25,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_mult_component_pkg is
-
-----------------------------------------------------------------------------
-- Stratix IV components
-----------------------------------------------------------------------------
@@ -176,7 +175,6 @@ package tech_mult_component_pkg is
);
end component;
-
component ip_arria10_complex_mult_rtl is
generic (
g_in_a_w : positive := 18;
@@ -266,7 +264,6 @@ package tech_mult_component_pkg is
);
end component;
-
-----------------------------------------------------------------------------
-- Arria 10 e3sge3 components
-----------------------------------------------------------------------------
diff --git a/libraries/technology/mult/tech_mult_pkg.vhd b/libraries/technology/mult/tech_mult_pkg.vhd
index d1721a41ffa3a486f7bf20d7d91efe3e4591e3c3..093a503af280e3ae167d8312b6ce3315a3cecc41 100644
--- a/libraries/technology/mult/tech_mult_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use technology_lib.technology_pkg.all;
package tech_mult_pkg is
-
type t_c_tech_mult_variant is record
-- PHY variant within a technology
name : string(1 to 3); -- = "RTL" or " IP"
diff --git a/libraries/technology/pll/tech_pll_clk125.vhd b/libraries/technology/pll/tech_pll_clk125.vhd
index 53b683d3ef4b9ffc3f42c979082a0a0c392ae0b4..674c4fdd68de58f68a167591b7cffd1aea9db052 100644
--- a/libraries/technology/pll/tech_pll_clk125.vhd
+++ b/libraries/technology/pll/tech_pll_clk125.vhd
@@ -47,9 +47,7 @@ entity tech_pll_clk125 is
end tech_pll_clk125;
architecture str of tech_pll_clk125 is
-
begin
-
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_pll_clk125
port map (
diff --git a/libraries/technology/pll/tech_pll_clk200.vhd b/libraries/technology/pll/tech_pll_clk200.vhd
index 9c12384460c6dd3a2cf5abcb4a15bf5567b96bf5..015ec5d6067375c3741d4f0fefe0cf501101dbf9 100644
--- a/libraries/technology/pll/tech_pll_clk200.vhd
+++ b/libraries/technology/pll/tech_pll_clk200.vhd
@@ -50,9 +50,7 @@ entity tech_pll_clk200 is
end tech_pll_clk200;
architecture str of tech_pll_clk200 is
-
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_pll_clk200
generic map (g_operation_mode, g_clk0_phase_shift, g_clk1_phase_shift)
diff --git a/libraries/technology/pll/tech_pll_clk200_p6.vhd b/libraries/technology/pll/tech_pll_clk200_p6.vhd
index c61ee97b77da1baa6c6b0e14fe1ef83542ea75a6..cecd550a403c1d215423f7a04d62419f963f637c 100644
--- a/libraries/technology/pll/tech_pll_clk200_p6.vhd
+++ b/libraries/technology/pll/tech_pll_clk200_p6.vhd
@@ -70,10 +70,8 @@ entity tech_pll_clk200_p6 is
);
end tech_pll_clk200_p6;
-
architecture str of tech_pll_clk200_p6 is
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : ip_stratixiv_pll_clk200_p6
generic map (g_pll_type, g_operation_mode,
diff --git a/libraries/technology/pll/tech_pll_clk25.vhd b/libraries/technology/pll/tech_pll_clk25.vhd
index cb34290234201a16b449296e7f146131c6c074a0..1bc410bbd632144ff2e6b63f950ad358f51ae234 100644
--- a/libraries/technology/pll/tech_pll_clk25.vhd
+++ b/libraries/technology/pll/tech_pll_clk25.vhd
@@ -49,9 +49,7 @@ entity tech_pll_clk25 is
end tech_pll_clk25;
architecture str of tech_pll_clk25 is
-
begin
-
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_pll_clk25
port map (
diff --git a/libraries/technology/pll/tech_pll_component_pkg.vhd b/libraries/technology/pll/tech_pll_component_pkg.vhd
index 9ed013940779cf1d17543110f908ebb648f2b28a..7cbbb3c3b45eb944e29202d73253f969ea5780e8 100644
--- a/libraries/technology/pll/tech_pll_component_pkg.vhd
+++ b/libraries/technology/pll/tech_pll_component_pkg.vhd
@@ -25,7 +25,6 @@ library IEEE;
use IEEE.std_logic_1164.all;
package tech_pll_component_pkg is
-
-- Choose multiple of 16 fs to avoid truncation by simulator
constant tech_pll_clk_644_period : time := 1551520 fs; -- = 1.551520 ns ~= 644.53125 MHz
constant tech_pll_clk_156_period : time := (tech_pll_clk_644_period * 33) / 8; -- = 6.400020 ns ~= 156.25 MHz
@@ -176,7 +175,6 @@ package tech_pll_component_pkg is
-- );
-- END COMPONENT;
-
-----------------------------------------------------------------------------
-- ip_arria10_e3sge3
-----------------------------------------------------------------------------
@@ -337,4 +335,3 @@ package tech_pll_component_pkg is
end component;
end tech_pll_component_pkg;
-
diff --git a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
index 6635385aba4b0e406dbe48e829c14e2bbd15f94a..148e7f171517c3f1325b04656323faeb02925aaa 100644
--- a/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
+++ b/libraries/technology/pll/tech_pll_xgmii_mac_clocks.vhd
@@ -61,15 +61,12 @@ entity tech_pll_xgmii_mac_clocks is
end tech_pll_xgmii_mac_clocks;
architecture str of tech_pll_xgmii_mac_clocks is
-
signal pll_locked : std_logic;
signal pll_locked_n : std_logic;
signal i_clk_156 : std_logic;
signal i_clk_312 : std_logic;
-
begin
-
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_pll_xgmii_mac_clocks
port map (
@@ -145,5 +142,4 @@ begin
clk => i_clk_312,
out_rst => rst_312
);
-
end architecture;
diff --git a/libraries/technology/technology_pkg.vhd b/libraries/technology/technology_pkg.vhd
index f6b5147a78223d6c5d26bd1043c0940c39b57dc1..5573eda84677695ae1ec8d0a8f5457cddae99ce9 100644
--- a/libraries/technology/technology_pkg.vhd
+++ b/libraries/technology/technology_pkg.vhd
@@ -38,7 +38,6 @@ use IEEE.std_logic_1164.all;
use IEEE.math_real.all;
package technology_pkg is
-
-- Technology identifiers
constant c_tech_inferred : integer := 0;
constant c_tech_virtex4 : integer := 1; -- e.g. used on RSP3 for Lofar
@@ -62,11 +61,9 @@ package technology_pkg is
function tech_ceil_div(n, d : natural) return natural; -- tech_ceil_div = n/d + (n MOD d)/=0
function tech_nat_to_mbps_str( n : in natural ) return string;
-
end technology_pkg;
package body technology_pkg is
-
function tech_sel_a_b(sel : boolean; a, b : string) return string is
begin
if sel = true then return a; else return b; end if;
diff --git a/libraries/technology/technology_select_pkg.vhd b/libraries/technology/technology_select_pkg.vhd
index 1c44674e5695a8649b2870aa94c0143917fbb206..4b17cd6cfbea493100a22a2339e90f4a2b0066c3 100644
--- a/libraries/technology/technology_select_pkg.vhd
+++ b/libraries/technology/technology_select_pkg.vhd
@@ -29,7 +29,5 @@ use IEEE.std_logic_1164.all;
use work.technology_pkg.all;
package technology_select_pkg is
-
constant c_tech_select_default : integer := c_tech_stratixiv;
-
end technology_select_pkg;
diff --git a/libraries/technology/technology_select_pkg_unb1.vhd b/libraries/technology/technology_select_pkg_unb1.vhd
index 1c44674e5695a8649b2870aa94c0143917fbb206..4b17cd6cfbea493100a22a2339e90f4a2b0066c3 100644
--- a/libraries/technology/technology_select_pkg_unb1.vhd
+++ b/libraries/technology/technology_select_pkg_unb1.vhd
@@ -29,7 +29,5 @@ use IEEE.std_logic_1164.all;
use work.technology_pkg.all;
package technology_select_pkg is
-
constant c_tech_select_default : integer := c_tech_stratixiv;
-
end technology_select_pkg;
diff --git a/libraries/technology/technology_select_pkg_unb2b.vhd b/libraries/technology/technology_select_pkg_unb2b.vhd
index 713431b756f6a8831b3ad8c8e8cb9106ee93d71d..c9e1cf9be5031733ac23ced9a6c5adcf79cc9be3 100644
--- a/libraries/technology/technology_select_pkg_unb2b.vhd
+++ b/libraries/technology/technology_select_pkg_unb2b.vhd
@@ -29,7 +29,5 @@ use IEEE.std_logic_1164.all;
use work.technology_pkg.all;
package technology_select_pkg is
-
constant c_tech_select_default : integer := c_tech_arria10_e1sg;
-
end technology_select_pkg;
diff --git a/libraries/technology/technology_select_pkg_unb2c.vhd b/libraries/technology/technology_select_pkg_unb2c.vhd
index f03ff136618973412b3c397a5fa5c80494c8a21e..9873490dede65b2028cea4efed1398da3a074946 100644
--- a/libraries/technology/technology_select_pkg_unb2c.vhd
+++ b/libraries/technology/technology_select_pkg_unb2c.vhd
@@ -29,7 +29,5 @@ use IEEE.std_logic_1164.all;
use work.technology_pkg.all;
package technology_select_pkg is
-
constant c_tech_select_default : integer := c_tech_arria10_e2sg;
-
end technology_select_pkg;
diff --git a/libraries/technology/transceiver/sim_transceiver_deserializer.vhd b/libraries/technology/transceiver/sim_transceiver_deserializer.vhd
index ad928b3a803833e3d742d03b64455b4c062aba87..b266cf3a13409b579c87466020a9c20e626a78ae 100644
--- a/libraries/technology/transceiver/sim_transceiver_deserializer.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_deserializer.vhd
@@ -28,7 +28,6 @@
-- See sim_transceiver_serializer.vhd
-- Remarks:
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -51,17 +50,12 @@ entity sim_transceiver_deserializer is
rx_serial_in : in std_logic
);
-
end sim_transceiver_deserializer;
-
architecture beh of sim_transceiver_deserializer is
-
constant c_line_clk_period : time := g_tr_clk_period * 8 / 10 / g_data_w;
constant c_nof_bytes_per_data : natural := g_data_w / c_byte_w;
-
begin
-
p_deserialize: process
variable v_rx_out_data : std_logic_vector(g_data_w - 1 downto 0);
variable v_rx_out_ctrl : std_logic_vector(g_data_w / c_byte_w - 1 downto 0);
@@ -112,7 +106,5 @@ begin
rx_out_sop <= v_rx_out_sop;
rx_out_eop <= v_rx_out_eop;
end loop;
-
end process;
-
end beh;
diff --git a/libraries/technology/transceiver/sim_transceiver_gx.vhd b/libraries/technology/transceiver/sim_transceiver_gx.vhd
index dc5318bcbb72474f43371b63934faae946f9c220..3b3671516dd856d69601e1411894773f1f759e4d 100644
--- a/libraries/technology/transceiver/sim_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_gx.vhd
@@ -86,11 +86,9 @@ entity sim_transceiver_gx is
rx_datain : in std_logic_vector(g_nof_gx - 1 downto 0);
tx_dataout : out std_logic_vector(g_nof_gx - 1 downto 0)
);
-
end sim_transceiver_gx;
architecture str of sim_transceiver_gx is
-
constant c_data_clk_period : time := 1 us * g_data_w * 10 / 8 / g_mbps;
constant c_tr_clk_period : time := 1 ns; -- run the GX model somewhat faster to support shorter tr_clk_period
@@ -113,9 +111,7 @@ architecture str of sim_transceiver_gx is
signal tr_end : std_logic := '0'; -- local detect whether the tr_clk has stopped by continuosly checking the toggling
signal sim_end : std_logic := '0'; -- in simulation stop internal clocks when tb_end='1' or tr_end='1' to support 'run -all'
-
begin
-
u_areset_tr_rst : entity common_lib.common_areset
generic map(
g_rst_level => '1'
@@ -235,8 +231,5 @@ begin
rx_sosi_arr(i).valid <= andv(rx_out_ctrl(i));
rx_sosi_arr(i).sop <= andv(rx_out_sop(i));
rx_sosi_arr(i).eop <= andv(rx_out_eop(i));
-
end generate;
-
end str;
-
diff --git a/libraries/technology/transceiver/sim_transceiver_serializer.vhd b/libraries/technology/transceiver/sim_transceiver_serializer.vhd
index 89e8a23d234d0b362ef0d4fb3efa17f539b3e4ed..16fe4c32c1c413dcc60064e9ea03b48dddc55abd 100644
--- a/libraries/technology/transceiver/sim_transceiver_serializer.vhd
+++ b/libraries/technology/transceiver/sim_transceiver_serializer.vhd
@@ -61,7 +61,6 @@
-- . The number of line clock cycles to transmit one data word fits within 1
-- tr_clk period. After every data word the data is realigned to the tr_clk.
-
library IEEE, common_lib;
use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
@@ -84,19 +83,14 @@ entity sim_transceiver_serializer is
tx_serial_out : out std_logic
);
-
end sim_transceiver_serializer;
-
architecture beh of sim_transceiver_serializer is
-
constant c_line_clk_period : time := g_tr_clk_period * 8 / 10 / g_data_w;
constant c_tr_clk_period_sim : time := c_line_clk_period * g_data_w * 10 / 8;
constant c_nof_bytes_per_data : natural := g_data_w / c_byte_w;
-
begin
-
p_serialize: process
variable v_tx_in_data : std_logic_vector(g_data_w - 1 downto 0);
variable v_tx_in_ctrl : std_logic_vector(g_data_w / c_byte_w - 1 downto 0);
@@ -141,9 +135,6 @@ begin
v_tx_in_ctrl := tx_in_ctrl;
v_tx_in_sop := tx_in_sop;
v_tx_in_eop := tx_in_eop;
-
end loop;
-
end process;
-
end beh;
diff --git a/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd b/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd
index ff3df14d99b6318c76e8a09c5afc75732ae9a4a8..1b3a3e3b583c40ab7fd0323d342bea869f343ef8 100644
--- a/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd
+++ b/libraries/technology/transceiver/tb_sim_transceiver_serdes.vhd
@@ -42,7 +42,6 @@ entity tb_sim_transceiver_serdes is
end entity tb_sim_transceiver_serdes;
architecture tb of tb_sim_transceiver_serdes is
-
constant c_data_w : natural := 32;
constant c_tr_clk_period : time := 6.4 ns; -- 156.25 MHz
@@ -67,9 +66,7 @@ architecture tb of tb_sim_transceiver_serdes is
signal prev_rx_out_data : std_logic_vector(c_data_w - 1 downto 0);
signal verify_en : std_logic := '0';
signal rd_ready : std_logic := '1';
-
begin
-
p_tb_end : process
begin
wait for c_tr_clk_period * 300;
@@ -145,5 +142,4 @@ begin
-- Verify dut output incrementing data
proc_common_verify_data(1, tr_clk, verify_en, rd_ready, rx_out_val, rx_out_data, prev_rx_out_data);
-
end tb;
diff --git a/libraries/technology/transceiver/tech_transceiver_arria10_1.vhd b/libraries/technology/transceiver/tech_transceiver_arria10_1.vhd
index e1c6a70ff2c6fec0d134d1c381bebda0b1632e75..ea176526eec894a70be3b258063ad0df9d5a58ce 100644
--- a/libraries/technology/transceiver/tech_transceiver_arria10_1.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_arria10_1.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-
entity tech_transceiver_arria10_1 is
generic (
g_nof_channels : natural := 1
@@ -45,9 +44,7 @@ entity tech_transceiver_arria10_1 is
);
end tech_transceiver_arria10_1;
-
architecture str of tech_transceiver_arria10_1 is
-
component transceiver_phy_1 is
port (
tx_analogreset : in std_logic_vector(g_nof_channels - 1 downto 0) := (others => 'X');
@@ -123,7 +120,6 @@ architecture str of tech_transceiver_arria10_1 is
);
end component pll_xgmii_mac_clocks;
-
-- signals for the transceivers
signal tx_data_valid : std_logic_vector(g_nof_channels - 1 downto 0) := (others => '1');
signal tx_clk : std_logic_vector(g_nof_channels - 1 downto 0);
@@ -148,10 +144,7 @@ architecture str of tech_transceiver_arria10_1 is
signal rx_pma_div_clkout : std_logic_vector(g_nof_channels - 1 downto 0);
signal clk_156_internal : std_logic_vector(g_nof_channels - 1 downto 0);
signal clk_312_internal : std_logic_vector(g_nof_channels - 1 downto 0);
-
begin
-
-
clk_156_arr <= clk_156_internal;
clk_312_arr <= clk_312_internal;
@@ -226,8 +219,6 @@ begin
outclk1 => clk_312_internal(0) -- outclk1.clk
);
-
tx_serial_clk <= (others => mcgb_serial_clk);
txpll_cal_busy <= tx_cal_busy when pll_cal_busy = '0' else (others => '1');
-
end;
diff --git a/libraries/technology/transceiver/tech_transceiver_arria10_48.vhd b/libraries/technology/transceiver/tech_transceiver_arria10_48.vhd
index c60b893764c52d4d73d89df37760cf3c7625b8e8..4303a17c1b1e7b2be48340e2389d85b8842f1234 100644
--- a/libraries/technology/transceiver/tech_transceiver_arria10_48.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_arria10_48.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-
entity tech_transceiver_arria10_48 is
generic (
g_nof_channels : natural := 48
@@ -45,9 +44,7 @@ entity tech_transceiver_arria10_48 is
);
end tech_transceiver_arria10_48;
-
architecture str of tech_transceiver_arria10_48 is
-
component transceiver_phy_48 is
port (
tx_analogreset : in std_logic_vector(47 downto 0) := (others => 'X');
@@ -151,10 +148,7 @@ architecture str of tech_transceiver_arria10_48 is
signal clk_312_internal : std_logic_vector(g_nof_channels - 1 downto 0);
signal clk_156 : std_logic;
signal clk_312 : std_logic;
-
begin
-
-
transceiver_phy : transceiver_phy_48
port map (
tx_analogreset => tx_analogreset,
@@ -235,6 +229,4 @@ begin
clk_312_internal <= (others => clk_312);
clk_156_arr <= clk_156_internal;
clk_312_arr <= clk_312_internal;
-
-
end;
diff --git a/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd b/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd
index 184d46bb4977c40b852d6fd40a32a8d57d1ff2fe..3508161b1cc4da72859a16f8095700bcbaf7ac8c 100644
--- a/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_component_pkg.vhd
@@ -26,7 +26,6 @@ use IEEE.std_logic_1164.all;
use technology_lib.technology_pkg.all;
package tech_transceiver_component_pkg is
-
------------------------------------------------------------------------------
-- ip_stratixiv
------------------------------------------------------------------------------
@@ -206,10 +205,8 @@ package tech_transceiver_component_pkg is
);
end component;
-
------------------------------------------------------------------------------
-- ip_arria10
------------------------------------------------------------------------------
-
end tech_transceiver_component_pkg;
diff --git a/libraries/technology/transceiver/tech_transceiver_gx.vhd b/libraries/technology/transceiver/tech_transceiver_gx.vhd
index 7396076ec176e2b7a8eee191f3926d73ef3ce560..88b4ca2fd7e6ce603dbfff5dcfcdde27dcf56e15 100644
--- a/libraries/technology/transceiver/tech_transceiver_gx.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_gx.vhd
@@ -63,12 +63,10 @@ entity tech_transceiver_gx is
rx_state : out std_logic_vector(2 * g_nof_gx - 1 downto 0);
rx_align_en : in std_logic_vector(g_nof_gx - 1 downto 0)
);
-
end tech_transceiver_gx;
architecture str of tech_transceiver_gx is
begin
-
gen_ip_stratixiv : if g_technology = c_tech_stratixiv generate
u0 : entity work.tech_transceiver_gx_stratix_iv
generic map (g_data_w, g_nof_gx, g_mbps, g_sim, g_tx, g_rx)
@@ -76,4 +74,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
index ef094f89ab6ef3f74998121cbff58559c85c71ec..4bf74473d82e6a6d490b5aed12bd1e689cfdddfb 100644
--- a/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_gx_stratixiv.vhd
@@ -63,11 +63,9 @@ entity tech_transceiver_gx_stratix_iv is
rx_state : out std_logic_vector(2 * g_nof_gx - 1 downto 0);
rx_align_en : in std_logic_vector(g_nof_gx - 1 downto 0)
);
-
end tech_transceiver_gx_stratix_iv;
architecture str of tech_transceiver_gx_stratix_iv is
-
constant c_align_pattern_32 : std_logic_vector := x"0000BC1C"; -- Change in megafunction first. BC is std. comma symbol (K.28.5).
constant c_inval_pattern_32 : std_logic_vector := x"3C3C3C3C"; -- comma symbol K.28.1 (decoded as 3C) is used as invalid data indicator.
@@ -122,9 +120,7 @@ architecture str of tech_transceiver_gx_stratix_iv is
signal rxc_rx_align_en : std_logic_vector(g_nof_gx - 1 downto 0); -- edge sensitive
signal rxc_rx_aligned : std_logic_vector(g_nof_gx - 1 downto 0) := (others => '1');
-
begin
-
------------------------------------------------------------------------------
-- ALTGX Megafunction
------------------------------------------------------------------------------
@@ -334,7 +330,6 @@ begin
end generate;
end generate;
-
------------------------------------------------------------------------------
-- Reset and alignment
------------------------------------------------------------------------------
@@ -350,7 +345,6 @@ begin
);
gen_tx : if g_tx = true generate
-
tx_clk <= i_tx_clk;
tx_rst <= i_tx_rst;
@@ -370,7 +364,6 @@ begin
);
gen_altgx: for i in 0 to g_nof_gx - 1 generate
-
u_areset_tx_rst : entity common_lib.common_areset
generic map(
g_rst_level => '1'
@@ -403,12 +396,10 @@ begin
tx_siso_arr(i).xon <= not tx_align_en_out(i);
tx_datain(i) <= c_align_pattern when tx_align_en_out(i) = '1' else tx_sosi_arr(i).data(g_data_w - 1 downto 0) when tx_sosi_arr(i).valid = '1' else c_inval_pattern;
txc_tx_ctrlenable(i) <= (others => '1') when tx_align_en_out(i) = '1' else (others => '0') when tx_sosi_arr(i).valid = '1' else (others => '1');
-
end generate;
end generate;
gen_rx : if g_rx = true generate
-
rx_clk <= i_rx_clk;
rx_rst <= i_rx_rst;
@@ -429,7 +420,6 @@ begin
not_trc_rx_rdy <= not(trc_rx_rdy);
i_rx_rst_align: for i in 0 to g_nof_gx - 1 generate
-
u_areset_i_rx_rst : entity common_lib.common_areset
generic map(
g_rst_level => '1'
@@ -480,7 +470,6 @@ begin
end generate;
end generate;
-
------------------------------------------------------------------------------
-- ALTGX_RECONFIG Megafunction
------------------------------------------------------------------------------
@@ -497,6 +486,4 @@ begin
busy => rec_busy,
reconfig_togxb => reconfig_togxb
);
-
end str;
-
diff --git a/libraries/technology/transceiver/tech_transceiver_rx_align.vhd b/libraries/technology/transceiver/tech_transceiver_rx_align.vhd
index 3b3b919f901726f71b96171f3278108993dc475c..bab913559a09d724ede22aa3987eb4f11e53e453 100644
--- a/libraries/technology/transceiver/tech_transceiver_rx_align.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_rx_align.vhd
@@ -42,7 +42,6 @@ entity tech_transceiver_rx_align is
end tech_transceiver_rx_align;
architecture rtl of tech_transceiver_rx_align is
-
constant c_rx_clk_freq : natural := (g_mbps / g_data_w) / 10 * 8 * 1000000;
constant c_timeout_1ms : natural := c_rx_clk_freq / 1000;
@@ -66,9 +65,7 @@ architecture rtl of tech_transceiver_rx_align is
signal nxt_rx_state : std_logic_vector(1 downto 0);
signal i_rx_state : std_logic_vector(1 downto 0);
-
begin
-
rx_state <= i_rx_state;
rx_align_en_out <= i_rx_align_en_out;
@@ -157,6 +154,4 @@ begin
nxt_state <= s_init;
end case;
end process;
-
end rtl;
-
diff --git a/libraries/technology/transceiver/tech_transceiver_rx_order.vhd b/libraries/technology/transceiver/tech_transceiver_rx_order.vhd
index dbc674e98a837baf883c221bcd9770c24b07dbcb..4c19a413e754351624654c175e5d93c2fd97beb5 100644
--- a/libraries/technology/transceiver/tech_transceiver_rx_order.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_rx_order.vhd
@@ -41,7 +41,6 @@ entity tech_transceiver_rx_order is
end entity;
architecture rtl of tech_transceiver_rx_order is
-
signal in_hi_dat : std_logic_vector(g_data_w / 2 - 1 downto 0);
signal in_lo_dat : std_logic_vector(g_data_w / 2 - 1 downto 0);
signal in_hi_val : std_logic;
@@ -53,9 +52,7 @@ architecture rtl of tech_transceiver_rx_order is
signal nxt_odd_dat : std_logic_vector(odd_dat'range);
signal odd_val : std_logic;
signal nxt_odd_val : std_logic;
-
begin
-
in_hi_dat <= rx_data_in(g_data_w - 1 downto g_data_w / 2);
in_hi_val <= not rx_ctrl_in(rx_ctrl_in'high);
@@ -90,7 +87,6 @@ begin
nxt_odd_dat <= in_hi_dat;
end process;
-
out_proc : process (in_hi_dat, in_hi_val, in_lo_dat, in_lo_val, odd_dat, odd_val)
begin
nxt_rx_valid_out <= (in_hi_val and in_lo_val) or (odd_val and (in_hi_val or in_lo_val));
@@ -102,5 +98,4 @@ begin
nxt_rx_data_out(2 * g_data_w / 2 - 1 downto 0) <= in_lo_dat & odd_dat;
end if;
end process;
-
end rtl;
diff --git a/libraries/technology/transceiver/tech_transceiver_rx_rst.vhd b/libraries/technology/transceiver/tech_transceiver_rx_rst.vhd
index 897815367650893054af8569ab980cc42fdcf5f3..ae67ed78162430985aad62984abd8add565d01c3 100644
--- a/libraries/technology/transceiver/tech_transceiver_rx_rst.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_rx_rst.vhd
@@ -41,7 +41,6 @@ entity tech_transceiver_rx_rst is
end tech_transceiver_rx_rst;
architecture rtl of tech_transceiver_rx_rst is
-
-- tLTD_auto: 4us. At 156.25MHz this equals 625 clock cycles.
constant c_ltd_auto : natural := 625;
constant c_ltd_auto_w : natural := ceil_log2(c_ltd_auto);
@@ -65,9 +64,7 @@ architecture rtl of tech_transceiver_rx_rst is
signal trc_rx_freq_locked : std_logic_vector(g_nof_gx - 1 downto 0);
signal trc_rec_busy : std_logic;
-
begin
-
trc_rx_digital_rst <= i_trc_rx_digital_rst;
trc_rx_analog_rst <= i_trc_rx_analog_rst;
trc_rx_rdy <= i_trc_rx_rdy;
@@ -125,7 +122,6 @@ begin
when others =>
nxt_state <= s_wait_while_busy;
end case;
-
end process;
u_async_busy : entity common_lib.common_async
@@ -153,4 +149,3 @@ begin
end generate;
end rtl;
-
diff --git a/libraries/technology/transceiver/tech_transceiver_tx_align.vhd b/libraries/technology/transceiver/tech_transceiver_tx_align.vhd
index 63644c32b4b477696ccecf6f699d4bc531ca2ec3..923ef491aae125b2313361189dbdf675ca3989de 100644
--- a/libraries/technology/transceiver/tech_transceiver_tx_align.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_tx_align.vhd
@@ -41,7 +41,6 @@ entity tech_transceiver_tx_align is
end tech_transceiver_tx_align;
architecture rtl of tech_transceiver_tx_align is
-
constant c_tx_clk_freq : natural := (g_mbps / g_data_w) / 10 * 8 * 1000000;
constant c_timeout_1s : natural := c_tx_clk_freq;
@@ -62,9 +61,7 @@ architecture rtl of tech_transceiver_tx_align is
signal nxt_tx_state : std_logic_vector(1 downto 0);
signal i_tx_state : std_logic_vector(1 downto 0);
-
begin
-
tx_state <= i_tx_state;
tx_align_en_out <= i_tx_align_en;
@@ -123,6 +120,4 @@ begin
nxt_state <= s_init_send_pattern;
end case;
end process;
-
end rtl;
-
diff --git a/libraries/technology/transceiver/tech_transceiver_tx_rst.vhd b/libraries/technology/transceiver/tech_transceiver_tx_rst.vhd
index b1ed29afb0cddc97bd85a2bcbe02384a736482bf..73c37e36cbd9b4566f16f823797d6ba98ec6d94f 100644
--- a/libraries/technology/transceiver/tech_transceiver_tx_rst.vhd
+++ b/libraries/technology/transceiver/tech_transceiver_tx_rst.vhd
@@ -40,7 +40,6 @@ entity tech_transceiver_tx_rst is
end tech_transceiver_tx_rst;
architecture rtl of tech_transceiver_tx_rst is
-
-- The minimum pulse width in to keep trc_tx_pll_powerdown asserted = 1us (stratix iv device datasheet).
-- At 156.25Mhz (6.4ns) this takes 156.25 cycles. As a lower data rate increases the tx_clk period,
-- we're already on the safe side using this value.
@@ -65,9 +64,7 @@ architecture rtl of tech_transceiver_tx_rst is
signal nxt_cycle_cnt : std_logic_vector(c_pll_powerdown_w - 1 downto 0);
signal trc_tx_pll_locked : std_logic_vector(g_nof_gx - 1 downto 0);
-
begin
-
trc_tx_pll_powerdown <= i_trc_tx_pll_powerdown;
trc_tx_digital_rst <= i_trc_tx_digital_rst;
trc_tx_rdy <= i_trc_tx_rdy;
@@ -136,4 +133,3 @@ begin
end generate;
end rtl;
-
diff --git a/libraries/technology/tse/sim_tse.vhd b/libraries/technology/tse/sim_tse.vhd
index 436e39cae695af9bfaa314c19d26e748fb4261f8..45c47f4822c0f22d78308587ae4f6f4f7c78b49c 100644
--- a/libraries/technology/tse/sim_tse.vhd
+++ b/libraries/technology/tse/sim_tse.vhd
@@ -79,11 +79,9 @@ entity sim_tse is
tse_led : out t_tech_tse_led
);
-
end sim_tse;
architecture str of sim_tse is
-
constant c_crc_sz : natural := 4; -- CRC word has 4 octets
signal tr_clk : std_logic;
@@ -112,9 +110,7 @@ architecture str of sim_tse is
signal gx_rx_src_out_arr : t_dp_sosi_arr(0 downto 0);
signal gx_rx_src_in_arr : t_dp_siso_arr(0 downto 0);
-
begin
-
-------------------------------------------------------------------------------
-- TX FIFO
-- . tx_snk_clk (dp_clk) -> tr_clk
@@ -233,7 +229,6 @@ begin
gx_tx_snk_in_arr(0) <= tx_pkt_sosi;
tx_pkt_siso <= gx_tx_snk_out_arr(0);
-
end generate;
-------------------------------------------------------------------------------
@@ -301,5 +296,4 @@ begin
src_out => rx_src_out,
src_in => rx_src_in
);
-
end str;
diff --git a/libraries/technology/tse/tb_tb_tech_tse.vhd b/libraries/technology/tse/tb_tb_tech_tse.vhd
index a1ee1c2ebe2e17bd9ec37f523c8e97b08c5bc95f..ad1cbfd3b206413a522c22010afd07a69fffa35d 100644
--- a/libraries/technology/tse/tb_tb_tech_tse.vhd
+++ b/libraries/technology/tse/tb_tb_tech_tse.vhd
@@ -34,21 +34,16 @@ use technology_lib.technology_pkg.all;
use technology_lib.technology_select_pkg.all;
use tech_tse_lib.tb_tech_tse_pkg.all;
-
entity tb_tb_tech_tse is
end tb_tb_tech_tse;
-
architecture tb of tb_tb_tech_tse is
-
constant c_tech : natural := c_tech_select_default;
constant c_tb_end_vec : std_logic_vector(15 downto 0) := (others => '1');
signal tb_end_vec : std_logic_vector(15 downto 0) := c_tb_end_vec; -- sufficiently long to fit all tb instances
signal tb_end : std_logic := '0';
-
begin
-
-- g_technology : NATURAL := c_tech_select_default;
-- -- g_data_type = c_tb_tech_tse_data_type_symbols = 0
-- -- g_data_type = c_tb_tech_tse_data_type_counter = 1
diff --git a/libraries/technology/tse/tb_tech_tse.vhd b/libraries/technology/tse/tb_tech_tse.vhd
index 0e2add58bbfa9de81c6c13ee9aa970adea124694..4df0ac76f04d086bbb8a0270b0ce8b79693a2784 100644
--- a/libraries/technology/tse/tb_tech_tse.vhd
+++ b/libraries/technology/tse/tb_tech_tse.vhd
@@ -41,7 +41,6 @@ use technology_lib.technology_select_pkg.all;
use WORK.tech_tse_pkg.all;
use WORK.tb_tech_tse_pkg.all;
-
entity tb_tech_tse is
-- Test bench control parameters
generic (
@@ -58,9 +57,7 @@ entity tb_tech_tse is
);
end tb_tech_tse;
-
architecture tb of tb_tech_tse is
-
-- as 10
-- run 50 us
@@ -131,9 +128,7 @@ architecture tb of tb_tech_tse is
-- Verification
signal tx_pkt_cnt : natural := 0;
signal rx_pkt_cnt : natural := 0;
-
begin
-
-- run 50 us
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
@@ -170,7 +165,6 @@ begin
wait;
end process;
-
p_ff_transmitter : process
begin
-- . Avalon ST
@@ -204,7 +198,6 @@ begin
wait;
end process;
-
p_ff_receiver : process
begin
-- . Avalon ST
@@ -222,7 +215,6 @@ begin
wait;
end process;
-
dut : entity work.tech_tse
generic map (
g_technology => g_technology,
@@ -293,5 +285,4 @@ begin
end if;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/tse/tb_tech_tse_pkg.vhd b/libraries/technology/tse/tb_tech_tse_pkg.vhd
index 90f51a2f4ed7254809ab7c4da791bff1eb3b2187..910d8e34cdaefd79db80454b70cc3d0bdb0a9152 100644
--- a/libraries/technology/tse/tb_tech_tse_pkg.vhd
+++ b/libraries/technology/tse/tb_tech_tse_pkg.vhd
@@ -33,9 +33,7 @@ use dp_lib.tb_dp_pkg.all;
use technology_lib.technology_pkg.all;
use WORK.tech_tse_pkg.all;
-
package tb_tech_tse_pkg is
-
-- Test bench supported packet data types
constant c_tb_tech_tse_data_type_symbols : natural := 0;
constant c_tb_tech_tse_data_type_counter : natural := 1;
@@ -93,12 +91,9 @@ package tb_tech_tse_pkg is
signal ff_clk : in std_logic;
signal ff_snk_in : in t_dp_sosi;
signal ff_snk_out : out t_dp_siso);
-
end tb_tech_tse_pkg;
-
package body tb_tech_tse_pkg is
-
------------------------------------------------------------------------------
-- LOCAL ITEMS
------------------------------------------------------------------------------
@@ -113,7 +108,6 @@ package body tb_tech_tse_pkg is
return pcs_addr * 2 + c_tech_tse_byte_addr_pcs_offset;
end func_map_pcs_addr;
-
------------------------------------------------------------------------------
-- GLOBAL ITEMS
------------------------------------------------------------------------------
@@ -128,7 +122,6 @@ package body tb_tech_tse_pkg is
return c_network_total_header_32b_nof_words;
end func_tech_tse_header_size;
-
-- Configure the TSE MAC
procedure proc_tech_tse_setup(constant c_technology : in natural;
constant c_promis_en : in boolean;
@@ -268,7 +261,6 @@ package body tb_tech_tse_pkg is
wait until rising_edge(mm_clk);
end proc_tech_tse_setup_arria10;
-
-- Transmit user packet
-- . Use word aligned payload data, so with half word inserted before the 14 byte header
-- . Packets can be send immediately after eachother so new sop directly after last eop
@@ -369,7 +361,6 @@ package body tb_tech_tse_pkg is
ff_src_out.empty <= TO_DP_EMPTY(0);
end proc_tech_tse_tx_packet;
-
-- Receive packet
-- . Use word aligned payload data, so with half word inserted before the 14 byte header
-- . Packets can be always be received, assume the user application is always ready
diff --git a/libraries/technology/tse/tb_tech_tse_with_setup.vhd b/libraries/technology/tse/tb_tech_tse_with_setup.vhd
index 6133481ade71f35e598d6274ca77be5d4093697c..701cbd3f55e7cf9a17c1ba4015c166315e6b8807 100644
--- a/libraries/technology/tse/tb_tech_tse_with_setup.vhd
+++ b/libraries/technology/tse/tb_tech_tse_with_setup.vhd
@@ -49,7 +49,6 @@ use technology_lib.technology_select_pkg.all;
use WORK.tech_tse_pkg.all;
use WORK.tb_tech_tse_pkg.all;
-
entity tb_tech_tse_with_setup is
-- Test bench control parameters
generic (
@@ -64,9 +63,7 @@ entity tb_tech_tse_with_setup is
);
end tb_tech_tse_with_setup;
-
architecture tb of tb_tech_tse_with_setup is
-
constant c_sim : boolean := true;
constant c_sim_level : natural := 0; -- 0 = use IP; 1 = use fast serdes model;
constant c_jumbo_en : boolean := true;
@@ -137,9 +134,7 @@ architecture tb of tb_tech_tse_with_setup is
-- Verification
signal tx_pkt_cnt : natural := 0;
signal rx_pkt_cnt : natural := 0;
-
begin
-
eth_clk <= not eth_clk after eth_clk_period / 2; -- TSE reference clock
sys_clk <= not sys_clk after sys_clk_period / 2; -- System clock
@@ -188,7 +183,6 @@ begin
wait;
end process;
-
p_ff_transmitter : process
begin
-- . Avalon ST
@@ -222,7 +216,6 @@ begin
wait;
end process;
-
p_ff_receiver : process
begin
-- . Avalon ST
@@ -240,7 +233,6 @@ begin
wait;
end process;
-
dut : entity work.tech_tse_with_setup
generic map (
g_technology => g_technology,
@@ -311,5 +303,4 @@ begin
end if;
wait;
end process;
-
end tb;
diff --git a/libraries/technology/tse/tech_tse.vhd b/libraries/technology/tse/tech_tse.vhd
index ffbe694082ff928facc436467019ca56cc37af38..a845de8a8e2b4e96ca18915d0c0edb3a356f9ab5 100644
--- a/libraries/technology/tse/tech_tse.vhd
+++ b/libraries/technology/tse/tech_tse.vhd
@@ -28,7 +28,6 @@ use common_lib.common_mem_pkg.all;
use dp_lib.dp_stream_pkg.all;
use work.tech_tse_pkg.all;
-
entity tech_tse is
generic (
g_technology : natural := c_tech_select_default;
@@ -77,7 +76,6 @@ entity tech_tse is
end tech_tse;
architecture str of tech_tse is
-
constant c_use_technology : boolean := g_sim = false or g_sim_level = 0;
constant c_use_sim_model : boolean := not c_use_technology;
@@ -121,9 +119,7 @@ architecture str of tech_tse is
tse_led : out t_tech_tse_led
);
end component;
-
begin
-
gen_ip_stratixiv : if c_use_technology = true and g_technology = c_tech_stratixiv generate
u0 : entity work.tech_tse_stratixiv
generic map (g_ETH_PHY)
diff --git a/libraries/technology/tse/tech_tse_arria10.vhd b/libraries/technology/tse/tech_tse_arria10.vhd
index 5970d7e869a7bc60343678abe4680eea21413783..31c266d5de41fc07629026a2aa86693a882da822 100644
--- a/libraries/technology/tse/tech_tse_arria10.vhd
+++ b/libraries/technology/tse/tech_tse_arria10.vhd
@@ -71,13 +71,10 @@ entity tech_tse_arria10 is
end tech_tse_arria10;
architecture str of tech_tse_arria10 is
-
signal ff_tx_mod : std_logic_vector(c_tech_tse_empty_w - 1 downto 0);
signal ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
-- Default frame level flow control
tx_snk_out.xon <= '1';
@@ -88,7 +85,6 @@ begin
rx_src_out <= ff_rx_out;
u_LVDS_tse: if g_ETH_PHY = "LVDS" generate
-
u_tse : ip_arria10_tse_sgmii_lvds
-- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -160,11 +156,9 @@ begin
txp => eth_txp,
rxp => eth_rxp
);
-
end generate;
u_XCVR_tse: if g_ETH_PHY = "XCVR" generate
-
u_tse : ip_arria10_tse_sgmii_gx
-- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -250,7 +244,6 @@ begin
rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => open -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
);
-
end generate;
end str;
diff --git a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
index 1bf652b8e9dbe0242f7f5e3644b72afa689f4e01..0444f9b47bb8e4406f17922234a414412196596e 100644
--- a/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e1sg.vhd
@@ -71,13 +71,10 @@ entity tech_tse_arria10_e1sg is
end tech_tse_arria10_e1sg;
architecture str of tech_tse_arria10_e1sg is
-
signal ff_tx_mod : std_logic_vector(c_tech_tse_empty_w - 1 downto 0);
signal ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
-- Default frame level flow control
tx_snk_out.xon <= '1';
@@ -88,7 +85,6 @@ begin
rx_src_out <= ff_rx_out;
u_LVDS_tse: if g_ETH_PHY = "LVDS" generate
-
u_tse : ip_arria10_e1sg_tse_sgmii_lvds
-- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -160,11 +156,9 @@ begin
txp => eth_txp,
rxp => eth_rxp
);
-
end generate;
u_XCVR_tse: if g_ETH_PHY = "XCVR" generate
-
u_tse : ip_arria10_e1sg_tse_sgmii_gx
-- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -250,7 +244,6 @@ begin
rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => open -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
);
-
end generate;
end str;
diff --git a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
index 7f472f65c61028e91ddca680144a758e699101da..11487915543524911bb789908bf4699f40e51c28 100644
--- a/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e2sg.vhd
@@ -71,13 +71,10 @@ entity tech_tse_arria10_e2sg is
end tech_tse_arria10_e2sg;
architecture str of tech_tse_arria10_e2sg is
-
signal ff_tx_mod : std_logic_vector(c_tech_tse_empty_w - 1 downto 0);
signal ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
-- Default frame level flow control
tx_snk_out.xon <= '1';
@@ -88,7 +85,6 @@ begin
rx_src_out <= ff_rx_out;
u_LVDS_tse: if g_ETH_PHY = "LVDS" generate
-
u_tse : ip_arria10_e2sg_tse_sgmii_lvds
-- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -160,11 +156,9 @@ begin
txp => eth_txp,
rxp => eth_rxp
);
-
end generate;
u_XCVR_tse: if g_ETH_PHY = "XCVR" generate
-
u_tse : ip_arria10_e2sg_tse_sgmii_gx
-- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -250,7 +244,6 @@ begin
rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => open -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
);
-
end generate;
end str;
diff --git a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
index e34e9c761bb8192f4b273670216d205ea92a431d..acc32ee58982acdbaf447f034ed0df9df424a2db 100644
--- a/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
+++ b/libraries/technology/tse/tech_tse_arria10_e3sge3.vhd
@@ -71,13 +71,10 @@ entity tech_tse_arria10_e3sge3 is
end tech_tse_arria10_e3sge3;
architecture str of tech_tse_arria10_e3sge3 is
-
signal ff_tx_mod : std_logic_vector(c_tech_tse_empty_w - 1 downto 0);
signal ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
-
begin
-
-- Default frame level flow control
tx_snk_out.xon <= '1';
@@ -88,7 +85,6 @@ begin
rx_src_out <= ff_rx_out;
u_LVDS_tse: if g_ETH_PHY = "LVDS" generate
-
u_tse : ip_arria10_e3sge3_tse_sgmii_lvds
-- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -160,11 +156,9 @@ begin
txp => eth_txp,
rxp => eth_rxp
);
-
end generate;
u_XCVR_tse: if g_ETH_PHY = "XCVR" generate
-
u_tse : ip_arria10_e3sge3_tse_sgmii_gx
-- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -250,7 +244,6 @@ begin
rx_is_lockedtoref => OPEN, -- : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
rx_is_lockedtodata => open -- : out std_logic_vector(0 downto 0) -- rx_is_lockedtodata.rx_is_lockedtodata
);
-
end generate;
end str;
diff --git a/libraries/technology/tse/tech_tse_component_pkg.vhd b/libraries/technology/tse/tech_tse_component_pkg.vhd
index 791a7bc360268f8518025b8a05d5ad3ff907ec88..7a2360d23e35a114a205e039b98c3ffd4bd99cf2 100644
--- a/libraries/technology/tse/tech_tse_component_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_component_pkg.vhd
@@ -26,7 +26,6 @@ use IEEE.std_logic_1164.all;
use technology_lib.technology_pkg.all;
package tech_tse_component_pkg is
-
------------------------------------------------------------------------------
-- ip_stratixiv
------------------------------------------------------------------------------
@@ -197,7 +196,6 @@ package tech_tse_component_pkg is
);
end component;
-
-- Copied from $HDL_BUILD_DIR/sim/ip_arria10_tse_sgmii_gx.vhd
component ip_arria10_tse_sgmii_gx is
port (
@@ -260,7 +258,6 @@ package tech_tse_component_pkg is
);
end component;
-
------------------------------------------------------------------------------
-- ip_arria10_e3sge3
------------------------------------------------------------------------------
@@ -315,7 +312,6 @@ package tech_tse_component_pkg is
);
end component;
-
-- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e3sge3_tse_sgmii_gx.vhd
component ip_arria10_e3sge3_tse_sgmii_gx is
port (
@@ -433,7 +429,6 @@ package tech_tse_component_pkg is
);
end component;
-
-- Copied from $HDL_BUILD_DIR/sim/ip_arria10_e1sg_tse_sgmii_gx.vhd
component ip_arria10_e1sg_tse_sgmii_gx is
port (
@@ -550,7 +545,6 @@ package tech_tse_component_pkg is
);
end component;
-
component ip_arria10_e2sg_tse_sgmii_gx is
port (
reg_data_out : out std_logic_vector(31 downto 0); -- control_port.readdata
diff --git a/libraries/technology/tse/tech_tse_pkg.vhd b/libraries/technology/tse/tech_tse_pkg.vhd
index 4d43ffc9354d2ea5fe056746469f6ed8ce3313f3..a38b153de7221a113fe9fdd8b135fee5ee0f58ec 100644
--- a/libraries/technology/tse/tech_tse_pkg.vhd
+++ b/libraries/technology/tse/tech_tse_pkg.vhd
@@ -25,7 +25,6 @@ use IEEE.std_logic_1164.all;
use common_lib.common_pkg.all;
package tech_tse_pkg is
-
constant c_tech_tse_reg_addr_w : natural := 8; -- = max 256 MAC registers
constant c_tech_tse_byte_addr_w : natural := c_tech_tse_reg_addr_w + 2;
constant c_tech_tse_byte_addr_pcs_offset : natural := 16#200#; -- table 4.8, 4.9 in ug_ethernet.pdf
@@ -86,9 +85,7 @@ package tech_tse_pkg is
end tech_tse_pkg;
-
package body tech_tse_pkg is
-
function func_tech_tse_map_pcs_addr(pcs_addr : natural) return natural is
begin
return pcs_addr * 2 + c_tech_tse_byte_addr_pcs_offset;
diff --git a/libraries/technology/tse/tech_tse_setup.vhd b/libraries/technology/tse/tech_tse_setup.vhd
index cf8121c6d004dbc7dbd6e1679428f20fca544e52..ee22a49906c6cd3c149e800f19134dc8f9fdaa0a 100644
--- a/libraries/technology/tse/tech_tse_setup.vhd
+++ b/libraries/technology/tse/tech_tse_setup.vhd
@@ -61,7 +61,6 @@ entity tech_tse_setup is
end tech_tse_setup;
architecture rtl of tech_tse_setup is
-
-- FALSE receive only frames for this src_mac and broadcast, TRUE receive all
constant c_promis_en : boolean := false;
@@ -88,9 +87,7 @@ architecture rtl of tech_tse_setup is
signal src_mac_0 : std_logic_vector(c_32 - 1 downto 0);
signal src_mac_1 : std_logic_vector(c_16 - 1 downto 0);
-
begin
-
setup_done <= not tse_init;
src_mac_0 <= hton(src_mac(c_48 - 1 downto c_16), 4);
@@ -252,8 +249,6 @@ begin
tse_ctlr_copi.rd <= '0';
state <= next_state;
end if;
-
end if;
end process;
-
end architecture;
diff --git a/libraries/technology/tse/tech_tse_stratixiv.vhd b/libraries/technology/tse/tech_tse_stratixiv.vhd
index 4911a87b9d02dc2008ad74e98108e85aa93b8f44..f94abe46c85f4cfc8109779a8675f53181d7349e 100644
--- a/libraries/technology/tse/tech_tse_stratixiv.vhd
+++ b/libraries/technology/tse/tech_tse_stratixiv.vhd
@@ -74,7 +74,6 @@ entity tech_tse_stratixiv is
end tech_tse_stratixiv;
architecture str of tech_tse_stratixiv is
-
signal ff_tx_mod : std_logic_vector(c_tech_tse_empty_w - 1 downto 0);
signal ff_rx_out : t_dp_sosi := c_dp_sosi_rst;
@@ -84,9 +83,7 @@ architecture str of tech_tse_stratixiv is
signal reconfig_togxb : std_logic_vector(3 downto 0);
signal reconfig_fromgxb : std_logic_vector(16 downto 0);
-
begin
-
-- Default frame level flow control
tx_snk_out.xon <= '1';
@@ -97,7 +94,6 @@ begin
rx_src_out <= ff_rx_out;
u_LVDS_tse: if g_ETH_PHY = "LVDS" generate
-
u_tse : ip_stratixiv_tse_sgmii_lvds
-- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -168,11 +164,9 @@ begin
txp => eth_txp,
rxp => eth_rxp
);
-
end generate;
u_XCVR_tse: if g_ETH_PHY = "XCVR" generate
-
u_tse : ip_stratixiv_tse_sgmii_gx
-- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
-- . ENABLE_SHIFT16 = 1 : Align packet headers to 32 bit, useful for Nios data handling
@@ -261,7 +255,6 @@ begin
busy => open,
reconfig_togxb => reconfig_togxb
);
-
end generate;
end str;
diff --git a/libraries/technology/tse/tech_tse_with_setup.vhd b/libraries/technology/tse/tech_tse_with_setup.vhd
index 8cacde3ea1e9bd6353c562c934adbc584fe8173c..d13a06071eee703f4dd3d74d22f85a156ae797b1 100644
--- a/libraries/technology/tse/tech_tse_with_setup.vhd
+++ b/libraries/technology/tse/tech_tse_with_setup.vhd
@@ -81,7 +81,6 @@ entity tech_tse_with_setup is
end tech_tse_with_setup;
architecture str of tech_tse_with_setup is
-
-- Peripheral side
signal mm_peri_copi : t_mem_copi;
signal mm_peri_cipo : t_mem_cipo;
@@ -92,9 +91,7 @@ architecture str of tech_tse_with_setup is
signal rx_mac_out : t_tech_tse_rx_mac;
signal tx_sosi : t_dp_sosi;
-
begin
-
-- Set up TSE as in unb_osy/unbos_eth.c
u_tech_tse_setup : entity work.tech_tse_setup
generic map (
@@ -169,5 +166,4 @@ begin
tse_led => tse_led
);
-
end architecture;
diff --git a/libraries/technology/xaui/sim_xaui.vhd b/libraries/technology/xaui/sim_xaui.vhd
index 5c3f2c2e03eadc89ab5cd3ad7c803e8d4cde9931..6ccb5a314d37ed3ebbce00ef89d3a3fc1fa198b1 100644
--- a/libraries/technology/xaui/sim_xaui.vhd
+++ b/libraries/technology/xaui/sim_xaui.vhd
@@ -73,9 +73,7 @@ entity sim_xaui is
);
end sim_xaui;
-
architecture wrap of sim_xaui is
-
constant c_tr_clk_period : time := 6.4 ns; -- 156.25 MHz --> model line rate : 156.25 MHz * 10/8 (encoding) * 64b (data width) / 4 (XAUI lanes) = 3125 Mbps / lane
constant c_xaui_serdes_data_w : natural := c_xgmii_data_w / c_nof_xaui_lanes; -- = 16b = 64 b / 4
@@ -88,9 +86,7 @@ architecture wrap of sim_xaui is
-- XGMII data
signal xgmii_tx_d_arr : t_xgmii_d_arr(g_nof_xaui - 1 downto 0);
signal xgmii_rx_d_arr : t_xgmii_d_arr(g_nof_xaui - 1 downto 0);
-
begin
-
-- Model rx_clk = tx_clk = tr_clk
rx_clk_arr_out <= tx_clk_arr;
@@ -98,7 +94,6 @@ begin
xaui_miso <= c_mem_miso_rst;
gen_nof_xaui : for i in g_nof_xaui - 1 downto 0 generate
-
-- Rewire XGMII
xgmii_tx_d_arr(i) <= func_xgmii_d(xgmii_tx_dc_arr(i));
xgmii_tx_c_arr(i) <= func_xgmii_c(xgmii_tx_dc_arr(i));
@@ -142,7 +137,6 @@ begin
);
gen_serdes: for j in c_nof_xaui_lanes - 1 downto 0 generate
-
u_ser: entity tech_transceiver_lib.sim_transceiver_serializer
generic map (
g_data_w => c_xaui_serdes_data_w,
@@ -172,10 +166,7 @@ begin
rx_serial_in => xaui_rx_arr(i)(j)
);
-
end generate;
end generate;
-
end wrap;
-
diff --git a/libraries/technology/xaui/tech_xaui.vhd b/libraries/technology/xaui/tech_xaui.vhd
index 31ec12c9a7297054c67d30c8423ef3479e24cfbb..037de428a0ce1152851490b1ff57373fb5d56c22 100644
--- a/libraries/technology/xaui/tech_xaui.vhd
+++ b/libraries/technology/xaui/tech_xaui.vhd
@@ -69,15 +69,10 @@ entity tech_xaui is
);
end tech_xaui;
-
-
architecture str of tech_xaui is
-
constant c_use_technology : boolean := g_sim = false or g_sim_level = 0;
constant c_use_sim_model : boolean := not c_use_technology;
-
begin
-
gen_ip_stratixiv : if c_use_technology = true and g_technology = c_tech_stratixiv generate
u0 : entity work.tech_xaui_stratixiv
generic map (g_sim, g_nof_xaui)
@@ -87,7 +82,6 @@ begin
xaui_tx_arr, xaui_rx_arr);
end generate;
-
gem_sim_xaui : if c_use_sim_model = true or g_technology /= c_tech_stratixiv generate
u0 : entity work.sim_xaui
generic map (g_sim, g_nof_xaui)
@@ -98,4 +92,3 @@ begin
end generate;
end str;
-
diff --git a/libraries/technology/xaui/tech_xaui_align_dly.vhd b/libraries/technology/xaui/tech_xaui_align_dly.vhd
index c60d32ceb462eb841c7f0c43603b54372a7ec8bf..1fb032b7681c35b1516bd31880823bb95cb1ffa5 100644
--- a/libraries/technology/xaui/tech_xaui_align_dly.vhd
+++ b/libraries/technology/xaui/tech_xaui_align_dly.vhd
@@ -46,13 +46,9 @@ entity tech_xaui_align_dly is
);
end tech_xaui_align_dly;
-
architecture rtl of tech_xaui_align_dly is
-
constant c_align_dly_cnt : natural := sel_a_b(g_sim, 50, 156250000); -- about 1 second on hw
-
begin
-
u_common_debounce : entity common_lib.common_debounce
generic map (
g_type => "HIGH", -- "HIGH" = debounce g_latency clk cycles for going high when d_in='1', go low immediately when d_in='0'
@@ -66,6 +62,4 @@ begin
d_in => a_rx_channelaligned,
q_out => txc_rx_channelaligned_dly
);
-
end rtl;
-
diff --git a/libraries/technology/xaui/tech_xaui_component_pkg.vhd b/libraries/technology/xaui/tech_xaui_component_pkg.vhd
index d1d2d3c5bae72cbb4fc8ab46a342ceeff885a769..68693bdce1f930b66f3d4cbfdfa5410ef715e35b 100644
--- a/libraries/technology/xaui/tech_xaui_component_pkg.vhd
+++ b/libraries/technology/xaui/tech_xaui_component_pkg.vhd
@@ -26,7 +26,6 @@ use IEEE.std_logic_1164.all;
use technology_lib.technology_pkg.all;
package tech_xaui_component_pkg is
-
function tech_xaui_mosi_addr_w(technology : in integer) return integer;
------------------------------------------------------------------------------
@@ -234,17 +233,16 @@ package tech_xaui_component_pkg is
);
end component;
-
end tech_xaui_component_pkg;
package body tech_xaui_component_pkg is
-
function tech_xaui_mosi_addr_w(technology : in integer) return integer is
begin
case technology is
when c_tech_stratixiv => return 9;
when others => return 9;
end case;
+
end;
end tech_xaui_component_pkg;
diff --git a/libraries/technology/xaui/tech_xaui_stratixiv.vhd b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
index 035b82abf4b712ba11a84a7f33bd7e89bc9ce0a7..9b6a4bb8ae00d0cba0a9ae433c607106b67900e0 100644
--- a/libraries/technology/xaui/tech_xaui_stratixiv.vhd
+++ b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
@@ -70,9 +70,7 @@ entity tech_xaui_stratixiv is
);
end tech_xaui_stratixiv;
-
architecture str of tech_xaui_stratixiv is
-
constant c_reconf_togxb_bus_w : natural := 4;
constant c_reconf_fromgxb_bus_w : natural := 17;
constant c_reconf_nof_gx : natural := 4; -- 1, 2, or 3 hard XAUI with 4, 8 or 12 transceivers all require only gxb_reconfig for 4 transceivers
@@ -102,11 +100,8 @@ architecture str of tech_xaui_stratixiv is
signal xaui_mosi_arr : t_mem_mosi_arr(g_nof_xaui - 1 downto 0);
signal xaui_miso_arr : t_mem_miso_arr(g_nof_xaui - 1 downto 0);
-
begin
-
gen_nof_xaui : for i in g_nof_xaui - 1 downto 0 generate
-
u_async_txc_tx_ready : entity common_lib.common_async
generic map(
g_rst_level => '0'
@@ -310,7 +305,6 @@ begin
reconfig_togxb => reconfig_soft_togxb
);
end generate;
-
end generate;
-----------------------------------------------------------------------------
@@ -327,6 +321,4 @@ begin
mosi_arr => xaui_mosi_arr,
miso_arr => xaui_miso_arr
);
-
end str;
-