added the fractional PLL for clk125

boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd

@@ -91,20 +91,20 @@ BEGIN
     );
   END GENERATE;
 
-  --gen_fractional_pll : IF g_use_fpll=TRUE GENERATE
-  --  u_pll : ENTITY tech_pll_lib.tech_pll_clk125
-  --  GENERIC MAP (
-  --    g_technology => g_technology
-  --  )
-  --  PORT MAP (
-  --    areset  => arst,
-  --    inclk0  => clk125buf,
-  --    c0      => c0_clk20,
-  --    c1      => c1_clk50,
-  --    c2      => c2_clk100,
-  --    c3      => c3_clk125,
-  --    locked  => pll_locked
-  --  );
-  --END GENERATE;
+  gen_fractional_pll : IF g_use_fpll=TRUE GENERATE
+    u_pll : ENTITY tech_fractional_pll_lib.tech_fractional_pll_clk125
+    GENERIC MAP (
+      g_technology => g_technology
+    )
+    PORT MAP (
+      areset  => arst,
+      inclk0  => clk125buf,
+      c0      => c0_clk20,
+      c1      => c1_clk50,
+      c2      => c2_clk100,
+      c3      => c3_clk125,
+      locked  => pll_locked
+    );
+  END GENERATE;
 
 END arria10;