From eb01df9829d18eec66d401920fa6680f79633271 Mon Sep 17 00:00:00 2001
From: Leon Hiemstra <hiemstra@astron.nl>
Date: Wed, 27 May 2015 10:18:03 +0000
Subject: [PATCH] added the fractional PLL for clk125
---
.../src/vhdl/unb2_board_clk125_pll.vhd | 30 +++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
index 54cb709666..858cc68b92 100644
--- a/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
+++ b/boards/uniboard2/libraries/unb2_board/src/vhdl/unb2_board_clk125_pll.vhd
@@ -91,20 +91,20 @@ BEGIN
);
END GENERATE;
- --gen_fractional_pll : IF g_use_fpll=TRUE GENERATE
- -- u_pll : ENTITY tech_pll_lib.tech_pll_clk125
- -- GENERIC MAP (
- -- g_technology => g_technology
- -- )
- -- PORT MAP (
- -- areset => arst,
- -- inclk0 => clk125buf,
- -- c0 => c0_clk20,
- -- c1 => c1_clk50,
- -- c2 => c2_clk100,
- -- c3 => c3_clk125,
- -- locked => pll_locked
- -- );
- --END GENERATE;
+ gen_fractional_pll : IF g_use_fpll=TRUE GENERATE
+ u_pll : ENTITY tech_fractional_pll_lib.tech_fractional_pll_clk125
+ GENERIC MAP (
+ g_technology => g_technology
+ )
+ PORT MAP (
+ areset => arst,
+ inclk0 => clk125buf,
+ c0 => c0_clk20,
+ c1 => c1_clk50,
+ c2 => c2_clk100,
+ c3 => c3_clk125,
+ locked => pll_locked
+ );
+ END GENERATE;
END arria10;
--
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