Added #1999, #2004.

applications/apertif/doc/apertif_fpga_firmware_planning_erko.txt

@@ -136,8 +136,8 @@ Done) #1722: RT4 BSN timeout UNB5-FN1 (node 41)
 Done) #1751: Writing application image in central UNB15-BN0 sometimes fails
 Done) #1758: FPGA can hang when application image is corrupt
 Done) #1870: I2C with RT-D, UNB-7, BN-3, ADU-CD fails and therefore it cannot lock
-  10 apr: RT8, X --> UNB-5 link issue?
-  20 apr: RT5, X --> UNB-7 BN-1 link 0 issue? The BSN aligner at the input does not pass on the other 2.
+*) #2004: Central UniBoard BSN timeouts (due to link error)
+
 
 ###############################################################################
 # SR4 31 May: Include dish C, D and 135 --> 200 MHz BW
@@ -151,9 +151,10 @@ Done) #895: PPS cable length compensation in BN filterbank
 Done) #1937: Make all visibility packet header flags writable by MAC
 
 Software issues
-*) #1518 : 135 --> 200 MHz
-   Kept MAC Rbeam settings in:
+Done) #1518: 135 --> 200 MHz
+   Kept MAC software Rbeam settings in:
      $RADIOHDL/applications/apertif/commissioning/mac_rbeam_coreDout.log
+   On 20 June 2018 --cmd 53 --scheme 300MHz_37CB was PASSED, so the MAC software programs 300MHz_37CB when at 200MHz.
      
 *) #1510: Integrate main.py into MAC software, purpose is to have MAC control and thus know all settings (one captain).
 
@@ -169,7 +170,7 @@ Software issues
     --> Conclusion: Keep wrap in node_apertif_unb1_fn_beamformer
     
 *) #1931: Confirm complex format of BF weights: is it (Im,Re) or (Re,Im).
-
+*) #1999: Use Apertif X image as factory image to avoid too much flash writing and to speed up main.py
 
 ###############################################################################
 # SR5 30 Jul: Start of Apertizer observations (enable pre-survey)
@@ -216,10 +217,7 @@ Done) #1163, #397: Flagging for failing links, RFI ? etc.
   - Failing links during observation can be handled by MAC
   - RFI is detected by astronomers at visibility level.
 
-!) #1543: End to end VHDL simulations using MM file IO (20 story points)
-  - Updated Visio drawings FB, BF, X
-  - VHDL simulation of the full chain (not feasible, instead use end to end WG - DW tests on hardware)
-  - Verify visibility output order and output load to DW, see tb_node_apertif_unb1_correlator_processing
+Done) #1543: End to end VHDL simulations using MM file IO (20 story points)
   
 *) #1655: Finalize quantisation (8 story points)
   - SST
@@ -254,8 +252,7 @@ Done) #1163, #397: Flagging for failing links, RFI ? etc.
 *) #1542: End to end WG to Correlator output test (8 story points)
   - Intermediate verification points are the SST, BST, but finally the visibilities should be verified given WG for single element BF
   - Overwrite statistics before reading to ensure fresh data
-  - Verify visibility output order and output load to DW using a databuffer in the correlator output, see
-    tb_node_apertif_unb1_correlator_processing_output
+  - Verify visibility output order and output load to DW using a databuffer in the correlator output, see also #1543
 
 *) #1868: wpfb_unit_dev force Fchan channel output data to 0 for first N_tap bin samples after sync