Added bsn_monitor_output

applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/apertif_unb1_fn_beamformer.vhd

@@ -208,7 +208,9 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
     
   SIGNAL dp_offload_tx_src_out_arr  : t_dp_sosi_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
   SIGNAL dp_offload_tx_src_in_arr   : t_dp_siso_arr(c_nof_10GbE_offload_streams-1 DOWNTO 0);
-
+  
+  SIGNAL bsn_in_sosi_arr            : t_dp_sosi_arr(2-1 DOWNTO 0);
+  
   -----------------------------------------------------------------------------
   -- Memory Mapped interfaces
   -----------------------------------------------------------------------------  
@@ -285,11 +287,16 @@ ARCHITECTURE str OF apertif_unb1_fn_beamformer IS
   SIGNAL reg_mdio_mosi_arr              : t_mem_mosi_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);
   SIGNAL reg_mdio_miso_arr              : t_mem_miso_arr(c_unb1_board_nof_mdio-1 DOWNTO 0);   
   -- . Pre-transpose
-  SIGNAL ram_ss_ss_transp_mosi      : t_mem_mosi;
-  SIGNAL ram_ss_ss_transp_miso      : t_mem_miso;
-  -- . DDR register map 
-  SIGNAL reg_io_ddr_mosi            : t_mem_mosi;       
-  SIGNAL reg_io_ddr_miso            : t_mem_miso;       
+  SIGNAL ram_ss_ss_transp_mosi          : t_mem_mosi;
+  SIGNAL ram_ss_ss_transp_miso          : t_mem_miso;
+  -- . DDR register map                 
+  SIGNAL reg_io_ddr_mosi                : t_mem_mosi;       
+  SIGNAL reg_io_ddr_miso                : t_mem_miso;    
+    -- . bsn_monitor
+  SIGNAL reg_bsn_monitor_output_mosi    : t_mem_mosi := c_mem_mosi_rst;
+  SIGNAL reg_bsn_monitor_output_miso    : t_mem_miso;
+
+  
 
 BEGIN
 
@@ -706,7 +713,32 @@ BEGIN
     SI_FN_2_CNTRL     => SI_FN_2_CNTRL,
     SI_FN_3_CNTRL     => SI_FN_3_CNTRL
   );
-
+  
+  u_bsn_monitor_align : ENTITY dp_lib.mms_dp_bsn_monitor
+  GENERIC MAP (
+    g_nof_streams        => 2, 
+    g_cross_clock_domain => TRUE,
+    g_bsn_w              => c_dp_stream_bsn_w,
+    g_cnt_sop_w          => c_word_w,
+    g_cnt_valid_w        => c_word_w,
+    g_log_first_bsn      => TRUE
+  )
+  PORT MAP (
+    -- Memory-mapped clock domain
+    mm_rst      => mm_rst,
+    mm_clk      => mm_clk,
+    reg_mosi    => reg_bsn_monitor_output_mosi,
+    reg_miso    => reg_bsn_monitor_output_miso,
+    
+    -- Streaming clock domain
+    dp_rst      => dp_rst,
+    dp_clk      => dp_clk,
+    in_siso_arr => (OTHERS=>c_dp_siso_rdy),
+    in_sosi_arr => bsn_in_sosi_arr(1 DOWNTO 0)
+  );
+  bsn_in_sosi_arr(0) <= udp_offload_snk_in_arr(0);
+  bsn_in_sosi_arr(1) <= dp_offload_tx_src_out_arr(0);
+  
   -----------------------------------------------------------------------------
   -- DP offload TX : BF out -> 10GbE
   -----------------------------------------------------------------------------  
@@ -834,7 +866,11 @@ BEGIN
     
     -- . DDR register map 
     reg_io_ddr_mosi                => reg_io_ddr_mosi,
-    reg_io_ddr_miso                => reg_io_ddr_miso,
+    reg_io_ddr_miso                => reg_io_ddr_miso,   
+    
+    -- . bsn_monitor_output                                                 
+    reg_bsn_monitor_output_mosi    => reg_bsn_monitor_output_mosi,
+    reg_bsn_monitor_output_miso    => reg_bsn_monitor_output_miso,
     
     -- eth1g     
     eth1g_tse_clk                  => eth1g_tse_clk,                  
@@ -860,3 +896,4 @@ END;
 
 
 
+