Added mm-port for bsn_monitor_output

applications/apertif/designs/apertif_unb1_fn_beamformer/src/vhdl/mmm_apertif_unb1_fn_beamformer.vhd

@@ -146,6 +146,10 @@ ENTITY mmm_apertif_unb1_fn_beamformer IS
     reg_io_ddr_mosi                : OUT t_mem_mosi;
     reg_io_ddr_miso                : IN  t_mem_miso := c_mem_miso_rst;
 
+    -- . bsn_monitor_output
+    reg_bsn_monitor_output_mosi    : OUT t_mem_mosi := c_mem_mosi_rst;
+    reg_bsn_monitor_output_miso    : IN  t_mem_miso;
+
     -- eth1g
     eth1g_tse_clk                  : OUT STD_LOGIC;
     eth1g_mm_rst                   : OUT STD_LOGIC;
@@ -172,6 +176,7 @@ ARCHITECTURE str OF mmm_apertif_unb1_fn_beamformer IS
   CONSTANT c_ram_diag_bg_addr_w                  : NATURAL := ceil_log2(c_bg_diag_wave_period) + ceil_log2(g_bf.nof_subbands*g_bf.nof_signal_paths/g_bf.nof_input_streams)+ceil_log2(g_bf.nof_input_streams); 
   CONSTANT c_dp_ram_mm_nof_words                 : NATURAL := c_network_total_header_32b_nof_words * (c_tech_tse_data_w/c_word_w);                            
   CONSTANT c_dp_ram_mm_adr_w                     : NATURAL := ceil_log2(g_bf.nof_bf_units * pow2(ceil_log2(c_dp_ram_mm_nof_words)));
+  CONSTANT c_reg_bsn_monitor_output_adr_w        : NATURAL := 5; 
 
   CONSTANT c_ram_ss_ss_transp_addr_w             : NATURAL := ceil_log2(g_reorder_seq.rd_chunksize*g_bf.nof_weights*2);     
   CONSTANT c_mm_reg_io_ddr_addr_w                : NATURAL := ceil_log2(16);
@@ -323,6 +328,9 @@ BEGIN
     u_mm_file_reg_io_ddr             : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_IO_DDR")
                                                   PORT MAP(mm_rst, i_mm_clk, reg_io_ddr_mosi, reg_io_ddr_miso);                                
 
+    u_mm_file_reg_bsn_monitor_output : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "REG_BSN_MONITOR_OUTPUT")
+                                                  PORT MAP(mm_rst, i_mm_clk, reg_bsn_monitor_output_mosi, reg_bsn_monitor_output_miso );
+                                               
     u_mm_file_reg_eth                : mm_file GENERIC MAP(mmf_unb_file_prefix(g_sim_unb_nr, c_sim_node_nr, c_sim_node_type) & "AVS_ETH_0_MMS_REG")
                                                   PORT MAP(mm_rst, i_mm_clk, i_eth1g_reg_mosi, eth1g_reg_miso );
 
@@ -459,6 +467,15 @@ BEGIN
       coe_write_export_from_the_reg_bsn_monitor               => reg_bsn_monitor_mosi.wr,
       coe_writedata_export_from_the_reg_bsn_monitor           => reg_bsn_monitor_mosi.wrdata(c_word_w-1 DOWNTO 0),
 
+      -- the_reg_bsn_monitor_output
+      coe_address_export_from_the_reg_bsn_monitor_output      => reg_bsn_monitor_output_mosi.address(c_reg_bsn_monitor_output_adr_w-1 DOWNTO 0),
+      coe_clk_export_from_the_reg_bsn_monitor_output          => OPEN,
+      coe_read_export_from_the_reg_bsn_monitor_output         => reg_bsn_monitor_output_mosi.rd,
+      coe_readdata_export_to_the_reg_bsn_monitor_output       => reg_bsn_monitor_output_miso.rddata(c_word_w-1 DOWNTO 0),
+      coe_reset_export_from_the_reg_bsn_monitor_output        => OPEN,
+      coe_write_export_from_the_reg_bsn_monitor_output        => reg_bsn_monitor_output_mosi.wr,
+      coe_writedata_export_from_the_reg_bsn_monitor_output    => reg_bsn_monitor_output_mosi.wrdata(c_word_w-1 DOWNTO 0),
+     
       -- the_pio_debug_wave
       out_port_from_the_pio_debug_wave                        => OPEN,