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Commit dff2da7d authored by Job van Wee's avatar Job van Wee
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1 merge request!236Resolve L2SDP-704
Pipeline #28623 passed
Stage: simulation
Stage: synthesis
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applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl.vhd
+ 4
− 2
View file @ dff2da7d
...@@ -85,6 +85,7 @@ ARCHITECTURE str OF ddrctrl IS ...@@ -85,6 +85,7 @@ ARCHITECTURE str OF ddrctrl IS
CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr ); CONSTANT c_io_ddr_data_w : NATURAL := func_tech_ddr_ctlr_data_w( g_tech_ddr );
CONSTANT c_wr_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K CONSTANT c_wr_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 and independent of wr burst size, default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
CONSTANT c_rd_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K CONSTANT c_rd_fifo_depth : NATURAL := 256; -- defined at DDR side of the FIFO, >=16 AND > max number of rd burst sizes (so > c_rd_fifo_af_margin), default >= 256 because 32b*256 fits in 1 M9K so c_ctlr_data_w=256b will require 8 M9K
CONSTANT c_rd_fifo_uw_w : NATURAL := ceil_log2(c_rd_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w));
-- signals for connecting the components -- signals for connecting the components
SIGNAL ctrl_clk : STD_LOGIC; SIGNAL ctrl_clk : STD_LOGIC;
...@@ -98,7 +99,7 @@ ARCHITECTURE str OF ddrctrl IS ...@@ -98,7 +99,7 @@ ARCHITECTURE str OF ddrctrl IS
SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst; SIGNAL rd_siso : t_dp_siso := c_dp_siso_rst;
SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_init; SIGNAL rd_sosi : t_dp_sosi := c_dp_sosi_init;
SIGNAL stop : STD_LOGIC; SIGNAL stop : STD_LOGIC;
SIGNAL rd_fifo_usedw: STD_LOGIC_VECTOR(ceil_log2(c_rd_fifo_depth*(func_tech_ddr_ctlr_data_w(g_tech_ddr)/c_io_ddr_data_w) )-1 DOWNTO 0); SIGNAL rd_fifo_usedw: STD_LOGIC_VECTOR(c_rd_fifo_uw_w-1 DOWNTO 0);
SIGNAL rd_ready : STD_LOGIC; SIGNAL rd_ready : STD_LOGIC;
SIGNAL inp_ds : NATURAL; SIGNAL inp_ds : NATURAL;
SIGNAL inp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0); SIGNAL inp_bsn : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
...@@ -236,7 +237,8 @@ BEGIN ...@@ -236,7 +237,8 @@ BEGIN
g_out_data_w => g_data_w, g_out_data_w => g_data_w,
g_wr_data_w => c_io_ddr_data_w, g_wr_data_w => c_io_ddr_data_w,
g_rd_fifo_depth => c_rd_fifo_depth, g_rd_fifo_depth => c_rd_fifo_depth,
g_rd_data_w => c_io_ddr_data_w g_rd_data_w => c_io_ddr_data_w,
g_rd_fifo_uw_w => c_rd_fifo_uw_w
) )
PORT MAP( PORT MAP(
clk => clk, clk => clk,
......
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_controller.vhd
+ 19
− 79
View file @ dff2da7d
...@@ -44,7 +44,8 @@ ENTITY ddrctrl_controller IS ...@@ -44,7 +44,8 @@ ENTITY ddrctrl_controller IS
g_out_data_w : NATURAL; g_out_data_w : NATURAL;
g_wr_data_w : NATURAL; g_wr_data_w : NATURAL;
g_rd_fifo_depth : NATURAL; g_rd_fifo_depth : NATURAL;
g_rd_data_w : NATURAL g_rd_data_w : NATURAL;
g_rd_fifo_uw_w : NATURAL
); );
PORT ( PORT (
clk : IN STD_LOGIC; clk : IN STD_LOGIC;
...@@ -62,7 +63,7 @@ ENTITY ddrctrl_controller IS ...@@ -62,7 +63,7 @@ ENTITY ddrctrl_controller IS
dvr_mosi : OUT t_mem_ctlr_mosi; dvr_mosi : OUT t_mem_ctlr_mosi;
dvr_miso : IN t_mem_ctlr_miso; dvr_miso : IN t_mem_ctlr_miso;
wr_sosi : OUT t_dp_sosi; wr_sosi : OUT t_dp_sosi;
rd_fifo_usedw : IN STD_LOGIC_VECTOR(ceil_log2(g_rd_fifo_depth * (func_tech_ddr_ctlr_data_w(g_tech_ddr)/g_rd_data_w) )-1 DOWNTO 0); rd_fifo_usedw : IN STD_LOGIC_VECTOR(g_rd_fifo_uw_w-1 DOWNTO 0);
-- ddrctrl_output -- ddrctrl_output
outp_ds : OUT NATURAL; outp_ds : OUT NATURAL;
...@@ -96,7 +97,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS ...@@ -96,7 +97,7 @@ ARCHITECTURE rtl OF ddrctrl_controller IS
-- state of program -- state of program
state : t_state; state : t_state;
-- stoppping signals -- stopping signals
stop_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0); stop_adr : STD_LOGIC_VECTOR(c_adr_w-1 DOWNTO 0);
stopped : STD_LOGIC; stopped : STD_LOGIC;
...@@ -131,22 +132,11 @@ BEGIN ...@@ -131,22 +132,11 @@ BEGIN
v := q_reg; v := q_reg;
CASE q_reg.state IS CASE q_reg.state IS
WHEN RESET => WHEN RESET =>
v := c_t_reg_init; v := c_t_reg_init;
IF rst = '1' THEN
v.state := RESET;
ELSIF stop_in = '1' THEN
v.state := SET_STOP;
ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING;
ELSIF v.stopped = '1' THEN
v.state := IDLE;
ELSE
v.state := WRITING;
END IF;
WHEN WRITING => WHEN WRITING =>
-- if adr mod c_burstsize = 0 -- if adr mod c_burstsize = 0
...@@ -167,20 +157,6 @@ BEGIN ...@@ -167,20 +157,6 @@ BEGIN
v.wr_sosi := inp_sosi; v.wr_sosi := inp_sosi;
IF rst = '1' THEN
v.state := RESET;
ELSIF stop_in = '1' THEN
v.state := SET_STOP;
ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING;
ELSIF v.stopped = '1' THEN
v.state := IDLE;
ELSE
v.state := WRITING;
END IF;
WHEN SET_STOP => WHEN SET_STOP =>
--setting a stop address dependend on the g_stop_percentage --setting a stop address dependend on the g_stop_percentage
IF inp_adr+c_pof_ma >= c_max_adr THEN IF inp_adr+c_pof_ma >= c_max_adr THEN
...@@ -209,20 +185,6 @@ BEGIN ...@@ -209,20 +185,6 @@ BEGIN
v.wr_sosi := inp_sosi; v.wr_sosi := inp_sosi;
IF rst = '1' THEN
v.state := RESET;
ELSIF stop_in = '1' THEN
v.state := SET_STOP;
ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING;
ELSIF v.stopped = '1' THEN
v.state := IDLE;
ELSE
v.state := WRITING;
END IF;
WHEN STOP_WRITING => WHEN STOP_WRITING =>
v.dvr_mosi.burstbegin := '0'; v.dvr_mosi.burstbegin := '0';
-- wait until the write burst is finished -- wait until the write burst is finished
...@@ -236,11 +198,6 @@ BEGIN ...@@ -236,11 +198,6 @@ BEGIN
END IF; END IF;
IF rst = '1' THEN
v.state := RESET;
END IF;
WHEN START_READING => WHEN START_READING =>
v.rd_burst_en := '1'; v.rd_burst_en := '1';
v.dvr_mosi.wr := '0'; v.dvr_mosi.wr := '0';
...@@ -256,13 +213,7 @@ BEGIN ...@@ -256,13 +213,7 @@ BEGIN
END LOOP; END LOOP;
v.outp_bsn := TO_UVEC(TO_UINT(inp_bsn)-((inp_bsn_adr+(c_max_adr-TO_UINT(q_reg.stop_adr)))*g_wr_data_w+v.outp_ds-inp_ds)/c_rd_data_w, c_dp_stream_bsn_w); -- WRONG, wil be fixed after L2SDP-705, 706, 707 and 708 v.outp_bsn := TO_UVEC(TO_UINT(inp_bsn)-((inp_bsn_adr+(c_max_adr-TO_UINT(q_reg.stop_adr)))*g_wr_data_w+v.outp_ds-inp_ds)/c_rd_data_w, c_dp_stream_bsn_w); -- WRONG, wil be fixed after L2SDP-705, 706, 707 and 708
v.state := READING;
IF rst = '1' THEN
v.state := RESET;
ELSE
v.state := READING;
END IF;
WHEN READING => WHEN READING =>
...@@ -285,9 +236,7 @@ BEGIN ...@@ -285,9 +236,7 @@ BEGIN
v.rd_burst_en := '1'; v.rd_burst_en := '1';
END IF; END IF;
IF rst = '1' THEN IF q_reg.read_cnt >= c_max_read_cnt THEN
v.state := RESET;
ELSIF q_reg.read_cnt >= c_max_read_cnt THEN
v.state := IDLE; v.state := IDLE;
ELSE ELSE
v.state := READING; v.state := READING;
...@@ -297,9 +246,17 @@ BEGIN ...@@ -297,9 +246,17 @@ BEGIN
WHEN IDLE => WHEN IDLE =>
-- the statemachine goes to Idle when its finished or when its waiting on other components. -- the statemachine goes to Idle when its finished or when its waiting on other components.
IF rst = '1' THEN
v.state := RESET;
ELSIF stop_in = '1' THEN WHEN OTHERS =>
v := c_t_reg_init;
END CASE;
IF q_reg.state = RESET OR q_reg.state = WRITING OR q_reg.state = SET_STOP OR q_reg.state = IDLE THEN
IF stop_in = '1' THEN
v.state := SET_STOP; v.state := SET_STOP;
ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING; v.state := STOP_WRITING;
...@@ -308,30 +265,13 @@ BEGIN ...@@ -308,30 +265,13 @@ BEGIN
ELSE ELSE
v.state := WRITING; v.state := WRITING;
END IF; END IF;
END IF;
WHEN OTHERS =>
v := c_t_reg_init;
IF rst = '1' THEN IF rst = '1' THEN
v.state := RESET; v.state := RESET;
ELSIF stop_in = '1' THEN
v.state := SET_STOP;
ELSIF v.stop_adr = TO_UVEC(inp_adr, c_adr_w) AND v.stop_adr(c_bitshift_adr-1 DOWNTO 0) = c_zeros(c_bitshift_adr-1 DOWNTO 0) AND q_reg.stopped = '0' THEN
v.state := STOP_WRITING;
ELSIF v.stopped = '1' THEN
v.state := IDLE;
ELSE
v.state := WRITING;
END IF; END IF;
END CASE;
d_reg <= v; d_reg <= v;
END PROCESS; END PROCESS;
......
applications/lofar2/libraries/ddrctrl/src/vhdl/ddrctrl_output_unpack.vhd
+ 10
− 24
View file @ dff2da7d
...@@ -108,9 +108,7 @@ BEGIN ...@@ -108,9 +108,7 @@ BEGIN
END IF; END IF;
IF rst = '1' THEN IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := RESET;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := OVER_HALF; v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
v.state := IDLE; v.state := IDLE;
...@@ -138,9 +136,7 @@ BEGIN ...@@ -138,9 +136,7 @@ BEGIN
END IF; END IF;
IF rst = '1' THEN IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := RESET;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := OVER_HALF; v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
v.state := IDLE; v.state := IDLE;
...@@ -166,9 +162,7 @@ BEGIN ...@@ -166,9 +162,7 @@ BEGIN
END IF; END IF;
IF rst = '1' THEN IF v.dd_fresh = '1' THEN
v.state := RESET;
ELSIF v.dd_fresh = '1' THEN
v.state := SECOND_READ; v.state := SECOND_READ;
ELSE ELSE
v.state := IDLE; v.state := IDLE;
...@@ -191,9 +185,7 @@ BEGIN ...@@ -191,9 +185,7 @@ BEGIN
END IF; END IF;
IF rst = '1' THEN IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := RESET;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' THEN
v.state := OVER_HALF; v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '0' THEN
v.state := IDLE; v.state := IDLE;
...@@ -209,14 +201,9 @@ BEGIN ...@@ -209,14 +201,9 @@ BEGIN
v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0); v.delay_data(g_in_data_w-1 DOWNTO 0) := in_sosi.data(g_in_data_w-1 DOWNTO 0);
v.dd_fresh := '1'; v.dd_fresh := '1';
END IF; END IF;
v.state := OFF;
IF rst = '1' THEN
v.state := RESET;
ELSE
v.state := OFF;
END IF;
WHEN IDLE => WHEN IDLE =>
-- the statemachine goes to Idle when its finished or when its waiting on other components. -- the statemachine goes to Idle when its finished or when its waiting on other components.
v.out_ready := '1'; v.out_ready := '1';
...@@ -228,9 +215,7 @@ BEGIN ...@@ -228,9 +215,7 @@ BEGIN
END IF; END IF;
IF rst = '1' THEN IF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '1' THEN
v.state := RESET;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '1' THEN
v.state := OVER_HALF; v.state := OVER_HALF;
ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '0' THEN ELSIF (g_out_data_w*(v.op_data_cnt+1))+q_reg.a_of >= g_in_data_w AND v.dd_fresh = '1' AND q_reg.sr_done = '0' THEN
v.state := SECOND_READ; v.state := SECOND_READ;
...@@ -251,9 +236,7 @@ BEGIN ...@@ -251,9 +236,7 @@ BEGIN
END IF; END IF;
IF rst = '1' THEN IF in_sosi.valid = '1' THEN
v.state := RESET;
ELSIF in_sosi.valid = '1' THEN
v.state := FIRST_READ; v.state := FIRST_READ;
ELSE ELSE
v.state := OFF; v.state := OFF;
...@@ -263,6 +246,9 @@ BEGIN ...@@ -263,6 +246,9 @@ BEGIN
END CASE; END CASE;
IF rst = '1' THEN
v.state := RESET;
END IF;
d_reg <= v; d_reg <= v;
END PROCESS; END PROCESS;
......
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