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Commit df84ed9e authored by Eric Kooistra's avatar Eric Kooistra
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Added purpose and usage. Use hton() from common_pkg.vhd. The tb simulates OK.

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...@@ -19,6 +19,17 @@ ...@@ -19,6 +19,17 @@
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Purpose: Testbench for ip_stratixiv_tse_sgmii_lvds.
-- Description:
-- The testbench in /testbench/tse_sgmii_lvds/tse_sgmii_lvds_tb.vhd that is
-- generated by the MegaWizard provides an elaborate testbench. For
-- Uniboard purposes in tb/ a minimal testbench tb_tse_sgmii_lvds.vhd was
-- derived manually from the generated testbench. This tb_tse_sgmii_lvds
-- is more easy to use.
-- Usage:
-- > as 10
-- > run 50 us
LIBRARY IEEE, common_lib; LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL; USE IEEE.numeric_std.ALL;
...@@ -247,15 +258,15 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS ...@@ -247,15 +258,15 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
-- DST MAC -- DST MAC
dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w)); dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
dp_src_out.data <= (OTHERS=>'0'); dp_src_out.data <= (OTHERS=>'0');
dp_src_out.data(15 DOWNTO 0) <= htons(dst_mac_addr(15 DOWNTO 0)); -- send to itself dp_src_out.data(15 DOWNTO 0) <= hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop); proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
dp_src_out.data <= htonl(dst_mac_addr(47 DOWNTO 16)); dp_src_out.data <= hton(dst_mac_addr(47 DOWNTO 16));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop); proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
-- SRC MAC -- SRC MAC
dp_src_out.data <= htonl(src_mac_addr(31 DOWNTO 0)); dp_src_out.data <= hton(src_mac_addr(31 DOWNTO 0));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop); proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
-- SRC MAC & ETHERTYPE -- SRC MAC & ETHERTYPE
dp_src_out.data <= htons(src_mac_addr(47 DOWNTO 32)) & htons(c_eth_ethertype); dp_src_out.data <= hton(src_mac_addr(47 DOWNTO 32)) & hton(c_eth_ethertype);
-- DATA -- DATA
FOR I IN 0 TO c_nof_data_beats-1 LOOP FOR I IN 0 TO c_nof_data_beats-1 LOOP
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop); proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
...@@ -333,16 +344,16 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS ...@@ -333,16 +344,16 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
-- Verify DST MAC -- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop); proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR; ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
ASSERT dp_snk_in.data(15 DOWNTO 0) = htons(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR; ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
proc_valid(dp_clk, dp_snk_in.valid); proc_valid(dp_clk, dp_snk_in.valid);
ASSERT dp_snk_in.data(31 DOWNTO 0) = htonl(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR; ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
-- Verify SRC MAC -- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid); proc_valid(dp_clk, dp_snk_in.valid);
ASSERT dp_snk_in.data(31 DOWNTO 0) = htonl(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR; ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
-- Verify SRC MAC & ETHERTYPE -- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid); proc_valid(dp_clk, dp_snk_in.valid);
ASSERT dp_snk_in.data(31 DOWNTO 16) = htons(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR; ASSERT dp_snk_in.data(31 DOWNTO 16) = hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
ASSERT dp_snk_in.data(15 DOWNTO 0) = htons(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR; ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
-- Verify DATA -- Verify DATA
v_first := TRUE; v_first := TRUE;
proc_valid(dp_clk, dp_snk_in.valid); proc_valid(dp_clk, dp_snk_in.valid);
......
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