From df84ed9eb93d968745ed230abc5c5de3bde821ab Mon Sep 17 00:00:00 2001
From: Erik Kooistra <kooistra@astron.nl>
Date: Wed, 11 Jun 2014 10:06:27 +0000
Subject: [PATCH] Added purpose and usage. Use hton() from common_pkg.vhd. The
tb simulates OK.
---
.../vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd | 31 +++++++++++++------
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd
index df04cadee4..3e52d14989 100644
--- a/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd
+++ b/libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb/vhdl/tb_ip_stratixiv_tse_sgmii_lvds.vhd
@@ -19,6 +19,17 @@
--
-------------------------------------------------------------------------------
+-- Purpose: Testbench for ip_stratixiv_tse_sgmii_lvds.
+-- Description:
+-- The testbench in /testbench/tse_sgmii_lvds/tse_sgmii_lvds_tb.vhd that is
+-- generated by the MegaWizard provides an elaborate testbench. For
+-- Uniboard purposes in tb/ a minimal testbench tb_tse_sgmii_lvds.vhd was
+-- derived manually from the generated testbench. This tb_tse_sgmii_lvds
+-- is more easy to use.
+-- Usage:
+-- > as 10
+-- > run 50 us
+
LIBRARY IEEE, common_lib;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
@@ -247,15 +258,15 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
-- DST MAC
dp_src_out.empty <= STD_LOGIC_VECTOR(TO_UNSIGNED(0, c_tse_empty_w));
dp_src_out.data <= (OTHERS=>'0');
- dp_src_out.data(15 DOWNTO 0) <= htons(dst_mac_addr(15 DOWNTO 0)); -- send to itself
+ dp_src_out.data(15 DOWNTO 0) <= hton(dst_mac_addr(15 DOWNTO 0)); -- send to itself
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '1', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
- dp_src_out.data <= htonl(dst_mac_addr(47 DOWNTO 16));
+ dp_src_out.data <= hton(dst_mac_addr(47 DOWNTO 16));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
-- SRC MAC
- dp_src_out.data <= htonl(src_mac_addr(31 DOWNTO 0));
+ dp_src_out.data <= hton(src_mac_addr(31 DOWNTO 0));
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
-- SRC MAC & ETHERTYPE
- dp_src_out.data <= htons(src_mac_addr(47 DOWNTO 32)) & htons(c_eth_ethertype);
+ dp_src_out.data <= hton(src_mac_addr(47 DOWNTO 32)) & hton(c_eth_ethertype);
-- DATA
FOR I IN 0 TO c_nof_data_beats-1 LOOP
proc_ready_latency(c_tx_ready_latency, dp_clk, dp_src_in.ready, '1', '0', '0', dp_src_out.valid, dp_src_out.sop, dp_src_out.eop);
@@ -332,17 +343,17 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
dp_snk_out.ready <= '1';
-- Verify DST MAC
proc_valid_sop(dp_clk, dp_snk_in.valid, dp_snk_in.sop);
- ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
- ASSERT dp_snk_in.data(15 DOWNTO 0) = htons(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = X"0000" REPORT "RX: Alignment half word not zero" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(dst_mac_addr(15 DOWNTO 0)) REPORT "RX: Wrong dst_mac_addr(15 DOWNTO 0)" SEVERITY ERROR;
proc_valid(dp_clk, dp_snk_in.valid);
- ASSERT dp_snk_in.data(31 DOWNTO 0) = htonl(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(dst_mac_addr(47 DOWNTO 16)) REPORT "RX: Wrong dst_mac_addr(47 DOWNTO 16)" SEVERITY ERROR;
-- Verify SRC MAC
proc_valid(dp_clk, dp_snk_in.valid);
- ASSERT dp_snk_in.data(31 DOWNTO 0) = htonl(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 0) = hton(src_mac_addr(31 DOWNTO 0)) REPORT "RX: Wrong src_mac_addr(31 DOWNTO 0)" SEVERITY ERROR;
-- Verify SRC MAC & ETHERTYPE
proc_valid(dp_clk, dp_snk_in.valid);
- ASSERT dp_snk_in.data(31 DOWNTO 16) = htons(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
- ASSERT dp_snk_in.data(15 DOWNTO 0) = htons(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(31 DOWNTO 16) = hton(src_mac_addr(47 DOWNTO 32)) REPORT "RX: Wrong src_mac_addr(47 DOWNTO 32)" SEVERITY ERROR;
+ ASSERT dp_snk_in.data(15 DOWNTO 0) = hton(c_eth_ethertype) REPORT "RX: Wrong ethertype" SEVERITY ERROR;
-- Verify DATA
v_first := TRUE;
proc_valid(dp_clk, dp_snk_in.valid);
--
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