Updated BF and XC part of station2_sdp_ring.txt.

applications/lofar2/doc/prestudy/station2_sdp_dsp.txt

@@ -44,11 +44,14 @@ M&C:
     
     The (x+y) could be implemented as first (x+y) and then *w, or as first weight and then add. 
 
+
 *******************************************************************************
 * Subband correlator
 *******************************************************************************
 
-
+First the local crosslets are correlated with themselves and then
+the local crosslets are kept in a barrel shifter, such that they can also be correlated with the
+remote crosslets that arrive in the packets.
 
 
 *******************************************************************************

applications/lofar2/doc/prestudy/station2_sdp_hdl_components.txt

@@ -44,7 +44,7 @@
 - RSP RAD frame:
   . uses: FSI, FSN, DATA, CRC.
   . The FSN is 16 bit but the MSbit is used for the sync. The other 15 bits count blocks.
-  . After Rx frame the FSI is stripped and the CRC is replace by a BRC.
+  . After Rx frame the FSI is stripped and the CRC is replace by a boolean check (BRC).
 
 - CRC Error checking:
   The CRC is a 32 bit number, so the chance that the CRC results in a false positive is 1/2**32 ~= 2.3e-10 or 1
@@ -123,7 +123,7 @@ to ensure that all inputs have the same 64 bit sync and BSN.
 
 
 *******************************************************************************
-* BSN aligner 
+* BSN aligner dp_bsn_align_v2
 *******************************************************************************
 
 Assumptions:
@@ -441,6 +441,12 @@ Design options:
     - flush per packet or flush until empty?
     - flush per input per input or flush all inputs?
     - flush by reading, or by reset or by moving a Rd pointer
+      A FIFO can be flushed by resetting it, but this requires careful control to ensure that the reset is
+      noticed in both clock domains, and that the reset is applied in between input packets to avoid that
+      only a tail of a packet gets into a FIFO. Therefore in LOFAR 1.0 and APERTIF a FIFO is flushed by
+      reading the packets from it until it is empty. This scheme also allows flushing per packet. The
+      disadvantage of reading the packets and the discard them, is that it takes as long as reading at full
+      speed.
     - Use packet count instead of FIFO full indicator
     - can we do without flushing the FIFO? Not if we need to realign.
     - If multiple packets on a remote input get lost, then the other inputs fill up if there is no timeout. Flush

applications/lofar2/doc/prestudy/station2_to_do_erko.txt

@@ -182,15 +182,16 @@ git remote remove <remote name> # remove a remote repo
 *******************************************************************************
 Open issues:
 - Central HDL_IO_FILE_SIM_DIR = build/sim --> Project local sim dir
-- avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR copies the
-  last <buildset>, using more than one buildset at a time gices conflicts.
+- avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR
+  copies the last <buildset>, using more than one buildset at a time gices conflicts.
 
 
 
 *******************************************************************************
 * To do:
 *******************************************************************************
-- Check that the Expert users (MB, SJW, MN), Maintainers (HM) and Local users are happy with the design decisions
+- Check that the Expert users (MB, SJW, MN), Maintainers (HM) and Local users are happy with the
+  design decisions
 - H6 M&C loads section
 - H3 Functions mapping
 - H3/4 Timing (1s default, PPS, event message)
@@ -225,7 +226,7 @@ Open issues:
 - Update RadioHDL docs
 - Write RadioHDL article
 - Write HDL RL=0 article - desp_hdl_design_article.txt
-
+- XST : SNR = 1 per visibility for 10000 samples, brigthtest sourcre log 19.5 --> 4.5 dB --> T_int = 1 s is ok.