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RTSD
HDL
Commits
b8cb8ce9
Commit
b8cb8ce9
authored
5 years ago
by
Pieter Donker
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libraries/base/diag/diag.peripheral.yaml
+11
-11
11 additions, 11 deletions
libraries/base/diag/diag.peripheral.yaml
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11 additions
and
11 deletions
libraries/base/diag/diag.peripheral.yaml
+
11
−
11
View file @
b8cb8ce9
...
...
@@ -27,44 +27,44 @@ peripherals:
-
-
field_name
:
Samples_per_packet
width
:
16
address_offset
:
0x
1
address_offset
:
0x
4
reset_value
:
256
field_description
:
|
"This REG specifies the number samples in a packet"
-
-
field_name
:
Blocks_per_sync
width
:
16
address_offset
:
0x
2
address_offset
:
0x
8
reset_value
:
781250
field_description
:
|
"This REG specifies the number of packets in a sync period"
-
-
field_name
:
Gapsize
width
:
16
address_offset
:
0x
3
address_offset
:
0x
c
reset_value
:
80
field_description
:
|
"This REG specifies the gap in number of clock cycles between two consecutive packets"
-
-
field_name
:
Mem_low_address
width
:
8
address_offset
:
0x
4
address_offset
:
0x
10
field_description
:
|
"This REG specifies the starting address for reading from the waveform memory"
-
-
field_name
:
Mem_high_address
width
:
8
address_offset
:
0x
5
address_offset
:
0x
14
field_description
:
|
"This REG specifies the last address to be read when from the waveform memory"
-
-
field_name
:
BSN_init_low
address_offset
:
0x
6
address_offset
:
0x
18
field_description
:
|
"This REG specifies the lower(LSB) 32 bits [31:0] of the initialization BSN"
-
-
field_name
:
BSN_init_high
address_offset
:
0x
7
address_offset
:
0x
1c
field_description
:
|
"This REG specifies the higher(MSB) 32 bits [63:32] of the initialization BSN"
...
...
@@ -102,26 +102,26 @@ peripherals:
-
-
field_name
:
Word_cnt
access_mode
:
RO
address_offset
:
0x
1
address_offset
:
0x
4
field_description
:
|
"Word_cnt indicates the number of word currently (ST) written in the buffer. Cleared on (ST) re-write of buffer."
-
-
field_name
:
Valid_cnt_arm_ena
address_offset
:
0x
2
address_offset
:
0x
8
field_description
:
|
"Valid_cnt contains the number of valid cycles since the last sync pulse. Cleared on every sync pulse.
Arm_enable: Write to this REG to arm the system.
After the system is armed the next syn pulse will trigger the acquisition of data."
-
-
field_name
:
Reg_sync_delay
address_offset
:
0x
3
address_offset
:
0x
c
field_description
:
|
"Reg_sync_delay contains the number of valid cycles to delay/wait after an armed-syncpulse,
before the data is written to the databuffer."
-
-
field_name
:
Version
access_mode
:
RO
address_offset
:
0x
7
address_offset
:
0x
1c
field_description
:
|
"Version contains the version number of the databuffer peripheral."
slave_description
:
"
"
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