Ported tse.vhd and tse_a_stratix4.vhd technology for ip_stratixiv v9.1 from...

Ported tse.vhd and tse_a_stratix4.vhd technology for ip_stratixiv v9.1 from $UNB to technology/tse in $RADIOHDL.

libraries/technology/tse/hdllib.cfg

+hdl_lib_name = tech_tse
+hdl_library_clause_name = tech_tse_lib
+hdl_lib_uses = technology ip_stratixiv_tse_sgmii_lvds ip_stratixiv_tse_sgmii_gx common dp
+
+build_sim_dir = $HDL_BUILD_DIR
+build_synth_dir = 
+
+synth_files =
+    tech_tse_component_pkg.vhd
+    tech_tse_pkg.vhd
+    tech_tse_stratixiv.vhd
+    tech_tse.vhd
+
+test_bench_files =

libraries/technology/tse/tech_tse.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, technology_lib, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.tech_tse_component_pkg.ALL;
+USE work.tech_tse_pkg.ALL;
+USE technology_lib.technology_pkg.ALL;
+USE technology_lib.technology_select_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+
+ENTITY tse IS
+  GENERIC (
+    g_technology   : NATURAL := c_tech_select_default;
+    g_ETH_PHY      : STRING  := "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+  );
+  PORT (
+    -- Clocks and reset
+    mm_rst         : IN  STD_LOGIC;
+    mm_clk         : IN  STD_LOGIC;
+    eth_clk        : IN  STD_LOGIC;
+    tx_snk_clk     : IN  STD_LOGIC;
+    rx_src_clk     : IN  STD_LOGIC;
+    
+    -- Calibration & reconfig clock
+    cal_rec_clk    : IN  STD_LOGIC := '0';
+    
+    -- Memory Mapped Slave
+    mm_sla_in      : IN  t_mem_mosi;
+    mm_sla_out     : OUT t_mem_miso;
+    
+    -- MAC transmit interface
+    -- . ST sink
+    tx_snk_in      : IN  t_dp_sosi;
+    tx_snk_out     : OUT t_dp_siso;
+    -- . MAC specific
+    tx_mac_in      : IN  t_tse_tx_mac;
+    tx_mac_out     : OUT t_tse_tx_mac;
+    
+    -- MAC receive interface
+    -- . ST Source
+    rx_src_in      : IN  t_dp_siso;
+    rx_src_out     : OUT t_dp_sosi;
+    -- . MAC specific
+    rx_mac_out     : OUT t_tse_rx_mac;
+
+    -- PHY interface
+    eth_txp        : OUT STD_LOGIC;
+    eth_rxp        : IN  STD_LOGIC;
+
+    tse_led        : OUT t_tse_led
+  );
+END tse;
+
+ARCHITECTURE str OF tech_memory_ram_crw_crw IS
+
+BEGIN
+
+  gen_ip_stratixiv : IF g_technology=c_tech_stratixiv GENERATE
+    u0 : ENTITY work.tech_tse_stratixiv
+    GENERIC MAP (g_ETH_PHY);
+    PORT MAP (mm_rst, mm_clk, eth_clk, tx_snk_clk, rx_src_clk,
+              cal_rec_clk,
+              mm_sla_in, mm_sla_out,
+              tx_snk_in, tx_snk_out,
+              tx_mac_in, tx_mac_out,
+              rx_src_in, rx_src_out,
+              rx_mac_out,
+              eth_txp, eth_rxp,
+              tse_led);
+  END GENERATE;
+   
+END ARCHITECTURE;
\ No newline at end of file

libraries/technology/tse/tech_tse_component_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2014
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+-- Purpose: IP components declarations for various devices that get wrapped by the tech components
+
+LIBRARY IEEE, technology_lib;
+USE IEEE.STD_LOGIC_1164.ALL;
+USE technology_lib.technology_pkg.ALL;
+
+PACKAGE tech_tse_component_pkg IS
+
+  ------------------------------------------------------------------------------
+  -- ip_stratixiv
+  ------------------------------------------------------------------------------
+  
+  COMPONENT ip_stratixiv_tse_sgmii_lvds IS 
+  PORT ( 
+     address  : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
+     clk  : IN  STD_LOGIC;
+     ff_rx_a_empty  : OUT  STD_LOGIC;
+     ff_rx_a_full : OUT  STD_LOGIC;
+     ff_rx_clk  : IN  STD_LOGIC;
+     ff_rx_data : OUT  STD_LOGIC_VECTOR (31 DOWNTO 0);
+     ff_rx_dsav : OUT  STD_LOGIC;
+     ff_rx_dval : OUT  STD_LOGIC;
+     ff_rx_eop  : OUT  STD_LOGIC;
+     ff_rx_mod  : OUT  STD_LOGIC_VECTOR (1 DOWNTO 0);
+     ff_rx_rdy  : IN  STD_LOGIC;
+     ff_rx_sop  : OUT  STD_LOGIC;
+     ff_tx_a_empty  : OUT  STD_LOGIC;
+     ff_tx_a_full : OUT  STD_LOGIC;
+     ff_tx_clk  : IN  STD_LOGIC;
+     ff_tx_crc_fwd  : IN  STD_LOGIC;
+     ff_tx_data : IN  STD_LOGIC_VECTOR (31 DOWNTO 0);
+     ff_tx_eop  : IN  STD_LOGIC;
+     ff_tx_err  : IN  STD_LOGIC;
+     ff_tx_mod  : IN  STD_LOGIC_VECTOR (1 DOWNTO 0);
+     ff_tx_rdy  : OUT  STD_LOGIC;
+     ff_tx_septy  : OUT  STD_LOGIC;
+     ff_tx_sop  : IN  STD_LOGIC;
+     ff_tx_wren : IN  STD_LOGIC;
+     led_an : OUT  STD_LOGIC;
+     led_char_err : OUT  STD_LOGIC;
+     led_disp_err : OUT  STD_LOGIC;
+     led_link : OUT  STD_LOGIC;
+     read : IN  STD_LOGIC;
+     readdata : OUT  STD_LOGIC_VECTOR (31 DOWNTO 0);
+     ref_clk  : IN  STD_LOGIC;
+     reset  : IN  STD_LOGIC;
+     rx_err : OUT  STD_LOGIC_VECTOR (5 DOWNTO 0);
+     rx_err_stat  : OUT  STD_LOGIC_VECTOR (17 DOWNTO 0);
+     rx_frm_type  : OUT  STD_LOGIC_VECTOR (3 DOWNTO 0);
+     rxp  : IN  STD_LOGIC;
+     tx_ff_uflow  : OUT  STD_LOGIC;
+     txp  : OUT  STD_LOGIC;
+     waitrequest  : OUT  STD_LOGIC;
+     write  : IN  STD_LOGIC;
+     writedata  : IN  STD_LOGIC_VECTOR (31 DOWNTO 0)
+  ); 
+  END COMPONENT;
+
+  COMPONENT ip_stratixiv_tse_sgmii_gx IS 
+  PORT ( 
+     address  : IN  STD_LOGIC_VECTOR (7 DOWNTO 0);
+     clk  : IN  STD_LOGIC;
+     ff_rx_a_empty  : OUT  STD_LOGIC;
+     ff_rx_a_full : OUT  STD_LOGIC;
+     ff_rx_clk  : IN  STD_LOGIC;
+     ff_rx_data : OUT  STD_LOGIC_VECTOR (31 DOWNTO 0);
+     ff_rx_dsav : OUT  STD_LOGIC;
+     ff_rx_dval : OUT  STD_LOGIC;
+     ff_rx_eop  : OUT  STD_LOGIC;
+     ff_rx_mod  : OUT  STD_LOGIC_VECTOR (1 DOWNTO 0);
+     ff_rx_rdy  : IN  STD_LOGIC;
+     ff_rx_sop  : OUT  STD_LOGIC;
+     ff_tx_a_empty  : OUT  STD_LOGIC;
+     ff_tx_a_full : OUT  STD_LOGIC;
+     ff_tx_clk  : IN  STD_LOGIC;
+     ff_tx_crc_fwd  : IN  STD_LOGIC;
+     ff_tx_data : IN  STD_LOGIC_VECTOR (31 DOWNTO 0);
+     ff_tx_eop  : IN  STD_LOGIC;
+     ff_tx_err  : IN  STD_LOGIC;
+     ff_tx_mod  : IN  STD_LOGIC_VECTOR (1 DOWNTO 0);
+     ff_tx_rdy  : OUT  STD_LOGIC;
+     ff_tx_septy  : OUT  STD_LOGIC;
+     ff_tx_sop  : IN  STD_LOGIC;
+     ff_tx_wren : IN  STD_LOGIC;
+     gxb_cal_blk_clk  : IN  STD_LOGIC;
+     led_an : OUT  STD_LOGIC;
+     led_char_err : OUT  STD_LOGIC;
+     led_disp_err : OUT  STD_LOGIC;
+     led_link : OUT  STD_LOGIC;
+     read : IN  STD_LOGIC;
+     readdata : OUT  STD_LOGIC_VECTOR (31 DOWNTO 0);
+     reconfig_clk : IN  STD_LOGIC;
+     reconfig_fromgxb : OUT  STD_LOGIC_VECTOR (16 DOWNTO 0);
+     reconfig_togxb : IN  STD_LOGIC_VECTOR (3 DOWNTO 0);
+     ref_clk  : IN  STD_LOGIC;
+     reset  : IN  STD_LOGIC;
+     rx_err : OUT  STD_LOGIC_VECTOR (5 DOWNTO 0);
+     rx_err_stat  : OUT  STD_LOGIC_VECTOR (17 DOWNTO 0);
+     rx_frm_type  : OUT  STD_LOGIC_VECTOR (3 DOWNTO 0);
+     rxp  : IN  STD_LOGIC;
+     tx_ff_uflow  : OUT  STD_LOGIC;
+     txp  : OUT  STD_LOGIC;
+     waitrequest  : OUT  STD_LOGIC;
+     write  : IN  STD_LOGIC;
+     writedata  : IN  STD_LOGIC_VECTOR (31 DOWNTO 0)
+   ); 
+  END COMPONENT;
+
+  COMPONENT ip_stratixiv_gx_reconfig IS
+  GENERIC (
+    g_nof_gx        : NATURAL;
+    g_fromgxb_bus_w : NATURAL := 17;
+    g_togxb_bus_w   : NATURAL := 4
+  );
+  PORT (
+    reconfig_clk     : IN STD_LOGIC;
+    reconfig_fromgxb : IN STD_LOGIC_VECTOR(tech_ceil_div(g_nof_gx, 4)*g_fromgxb_bus_w-1 DOWNTO 0);
+    busy             : OUT STD_LOGIC;
+    reconfig_togxb   : OUT STD_LOGIC_VECTOR(g_togxb_bus_w-1 DOWNTO 0)
+  );
+  END COMPONENT;
+  
+END tech_tse_component_pkg;

libraries/technology/tse/tech_tse_pkg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib;
+USE IEEE.std_logic_1164.ALL;
+USE common_lib.common_pkg.ALL;
+
+PACKAGE tech_tse_pkg IS
+
+  CONSTANT c_tse_reg_addr_w           : NATURAL := 8;         -- = max 256 MAC registers
+  CONSTANT c_tse_byte_addr_w          : NATURAL := c_tse_reg_addr_w + 2;
+  CONSTANT c_tse_byte_addr_pcs_offset : NATURAL := 16#200#;   -- table 4.8, 4.9 in ug_ethernet.pdf
+  CONSTANT c_tse_data_w               : NATURAL := c_word_w;  -- = 32
+
+  CONSTANT c_tse_symbol_w             : NATURAL := c_byte_w;                       -- = 8
+  CONSTANT c_tse_symbol_max           : NATURAL := 2**c_tse_symbol_w-1;            -- = 255
+  CONSTANT c_tse_symbols_per_beat     : NATURAL := c_tse_data_w / c_tse_symbol_w;  -- = 4
+
+  CONSTANT c_tse_pcs_reg_addr_w       : NATURAL := 5;         -- = max 32 PCS registers
+  CONSTANT c_tse_pcs_halfword_addr_w  : NATURAL := c_tse_pcs_reg_addr_w + 1;  -- table 4.17 in ug_ethernet.pdf
+  CONSTANT c_tse_pcs_byte_addr_w      : NATURAL := c_tse_pcs_reg_addr_w + 2;
+  CONSTANT c_tse_pcs_data_w           : NATURAL := c_halfword_w;  -- = 16;
+
+  CONSTANT c_tse_empty_w              : NATURAL := 2;
+  CONSTANT c_tse_tx_error_w           : NATURAL := 1;
+  CONSTANT c_tse_rx_error_w           : NATURAL := 6;
+  CONSTANT c_tse_error_w              : NATURAL := largest(c_tse_tx_error_w, c_tse_rx_error_w);
+  CONSTANT c_tse_err_stat_w           : NATURAL := 18;
+  CONSTANT c_tse_frm_type_w           : NATURAL := 4;
+  
+  CONSTANT c_tse_rx_ready_latency     : NATURAL := 2;    -- 2 = default when FIFO is used
+  CONSTANT c_tse_tx_ready_latency     : NATURAL := 1;    -- c_tse_tx_ready_latency + 3 = TX_ALMOST_FULL
+
+  CONSTANT c_tse_tx_fifo_depth        : NATURAL := 256;  -- nof words for Tx FIFO
+  CONSTANT c_tse_rx_fifo_depth        : NATURAL := 256;  -- nof words for Rx FIFO
+
+  TYPE t_tse_tx_mac IS RECORD
+    -- Tx MAC inputs
+    crc_fwd  : STD_LOGIC;
+    -- Tx MAC outputs
+    septy    : STD_LOGIC;
+    a_full   : STD_LOGIC;
+    a_empty  : STD_LOGIC;
+    uflow    : STD_LOGIC;
+  END RECORD;
+
+  TYPE t_tse_rx_mac IS RECORD
+    -- Rx MAC inputs
+    -- Rx MAC outputs
+    ethertype: STD_LOGIC_VECTOR(c_tse_err_stat_w-1 DOWNTO 0);
+    frm_type : STD_LOGIC_VECTOR(c_tse_frm_type_w-1 DOWNTO 0);
+    dsav     : STD_LOGIC;
+    a_full   : STD_LOGIC;
+    a_empty  : STD_LOGIC;
+  END RECORD;
+
+  TYPE t_tse_led IS RECORD
+    an       : STD_LOGIC;
+    link     : STD_LOGIC;
+    disp_err : STD_LOGIC;
+    char_err : STD_LOGIC;
+    crs      : STD_LOGIC;
+    col      : STD_LOGIC;
+  END RECORD;
+  
+END tech_tse_pkg;
+
+
+PACKAGE BODY tech_tse_pkg IS
+END tech_tse_pkg;

libraries/technology/tse/tech_tse_stratixiv.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright (C) 2010
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- This program is free software: you can redistribute it and/or modify
+-- it under the terms of the GNU General Public License as published by
+-- the Free Software Foundation, either version 3 of the License, or
+-- (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
+--
+-------------------------------------------------------------------------------
+
+LIBRARY IEEE, common_lib, dp_lib;
+USE IEEE.std_logic_1164.ALL;
+USE work.tech_tse_component_pkg.ALL;
+USE work.tech_tse_pkg.ALL;
+USE common_lib.common_mem_pkg.ALL;
+USE dp_lib.dp_stream_pkg.ALL;
+
+-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
+LIBRARY ip_stratixiv_tse_sgmii_lvds_lib;
+LIBRARY ip_stratixiv_tse_sgmii_gx_lib;
+
+ENTITY tech_tse_stratixiv IS
+  GENERIC (
+    g_ETH_PHY      : STRING  := "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+  );
+  PORT (
+    -- Clocks and reset
+    mm_rst         : IN  STD_LOGIC;
+    mm_clk         : IN  STD_LOGIC;
+    eth_clk        : IN  STD_LOGIC;
+    tx_snk_clk     : IN  STD_LOGIC;
+    rx_src_clk     : IN  STD_LOGIC;
+    
+    -- Calibration & reconfig clock
+    cal_rec_clk    : IN  STD_LOGIC := '0';
+    
+    -- Memory Mapped Slave
+    mm_sla_in      : IN  t_mem_mosi;
+    mm_sla_out     : OUT t_mem_miso;
+    
+    -- MAC transmit interface
+    -- . ST sink
+    tx_snk_in      : IN  t_dp_sosi;
+    tx_snk_out     : OUT t_dp_siso;
+    -- . MAC specific
+    tx_mac_in      : IN  t_tse_tx_mac;
+    tx_mac_out     : OUT t_tse_tx_mac;
+    
+    -- MAC receive interface
+    -- . ST Source
+    rx_src_in      : IN  t_dp_siso;
+    rx_src_out     : OUT t_dp_sosi;
+    -- . MAC specific
+    rx_mac_out     : OUT t_tse_rx_mac;
+
+    -- PHY interface
+    eth_txp        : OUT STD_LOGIC;
+    eth_rxp        : IN  STD_LOGIC;
+
+    tse_led        : OUT t_tse_led
+  );
+END tech_tse_stratixiv;
+
+ARCHITECTURE str OF tech_tse_stratixiv IS
+
+  SIGNAL ff_tx_mod        : STD_LOGIC_VECTOR(c_tse_empty_w-1 DOWNTO 0);
+  
+  SIGNAL ff_rx_out        : t_dp_sosi := c_dp_sosi_rst;
+  
+  -- ALTGX_RECONFIG
+  CONSTANT c_nof_gx       : NATURAL := 1;
+  
+  SIGNAL reconfig_togxb   : STD_LOGIC_VECTOR (3 DOWNTO 0);
+  SIGNAL reconfig_fromgxb : STD_LOGIC_VECTOR (16 DOWNTO 0);
+    
+BEGIN
+
+  -- Default frame level flow control
+  tx_snk_out.xon <= '1';
+  
+  -- Force empty = 0 when eop = '0' to avoid TSE MAC bug of missing two bytes when empty = 2
+  ff_tx_mod <= tx_snk_in.empty(c_tse_empty_w-1 DOWNTO 0) WHEN tx_snk_in.eop='1' ELSE (OTHERS=>'0');
+
+  -- Force unused bits and fields in rx_src_out to c_dp_sosi_rst to avoid confusing 'X' in wave window
+  rx_src_out <= ff_rx_out;
+  
+  u_LVDS_tse: IF g_ETH_PHY = "LVDS" GENERATE
+
+    u_tse : ip_stratixiv_tse_sgmii_lvds
+      -- The tse_sgmii_lvds needs to be regenerated if its parameters are changed.
+      -- . ENABLE_SHIFT16  = 1   : Align packet headers to 32 bit, useful for Nios data handling
+      -- . ENABLE_SUP_ADDR = 0   : An extra MAC addresses can e.g. be used as service MAC for tests
+      -- . ENA_HASH        = 0   : A multi cast hash table can be used to address all nodes at once
+      -- . STAT_CNT_ENA    = 0   : PHY statistics counts are useful for monitoring, but not realy needed
+      -- . EG_FIFO         = 256 : Tx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+      -- . ING_FIFO        = 256 : Rx FIFO depth in nof 32 bit words (256 --> 1 M9K)
+      -- . ENABLE_SGMII    = 0   : PHY access 1000BASE-X
+    PORT MAP (
+      -- MAC transmit interface
+      -- . Avalon ST
+      ff_tx_clk     => tx_snk_clk,
+      ff_tx_rdy     => tx_snk_out.ready,
+      ff_tx_data    => tx_snk_in.data(c_tse_data_w-1 DOWNTO 0),
+      ff_tx_wren    => tx_snk_in.valid,
+      ff_tx_sop     => tx_snk_in.sop,
+      ff_tx_eop     => tx_snk_in.eop,
+      ff_tx_mod     => ff_tx_mod,
+      ff_tx_err     => tx_snk_in.err(0),
+      -- . MAC specific
+      ff_tx_crc_fwd => tx_mac_in.crc_fwd,   -- when '0' MAC inserts CRC32 after eop
+      ff_tx_septy   => tx_mac_out.septy,    -- when '0' then tx FIFO goes above section-empty threshold
+      ff_tx_a_full  => tx_mac_out.a_full,   -- when '1' then tx FIFO goes above almost-full threshold
+      ff_tx_a_empty => tx_mac_out.a_empty,  -- when '1' then tx FIFO goes below almost-empty threshold
+      tx_ff_uflow   => tx_mac_out.uflow,    -- when '1' then tx FIFO underflow
+      -- MAC receive interface
+      -- . Avalon ST
+      ff_rx_clk     => rx_src_clk,
+      ff_rx_rdy     => rx_src_in.ready,
+      ff_rx_data    => ff_rx_out.data(c_tse_data_w-1 DOWNTO 0),
+      ff_rx_dval    => ff_rx_out.valid,
+      ff_rx_sop     => ff_rx_out.sop,
+      ff_rx_eop     => ff_rx_out.eop,
+      ff_rx_mod     => ff_rx_out.empty(c_tse_empty_w-1 DOWNTO 0),
+      rx_err        => ff_rx_out.err(c_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+                                                                -- [4] PHY error on GMII
+                                                                -- [3] receive frame truncated due to FIFO overflow
+                                                                -- [2] CRC-32 error
+                                                                -- [1] invalid length
+                                                                -- [0] = OR of [1:5]
+      -- . MAC specific
+      rx_err_stat   => rx_mac_out.ethertype,  -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+      rx_frm_type   => rx_mac_out.frm_type,   -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+      ff_rx_dsav    => rx_mac_out.dsav,       -- rx frame available, but not necessarily a complete frame
+      ff_rx_a_full  => rx_mac_out.a_full,     -- when '1' then rx FIFO goes above almost-full threshold
+      ff_rx_a_empty => rx_mac_out.a_empty,    -- when '1' then rx FIFO goes below almost-empty threshold
+      -- Reset
+      reset         => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
+      -- MM control interface
+      clk           => mm_clk,
+      address       => mm_sla_in.address(c_tse_byte_addr_w-1 DOWNTO 2),
+      readdata      => mm_sla_out.rddata(c_tse_data_w-1 DOWNTO 0),
+      read          => mm_sla_in.rd,
+      writedata     => mm_sla_in.wrdata(c_tse_data_w-1 DOWNTO 0),
+      write         => mm_sla_in.wr,
+      waitrequest   => mm_sla_out.waitrequest,
+      -- Status LEDs
+      led_an        => tse_led.an,        -- '1' = autonegation completed
+      led_link      => tse_led.link,      -- '1' = successful link synchronisation
+      led_disp_err  => tse_led.disp_err,  -- TBI character error
+      led_char_err  => tse_led.char_err,  -- TBI disparity error
+      -- crs and col are only available with the SGMII bridge
+  --     led_crs       => tse_led.crs,       -- carrier sense '1' when there is tx/rx activity on the line
+  --     led_col       => tse_led.col,       -- tx collision detected (always '0' for full duplex)
+      -- Serial 1.25 Gbps
+      ref_clk       => eth_clk,
+      txp           => eth_txp,
+      rxp           => eth_rxp
+    );
+
+  END GENERATE;
+  
+  u_XCVR_tse: IF g_ETH_PHY = "XCVR" GENERATE
+
+    u_tse : ip_stratixiv_tse_sgmii_gx
+      -- The tse_sgmii_xcvr needs to be regenerated if its parameters are changed.
+      -- . ENABLE_SHIFT16  = 1   : Align packet headers to 32 bit, useful for Nios data handling
+      -- . ENABLE_SUP_ADDR = 0   : An extra MAC addresses can e.g. be used as service MAC for tests
+      -- . ENA_HASH        = 0   : A multi cast hash table can be used to address all nodes at once
+      -- . STAT_CNT_ENA    = 0   : PHY statistics counts are useful for monitoring, but not realy needed
+      -- . EG_FIFO         = 2048 : Tx FIFO depth in nof 32 bit words (2048 --> 4 M9K)
+      -- . ING_FIFO        = 2048 : Rx FIFO depth in nof 32 bit words (2048 --> 4 M9K)
+      -- . ENABLE_SGMII    = 0   : PHY access 1000BASE-X
+    PORT MAP (
+      -- MAC transmit interface
+      -- . Avalon ST
+      ff_tx_clk     => tx_snk_clk,
+      ff_tx_rdy     => tx_snk_out.ready,
+      ff_tx_data    => tx_snk_in.data(c_tse_data_w-1 DOWNTO 0),
+      ff_tx_wren    => tx_snk_in.valid,
+      ff_tx_sop     => tx_snk_in.sop,
+      ff_tx_eop     => tx_snk_in.eop,
+      ff_tx_mod     => ff_tx_mod,
+      ff_tx_err     => tx_snk_in.err(0),
+      -- . MAC specific
+      ff_tx_crc_fwd => tx_mac_in.crc_fwd,   -- when '0' MAC inserts CRC32 after eop
+      ff_tx_septy   => tx_mac_out.septy,    -- when '0' then tx FIFO goes above section-empty threshold
+      ff_tx_a_full  => tx_mac_out.a_full,   -- when '1' then tx FIFO goes above almost-full threshold
+      ff_tx_a_empty => tx_mac_out.a_empty,  -- when '1' then tx FIFO goes below almost-empty threshold
+      tx_ff_uflow   => tx_mac_out.uflow,    -- when '1' then tx FIFO underflow
+      -- MAC receive interface
+      -- . Avalon ST
+      ff_rx_clk     => rx_src_clk,
+      ff_rx_rdy     => rx_src_in.ready,
+      ff_rx_data    => ff_rx_out.data(c_tse_data_w-1 DOWNTO 0),
+      ff_rx_dval    => ff_rx_out.valid,
+      ff_rx_sop     => ff_rx_out.sop,
+      ff_rx_eop     => ff_rx_out.eop,
+      ff_rx_mod     => ff_rx_out.empty(c_tse_empty_w-1 DOWNTO 0),
+      rx_err        => ff_rx_out.err(c_tse_error_w-1 DOWNTO 0), -- [5] collision error (can only occur in half duplex mode)
+                                                                -- [4] PHY error on GMII
+                                                                -- [3] receive frame truncated due to FIFO overflow
+                                                                -- [2] CRC-32 error
+                                                                -- [1] invalid length
+                                                                -- [0] = OR of [1:5]
+      -- . MAC specific
+      rx_err_stat   => rx_mac_out.ethertype,  -- [17,16] VLAN info, [15:0] Ethernet lentgh/type field
+      rx_frm_type   => rx_mac_out.frm_type,   -- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
+      ff_rx_dsav    => rx_mac_out.dsav,       -- rx frame available, but not necessarily a complete frame
+      ff_rx_a_full  => rx_mac_out.a_full,     -- when '1' then rx FIFO goes above almost-full threshold
+      ff_rx_a_empty => rx_mac_out.a_empty,    -- when '1' then rx FIFO goes below almost-empty threshold
+      -- Reset
+      reset         => mm_rst,           -- asynchronous reset (choose synchronous to mm_clk)
+      -- MM control interface
+      clk           => mm_clk,
+      address       => mm_sla_in.address(c_tse_byte_addr_w-1 DOWNTO 2),
+      readdata      => mm_sla_out.rddata(c_tse_data_w-1 DOWNTO 0),
+      read          => mm_sla_in.rd,
+      writedata     => mm_sla_in.wrdata(c_tse_data_w-1 DOWNTO 0),
+      write         => mm_sla_in.wr,
+      waitrequest   => mm_sla_out.waitrequest,
+      -- ALTGX_RECONFIG
+      reconfig_clk      => cal_rec_clk,
+      reconfig_togxb    => reconfig_togxb,
+      reconfig_fromgxb  => reconfig_fromgxb,
+      gxb_cal_blk_clk   => eth_clk,
+      -- Status LEDs
+      led_an        => tse_led.an,        -- '1' = autonegation completed
+      led_link      => tse_led.link,      -- '1' = successful link synchronisation
+      led_disp_err  => tse_led.disp_err,  -- TBI character error
+      led_char_err  => tse_led.char_err,  -- TBI disparity error
+      -- crs and col are only available with the SGMII bridge
+  --     led_crs       => tse_led.crs,       -- carrier sense '1' when there is tx/rx activity on the line
+  --     led_col       => tse_led.col,       -- tx collision detected (always '0' for full duplex)
+      -- Serial 1.25 Gbps
+      ref_clk       => eth_clk,
+      txp           => eth_txp,
+      rxp           => eth_rxp
+    );
+    
+    u_gx_reconfig : ENTITY ip_stratixiv_gx_reconfig
+    GENERIC MAP (
+      g_nof_gx        => c_nof_gx,
+      g_fromgxb_bus_w => reconfig_fromgxb'LENGTH,
+      g_togxb_bus_w   => reconfig_togxb'LENGTH
+    );
+    PORT MAP (
+      reconfig_clk     => cal_rec_clk,
+      reconfig_fromgxb => reconfig_fromgxb,
+      busy             => open,
+      reconfig_togxb   => reconfig_togxb
+    );
+
+  END GENERATE;
+  
+END str;