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RTSD
HDL
Commits
85a5a701
Commit
85a5a701
authored
10 years ago
by
Eric Kooistra
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Made tb self checking abnd able to use run -all. Verify based on nof rx = nof tx.
parent
1e86315e
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libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
+34
-6
34 additions, 6 deletions
...ratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
with
34 additions
and
6 deletions
libraries/technology/ip_stratixiv/tse_sgmii_lvds/tb_ip_stratixiv_tse_sgmii_lvds.vhd
+
34
−
6
View file @
85a5a701
...
...
@@ -28,7 +28,7 @@
-- is more easy to use.
-- Usage:
-- > as 10
-- > run
50 us
-- > run
-all
LIBRARY
IEEE
,
common_lib
;
USE
IEEE
.
std_logic_1164
.
ALL
;
...
...
@@ -405,6 +405,7 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
-- Clocks and reset
SIGNAL
tb_end
:
STD_LOGIC
:
=
'0'
;
SIGNAL
eth_clk
:
STD_LOGIC
:
=
'0'
;
SIGNAL
sys_clk
:
STD_LOGIC
:
=
'0'
;
SIGNAL
dp_clk
:
STD_LOGIC
;
...
...
@@ -447,6 +448,10 @@ ARCHITECTURE tb OF tb_ip_stratixiv_tse_sgmii_lvds IS
SIGNAL
eth_txp
:
STD_LOGIC
;
SIGNAL
eth_rxp
:
STD_LOGIC
;
-- Verification
SIGNAL
tx_pkt_cnt
:
NATURAL
:
=
0
;
SIGNAL
rx_pkt_cnt
:
NATURAL
:
=
0
;
-- Debug signals to combine valid in and out of records
SIGNAL
dbg_mm
:
t_mm_bus
;
SIGNAL
dbg_ff_tx
:
t_tse_stream
;
...
...
@@ -599,7 +604,8 @@ BEGIN
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
-- proc_tx_packet(c_eth_src_mac, c_eth_src_mac, c_eth_ethertype, 1500, dp_clk, ff_tx_src_in, ff_tx_src_out);
FOR
I
IN
0
TO
1500
*
2
LOOP
WAIT
UNTIL
rising_edge
(
dp_clk
);
END
LOOP
;
tb_end
<=
'1'
;
WAIT
;
END
PROCESS
;
...
...
@@ -646,7 +652,7 @@ BEGIN
ff_tx_a_empty
=>
ff_tx_a_empty
,
-- when '1' then tx FIFO goes below almost-empty threshold
tx_ff_uflow
=>
ff_tx_uflow
,
-- when '1' then tx FIFO underflow
-- MAC receive interface
-- . Avalon ST
-- . Avalon ST
s
ff_rx_clk
=>
dp_clk
,
ff_rx_rdy
=>
ff_rx_snk_out
.
ready
,
ff_rx_data
=>
ff_rx_snk_in
.
data
,
...
...
@@ -665,7 +671,7 @@ BEGIN
rx_frm_type
=>
ff_rx_frm_type
,
-- [3]=VLAN, [2]=Broadcast, [1]=Multicast, [0]=Unicast
ff_rx_dsav
=>
ff_rx_dsav
,
-- rx frame available, but not necessarily a complete frame
ff_rx_a_full
=>
ff_rx_a_full
,
-- when '1' then rx FIFO goes above almost-full threshold
ff_rx_a_empty
=>
ff_rx_a_empty
,
-- when '1' then rx FIFO goes below almost-empty threshold
ff_rx_a_empty
=>
ff_rx_a_empty
,
-- when '1'
s
then rx FIFO goes below almost-empty threshold
-- Reset
reset
=>
mm_rst
,
-- asynchronous reset (choose synchronous to mm_clk)
-- MM control interface
...
...
@@ -680,7 +686,7 @@ BEGIN
led_an
=>
tse_led_an
,
-- '1' = autonegation completed
led_link
=>
tse_led_link
,
-- '1' = successful link synchronisation
led_disp_err
=>
OPEN
,
-- TBI character error
led_char_err
=>
OPEN
,
-- TBI disparity error
led_char_err
=>
OPEN
,
-- TBI disparity error
received
-- Serial 1.25 Gbps
ref_clk
=>
eth_clk
,
txp
=>
eth_txp
,
...
...
@@ -689,5 +695,27 @@ BEGIN
-- Loopback
eth_rxp
<=
eth_txp
;
-- Verification
tx_pkt_cnt
<=
tx_pkt_cnt
+
1
WHEN
ff_tx_src_out
.
sop
=
'1'
AND
rising_edge
(
dp_clk
);
rx_pkt_cnt
<=
rx_pkt_cnt
+
1
WHEN
ff_rx_snk_in
.
eop
=
'1'
AND
rising_edge
(
dp_clk
);
p_tb_end
:
PROCESS
BEGIN
WAIT
UNTIL
tb_end
=
'1'
;
-- Verify that all transmitted packets have been received
IF
tx_pkt_cnt
=
0
THEN
REPORT
"No packets were transmitted."
SEVERITY
ERROR
;
ELSIF
rx_pkt_cnt
=
0
THEN
REPORT
"No packets were received."
SEVERITY
ERROR
;
ELSIF
tx_pkt_cnt
/=
rx_pkt_cnt
THEN
REPORT
"Not all transmitted packets were received."
SEVERITY
ERROR
;
END
IF
;
-- Stop the simulation
ASSERT
FALSE
REPORT
"Simulation finished."
SEVERITY
FAILURE
;
WAIT
;
END
PROCESS
;
END
tb
;
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