added comment

libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd

@@ -64,7 +64,7 @@ ARCHITECTURE tb OF tb_dp_block_from_mm IS
 
   CONSTANT c_ram           : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
 
-  CONSTANT c_init          : NATURAL := 42; -- should be > 0
+  CONSTANT c_init          : NATURAL := 42; -- inital data counter value, should be > 0 for better test coverage.
 
   SIGNAL tb_end            : STD_LOGIC := '0';
   SIGNAL clk               : STD_LOGIC := '1';