Improved TB to check values on address 0.

libraries/base/dp/tb/vhdl/tb_dp_block_from_mm.vhd

@@ -59,11 +59,13 @@ END tb_dp_block_from_mm;
 ARCHITECTURE tb OF tb_dp_block_from_mm IS
 
   CONSTANT c_nof_blocks    : NATURAL := g_step_size / g_data_size;
-  CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks + g_data_size;  -- Size is g_data_size addresses more than needed, to check for oversized blocks.
+  CONSTANT c_ram_data_size : NATURAL := g_nof_data * g_data_size * c_nof_blocks; 
   CONSTANT c_ram_adr_w     : NATURAL := ceil_log2(c_ram_data_size);
 
   CONSTANT c_ram           : t_c_mem := (1, c_ram_adr_w, c_word_w, 2**c_ram_adr_w, '0');
 
+  CONSTANT c_init          : NATURAL := 42; -- should be > 0
+
   SIGNAL tb_end            : STD_LOGIC := '0';
   SIGNAL clk               : STD_LOGIC := '1';
   SIGNAL rst               : STD_LOGIC := '1';
@@ -117,8 +119,8 @@ BEGIN
     proc_common_wait_until_low(clk, rst);
     proc_common_wait_some_cycles(clk, 10);
     FOR i IN 0 TO c_ram_data_size - 1 LOOP
-      ram_wr_adr <= TO_UVEC(i, c_ram.adr_w);
-      ram_wr_dat <= TO_UVEC(i, c_ram.dat_w);
+      ram_wr_adr <= TO_UVEC(         i, c_ram.adr_w);
+      ram_wr_dat <= TO_UVEC(c_init + i, c_ram.dat_w);
       ram_wr_en  <= '1'; 
       proc_common_wait_some_cycles(clk, 1);
     END LOOP;
@@ -154,7 +156,7 @@ BEGIN
     WHILE tb_end = '0' LOOP
       WAIT UNTIL rising_edge(clk);
       IF block_done = '1' THEN
-        ASSERT stop_address = TO_UINT(wr_mosi.wrdata(c_ram.dat_w-1 DOWNTO 0)) REPORT "wrong data at mm_done signal, must be same as stop_address" SEVERITY ERROR;
+        ASSERT stop_address = TO_UINT(wr_mosi.wrdata(c_ram.dat_w-1 DOWNTO 0)) - c_init REPORT "wrong data at mm_done signal, must be same as stop_address + c_init" SEVERITY ERROR;
       END IF;
     END LOOP;  
     WAIT;
@@ -179,22 +181,20 @@ BEGIN
 
   ram_prev_rd_val <= ram_rd_val WHEN rising_edge(clk);
 
+  rd_data <= TO_UINT(ram_rd_dat);
   p_verify_read_ram_data: PROCESS
   BEGIN
-    rd_nxt_data  <= 1;
+    rd_nxt_data  <= c_init;
     proc_common_wait_until_high(clk, transfer_done);
     WHILE tb_end = '0' LOOP
       WAIT UNTIL rising_edge(clk);
-      rd_data <= TO_UINT(ram_rd_dat);
-      IF rd_data > 0 THEN
-        IF ram_rd_val = '1' THEN
-          ASSERT rd_data = rd_nxt_data REPORT "wrong order of RAM values" SEVERITY ERROR;
-          ASSERT rd_data <= stop_address REPORT "wrong RAM values, greater then block size" SEVERITY ERROR;
-          rd_nxt_data <= rd_nxt_data + 1;
-        END IF;
-        IF ram_rd_val = '0' AND ram_prev_rd_val = '1' THEN  -- If ram_rd_val goes from hi tot lo.
-          ASSERT rd_data = stop_address REPORT "wrong last RAM values, not same as block size" SEVERITY ERROR;
-        END IF;
+      IF ram_rd_val = '1' THEN
+        ASSERT rd_data = rd_nxt_data REPORT "wrong order of RAM values" SEVERITY ERROR;
+        ASSERT rd_data - c_init <= stop_address REPORT "wrong RAM values, greater than block size" SEVERITY ERROR;
+        rd_nxt_data <= rd_nxt_data + 1;
+      END IF;
+      IF ram_rd_val = '0' AND ram_prev_rd_val = '1' THEN  -- If ram_rd_val goes from hi tot lo.
+        ASSERT rd_data - c_init = stop_address REPORT "wrong last RAM values, not same as block size" SEVERITY ERROR;
       END IF;
     END LOOP;
     WAIT;