-Added PPS delay generic.

boards/uniboard1/libraries/unb1_board/src/vhdl/ctrl_unb1_board.vhd

@@ -55,7 +55,8 @@ ENTITY ctrl_unb1_board IS
     g_design_note     : STRING  := "UNUSED";
     g_mm_clk_freq     : NATURAL := c_unb1_board_mm_clk_freq_125M;  -- default use same MM clock as for TSE clock
     g_xo_clk_use_pll  : BOOLEAN := FALSE;
-    
+    g_dp_clk_use_xo_pll : BOOLEAN := FALSE; -- Use the 200MHz XO PLL output (no external CLK)
+
     ----------------------------------------------------------------------------
     -- External CLK
     ----------------------------------------------------------------------------
@@ -98,7 +99,16 @@ ENTITY ctrl_unb1_board IS
     g_dp_clk_phase         : STRING := "0";      -- phase offset for PLL c0, typically any phase is fine, do not use 225 +-30 degrees because there the PPS edge occurs
     g_dp_phs_clk_vec_w     : NATURAL := 0;       -- >= 0 and <= 6, nof extra PLL output clocks dp_phs_clk_vec[5:0] = [c6, c5, c4, c3, c2, c1]
     g_dp_phs_clk_divide_by : NATURAL := 32;      -- divided by factor for dp_phs_clk_vec[5:0]
-    
+
+    ----------------------------------------------------------------------------
+    -- PPS delay
+    -- . Maximum number of dp_clk cycles that pps can be delayed. Actual number
+    --   is determined dynamically by MM register.
+    --   . 0  : Don't instantiate delay component. Does not add extra MM register.
+    --   . >0 : Instantiate delay component. Adds an extra MM register.
+    ----------------------------------------------------------------------------
+    g_pps_delay_max      : NATURAL := 0;
+
     ----------------------------------------------------------------------------
     -- Use PHY Interface
     ----------------------------------------------------------------------------
@@ -119,7 +129,7 @@ ENTITY ctrl_unb1_board IS
     ----------------------------------------------------------------------------
     g_udp_offload             : BOOLEAN := FALSE;
     g_udp_offload_nof_streams : NATURAL := c_eth_nof_udp_ports;
-    
+  
     ----------------------------------------------------------------------------
     -- Auxiliary Interface
     ----------------------------------------------------------------------------
@@ -276,6 +286,7 @@ ARCHITECTURE str OF ctrl_unb1_board IS
   SIGNAL i_xo_rst_n             : STD_LOGIC;
   SIGNAL i_mm_rst               : STD_LOGIC;
 
+  SIGNAL clk200M                : STD_LOGIC := '1';
   SIGNAL clk125M                : STD_LOGIC := '1';
   SIGNAL clk40M                 : STD_LOGIC := '1';
   SIGNAL clk50M                 : STD_LOGIC := '1';
@@ -376,7 +387,7 @@ BEGIN
     );
   END GENERATE;
 
-  no_pll: IF g_dp_clk_use_pll = FALSE GENERATE
+  no_pll: IF g_dp_clk_use_pll = FALSE AND g_dp_clk_use_xo_pll=FALSE GENERATE
     dp_clk              <= ext_clk;
 
     dp_rst              <= node_ctrl_dp_rst_out;
@@ -391,6 +402,14 @@ BEGIN
                   clk50M  WHEN g_mm_clk_freq = c_unb1_board_mm_clk_freq_50M  ELSE
                   clk50M;
 
+    gen_dp_clk : IF g_dp_clk_use_xo_pll = TRUE AND g_dp_clk_use_pll=FALSE GENERATE
+      dp_clk <= clk200M;
+
+      dp_rst              <= node_ctrl_dp_rst_out;
+      node_ctrl_dp_clk_in <= dp_clk_in;
+
+    END GENERATE;
+
     u_unb1_board_clk25_pll : ENTITY work.unb1_board_clk25_pll
     GENERIC MAP (
       g_technology => g_technology
@@ -402,6 +421,7 @@ BEGIN
       c1_clk40   => clk40M,
       c2_clk50   => clk50M,
       c3_clk125  => clk125M,
+      c4_clk200  => clk200M,
       pll_locked => mm_locked_out
     );
   END GENERATE;
@@ -578,7 +598,8 @@ BEGIN
   
   u_mms_ppsh : ENTITY ppsh_lib.mms_ppsh
   GENERIC MAP (
-    g_st_clk_freq     => g_dp_clk_freq
+    g_st_clk_freq     => g_dp_clk_freq,
+    g_pps_delay_max   => g_pps_delay_max
   )
   PORT MAP (
     -- Clocks and reset