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Commit 16c839d2 authored by Daniel van der Schuur's avatar Daniel van der Schuur
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-Defaulted g_pps_delay to 0 in which case no common_pulse_delay is instantiated

 and no register is added.
parent bbc401b3
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...@@ -474,8 +474,12 @@ PACKAGE BODY common_pkg IS ...@@ -474,8 +474,12 @@ PACKAGE BODY common_pkg IS
-- Same as true_log2() except ceil_log2(1) = 1, which is needed to support -- Same as true_log2() except ceil_log2(1) = 1, which is needed to support
-- the vector width width for 1 address, to avoid NULL array for single -- the vector width width for 1 address, to avoid NULL array for single
-- word register address. -- word register address.
-- If n = 0, return 0 so we get a NULL array when using
-- STD_LOGIC_VECTOR(ceil_log2(g_addr_w)-1 DOWNTO 0), instead of an error.
BEGIN BEGIN
IF n = 1 THEN IF n = 0 THEN
RETURN 0; -- Get NULL array
ELSIF n = 1 THEN
RETURN 1; -- avoid NULL array RETURN 1; -- avoid NULL array
ELSE ELSE
RETURN true_log2(n); RETURN true_log2(n);
......
...@@ -34,7 +34,7 @@ ENTITY mms_ppsh IS ...@@ -34,7 +34,7 @@ ENTITY mms_ppsh IS
g_technology : NATURAL := c_tech_select_default; g_technology : NATURAL := c_tech_select_default;
g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
g_st_clk_freq : NATURAL := 200*10**6; -- clk frequency in Hz g_st_clk_freq : NATURAL := 200*10**6; -- clk frequency in Hz
g_pps_delay_max : NATURAL := 10 -- Maximum number of clk cycles that pps can be delayed g_pps_delay_max : NATURAL := 0 -- Maximum number of clk cycles that pps can be delayed. >0 adds an extra MM register.
); );
PORT ( PORT (
-- Clocks and reset -- Clocks and reset
...@@ -85,7 +85,6 @@ BEGIN ...@@ -85,7 +85,6 @@ BEGIN
u_ppsh : ENTITY work.ppsh u_ppsh : ENTITY work.ppsh
GENERIC MAP ( GENERIC MAP (
g_technology => g_technology,
g_clk_freq => g_st_clk_freq, g_clk_freq => g_st_clk_freq,
g_pps_delay_max => g_pps_delay_max g_pps_delay_max => g_pps_delay_max
) )
......
...@@ -57,7 +57,7 @@ ENTITY ppsh IS ...@@ -57,7 +57,7 @@ ENTITY ppsh IS
GENERIC ( GENERIC (
g_technology : NATURAL := c_tech_select_default; g_technology : NATURAL := c_tech_select_default;
g_clk_freq : NATURAL := 200 * 10**6; -- clock frequency of clk in Hz g_clk_freq : NATURAL := 200 * 10**6; -- clock frequency of clk in Hz
g_pps_delay_max : NATURAL := 10 -- Maximum number of clk cycles that pps can be delayed g_pps_delay_max : NATURAL := 0 -- Maximum number of clk cycles that pps can be delayed.
); );
PORT ( PORT (
rst : IN STD_LOGIC; rst : IN STD_LOGIC;
...@@ -164,6 +164,7 @@ BEGIN ...@@ -164,6 +164,7 @@ BEGIN
); );
-- Apply a number of clk cycles of delay to pps_ext_revt -- Apply a number of clk cycles of delay to pps_ext_revt
gen_common_pulse_delay : IF g_pps_delay_max>0 GENERATE
u_common_pulse_delay : ENTITY common_lib.common_pulse_delay u_common_pulse_delay : ENTITY common_lib.common_pulse_delay
GENERIC MAP ( GENERIC MAP (
g_pulse_delay_max => g_pps_delay_max, g_pulse_delay_max => g_pps_delay_max,
...@@ -176,6 +177,11 @@ BEGIN ...@@ -176,6 +177,11 @@ BEGIN
pulse_delay => pps_delay, pulse_delay => pps_delay,
pulse_out => pps_ext_revt_dly pulse_out => pps_ext_revt_dly
); );
END GENERATE;
no_common_pulse_delay : IF g_pps_delay_max=0 GENERATE
pps_ext_revt_dly <= pps_ext_revt;
END GENERATE;
u_capture_cnt : ENTITY common_lib.common_interval_monitor u_capture_cnt : ENTITY common_lib.common_interval_monitor
GENERIC MAP ( GENERIC MAP (
......
...@@ -45,7 +45,7 @@ ENTITY ppsh_reg IS ...@@ -45,7 +45,7 @@ ENTITY ppsh_reg IS
GENERIC ( GENERIC (
g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain g_cross_clock_domain : BOOLEAN := TRUE; -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
g_st_clk_freq : NATURAL := 200 * 10**6; -- clock frequency of st_clk in Hz g_st_clk_freq : NATURAL := 200 * 10**6; -- clock frequency of st_clk in Hz
g_pps_delay_max : NATURAL := 10 -- Maximum number of clk cycles that pps can be delayed g_pps_delay_max : NATURAL := 0 -- Maximum number of clk cycles that pps can be delayed
); );
PORT ( PORT (
-- Clocks and reset -- Clocks and reset
...@@ -74,11 +74,13 @@ END ppsh_reg; ...@@ -74,11 +74,13 @@ END ppsh_reg;
ARCHITECTURE rtl OF ppsh_reg IS ARCHITECTURE rtl OF ppsh_reg IS
CONSTANT c_nof_mm_regs : NATURAL := sel_a_b(g_pps_delay_max>0, 3, 2); -- One register more in case user want to be able to delay PPS.
-- Define the actual size of the MM slave register -- Define the actual size of the MM slave register
CONSTANT c_mm_reg : t_c_mem := (latency => 1, CONSTANT c_mm_reg : t_c_mem := (latency => 1,
adr_w => ceil_log2(2), adr_w => ceil_log2(c_nof_mm_regs),
dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers dat_w => c_word_w, -- Use MM bus data width = c_word_w = 32 for all MM registers
nof_dat => 2, nof_dat => c_nof_mm_regs,
init_sl => '0'); init_sl => '0');
-- Register access control signal in mm_clk domain -- Register access control signal in mm_clk domain
......
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