Made the tb self checking.

libraries/technology/tse/tb_tech_tse.vhd

@@ -19,28 +19,37 @@
 --
 -------------------------------------------------------------------------------
 
-LIBRARY IEEE, common_lib, dp_lib;
+-- Purpose: Testbench for tech_tse the Tripple Speed Ethernet IP technology wrapper.
+-- Description:
+--   The tb is self checking based on that tx_pkt_cnt=rx_pkt_cnt must be true
+--   at the tb_end.
+-- Usage:
+--   > as 10
+--   > run -all
+
+LIBRARY IEEE, technology_lib, common_lib, dp_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
+USE technology_lib.technology_pkg.ALL;
 USE common_lib.common_pkg.ALL;
 USE common_lib.common_mem_pkg.ALL;
 USE dp_lib.dp_stream_pkg.ALL;
 USE common_lib.eth_layers_pkg.ALL;
-USE WORK.tse_pkg.ALL;
-USE WORK.tb_tse_pkg.ALL;
+USE WORK.tech_tse_pkg.ALL;
+USE WORK.tb_tech_tse_pkg.ALL;
 
 
-ENTITY tb_tse IS
+ENTITY tb_tech_tse IS
   -- Test bench control parameters
   GENERIC (
     --   g_data_type = c_tb_tse_data_type_symbols  = 0
     --   g_data_type = c_tb_tse_data_type_counter  = 1
     g_data_type : NATURAL := c_tb_tse_data_type_symbols
   );
-END tb_tse;
+END tb_tech_tse;
 
 
-ARCHITECTURE tb OF tb_tse IS
+ARCHITECTURE tb OF tb_tech_tse IS
 
   -- as 10
   -- run 50 us
@@ -67,6 +76,7 @@ ARCHITECTURE tb OF tb_tse IS
   SIGNAL total_header_etherlen   : t_eth_total_header;
   
   -- Clocks and reset
+  SIGNAL tb_end            : STD_LOGIC := '0';
   SIGNAL eth_clk           : STD_LOGIC := '0';  -- tse reference clock
   SIGNAL sys_clk           : STD_LOGIC := '0';  -- system clock
   SIGNAL st_clk            : STD_LOGIC;         -- stream clock
@@ -102,6 +112,10 @@ ARCHITECTURE tb OF tb_tse IS
 
   SIGNAL tse_led           : t_tse_led;
 
+  -- Verification
+  SIGNAL tx_pkt_cnt     : NATURAL := 0;
+  SIGNAL rx_pkt_cnt     : NATURAL := 0;
+  
 BEGIN
 
   -- run 50 us
@@ -183,6 +197,8 @@ BEGIN
 --     proc_tse_tx_packet(total_header_loopback, 1501, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);  -- verify c_eth_payload_max
 --     proc_tse_tx_packet(total_header_loopback,  100, g_data_type, c_tx_ready_latency, c_nof_tx_not_valid, st_clk, tx_en, tx_siso, tx_sosi);
 
+    FOR I IN 0 TO 1500 * 2 LOOP WAIT UNTIL rising_edge(st_clk); END LOOP;
+    tb_end <= '1';
     WAIT;
   END PROCESS;
 
@@ -205,7 +221,11 @@ BEGIN
   END PROCESS;
 
   
-  dut : ENTITY work.tse            -- uses stratix4 architecture tse_sgmii_lvds
+  dut : ENTITY work.tech_tse
+  GENERIC MAP (
+    g_technology => c_tech_stratixiv,
+    g_ETH_PHY    => "LVDS" -- "LVDS" (default): uses LVDS IOs for ctrl_unb_common, "XCVR": uses tranceiver PHY
+  )
   PORT MAP (
     -- Clocks and reset
     mm_rst         => mm_rst,
@@ -243,4 +263,26 @@ BEGIN
   -- Loopback
   eth_rxp <= TRANSPORT eth_txp AFTER cable_delay;
 
+  -- Verification
+  tx_pkt_cnt <= tx_pkt_cnt + 1 WHEN tx_sosi.sop='1' AND rising_edge(st_clk);
+  rx_pkt_cnt <= rx_pkt_cnt + 1 WHEN rx_sosi.eop='1' AND rising_edge(st_clk);
+  
+  p_tb_end : PROCESS  
+  BEGIN
+    WAIT UNTIL tb_end='1';
+    
+    -- Verify that all transmitted packets have been received
+    IF tx_pkt_cnt=0 THEN
+      REPORT "No packets were transmitted." SEVERITY ERROR;
+    ELSIF rx_pkt_cnt=0 THEN
+      REPORT "No packets were received." SEVERITY ERROR;
+    ELSIF tx_pkt_cnt/=rx_pkt_cnt THEN
+      REPORT "Not all transmitted packets were received." SEVERITY ERROR;
+    END IF;
+    
+    -- Stop the simulation
+    ASSERT FALSE REPORT "Simulation finished." SEVERITY FAILURE;
+    WAIT;
+  END PROCESS;
+  
 END tb;