reduce bsn_align_latency from 3 to 1 to reduce fifo size

applications/arts/designs/arts_unb2b_sc3/src/vhdl/arts_unb2b_sc3_input.vhd

@@ -187,7 +187,7 @@ ARCHITECTURE str OF arts_unb2b_sc3_input IS
   CONSTANT c_block_size               : NATURAL := 96; --96 6b4 words carrying 128 48b words
   CONSTANT c_block_period             : NATURAL := 137; -- 140.625MSps/200MSps = 96/137
 
-  CONSTANT c_bsn_align_latency        : NATURAL := 3;
+  CONSTANT c_bsn_align_latency        : NATURAL := 1; --3;
   CONSTANT c_bsn_align_sop_timeout    : NATURAL := (c_bsn_align_latency + 1) * c_block_period;  -- wait somewhat more than c_bsn_align_latency periods
   CONSTANT c_dp_fifo_size             : NATURAL := (c_bsn_align_latency + 5) * c_block_size;    -- be able to fit blocks for as long as sop time out;
   CONSTANT c_dp_fifo_fill             : NATURAL := c_block_size;