Corrected tb verification of BSN at sync.

libraries/base/dp/tb/vhdl/tb_mms_dp_bsn_source_v2.vhd

@@ -53,11 +53,11 @@ architecture tb of tb_mms_dp_bsn_source_v2 is
 
   constant c_block_size                 : natural := 100;
   constant c_nof_block_per_sync         : natural := 15;
-  constant c_sync_interval              : natural := c_nof_block_per_sync * c_block_size;
-  constant c_bsn_init                   : natural := c_nof_block_per_sync;
+  constant c_nof_clk_per_sync           : natural := c_nof_block_per_sync * c_block_size;
+  constant c_bsn_init                   : natural := 7;
 
   constant c_mm_addr_dp_on              : natural := 0;
-  constant c_mm_addr_nof_block_per_sync : natural := 1;
+  constant c_mm_addr_nof_clk_per_sync   : natural := 1;
   constant c_mm_addr_bsn_lo             : natural := 2;
   constant c_mm_addr_bsn_hi             : natural := 3;
   constant c_mm_addr_bsn_time_offset    : natural := 4;
@@ -75,8 +75,6 @@ architecture tb of tb_mms_dp_bsn_source_v2 is
 
   signal mm_dp_on_status      : natural;
   signal mm_bsn               : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
-  signal mm_bsn_prev          : std_logic_vector(c_dp_stream_bsn_w - 1 downto 0) := (others => '0');
-
   signal mm_bsn_time_offset   : std_logic_vector(c_bsn_time_offset_w - 1 downto 0) := (others => '0');
 
   signal mm_mosi              : t_mem_mosi := c_mem_mosi_rst;
@@ -93,15 +91,15 @@ begin
      proc_common_wait_some_cycles(clk, 10);
 
      -- Write initial BSN and number of block per sync interval
+     -- .   -- must also write hi part to trigger transfer across clock domain
      proc_mem_mm_bus_wr(c_mm_addr_bsn_lo,                   c_bsn_init, clk, mm_miso, mm_mosi);
-     proc_mem_mm_bus_wr(c_mm_addr_bsn_hi,                                0, clk, mm_miso, mm_mosi);  -- must also write hi part to trigger transfer accross clock domain
-     proc_mem_mm_bus_wr(c_mm_addr_nof_block_per_sync, c_nof_block_per_sync, clk, mm_miso, mm_mosi);
+     proc_mem_mm_bus_wr(c_mm_addr_bsn_hi,                            0, clk, mm_miso, mm_mosi);
+     proc_mem_mm_bus_wr(c_mm_addr_nof_clk_per_sync, c_nof_clk_per_sync, clk, mm_miso, mm_mosi);
      proc_common_wait_some_cycles(clk, c_cross_clock_domain_latency);
 
      --------------------------------------------------------------------------
      -- DP on immediate
      --------------------------------------------------------------------------
-
      -- Wait until after PPS
      proc_common_wait_until_hi_lo(clk, pps);
 
@@ -118,19 +116,21 @@ begin
        report "Wrong DP on status, expected DP on immediate."
        severity ERROR;
 
-     -- Read BSN twice in same PPS interval
-     proc_common_wait_some_cycles(clk, c_block_size);
-
+     -- Read BSN in first sync interval
+     proc_common_wait_some_cycles(clk, c_nof_clk_per_sync / 2);
      proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
      proc_mem_mm_bus_rd_latency(1, clk);
      mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
      proc_mem_mm_bus_rd(c_mm_addr_bsn_hi, clk, mm_miso, mm_mosi);
      proc_mem_mm_bus_rd_latency(1, clk);
      mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
+     proc_common_wait_some_cycles(clk, 1);
+     assert TO_UINT(mm_bsn) = c_bsn_init
+       report "Wrong BSN at sync in first interval."
+       severity ERROR;
 
-     proc_common_wait_some_cycles(clk, c_block_size);
-
-     mm_bsn_prev <= mm_bsn;
+     -- Read BSN in second sync interval
+     proc_common_wait_some_cycles(clk, c_nof_clk_per_sync);
      proc_mem_mm_bus_rd(c_mm_addr_bsn_lo, clk, mm_miso, mm_mosi);
      proc_mem_mm_bus_rd_latency(1, clk);
      mm_bsn(c_word_w - 1 downto 0) <= mm_miso.rddata(c_word_w - 1 downto 0);
@@ -138,15 +138,12 @@ begin
      proc_mem_mm_bus_rd_latency(1, clk);
      mm_bsn(2 * c_word_w - 1 downto c_word_w) <= mm_miso.rddata(c_word_w - 1 downto 0);
      proc_common_wait_some_cycles(clk, 1);
-
-     -- Uncomment appropriate assert line dependent on fixed code for capture_bsn in mms_dp_bsn_source:
-     --ASSERT mm_bsn_prev<mm_bsn REPORT "Wrong BSN, expected incrementing BSN during PPS or sync interval." SEVERITY ERROR;
-     assert mm_bsn_prev = mm_bsn
-       report "Wrong BSN, expected constant BSN during PPS or sync interval."
+     assert TO_UINT(mm_bsn) = c_bsn_init + c_nof_block_per_sync
+       report "Wrong BSN at sync in second interval."
        severity ERROR;
 
      -- Run few sync intervals
-     proc_common_wait_some_cycles(clk, 3 * c_sync_interval);
+     proc_common_wait_some_cycles(clk, 3 * c_nof_clk_per_sync);
 
      -- Write DP off
      proc_mem_mm_bus_wr(c_mm_addr_dp_on, c_mm_dp_off, clk, mm_miso, mm_mosi);
@@ -184,14 +181,14 @@ begin
        report "Wrong offset, expected 5"
        severity ERROR;
 
-     proc_common_wait_some_cycles(clk, c_sync_interval);
+     proc_common_wait_some_cycles(clk, c_nof_clk_per_sync);
      tb_end <= '1';
      wait;
   end process;
 
   u_dut : entity work.mms_dp_bsn_source_v2
   generic map (
-    g_cross_clock_domain => true,  -- use FALSE when mm_clk and st_clk are the same, else use TRUE to cross the clock domain
+    g_cross_clock_domain => true,
     g_block_size         => c_block_size,
     g_nof_clk_per_sync   => 200 * 10**6,  -- overrule via MM write
     g_bsn_w              => c_dp_stream_bsn_w