Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
H
HDL
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Iterations
Wiki
Requirements
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Locked files
Build
Pipelines
Jobs
Pipeline schedules
Test cases
Artifacts
Deploy
Releases
Container registry
Model registry
Operate
Environments
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Code review analytics
Issue analytics
Insights
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
RTSD
HDL
Commits
d61c490e
Commit
d61c490e
authored
10 years ago
by
Eric Kooistra
Browse files
Options
Downloads
Patches
Plain Diff
Rename ctrl into ctlr.
parent
49acc58d
No related branches found
No related tags found
No related merge requests found
Changes
2
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
libraries/technology/ddr/tech_ddr.vhd
+3
-3
3 additions, 3 deletions
libraries/technology/ddr/tech_ddr.vhd
libraries/technology/ddr/tech_ddr_stratixiv.vhd
+20
-20
20 additions, 20 deletions
libraries/technology/ddr/tech_ddr_stratixiv.vhd
with
23 additions
and
23 deletions
libraries/technology/ddr/tech_ddr.vhd
+
3
−
3
View file @
d61c490e
...
@@ -44,8 +44,8 @@ ENTITY tech_ddr IS
...
@@ -44,8 +44,8 @@ ENTITY tech_ddr IS
ctlr_init_done
:
OUT
STD_LOGIC
;
ctlr_init_done
:
OUT
STD_LOGIC
;
ct
r
l_mosi
:
IN
t_tech_ddr_mosi
;
ctl
r
_mosi
:
IN
t_tech_ddr_mosi
;
ct
r
l_miso
:
OUT
t_tech_ddr_miso
;
ctl
r
_miso
:
OUT
t_tech_ddr_miso
;
-- PHY interface
-- PHY interface
phy_in
:
IN
t_tech_ddr_phy_in
;
phy_in
:
IN
t_tech_ddr_phy_in
;
...
@@ -65,7 +65,7 @@ BEGIN
...
@@ -65,7 +65,7 @@ BEGIN
PORT
MAP
(
ctlr_ref_clk
,
ctlr_ref_rst
,
PORT
MAP
(
ctlr_ref_clk
,
ctlr_ref_rst
,
ctlr_gen_clk
,
ctlr_gen_rst
,
ctlr_gen_clk_2x
,
ctlr_gen_rst_2x
,
ctlr_gen_clk
,
ctlr_gen_rst
,
ctlr_gen_clk_2x
,
ctlr_gen_rst_2x
,
ctlr_init_done
,
ctlr_init_done
,
ct
r
l_mosi
,
ct
r
l_miso
,
ctl
r
_mosi
,
ctl
r
_miso
,
phy_in
,
phy_io
,
phy_ou
);
phy_in
,
phy_io
,
phy_ou
);
END
GENERATE
;
END
GENERATE
;
...
...
This diff is collapsed.
Click to expand it.
libraries/technology/ddr/tech_ddr_stratixiv.vhd
+
20
−
20
View file @
d61c490e
...
@@ -47,8 +47,8 @@ ENTITY tech_ddr_stratixiv IS
...
@@ -47,8 +47,8 @@ ENTITY tech_ddr_stratixiv IS
ctlr_init_done
:
OUT
STD_LOGIC
;
ctlr_init_done
:
OUT
STD_LOGIC
;
ct
r
l_mosi
:
IN
t_tech_ddr_mosi
;
ctl
r
_mosi
:
IN
t_tech_ddr_mosi
;
ct
r
l_miso
:
OUT
t_tech_ddr_miso
;
ctl
r
_miso
:
OUT
t_tech_ddr_miso
;
-- PHY interface
-- PHY interface
phy_in
:
IN
t_tech_ddr_phy_in
;
phy_in
:
IN
t_tech_ddr_phy_in
;
...
@@ -100,16 +100,16 @@ BEGIN
...
@@ -100,16 +100,16 @@ BEGIN
mem_dqs
=>
phy_io
.
dqs
(
g_tech_ddr
.
dqs_w
-1
DOWNTO
0
),
-- .mem_dqs
mem_dqs
=>
phy_io
.
dqs
(
g_tech_ddr
.
dqs_w
-1
DOWNTO
0
),
-- .mem_dqs
mem_dqs_n
=>
phy_io
.
dqs_n
(
g_tech_ddr
.
dqs_w
-1
DOWNTO
0
),
-- .mem_dqs_n
mem_dqs_n
=>
phy_io
.
dqs_n
(
g_tech_ddr
.
dqs_w
-1
DOWNTO
0
),
-- .mem_dqs_n
mem_odt
=>
phy_ou
.
odt
(
g_tech_ddr
.
odt_w
-1
DOWNTO
0
),
-- .mem_odt
mem_odt
=>
phy_ou
.
odt
(
g_tech_ddr
.
odt_w
-1
DOWNTO
0
),
-- .mem_odt
avl_ready
=>
ct
r
l_miso
.
waitrequest_n
,
-- avl.waitrequest_n
avl_ready
=>
ctl
r
_miso
.
waitrequest_n
,
-- avl.waitrequest_n
avl_burstbegin
=>
ct
r
l_mosi
.
burstbegin
,
-- .beginbursttransfer
avl_burstbegin
=>
ctl
r
_mosi
.
burstbegin
,
-- .beginbursttransfer
avl_addr
=>
ct
r
l_mosi
.
address
(
c_ctlr_address_w
-1
DOWNTO
0
),
-- .address
avl_addr
=>
ctl
r
_mosi
.
address
(
c_ctlr_address_w
-1
DOWNTO
0
),
-- .address
avl_rdata_valid
=>
ct
r
l_miso
.
rdval
,
-- .readdatavalid
avl_rdata_valid
=>
ctl
r
_miso
.
rdval
,
-- .readdatavalid
avl_rdata
=>
ct
r
l_miso
.
rddata
(
c_ctlr_data_w
-1
DOWNTO
0
),
-- .readdata
avl_rdata
=>
ctl
r
_miso
.
rddata
(
c_ctlr_data_w
-1
DOWNTO
0
),
-- .readdata
avl_wdata
=>
ct
r
l_mosi
.
wrdata
(
c_ctlr_data_w
-1
DOWNTO
0
),
-- .writedata
avl_wdata
=>
ctl
r
_mosi
.
wrdata
(
c_ctlr_data_w
-1
DOWNTO
0
),
-- .writedata
avl_be
=>
(
OTHERS
=>
'1'
),
-- .byteenable
avl_be
=>
(
OTHERS
=>
'1'
),
-- .byteenable
avl_read_req
=>
ct
r
l_mosi
.
rd
,
-- .read
avl_read_req
=>
ctl
r
_mosi
.
rd
,
-- .read
avl_write_req
=>
ct
r
l_mosi
.
wr
,
-- .write
avl_write_req
=>
ctl
r
_mosi
.
wr
,
-- .write
avl_size
=>
ct
r
l_mosi
.
burstsize
(
g_tech_ddr
.
maxburstsize_w
-1
DOWNTO
0
),
-- .burstcount
avl_size
=>
ctl
r
_mosi
.
burstsize
(
g_tech_ddr
.
maxburstsize_w
-1
DOWNTO
0
),
-- .burstcount
local_init_done
=>
ctlr_init_done
,
-- status.local_init_done
local_init_done
=>
ctlr_init_done
,
-- status.local_init_done
local_cal_success
=>
OPEN
,
-- .local_cal_success
local_cal_success
=>
OPEN
,
-- .local_cal_success
local_cal_fail
=>
OPEN
,
-- .local_cal_fail
local_cal_fail
=>
OPEN
,
-- .local_cal_fail
...
@@ -152,16 +152,16 @@ BEGIN
...
@@ -152,16 +152,16 @@ BEGIN
mem_dqs
=>
phy_io
.
dqs
(
g_tech_ddr
.
dqs_w
-1
DOWNTO
0
),
-- .mem_dqs
mem_dqs
=>
phy_io
.
dqs
(
g_tech_ddr
.
dqs_w
-1
DOWNTO
0
),
-- .mem_dqs
mem_dqs_n
=>
phy_io
.
dqs_n
(
g_tech_ddr
.
dqs_w
-1
DOWNTO
0
),
-- .mem_dqs_n
mem_dqs_n
=>
phy_io
.
dqs_n
(
g_tech_ddr
.
dqs_w
-1
DOWNTO
0
),
-- .mem_dqs_n
mem_odt
=>
phy_ou
.
odt
(
g_tech_ddr
.
odt_w
-1
DOWNTO
0
),
-- .mem_odt
mem_odt
=>
phy_ou
.
odt
(
g_tech_ddr
.
odt_w
-1
DOWNTO
0
),
-- .mem_odt
avl_ready
=>
ct
r
l_miso
.
waitrequest_n
,
-- avl.waitrequest_n
avl_ready
=>
ctl
r
_miso
.
waitrequest_n
,
-- avl.waitrequest_n
avl_burstbegin
=>
ct
r
l_mosi
.
burstbegin
,
-- .beginbursttransfer
avl_burstbegin
=>
ctl
r
_mosi
.
burstbegin
,
-- .beginbursttransfer
avl_addr
=>
ct
r
l_mosi
.
address
(
c_ctlr_address_w
-1
DOWNTO
0
),
-- .address
avl_addr
=>
ctl
r
_mosi
.
address
(
c_ctlr_address_w
-1
DOWNTO
0
),
-- .address
avl_rdata_valid
=>
ct
r
l_miso
.
rdval
,
-- .readdatavalid
avl_rdata_valid
=>
ctl
r
_miso
.
rdval
,
-- .readdatavalid
avl_rdata
=>
ct
r
l_miso
.
rddata
(
c_ctlr_data_w
-1
DOWNTO
0
),
-- .readdata
avl_rdata
=>
ctl
r
_miso
.
rddata
(
c_ctlr_data_w
-1
DOWNTO
0
),
-- .readdata
avl_wdata
=>
ct
r
l_mosi
.
wrdata
(
c_ctlr_data_w
-1
DOWNTO
0
),
-- .writedata
avl_wdata
=>
ctl
r
_mosi
.
wrdata
(
c_ctlr_data_w
-1
DOWNTO
0
),
-- .writedata
avl_be
=>
(
OTHERS
=>
'1'
),
-- .byteenable
avl_be
=>
(
OTHERS
=>
'1'
),
-- .byteenable
avl_read_req
=>
ct
r
l_mosi
.
rd
,
-- .read
avl_read_req
=>
ctl
r
_mosi
.
rd
,
-- .read
avl_write_req
=>
ct
r
l_mosi
.
wr
,
-- .write
avl_write_req
=>
ctl
r
_mosi
.
wr
,
-- .write
avl_size
=>
ct
r
l_mosi
.
burstsize
(
g_tech_ddr
.
maxburstsize_w
-1
DOWNTO
0
),
-- .burstcount
avl_size
=>
ctl
r
_mosi
.
burstsize
(
g_tech_ddr
.
maxburstsize_w
-1
DOWNTO
0
),
-- .burstcount
local_init_done
=>
ctlr_init_done
,
-- status.local_init_done
local_init_done
=>
ctlr_init_done
,
-- status.local_init_done
local_cal_success
=>
OPEN
,
-- .local_cal_success
local_cal_success
=>
OPEN
,
-- .local_cal_success
local_cal_fail
=>
OPEN
,
-- .local_cal_fail
local_cal_fail
=>
OPEN
,
-- .local_cal_fail
...
...
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment