fixed QSYS when using mm_clk/PLL from ctrl_unb1_board.vhd

boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd

@@ -331,7 +331,7 @@ BEGIN
     u_qsys : qsys_unb1_test
     PORT MAP (
       clk_0                                         => mm_clk, 
-      reset_n                                       => mm_rst,
+      reset_n                                       => NOT mm_rst,
   
       -- the_avs_eth_0
       coe_clk_export_from_the_avs_eth_0             => OPEN,

boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd

@@ -507,13 +507,13 @@ BEGIN
   -----------------------------------------------------------------------------
   u_mmm : ENTITY work.mmm_unb1_test
   GENERIC MAP (
-    g_sim           => g_sim,
-    g_sim_unb_nr    => g_sim_unb_nr,
-    g_sim_node_nr   => g_sim_node_nr,
+    g_sim               => g_sim,
+    g_sim_unb_nr        => g_sim_unb_nr,
+    g_sim_node_nr       => g_sim_node_nr,
     g_nof_streams_10GbE => c_nof_streams_10GbE,
     g_nof_streams_ddr   => c_nof_streams_ddr,
-    g_bg_block_size => c_bg_block_size,
-    g_hdr_field_arr => c_hdr_field_arr
+    g_bg_block_size     => c_bg_block_size,
+    g_hdr_field_arr     => c_hdr_field_arr
    )
   PORT MAP(  
     mm_rst                         => mm_rst,
@@ -980,11 +980,11 @@ BEGIN
   gen_MB_I : IF g_use_MB_I = 1 GENERATE
     u_mms_ddr3_i: ENTITY io_ddr_lib.io_ddr
     GENERIC MAP (
-      g_technology       => g_technology,
-      g_tech_ddr         => c_ddr_master,
-      g_sim              => g_sim,
-      g_wr_data_w        => c_st_dat_w,
-      g_rd_data_w        => c_st_dat_w
+      g_technology           => g_technology,
+      g_tech_ddr             => c_ddr_master,
+      g_use_ddr_memory_model => g_sim,
+      g_wr_data_w            => c_st_dat_w,
+      g_rd_data_w            => c_st_dat_w
     )
     PORT MAP (
       ctlr_ref_clk       => dp_clk,