fixed QSYS when using mm_clk/PLL from ctrl_unb1_board.vhd

boards/uniboard1/designs/unb1_test/src/vhdl/mmm_unb1_test.vhd

@@ -331,7 +331,7 @@ BEGIN
     u_qsys : qsys_unb1_test
     PORT MAP (
       clk_0                                         => mm_clk, 
-      reset_n                                       => mm_rst,
+      reset_n                                       => NOT mm_rst,
   
       -- the_avs_eth_0
       coe_clk_export_from_the_avs_eth_0             => OPEN,

boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd

@@ -982,7 +982,7 @@ BEGIN
     GENERIC MAP (
       g_technology           => g_technology,
       g_tech_ddr             => c_ddr_master,
-      g_sim              => g_sim,
+      g_use_ddr_memory_model => g_sim,
       g_wr_data_w            => c_st_dat_w,
       g_rd_data_w            => c_st_dat_w
     )