Use DDR3 phy records t_tech_ddr3_phy_in from tech_ddr_pkg.

libraries/base/reorder/tb/vhdl/tb_reorder_transpose.vhd

@@ -26,10 +26,10 @@
 --
 -- Usage:
 --   > as 8
---   > run -all
+--   > run -all (about 300 us is enough)
 --   > run python script in separate terminal: "python tc_reorder_transpose.py --unb 0 --fn 0 --sim"
 --   > Stop the simulation manually in Modelsim by pressing the stop-button.
---   > Evalute the WAVE window. 
+--   > Evalute u_dr_mem_ctrl/u_io_driver/ctlr_mosi in the WAVE window for wr and rd activity. 
 
 LIBRARY IEEE, common_lib, mm_lib, diag_lib, dp_lib, io_ddr_lib, technology_lib, tech_ddr_lib;
 USE IEEE.std_logic_1164.ALL;
@@ -65,8 +65,6 @@ END tb_reorder_transpose;
 
 ARCHITECTURE tb OF tb_reorder_transpose IS
   
-  CONSTANT c_sim                : BOOLEAN := TRUE;
-
   ----------------------------------------------------------------------------
   -- Clocks and resets
   ----------------------------------------------------------------------------   
@@ -188,9 +186,9 @@ ARCHITECTURE tb OF tb_reorder_transpose IS
   SIGNAL from_mem_siso              : t_dp_siso := c_dp_siso_rdy;
   SIGNAL from_mem_sosi              : t_dp_sosi;
 
-  SIGNAL phy_in                     : t_tech_ddr_phy_in;
-  SIGNAL phy_io                     : t_tech_ddr_phy_io;
-  SIGNAL phy_ou                     : t_tech_ddr_phy_ou;  
+  SIGNAL phy_in                     : t_tech_ddr3_phy_in;
+  SIGNAL phy_io                     : t_tech_ddr3_phy_io;
+  SIGNAL phy_ou                     : t_tech_ddr3_phy_ou;  
    
 
 BEGIN
@@ -273,7 +271,6 @@ BEGIN
   ---------------------------------------------------------------------------- 
   u_dut: ENTITY work.reorder_transpose
   GENERIC MAP(
-    g_sim              => c_sim,   
     g_nof_streams      => c_bg_nof_output_streams,      
     g_in_dat_w         => c_bg_buf_dat_w/c_nof_complex, 
     g_frame_size_in    => g_wr_chunksize,               
@@ -316,7 +313,6 @@ BEGIN
   
   u_ddr_mem_ctrl : ENTITY io_ddr_lib.io_ddr
   GENERIC MAP( 
-    g_sim                    => c_sim,
     g_technology             => c_tech_select_default,    --  : NATURAL := c_tech_select_default;
     g_tech_ddr               => c_tech_ddr,      --  : t_c_tech_ddr;
     g_cross_domain_dvr_ctlr  => FALSE, --TRUE,   --  : BOOLEAN := TRUE;
@@ -364,21 +360,20 @@ BEGIN
     rd_sosi       => from_mem_sosi,
     rd_siso       => from_mem_siso,     
 
-    phy_in        => phy_in,
-    phy_io        => phy_io,  
-    phy_ou        => phy_ou
+    -- DDR3 PHY external interface
+    phy3_in       => phy_in,
+    phy3_io       => phy_io,  
+    phy3_ou       => phy_ou
   );
   
-  external_ddr_memory_model : IF c_sim=FALSE GENERATE
-    u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
-    GENERIC MAP (
-      g_tech_ddr => c_tech_ddr
-    )
-    PORT MAP (
-      mem_in => phy_ou,
-      mem_io => phy_io
-    );
-  END GENERATE;
+  u_tech_ddr_memory_model : ENTITY tech_ddr_lib.tech_ddr_memory_model
+  GENERIC MAP (
+    g_tech_ddr => c_tech_ddr
+  )
+  PORT MAP (
+    mem3_in => phy_ou,
+    mem3_io => phy_io
+  );
 
   ----------------------------------------------------------------------------
   -- Sink: data buffer real