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Commit d2eb03a5 authored by Kenneth Hiemstra's avatar Kenneth Hiemstra
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10GbE experiments

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boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
+ 2
− 1
View file @ d2eb03a5
...@@ -36,6 +36,7 @@ ARCHITECTURE tb OF tb_unb1_test_10GbE IS ...@@ -36,6 +36,7 @@ ARCHITECTURE tb OF tb_unb1_test_10GbE IS
BEGIN BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP ( GENERIC MAP (
g_design_name => "unb1_test_10GbE" g_design_name => "unb1_test_10GbE",
g_sim_node_nr => 0
); );
END tb; END tb;
boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+ 1
− 1
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...@@ -30,7 +30,7 @@ ENTITY unb1_test_10GbE IS ...@@ -30,7 +30,7 @@ ENTITY unb1_test_10GbE IS
g_design_note : STRING := "Test Design with 10GbE"; g_design_note : STRING := "Test Design with 10GbE";
g_sim : BOOLEAN := FALSE; --Overridden by TB g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; g_sim_node_nr : NATURAL := 0; -- FN0
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
......
boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd
+ 1
− 1
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...@@ -30,7 +30,7 @@ ENTITY unb1_test_lpbk IS ...@@ -30,7 +30,7 @@ ENTITY unb1_test_lpbk IS
g_design_note : STRING := "Test Design with loopback"; g_design_note : STRING := "Test Design with loopback";
g_sim : BOOLEAN := FALSE; --Overridden by TB g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0; g_sim_unb_nr : NATURAL := 0;
g_sim_node_nr : NATURAL := 0; g_sim_node_nr : NATURAL := 7;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
......
boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+ 53
− 50
View file @ d2eb03a5
...@@ -128,10 +128,12 @@ ARCHITECTURE str OF unb1_test IS ...@@ -128,10 +128,12 @@ ARCHITECTURE str OF unb1_test IS
-- Block generator -- Block generator
CONSTANT c_bg_block_size : NATURAL := 900; --CONSTANT c_bg_block_size : NATURAL := 900;
CONSTANT c_bg_block_size : NATURAL := 700;
CONSTANT c_bg_gapsize : NATURAL := 100; CONSTANT c_bg_gapsize : NATURAL := 100;
CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable --CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable
'0', -- enable_sync '0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w), TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w), TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
...@@ -733,7 +735,8 @@ BEGIN ...@@ -733,7 +735,8 @@ BEGIN
g_nof_streams => c_nof_streams, g_nof_streams => c_nof_streams,
g_data_w => c_data_w, g_data_w => c_data_w,
g_buf_nof_data => 1024, g_buf_nof_data => 1024,
g_buf_use_sync => TRUE --g_buf_use_sync => TRUE
g_buf_use_sync => FALSE
) )
PORT MAP ( PORT MAP (
mm_rst => mm_rst, mm_rst => mm_rst,
...@@ -782,7 +785,7 @@ BEGIN ...@@ -782,7 +785,7 @@ BEGIN
g_sim_level => 1, g_sim_level => 1,
g_nof_macs => c_nof_streams, g_nof_macs => c_nof_streams,
g_use_mdio => TRUE, g_use_mdio => TRUE,
g_mdio_epcs_dis => c_use_pc_target, --g_mdio_epcs_dis => c_use_pc_target,
g_pkt_len => c_def_10GbE_block_size g_pkt_len => c_def_10GbE_block_size
) )
PORT MAP ( PORT MAP (
......
boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+ 22
− 52
View file @ d2eb03a5
...@@ -51,17 +51,16 @@ USE common_lib.tb_common_pkg.ALL; ...@@ -51,17 +51,16 @@ USE common_lib.tb_common_pkg.ALL;
ENTITY tb_unb1_test IS ENTITY tb_unb1_test IS
GENERIC ( GENERIC (
g_design_name : STRING := "unb1_test" g_design_name : STRING := "unb1_test";
g_sim_unb_nr : NATURAL := 0; -- UniBoard 0
g_sim_node_nr : NATURAL := 7 -- Back node 3
); );
END tb_unb1_test; END tb_unb1_test;
ARCHITECTURE tb OF tb_unb1_test IS ARCHITECTURE tb OF tb_unb1_test IS
CONSTANT c_sim : BOOLEAN := TRUE; CONSTANT c_sim : BOOLEAN := TRUE;
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(g_sim_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(g_sim_node_nr, c_unb1_board_nof_chip_w);
CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
CONSTANT c_node_nr : NATURAL := 7; -- Back node 3
CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00"; CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0); CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
...@@ -69,7 +68,7 @@ ARCHITECTURE tb OF tb_unb1_test IS ...@@ -69,7 +68,7 @@ ARCHITECTURE tb OF tb_unb1_test IS
CONSTANT c_cable_delay : TIME := 12 ns; CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
CONSTANT c_clk_period : TIME := 5 ns; CONSTANT c_clk_period : TIME := 5 ns;
CONSTANT c_tr_clk_period : TIME := 40 ns; CONSTANT c_sa_clk_period : TIME := 6.4 ns;
CONSTANT c_pps_period : NATURAL := 1000; CONSTANT c_pps_period : NATURAL := 1000;
-- DUT -- DUT
...@@ -93,36 +92,13 @@ ARCHITECTURE tb OF tb_unb1_test IS ...@@ -93,36 +92,13 @@ ARCHITECTURE tb OF tb_unb1_test IS
SIGNAL sens_sda : STD_LOGIC; SIGNAL sens_sda : STD_LOGIC;
-- 10GbE -- 10GbE
SIGNAL tr_clk : STD_LOGIC := '0'; SIGNAL sa_clk : STD_LOGIC := '1';
-- Serial I/O -- Serial I/O
SIGNAL SI_FN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SIGNAL si_fn_lpbk_0 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL si_fn_lpbk_1 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_0_TXp : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SIGNAL si_fn_lpbk_2 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_0_RXp : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0); SIGNAL si_fn_lpbk_3 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL SI_FN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL SI_FN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL SI_FN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL SI_FN_0_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
SIGNAL SI_FN_1_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SIGNAL SI_FN_2_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SIGNAL SI_FN_3_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
SIGNAL SI_FN_RSTN : STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
SIGNAL BN_BI_0_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL BN_BI_0_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL BN_BI_1_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL BN_BI_1_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL BN_BI_2_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL BN_BI_2_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
SIGNAL BN_BI_3_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
SIGNAL BN_BI_3_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-- Model I2C sensor slaves as on the UniBoard -- Model I2C sensor slaves as on the UniBoard
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
...@@ -143,7 +119,7 @@ BEGIN ...@@ -143,7 +119,7 @@ BEGIN
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz) clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz) eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2; -- Ethernet ref clock (25 MHz) sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2; -- sa clock (156.25 MHz)
INTA <= 'H'; -- pull up INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up INTB <= 'H'; -- pull up
...@@ -161,19 +137,14 @@ BEGIN ...@@ -161,19 +137,14 @@ BEGIN
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay; eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
------------------------------------------------------------------------------
-- 10GbE Loopback model
------------------------------------------------------------------------------
SI_FN_0_RXp <= TRANSPORT SI_FN_0_TXp;-- AFTER c_cable_delay;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- DUT -- DUT
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
u_unb1_test : ENTITY work.unb1_test u_unb1_test : ENTITY work.unb1_test
GENERIC MAP ( GENERIC MAP (
g_sim => c_sim, g_sim => c_sim,
g_sim_unb_nr => c_unb_nr, g_sim_unb_nr => g_sim_unb_nr,
g_sim_node_nr => c_node_nr, g_sim_node_nr => g_sim_node_nr,
g_design_name => g_design_name g_design_name => g_design_name
) )
PORT MAP ( PORT MAP (
...@@ -198,18 +169,17 @@ BEGIN ...@@ -198,18 +169,17 @@ BEGIN
ETH_SGOUT => eth_txp, ETH_SGOUT => eth_txp,
-- Transceiver clocks -- Transceiver clocks
SA_CLK => tr_clk, SA_CLK => sa_clk,
--SB_CLK => tr_clk,
-- Serial I/O -- Serial I/O
SI_FN_0_TX => SI_FN_0_TXp, SI_FN_0_TX => si_fn_lpbk_0,
SI_FN_0_RX => SI_FN_0_RXp, SI_FN_0_RX => si_fn_lpbk_0,
SI_FN_1_TX => OPEN, SI_FN_1_TX => si_fn_lpbk_1,
SI_FN_1_RX => (OTHERS=>'0'), SI_FN_1_RX => si_fn_lpbk_1,
SI_FN_2_TX => OPEN, SI_FN_2_TX => si_fn_lpbk_2,
SI_FN_2_RX => (OTHERS=>'0'), SI_FN_2_RX => si_fn_lpbk_2,
SI_FN_3_TX => OPEN, SI_FN_3_TX => si_fn_lpbk_3,
SI_FN_3_RX => (OTHERS=>'0'), SI_FN_3_RX => si_fn_lpbk_3,
BN_BI_0_TX => OPEN, BN_BI_0_TX => OPEN,
BN_BI_0_RX => (OTHERS=>'0'), BN_BI_0_RX => (OTHERS=>'0'),
......
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