diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
index 9b8f7d9e49a79d77b43428212041eb656a41ff97..641207066e92e4eb2ecdf9dcea5d52a588114795 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/tb_unb1_test_10GbE.vhd
@@ -36,6 +36,7 @@ ARCHITECTURE tb OF tb_unb1_test_10GbE IS
BEGIN
u_tb_unb1_test : ENTITY unb1_test_lib.tb_unb1_test
GENERIC MAP (
- g_design_name => "unb1_test_10GbE"
+ g_design_name => "unb1_test_10GbE",
+ g_sim_node_nr => 0
);
END tb;
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
index 1779dd506b6ed8eeaae32ad147082954adf49efd..ee36e6b9e357f3d6ec9fd4a303bd85f97d15f933 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_10GbE/unb1_test_10GbE.vhd
@@ -30,7 +30,7 @@ ENTITY unb1_test_10GbE IS
g_design_note : STRING := "Test Design with 10GbE";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 0; -- FN0
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
diff --git a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd
index 1066f91b7925201fd246e8f2a1708217e7294058..6b5c09729eff0cb798cd1bad7e8a176fa8c2552f 100644
--- a/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd
+++ b/boards/uniboard1/designs/unb1_test/revisions/unb1_test_lpbk/unb1_test_lpbk.vhd
@@ -30,7 +30,7 @@ ENTITY unb1_test_lpbk IS
g_design_note : STRING := "Test Design with loopback";
g_sim : BOOLEAN := FALSE; --Overridden by TB
g_sim_unb_nr : NATURAL := 0;
- g_sim_node_nr : NATURAL := 0;
+ g_sim_node_nr : NATURAL := 7;
g_stamp_date : NATURAL := 0; -- Date (YYYYMMDD) -- set by QSF
g_stamp_time : NATURAL := 0; -- Time (HHMMSS) -- set by QSF
g_stamp_svn : NATURAL := 0 -- SVN revision -- set by QSF
diff --git a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
index 655243c41141d2b30b80c4f9aa091175b46198b8..2d10b3fb830b5c8ad929f0ef8e5c40372094da3e 100644
--- a/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/src/vhdl/unb1_test.vhd
@@ -47,7 +47,7 @@ ENTITY unb1_test IS
);
PORT (
-- GENERAL
- --CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
+ --CLK : IN STD_LOGIC; -- System Clock - not used as the SOPC generates dp_clk.
PPS : IN STD_LOGIC; -- System Sync
WDI : OUT STD_LOGIC; -- Watchdog Clear
INTA : INOUT STD_LOGIC; -- FPGA interconnect line
@@ -128,10 +128,12 @@ ARCHITECTURE str OF unb1_test IS
-- Block generator
- CONSTANT c_bg_block_size : NATURAL := 900;
+ --CONSTANT c_bg_block_size : NATURAL := 900;
+ CONSTANT c_bg_block_size : NATURAL := 700;
CONSTANT c_bg_gapsize : NATURAL := 100;
CONSTANT c_bg_blocks_per_sync : NATURAL := sel_a_b(g_sim, 10, 200000); -- 200000*(900+100) = 200000000 cycles = 1 second
- CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
+ --CONSTANT c_bg_ctrl : t_diag_block_gen := ('1', -- enable
+ CONSTANT c_bg_ctrl : t_diag_block_gen := ('0', -- enable
'0', -- enable_sync
TO_UVEC( c_bg_block_size, c_diag_bg_samples_per_packet_w),
TO_UVEC(c_bg_blocks_per_sync, c_diag_bg_blocks_per_sync_w),
@@ -452,68 +454,68 @@ BEGIN
g_hdr_field_arr => c_hdr_field_arr
)
PORT MAP(
- xo_clk => xo_clk,
- xo_rst_n => xo_rst_n,
- xo_rst => xo_rst,
+ xo_clk => xo_clk,
+ xo_rst_n => xo_rst_n,
+ xo_rst => xo_rst,
- mm_rst => mm_rst,
- mm_clk => mm_clk,
- mm_locked => mm_locked,
+ mm_rst => mm_rst,
+ mm_clk => mm_clk,
+ mm_locked => mm_locked,
- epcs_clk => epcs_clk,
- cal_rec_clk => cal_rec_clk,
- dp_clk => dp_clk,
+ epcs_clk => epcs_clk,
+ cal_rec_clk => cal_rec_clk,
+ dp_clk => dp_clk,
-- PIOs
- pout_wdi => pout_wdi,
+ pout_wdi => pout_wdi,
-- Manual WDI override
- reg_wdi_mosi => reg_wdi_mosi,
- reg_wdi_miso => reg_wdi_miso,
+ reg_wdi_mosi => reg_wdi_mosi,
+ reg_wdi_miso => reg_wdi_miso,
-- system_info
- reg_unb_system_info_mosi => reg_unb_system_info_mosi,
- reg_unb_system_info_miso => reg_unb_system_info_miso,
- rom_unb_system_info_mosi => rom_unb_system_info_mosi,
- rom_unb_system_info_miso => rom_unb_system_info_miso,
+ reg_unb_system_info_mosi => reg_unb_system_info_mosi,
+ reg_unb_system_info_miso => reg_unb_system_info_miso,
+ rom_unb_system_info_mosi => rom_unb_system_info_mosi,
+ rom_unb_system_info_miso => rom_unb_system_info_miso,
-- UniBoard I2C sensors
- reg_unb_sens_mosi => reg_unb_sens_mosi,
- reg_unb_sens_miso => reg_unb_sens_miso,
+ reg_unb_sens_mosi => reg_unb_sens_mosi,
+ reg_unb_sens_miso => reg_unb_sens_miso,
-- PPSH
- reg_ppsh_mosi => reg_ppsh_mosi,
- reg_ppsh_miso => reg_ppsh_miso,
+ reg_ppsh_mosi => reg_ppsh_mosi,
+ reg_ppsh_miso => reg_ppsh_miso,
-- eth1g
- eth1g_tse_clk => eth1g_tse_clk,
- eth1g_mm_rst => eth1g_mm_rst,
- eth1g_tse_mosi => eth1g_tse_mosi,
- eth1g_tse_miso => eth1g_tse_miso,
- eth1g_reg_mosi => eth1g_reg_mosi,
- eth1g_reg_miso => eth1g_reg_miso,
- eth1g_reg_interrupt => eth1g_reg_interrupt,
- eth1g_ram_mosi => eth1g_ram_mosi,
- eth1g_ram_miso => eth1g_ram_miso,
+ eth1g_tse_clk => eth1g_tse_clk,
+ eth1g_mm_rst => eth1g_mm_rst,
+ eth1g_tse_mosi => eth1g_tse_mosi,
+ eth1g_tse_miso => eth1g_tse_miso,
+ eth1g_reg_mosi => eth1g_reg_mosi,
+ eth1g_reg_miso => eth1g_reg_miso,
+ eth1g_reg_interrupt => eth1g_reg_interrupt,
+ eth1g_ram_mosi => eth1g_ram_mosi,
+ eth1g_ram_miso => eth1g_ram_miso,
-- EPCS read
- reg_dpmm_data_mosi => reg_dpmm_data_mosi,
- reg_dpmm_data_miso => reg_dpmm_data_miso,
- reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
- reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
+ reg_dpmm_data_mosi => reg_dpmm_data_mosi,
+ reg_dpmm_data_miso => reg_dpmm_data_miso,
+ reg_dpmm_ctrl_mosi => reg_dpmm_ctrl_mosi,
+ reg_dpmm_ctrl_miso => reg_dpmm_ctrl_miso,
-- EPCS write
- reg_mmdp_data_mosi => reg_mmdp_data_mosi,
- reg_mmdp_data_miso => reg_mmdp_data_miso,
- reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
- reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
+ reg_mmdp_data_mosi => reg_mmdp_data_mosi,
+ reg_mmdp_data_miso => reg_mmdp_data_miso,
+ reg_mmdp_ctrl_mosi => reg_mmdp_ctrl_mosi,
+ reg_mmdp_ctrl_miso => reg_mmdp_ctrl_miso,
- reg_epcs_mosi => reg_epcs_mosi,
- reg_epcs_miso => reg_epcs_miso,
+ reg_epcs_mosi => reg_epcs_mosi,
+ reg_epcs_miso => reg_epcs_miso,
- reg_remu_mosi => reg_remu_mosi,
- reg_remu_miso => reg_remu_miso,
+ reg_remu_mosi => reg_remu_mosi,
+ reg_remu_miso => reg_remu_miso,
ram_diag_bg_mosi => ram_diag_bg_mosi,
ram_diag_bg_miso => ram_diag_bg_miso,
@@ -540,10 +542,10 @@ BEGIN
reg_diag_data_buf_mosi => reg_diag_data_buf_mosi,
reg_diag_data_buf_miso => reg_diag_data_buf_miso,
- reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
- reg_tr_10GbE_miso => reg_tr_10GbE_miso,
- reg_tr_xaui_mosi => reg_tr_xaui_mosi,
- reg_tr_xaui_miso => reg_tr_xaui_miso
+ reg_tr_10GbE_mosi => reg_tr_10GbE_mosi,
+ reg_tr_10GbE_miso => reg_tr_10GbE_miso,
+ reg_tr_xaui_mosi => reg_tr_xaui_mosi,
+ reg_tr_xaui_miso => reg_tr_xaui_miso
);
@@ -733,7 +735,8 @@ BEGIN
g_nof_streams => c_nof_streams,
g_data_w => c_data_w,
g_buf_nof_data => 1024,
- g_buf_use_sync => TRUE
+ --g_buf_use_sync => TRUE
+ g_buf_use_sync => FALSE
)
PORT MAP (
mm_rst => mm_rst,
@@ -782,7 +785,7 @@ BEGIN
g_sim_level => 1,
g_nof_macs => c_nof_streams,
g_use_mdio => TRUE,
- g_mdio_epcs_dis => c_use_pc_target,
+ --g_mdio_epcs_dis => c_use_pc_target,
g_pkt_len => c_def_10GbE_block_size
)
PORT MAP (
diff --git a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
index 279315a4fc3d3920e69ed4e00f16792f69376383..16bc28cd5539d1e05e711c08969e2b8b192e5dce 100644
--- a/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
+++ b/boards/uniboard1/designs/unb1_test/tb/vhdl/tb_unb1_test.vhd
@@ -51,17 +51,16 @@ USE common_lib.tb_common_pkg.ALL;
ENTITY tb_unb1_test IS
GENERIC (
- g_design_name : STRING := "unb1_test"
+ g_design_name : STRING := "unb1_test";
+ g_sim_unb_nr : NATURAL := 0; -- UniBoard 0
+ g_sim_node_nr : NATURAL := 7 -- Back node 3
);
END tb_unb1_test;
ARCHITECTURE tb OF tb_unb1_test IS
CONSTANT c_sim : BOOLEAN := TRUE;
-
- CONSTANT c_unb_nr : NATURAL := 0; -- UniBoard 0
- CONSTANT c_node_nr : NATURAL := 7; -- Back node 3
- CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(c_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(c_node_nr, c_unb1_board_nof_chip_w);
+ CONSTANT c_id : STD_LOGIC_VECTOR(7 DOWNTO 0) := TO_UVEC(g_sim_unb_nr, c_unb1_board_nof_uniboard_w) & TO_UVEC(g_sim_node_nr, c_unb1_board_nof_chip_w);
CONSTANT c_version : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
CONSTANT c_fw_version : t_unb1_board_fw_version := (1, 0);
@@ -69,7 +68,7 @@ ARCHITECTURE tb OF tb_unb1_test IS
CONSTANT c_cable_delay : TIME := 12 ns;
CONSTANT c_eth_clk_period : TIME := 40 ns; -- 25 MHz XO on UniBoard
CONSTANT c_clk_period : TIME := 5 ns;
- CONSTANT c_tr_clk_period : TIME := 40 ns;
+ CONSTANT c_sa_clk_period : TIME := 6.4 ns;
CONSTANT c_pps_period : NATURAL := 1000;
-- DUT
@@ -93,36 +92,13 @@ ARCHITECTURE tb OF tb_unb1_test IS
SIGNAL sens_sda : STD_LOGIC;
-- 10GbE
- SIGNAL tr_clk : STD_LOGIC := '0';
+ SIGNAL sa_clk : STD_LOGIC := '1';
-- Serial I/O
- SIGNAL SI_FN_0_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL SI_FN_0_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL SI_FN_0_TXp : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL SI_FN_0_RXp : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-
- SIGNAL SI_FN_1_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL SI_FN_1_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL SI_FN_2_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL SI_FN_2_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL SI_FN_3_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL SI_FN_3_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-
- SIGNAL SI_FN_0_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0); -- (0 = LASI; 1=MDC; 2=MDIO)
- SIGNAL SI_FN_1_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SIGNAL SI_FN_2_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SIGNAL SI_FN_3_CNTRL : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.cntrl_w-1 DOWNTO 0);
- SIGNAL SI_FN_RSTN : STD_LOGIC := '1'; -- ResetN is pulled up in the Vitesse chip, but pulled down again by external 1k resistor.
-
- SIGNAL BN_BI_0_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL BN_BI_0_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL BN_BI_1_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL BN_BI_1_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL BN_BI_2_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL BN_BI_2_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
- SIGNAL BN_BI_3_TX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
- SIGNAL BN_BI_3_RX : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0) := (OTHERS=>'0');
-
+ SIGNAL si_fn_lpbk_0 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_lpbk_1 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_lpbk_2 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
+ SIGNAL si_fn_lpbk_3 : STD_LOGIC_VECTOR(c_unb1_board_ci.tr.bus_w-1 DOWNTO 0);
-- Model I2C sensor slaves as on the UniBoard
CONSTANT c_fpga_temp_address : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0011000"; -- MAX1618 address LOW LOW
@@ -143,7 +119,7 @@ BEGIN
----------------------------------------------------------------------------
clk <= NOT clk AFTER c_clk_period/2; -- External clock (200 MHz)
eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2; -- Ethernet ref clock (25 MHz)
- tr_clk <= NOT tr_clk AFTER c_tr_clk_period/2; -- Ethernet ref clock (25 MHz)
+ sa_clk <= NOT sa_clk AFTER c_sa_clk_period/2; -- sa clock (156.25 MHz)
INTA <= 'H'; -- pull up
INTB <= 'H'; -- pull up
@@ -161,19 +137,14 @@ BEGIN
------------------------------------------------------------------------------
eth_rxp <= TRANSPORT eth_txp AFTER c_cable_delay;
- ------------------------------------------------------------------------------
- -- 10GbE Loopback model
- ------------------------------------------------------------------------------
- SI_FN_0_RXp <= TRANSPORT SI_FN_0_TXp;-- AFTER c_cable_delay;
-
------------------------------------------------------------------------------
-- DUT
------------------------------------------------------------------------------
u_unb1_test : ENTITY work.unb1_test
GENERIC MAP (
g_sim => c_sim,
- g_sim_unb_nr => c_unb_nr,
- g_sim_node_nr => c_node_nr,
+ g_sim_unb_nr => g_sim_unb_nr,
+ g_sim_node_nr => g_sim_node_nr,
g_design_name => g_design_name
)
PORT MAP (
@@ -198,18 +169,17 @@ BEGIN
ETH_SGOUT => eth_txp,
-- Transceiver clocks
- SA_CLK => tr_clk,
- --SB_CLK => tr_clk,
+ SA_CLK => sa_clk,
-- Serial I/O
- SI_FN_0_TX => SI_FN_0_TXp,
- SI_FN_0_RX => SI_FN_0_RXp,
- SI_FN_1_TX => OPEN,
- SI_FN_1_RX => (OTHERS=>'0'),
- SI_FN_2_TX => OPEN,
- SI_FN_2_RX => (OTHERS=>'0'),
- SI_FN_3_TX => OPEN,
- SI_FN_3_RX => (OTHERS=>'0'),
+ SI_FN_0_TX => si_fn_lpbk_0,
+ SI_FN_0_RX => si_fn_lpbk_0,
+ SI_FN_1_TX => si_fn_lpbk_1,
+ SI_FN_1_RX => si_fn_lpbk_1,
+ SI_FN_2_TX => si_fn_lpbk_2,
+ SI_FN_2_RX => si_fn_lpbk_2,
+ SI_FN_3_TX => si_fn_lpbk_3,
+ SI_FN_3_RX => si_fn_lpbk_3,
BN_BI_0_TX => OPEN,
BN_BI_0_RX => (OTHERS=>'0'),