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Commit d129e115 authored by Jonathan Hargreaves's avatar Jonathan Hargreaves
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Merge branch 'master' into stat-313 

Conflicts:
	boards/uniboard2b/libraries/unb2b_board/src/vhdl/unb2b_board_system_info_reg.vhd
parents ce4e177f 942d8f38
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2 merge requests!6Master,!4Stat 313
This commit is part of merge request !4. Comments created here will be created in the context of that merge request.
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applications/lofar2/doc/prestudy/desp_howtools_erko.txt
+ 183
− 12
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* RadioHDL with GIT (LOFAR2.0)
* RadioHDL with SVN (APERTIF/ARTS)
* GIT workflow
* Confluence
* Polarion
* Latex
* Markdown
*******************************************************************************
* RadioHDL with GIT
*******************************************************************************
# Setup vendor specific environment variables in .bashrc
* bashrc defines root directories that contain one or more versions of tool installations
- define MENTOR_DIR : modelsim installations
- define ALTERA_DIR : altera installations
- define MODELSIM_ALTERA_LIBS_DIR : compiled modelsim simulation libraries for altera components
- LM_LICENSE_FILE=<our_license@our_compagny>
# Setup RadioHDL development environment for hdl/. The hdl/libraries, hdl/boards and hdl/applications are
# developed simultaneously and therefor in one git hdl/ repository
> cd ~/git/hdl
> . ./init_hdl.sh
* init_hdl.sh defines:
- RADIOHDL_WORK directory for where the source code resides
- RADIOHDL_BUILD_DIR directory for where the targets will be build
- HDL_IOFILE_SIM_DIR=${RADIOHDL_BUILD_DIR}/sim for simulating with Modelsim using file IO
* init_hdl.sh copies git user_components.ipx into Altera dir's
- cp ${RADIOHDL_WORK}/hdl_user_components.ipx $altera_dir/ip/altera/user_components.ipx
* init_hdl.sh automatically also sources ../radiohdl/init_radiohdl.sh if necessary
source also radiohdl tools
. ../radiohdl/init_radiohdl.sh
* init_radiohdl.sh defines:
- RADIOHDL_GEAR directory of where the init_radiohdl.sh is located
- RADIOHDL_BUILD_DIR = ${RADIOHDL_BUILD_DIR}/build if not already defined
- RADIOHDL_CONFIG = ${RADIOHDL_GEAR}/config if not already defined
* init_radiohdl.sh extends:
- PATH with ${RADIOHDL_GEAR}/core
${RADIOHDL_GEAR}/quartus
${RADIOHDL_GEAR}/modelsim
- PYTHONPATH with ${RADIOHDL_GEAR}/core
${RADIOHDL_GEAR}/components
> compile_altera_simlibs unb1 # creates build/unb1/hdl_libraries_ip_stratixiv.txt
# creates build/quartus/<tool version> simulation models that need to be moved
# manually to $MODELSIM_ALTERA_LIBS_DIR/<tool version>
> generate_ip_libs unb1 # creates build/unb1/qmegawiz/
# creates build/unb1/quartus_sh --> empty dir, why is it there?
> quartus_config unb1 # creates build/unb1/quartus/<hdllib libraries> for synthesis
# creates build/unb1/quartus/technology_select_pkg.vhd
> modelsim_config unb1 # creates build/unb1/modelsim/<hdllib libraries> for simulation
# creates build/unb1/modelsim/modelsim_project_files.txt for Modelsim commands.do
# creates build/unb1/modelsim/technology_select_pkg.vhd
> run_qsys unb1 unb1_minimal_qsys # creates QSYS block in build/unb1/quartus/unb1_minimal_qsys
> run_qcomp unb1 unb1_minimal_qsys # creates
> run_modelsim unb1 &
*******************************************************************************
* RadioHDL with SVN
*******************************************************************************
echo "Uniboard trunk is selected"
export SVN=${HOME}/svnroot/UniBoard_FP7
#Setup RadioHDL environment for UniBoard2 and and new Uniboard1 applications
. ${SVN}/RadioHDL/trunk/tools/setup_radiohdl.sh
# Support old UniBoard environment (including Aarfaac and Paasar)
. ${SVN}/RadioHDL/trunk/tools/setup_unb.sh
*******************************************************************************
* GIT workflow
......@@ -28,6 +111,7 @@ cd ~/git
git init # start new repo at this dir, creates .git/
git clone # get and start with existing repo
git clone git@git.astron.nl:desp/args.git
git clone git@git.astron.nl:desp/sampy.git
git status # what is in stage area and what is modified
......@@ -114,12 +198,44 @@ git status
# delete branch and fetch npstream if the pull request was accepted
git remote remove <remote name> # remove a remote repo
Review process
* Jira ticket defines the work to be done
* coder works on branch with Jira ticket number
* manually run regression test to test the changes (for Casacore SW the merge
request makes github automatically issue a regression test in the cloud)
* coder does merge request to reviewer
* gitlab will warn if the branch will lead to a merge conflict, the coder then
first has to fix the merge conflict by merging the master to the branch.
The merge can use merging or rebasing, Ger typically uses merging.
* reviewer reviews the code per line and in general comments in gitlab GUI,
so no need to pull the branch locally
* Use 'Open in Web IDE' button to see max about 10 changes, Use 'Changes' menu
to see all changes. Green is new file, orange is change file, + is new lines
- is removed lines.
* coder does updates on branch until both coder and reviewer are ok, they are
notified by gitlab
* when review is done then the reviewer does the merge.
* the merge automatically deletes the branch (if selected to do so in gitlab)
locally the coder manually needs to delete the branch
* Use Jira tag in commit message to have link between GIT and Jira. The link
was made via Settings/Intergations/Jira
Note:
* In github a merge request is called a pull request
* Default a pull pulls the master. Typically it is not necessary to pull a
branch because the reviewer does not need to compile and run the code and
because typically only one coder works on a branch.
*******************************************************************************
* Confluence:
*******************************************************************************
- space tools menu links onder om secties the ordenen.
- space tools menu, content tools, custom export to PDF --> to export multiple
pages to PDF and to preserve th ASTRON logo in the export
*******************************************************************************
......@@ -140,4 +256,59 @@ git remote remove <remote name> # remove a remote repo
.
\ No newline at end of file
*******************************************************************************
* Markdown
*******************************************************************************
Text will wrap.
Backslash is escape chararcter.
# Heading 1
## Heading 2
### Heading 3
#### Heading 4
##### Heading 5
###### Heading 6
Horizontal rules three or more of ***, ___, ---
*italic*
_italic_
**bold**
__bold__
**bold and _bolditalic_** combined
`boxed`
~~strike through~~
Block quotes (alinea with an indent bar):
> Block text will wrap
Unordered list using *, -, +, indent >= 1 space
* Main item 1
* Main item 2
* sub item 2a use 2 trailing spaces for return inside paragraph
* sub item 2b
Ordered list
1. Main item 1
2. Main item 2
2.1 sub item 2a
2.2 sub item 2b
Images
![Logo](path to image file)
![Logo](web link to image file)
![Logo][image1]
[image1]:web link to image file
Links:
[ASTRON]:https://www.astron.nl
Table:
|col1 | col2| Col3 | column titles
|---|:---:|--:| >= 3 dashes, colon for left, center, right align
| row text | row text | row text|
| row text | row text | row text|
applications/lofar2/doc/prestudy/desp_radiohdl_article.txt
+ 51
− 157
View file @ d129e115
......@@ -4,112 +4,69 @@
Title: RadioHDL build environment for FPGA firmware
Purpose: Ease the FPGA firmware development flow
How:
- Organize the /source/ code in separate /libraries/
- /Automate/ the flow from source code to target file in a transparent way
- Use /configuration/ files and /target/ specific scripts
The name RadioHDL reflects that it was first used for HDL development in FPGA projects for radio
astronomy, but it can be used for any HDL development project.
*******************************************************************************
* 2) User guide topics
*******************************************************************************
a) Introduction:
Technology independence
- Using sim models
- c_technology = sim or using g_sim?
The HDL libraries provide a hierarchy that promotes code reuse. The top level component that
can run on an FPGA is also a HDL library. Technology dependent IP for e.g. PLL, RAM, FIFO,
transceivers, DDR4 is included via HDL libraries as well. The technology dependent IP is
pregenerated and instantiated using wrapper HDL. The wrapper HDL around the technology
dependent IP makes the IP vendor agnostic. The wrapper HDL can select one or more vendor IP.
The wrapper IP can also select a behavioral simulation model of the IP, to speed up the HDL
simulation or to simulate without any vendor dependence. Fig 2 shows a possible hierarchy
of HDL libraries.
RadioHDL is a highly flexible automated build environment for HDL source code. The HDL is
organized in HDL libraries. The HDL libraries promote code reuse. The top level component
that can run on an FPGA is also a HDL library. The parameters for HDL libraries, the build
tools and target FPGA are kept in configuration files. The configuration files and source
code are the inputs for the RadioHDL tool. The output is a build result that depends on
which build tool is used. The buil result can e.g. be a project file for Modelsim to
simulate the HDL, a project for Quartus to synthesize the HDL, a report log from a
regression test that simulated the HDL.
Application
Board
DSP
IO
external
base
technology
IP
Fig 2. Organize firmware in libraries (see 30_FWbuild_Eric, SKA Hongkong)
Technology dependent IP for e.g. PLL, RAM, FIFO, transceivers, DDR4 is included via HDL
libraries as well. The technology dependent IP is pregenerated and instantiated using wrapper
HDL. The wrapper HDL around the technology dependent IP makes the IP vendor agnostic. The
wrapper HDL can select one or more vendor IP. The wrapper IP can also select a behavioral
simulation model of the IP, to speed up the HDL simulation or to simulate without any vendor
dependence.
Features:
- Gear scripting based on Pyhton 3.x
- Configuration files to define the sources and how to build them
- RadioHDL scripting based on Python 3.x
- Configuration files to define the sources and how to automatically build them
- Separation of source files and build result files
- All HDL organised in HDL libraries that
. provide hierarchical structure and promote reuse
. can be used to build different revisions of the same source code based on generics
. allow separation of technology dependent libraries, board specific libraries, general
libraries and application specific libraries
. can be used to build different revisions of the same source code based on generics
. can include local test benches to verify the library in a regression test
b) Quick start:
c) Config files:
hdllib.cfg :
. Each HDL Library has a local hdllib.cfg configuration file that defines the sources and
supported tools
. many, each local per HDL library in a sub directory of $RADIOHDL_WORK
hdl_buildset_<buildset_name>.cfg
. A central hdl_buildset_<name> build configuration file defines the combination of sources,
FPGA type and version and tool versions that are needed to build target FPGA type (board)
and type and version of the tools for synthesis, simulation.
. defines a combination of board, FPGA and tool versions
. one central per buildset located at $RADIOHDL_CONFIG
hdl_tool_<tool_name>.cfg
. A central hdl_tool_<name>.cfg tool configuration file that defines central setting for
that tool. Typical tools are e.g. Modelsim for simulation and Quartus for synthesis, but
other tool vendors can also be supported and other tools like a reggression test that
runs a set of test benches for a set of HDL libraries.
. defines tool specific settings (e.g. modelsim, quartus)
. one central per tool located at $RADIOHDL_CONFIG
d) Environment setup
* Operating system
RadioHDL supports both Windows and Linux operating systems. The following tools need to be
availabel in order to build target files (TBC):
- Make (available in /bin for win32 platforms)
- Python 3.x
- Pyhton libraries (numpy, pylatex, yaml)
* Environment variables
.bashrc
- ALTERA_DIR is set to where Altera tool version is installed (i.e. Quartus)
- MENTOR_DIR is set to where Mentor tool version is installed (i.e. Modelsim)
- MODELSIM_ALTERA_LIBS_DIR is set to where the compiled Altera tool versions HDL libraries
for simulation with Modelsim are stored
init_<my_project>.sh
- RADIOHDL_WORK is set to location of this init_<my_project>.sh and defines the root
directory from where all HDL libraries source files (hdllib.cfg) can be
found
- RADIOHDL_BUILD_DIR is set to ${RADIOHDL_WORK}/build and defines where all build results will
be put
- HDL_IOFILE_SIM_DIR is set to ${RADIOHDL_BUILD_DIR}/sim and defines where Modelsim simulation
will keep temporary file IO files.
init_radiohdl.sh
- RADIOHDL_GEAR is set to location of this init_radiohdl.sh and defines the root directory
of where the RadioHDL tool is installed.
- RADIOHDL_CONFIG is set to ${RADIOHDL_GEAR}/config if not already defined by the user and
defines where the central configuration scripts for buildsets (unb1, unb2b)
and tools (modelsim, quartus) are kept.
Environment variables for build tools (e.g. modelsim, quartus) are set automatically (TBC)
MODEL_TECH_DIR
* Environment files
Altera hdl_user_components.ipx:
This hdl_user_components.ipx defines where Quartus QSYS searches for user components. The
init_<my_project>.sh copies hdl_user_components.ipx from $RADIOHDL_WORK to
${ALTERA_DIR}/ip/altera/user_components.ipx.
*******************************************************************************
* Open issues:
*******************************************************************************
- Support more roots in RADIOHDL_WORK for searching HDL libraries
- Central HDL_IO_FILE_SIM_DIR = build/sim --> Project local sim dir
- avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR
copies the last <buildset>, using more than one buildset at a time gices conflicts.
- RadioHDL improvements requested by CSIRO for Vivado
f) Directory structure
*******************************************************************************
* Source directory structure
*******************************************************************************
RadioHDL requires that:
......@@ -183,77 +140,14 @@ pre generated and then wrapped by a technology agnostic wrapper entity. These wr
are then used by the other libraries.
g) Top level HDL library:
A top level HDL library is defined as a HDL library that contains a top level entity and
configuration parameters to synthesize it to an FPGA image that can run on an FPGA.
A top level HDL library should not be reused in other HDL libraries, to avoid confusion
that can occur due to conflicting or dupplciate
*******************************************************************************
* Run RadioHDL with GIT
> cd ~/git/hdl
> . ./init_hdl.sh # setup development environment for hdl/
# hdl/libraries, hdl/boards and hdl/applications are developed simultaneously and therefor in one git hdl/ repository
# automatically also sources ../radiohdl/init_radiohdl.sh if necessary
> compile_altera_simlibs unb1 # creates build/unb1/hdl_libraries_ip_stratixiv.txt
# creates build/quartus/<tool version> simulation models that need to be moved to /home/software/modelsim_altera_libs
> generate_ip_libs unb1 # creates build/unb1/qmegawiz/
# creates build/unb1/quartus_sh --> empty dir, why is it there?
> quartus_config unb1 # creates build/unb1/quartus/<hdllib libraries> for synthesis
# creates build/unb1/quartus/technology_select_pkg.vhd
> modelsim_config unb1 # creates build/unb1/modelsim/<hdllib libraries> for simulation
# creates build/unb1/modelsim/modelsim_project_files.txt for Modelsim commands.do
# creates build/unb1/modelsim/technology_select_pkg.vhd
> run_qsys unb1 unb1_minimal_qsys
*******************************************************************************
* Run RadioHDL with SVN
echo "Uniboard trunk is selected"
export SVN=${HOME}/svnroot/UniBoard_FP7
#Setup RadioHDL environment for UniBoard2 and and new Uniboard1 applications
. ${SVN}/RadioHDL/trunk/tools/setup_radiohdl.sh
# Support old UniBoard environment (including Aarfaac and Paasar)
. ${SVN}/RadioHDL/trunk/tools/setup_unb.sh
*******************************************************************************
* 3) Programmers guide topics
* Simulation using file IO
*******************************************************************************
RadioHDL gear directory structure
$RADIOHDL_GEAR/config # central config files for buildsets and tools
/core # RadioHDL gear scripts
/doc # manuals
/ise # scripts for Xilinx ISE, Impact tools
/modelsim # scripts for Mentor Modelsim tool
/quartus # scripts for Altera Quartus, SOPC, QSYS tools
init_radiohdl.sh # Initialize RadioHDL for a project at $RADIOHDL_WORK
generic.sh # Collection of useful functions
HDL_IOFILE_SIM_DIR is set to ${RADIOHDL_BUILD_DIR}/sim and defines where Modelsim simulation
will keep temporary file IO files.
# Scripts to adopt RadioHDL configuration parameters as environment variables
# or paths
set_config_path # expand config paths
set_config_variable # export config variables
set_hdllib_variable # export hdllib variables
*******************************************************************************
* Open issues:
*******************************************************************************
- Support more roots in RADIOHDL_WORK for searching HDL libraries
- Central HDL_IO_FILE_SIM_DIR = build/sim --> Project local sim dir
- avs_eth_coe.vhd per tool version? Because copying avs_eth_coe_<buildset>_hw.tcl to $HDL_BUILD_DIR
copies the last <buildset>, using more than one buildset at a time gices conflicts.
- RadioHDL improvements requested by CSIRO for Vivado
\ No newline at end of file
applications/lofar2/doc/prestudy/station2_opc_ua.txt
+ 13
− 0
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......@@ -76,3 +76,16 @@ Needed:
The tasks of the SDP OPC-UA server are:
* Translate between OPC-UA interface at Station Control side and Gemini protocol over UDP/IP at
UniBoard2 side
* Obtain the named register map of the FPGA firmware from a definition in YAML (the schema for
the description in YAML is defined in ARGS = automatic register generation system).
* Present the registers per FPGA for the array of FPGAs as data points in OPC-UA. This could be
generated automatically based on the regmap description in YAML for each FPGA
* Present registers that are distributed over an array of FPGAs as a single array of data points
in OPC-UA (e.g. for beamformer weights, crosslet statistics). This abstracts away the notion
of which FPGA takes care of which signal inputs, instead all signal inputs are represented as
a single array. This is probably a manually written software layer / add-on in the SDP
OPC-CU server.
applications/lofar2/doc/prestudy/station2_sdp_srs.txt 0 → 100755
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LRU --> UniBoard2
LOFAR2-4384 Hot replaceable LRUs
LOFAR2-4196 Unique LRU ID number
LOFAR2-4004 LRU physical label (Loaction, ID number, lifetime)
LOFAR2-2229 Remote readout of ID number
LOFAR2-3677 LRU lifetime >= 10 years
LOFAR2-2232 Production pass/fail test
LOFAR2-6726 Station mean time before failure > TBD years
LOFAR2-2188 Station mean time to repair < 1 hour
LOFAR2-3083 Information for configuration management tool
LOFAR2-2202 CE approval
LOFAR2-2258 Safety after failure
LOFAR2-2166 Fire retardant
LOFAR2-4483 Station manuals for maintainer
System
. General
LOFAR2-4481 Station documentation of interfaces
LOFAR2-4482 Station documentation of interfaces
LOFAR2-4483 Station manuals for maintainer
LOFAR2-2318 Station Modes
LOFAR2-3187 Simultaneous existance of production modes
LOFAR2-3269 Justification of single-points of failure
LOFAR2-4000 Robustness: No single point of failure
LOFAR2-4001 Graceful degradation
. Monitor HW, FW and interfaces --> Ring, 1GbE, 10GbE, DDR4, PPS, JESD
LOFAR2-3227 x--> 3248
LOFAR2-3209 Monitoring in Hybernate State
LOFAR2-3080 Monitoring in On State
LOFAR2-3248 Self test to isolate failures down to LRU level
LOFAR2-6727 Failure detection latency < TBD s
LOFAR2-4369 Periodic monitoring interval: 1 s, 10 s or 300 s
LOFAR2-2412 Station internal synchronization --> Timing
LOFAR2-3578 HBA 170 to 230 MHz (nice to have) --> 160M
LOFAR2-3304 Dual polarisation --> Form beamlets, SI mapping
LOFAR2-3677 Life time > 10 years
(LOFAR2-3195 Single central clock for RS and CS)
LOFAR2-3976 Timing accuracy and budgets
BSP
LOFAR2-2371 Remote readout of software version number
LOFAR2-4386 Remote reinstallation of SW, FW --> BSP
LOFAR2-2179 Remote SW, FW update --> BSP
LOFAR2-3176 Reconfiguration time: < 20 s --> BSP
LOFAR2-3209 Monitoring in Hybernate State
Ring
LOFAR2-3269 Justification of single-points of failure
LOFAR2-3248 Self test to isolate failures down to LRU level
LOFAR2-4369 Periodic monitoring interval: 1 s, 10 s or 300 s
LOFAR2-2412 Station internal synchronization --> Timing
ADC and Timestamp
LOFAR2-3129 Timestamp precision < 1 ns relative to TBC reference --> Timing, BSN source
LOFAR2-2412 Station internal synchronization --> Timing, JESD204B, Sample delay buffer
LOFAR2-4303 Beamform synchronized start at pulse from TD --> Timing, PPS
LOFAR2-3220 Examine data at each processing step --> DB
LOFAR2-3248 Station self-test --> WG, BSN scheduler
LOFAR2-3225 Monitoring data quality --> JESD status, AST, DB
Subband Filterbank
LOFAR2-3206 RFI mitigation, minimize affect on (a)periodic celestial signals --> PFB
LOFAR2-3578 HBA 170 to 230 MHz (nice to have) --> 160M
LOFAR2-3203 LOFAR1 - LOFAR2.0 operation together --> PFB critically sampled
LOFAR2-3305 Beamlet bandwidth 195k, 156k --> PFB
LOFAR2-3099 Subband frequency grid --> PFB
LOFAR2-3148 Subband stopband --> PFB
LOFAR2-4490 Same beamlet spectral filter as in LOFAR1 --> PFB
LOFAR2-2278 Alias free broadband --> PFB oversampled
LOFAR2-3191 Calbration gain error, <= 0.2 % --> Subband weights
LOFAR2-3961 Real time RFI detection --> SST
LOFAR2-3225 Monitoring data quality --> SST
LOFAR2-7519 Stand-alone Mode use LOFAR1 format for statistics --> SST
Subband Correlator --> XST (one subband per one second for all inputs)
LOFAR2-3626 Subband correlator mode
LOFAR2-4053 Array correlation matrix (ACM)
LOFAR2-4052 ACM Subband bandwidth 195k, 156k
LOFAR2-3961 Real time RFI detection
LOFAR2-4296 Monitoring correlate data quality
LOFAR2-3220 Examine data at each processing step
LOFAR2-7519 Stand-alone Mode use LOFAR1 format for statistics
Beamformer
LOFAR2-3421 Beamform mode --> Form beamlets
LOFAR2-3098 LBA 488 independent beamlets --> Form beamlets, Subband select
LOFAR2-6996 HBA remote station 488, core station 976 independent beamlets --> Form beamlets, Subband select
LOFAR2-4478 Station maximum beamwidth (single element beam) --> Form beamlets
LOFAR2-3538 Beam tracking accuracy within TBC degrees --> Form beamlets
LOFAR2-4495 Beamform accuracy HPBW --> Form beamlets
LOFAR2-3181 Temporal amplitude gain drift, rate <= 0.8 % radian/minute --> Form beamlets
LOFAR2-2235 Temporal phase drift, rate <= 1 radian/minute --> Form beamlets
LOFAR2-3191 Calbration gain error, <= 0.2 % --> Form beamlets
LOFAR2-6582 Digital beamforming efficiency --> Form beamlets
LOFAR2-3304 Dual polarisation --> Form beamlets
LOFAR2-3960 Real-time RFI suppression in BF mode (nice to have)--> Form beamlets
LOFAR2-3231 Control start/stop of RFI suppression in BF mode (nice to have) --> Form beamlets
LOFAR2-3125 Beam repositioning latency <= 1 s --> Form beamlets
LOFAR2-4303 Beamform synchronised start within TBD s --> Form beamlets
LOFAR2-3961 Real-time RFI detection in BF mode (nice to have) --> BST
LOFAR2-3317 Monitoring beamform data quality --> BST
LOFAR2-7519 Stand-alone Mode use LOFAR1 format for statistics --> BST
LOFAR2-3220 Examine data at each processing step --> Subband select
LOFAR2-3305 Beamlet bandwidth 195k, 156k --> Output beamlets
LOFAR2-3099 Beamlet frequency axis --> Output beamlets
LOFAR2-3123 Flag repositioning of beam --> Output beamlets
LOFAR2-2413 Beamlet output destination --> Output beamlets
LOFAR2-5618 Beamlet output via UDP --> Output beamlets
LOFAR2-6893 Beamlet output rate to CEP < 10 G (TBC) --> Output beamlets
LOFAR2-6894 Beamlet output via UDP/IPv4 --> Output beamlets
LOFAR2-7513 Stand-alone Mode beamlet output to SSU --> Output beamlets
LOFAR2-7515 Stand-alone Mode output destination IP/UDP port --> Output beamlets
LOFAR2-4299 Redirect station beamlet --> Output beamlets
LOFAR2-4301 Start station beamlet output --> Output beamlets
LOFAR2-4300 Stop station beamlet output --> Output beamlets
LOFAR2-3220 Examine data at each processing step --> DB
Transient buffer
LOFAR2-3420 Transient buffer --> Buffer
LOFAR2-2305 Buffer length >= 2.5 s --> Buffer
LOFAR2-3220 Examine data at each processing step --> Buffer
LOFAR2-3146 Store baseband or subband data --> Select and record
LOFAR2-2295 Trade bandwidth for duration --> Select and record
LOFAR2-4039 Staggered range --> Select and record
LOFAR2-2299 Freeze latency <= 0.1 s --> Buffer
LOFAR2-4509 Unfreeze buffer --> Buffer
LOFAR2-3147 Freeze duration <= 20 min --> Select and readout
LOFAR2-6894 Transient data output rate to CEP < 10 G (TBC) --> Select and readout
LOFAR2-4510 Update destination of stream readout --> Select and readout
LOFAR2-4038 Readout part of buffer --> Select and readout
LOFAR2-4508 Control start stream readout of buffer --> Select and readout
LOFAR2-4507 Control stop stream readout of buffer --> Select and readout
LOFAR2-7512 Stand-alone Mode transient data output to SSU --> Select and readout
LOFAR2-7515 Stand-alone Mode output destination IP/UDP port --> Select and readout
Transient detection
LOFAR2-3144 Transient detection mode
LOFAR2-2310 Send trigger to TM --> Trigger to SC
Subband offload
None
\ No newline at end of file
applications/lofar2/doc/prestudy/station2_sdp_timing.py 0 → 100644
+ 130
− 0
View file @ d129e115
###############################################################################
#
# Copyright 2019
# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
###############################################################################
# Author: Eric Kooistra
"""Show PPS and SDP timing grid information for LOFAR2.0 Station
Usage:
> python station2_sdp_timing.py -h
"""
import argparse
import math
figNr = 1
# Parse arguments to derive user parameters
_parser = argparse.ArgumentParser('station2_sdp_timing')
_parser.add_argument('-n', default=10, type=int, help='Number of seconds')
_parser.add_argument('-f', default=200, type=int, help='Sample frequency in [MHz]')
_parser.add_argument('-q', default=32, type=int, help='Oversampling rate 32/q')
args = _parser.parse_args()
Nsec = args.n
fadc = args.f * 1000000 # ADC sample frequency in [Hz]
Tadc = 1000. / args.f # ADC sample period in [ns]
p = 32
q = args.q # Subband oversampling rate for Ros = p / q, where p = 32
Nsub = 512 # Number of subbands
Ncomplex = 2
Nfft = Nsub * Ncomplex # Subband filterbank FFT size
Nblk = Nfft * q / p # Subband period in [Tadc]
Tsub = Nblk * Tadc # Subband period in [ns]
# Check that Tsub can be expressed as an integer number of ns
result = 'PASSED'
if int(Tsub) != Tsub:
print ''
result = 'WARNING'
print 'Warning: Tsub = %f ns, choose f such that Tsub is an integer number of ns' % Tsub
print ''
print ' SSN | first ToD | | nof BSN'
print ' of PPS | BSN in PPS at first | offset | in PPS'
print ' grid | interval * Tsub = BSN | to PPS | interval'
print ' [s] | [ns] [ns] | [ns] [Tadc] | '
print '--------+-----------------------------------+-----------------+---------'
# BSN = Block Sequence Number of first block in this PPS interval
BSN = 0
nofBSN_hi = 0
nofBSN_lo = 0
prevToffset = 0
for SSN in range(Nsec):
# SSN = Second Sequence Number of this PPS interval
# Determine BSN of first block in next PPS interval
nextSSN = SSN + 1
nextBSN = math.ceil((1.0 * nextSSN * fadc) / Nblk)
# Determine timing for this PPS interval
# . Time of Day at BSN in [ns]
ToD_ns = BSN * Tsub
# . Offset of ToD at BSN relative to PPS in [Tadc]
Toffset = BSN * Nblk - SSN * fadc
# Note: ToD_ns - SSN * 1000000000 yields Toffset in [ns], but first
# derive Toffset in [Tadc] units. to avoid the division (which could
# lead to integer truncation but not for f = 160 or f = 200) that is
# used to calculate ToD_ns.
# . Number of blocks in this PPS interval
nofBSN = nextBSN - BSN
# . Maintain count of number of BSN intervals with 1 extra BSN
if SSN == 0:
nofBSN_H = nofBSN
nofBSN_L = nofBSN
nofHiBSN = 1
nofLoBSN = 0
else:
if nofBSN_H == nofBSN:
nofHiBSN += 1
else:
nofBSN_L = nofBSN # nofBSN_H = nofBSN_L + 1 by design
nofLoBSN += 1
# Print timing information
if Toffset == 0 and prevToffset != 0:
# insert divider row each time BSN grid coincides with PPS grid again
print ' | | | '
print '%7d | %10d * %5d = %12d | %6d %8d | %8d' % (SSN, BSN, Tsub, ToD_ns, Toffset*Tadc, Toffset, nofBSN)
# Prepare for next PPS interval
BSN = nextBSN
prevToffset = Toffset
print ''
if nofBSN_H != nofBSN_L:
print 'nofBSN = %d occured %d time' % (nofBSN_H, nofHiBSN)
print 'nofBSN = %d occured %d time' % (nofBSN_L, nofLoBSN)
timeBSN = (nofBSN_H * nofHiBSN + nofBSN_L * nofLoBSN)
timeBSN_ns = timeBSN * Tsub
timeSSN_ns = Nsec * 1000000000
print 'time SSN = %d [ns]' % timeSSN_ns
print 'time BSN = %d [ns] = %d * %d + %d * %d = %d [Tsub]' % (timeBSN_ns, nofBSN_H, nofHiBSN, nofBSN_L, nofLoBSN, timeBSN)
if timeBSN_ns != timeSSN_ns:
result = 'WARNING'
print 'Warning: not an integer number of BSN in n PPS intervals, choose n multiple of q'
print ''
print result
print ''
applications/lofar2/doc/prestudy/station2_sdp_timing.txt
+ 29
− 24
View file @ d129e115
......@@ -95,13 +95,13 @@ and any M&C upon the data, because:
The actual resolution T_sub of the Station BSN in LOFAR2 depends on the ADC sample frequency and on the
subband filterbank:
N_blk T_adc T_sub T_sub_i
1024 * 5 ns = 5120 ns = 25600 [0.2 ns] for critical sampled filterbank at 200 MHz
1024 * 6.4 ns = 6553.6 ns = 32768 [0.2 ns] for critical sampled filterbank at 160 MHz
864 * 5 ns = 4320 ns = 21600 [0.2 ns] for oversampled filterbank R_os = 32/27 = 1.185 at 200 MHz
864 * 6.4 ns = 5529.6 ns = 27648 [0.2 ns] for oversampled filterbank R_os = 32/27 = 1.185 at 160 MHz
800 * 5 ns = 4000 ns = 20000 [0.2 ns] for oversampled filterbank R_os = 32/25 = 1.28 at 200 MHz
800 * 6.4 ns = 5120 ns = 25600 [0.2 ns] for oversampled filterbank R_os = 32/25 = 1.28 at 160 MHz
N_blk T_adc T_sub
1024 * 5 ns = 5120 ns for critical sampled filterbank at 200 MHz
1024 * 6.25 ns = 6400 ns for critical sampled filterbank at 160 MHz
864 * 5 ns = 4320 ns for oversampled filterbank R_os = 32/27 = 1.185 at 200 MHz
864 * 6.25 ns = 5400 ns for oversampled filterbank R_os = 32/27 = 1.185 at 160 MHz
800 * 5 ns = 4000 ns for oversampled filterbank R_os = 32/25 = 1.28 at 200 MHz
800 * 6.25 ns = 5000 ns for oversampled filterbank R_os = 32/25 = 1.28 at 160 MHz
In LOFAR2 the timestamp should be independent of:
......@@ -110,35 +110,39 @@ In LOFAR2 the timestamp should be independent of:
If T_sub was fixed then T_sub could be used as timestamp resolution (like in APERTIF). However T_sub depends
on the type of subband filterbank with a resolution of T_adc. If T_adc was fixed then T_adc could be used
as timestamp resolution. However T_adc depends on the sample clock rate. Therefore the timestamp resolution
needs to be as fine as the greatest common time resolution of T_adc = 5 ns and T_adc = 6.4 ns, which is 0.2 ns.
A 64 bit timestamp with 0.2 ns resolution can count 2**64 / (365.25 * 24 * 3600 / 0.2e-9) = 116 years. Hence
for t_epoch = 1970 this is until 2086, which is sufficient for the lifetime of LOFAR2.0. Internally in SDP
as timestamp resolution. However T_adc depends on the sample clock rate. At most the timestamp resolution
needs to be as fine as the greatest common time resolution of T_adc = 5 ns and T_adc = 6.25 ns, which is
0.25 ns. However typical R_os = p/q have p is a power of 2 and p <= 64, because N_FFT = 1024 = 2**10. Hence
N_FFT / p >= 16, so typical subband periods can always be expressed as a multiple of 16* 6.25 = 100 ns or
16 * 5 = 80 ns. Therefore the minimum required time stamp resolution is gcd(100, 80) = 20 ns. For human
readability choose 1 ns as timestamp resolution
A 64 bit unsigned timestamp with 1 ns resolution can count 2**64 / (365.25 * 24 * 3600 / 1e-9) = 584 years.
Hence for t_epoch = 1970 this is more than enough for the lifetime of LOFAR2.0. Internally in SDP
firmware use the BSN to count T_sub. Externally at the SDP interface use timestamp values with a resolution
of 0.2 ns such that they are:
of 1 ns such that they are:
* integer values, and
* independent of the sample period.
The actual timestamp in fractional seconds of 0.2 ns follows from:
The actual timestamp in units of 1 ns follows from:
timestamp = Station BSN * T_sub_i * 0.2 [ns].
timestamp = Station BSN * T_sub [ns].
The BSN and T_sub_i can be specified as:
The BSN and T_sub can be specified as:
- single 64 bit integer timestamp value of BSN * T_sub_i [0.2 ns]
- two separate fields with an incrementing BSN and resolution given by T_sub_i [0.2 ns]
- single 64 bit unsigned integer timestamp value of BSN * T_sub [ns]
- two separate fields with an incrementing BSN and resolution given by T_sub [ns]
To cover 116 years for a BSN with smallest T_sub = 4000 ns for R_os = 32/25 = 1.28 requires:
To cover 100 years for a BSN with smallest T_sub = 4000 ns for R_os = 32/25 = 1.28 requires:
log2( 116 * (365.25 * 24 * 3600 / 4000e-9) ) = 49.7, so 50 bits
log2( 100 * (365.25 * 24 * 3600 / 4000e-9) ) = 49.7, so 50 bits
Therefore allocate 64b in a packet header to send the BSN information. The BSN and timestamp are direcly
related via T_sub_i, but the advantage of providing the BSN separately is that it increments by 1 for
related via T_sub, but the advantage of providing the BSN separately is that it increments by 1 for
each block period T_sub, so it can be used as block index.
The range of T_sub is 4000 ns - 5120 ns, so the range of T_sub_i is 20000 - 25600. These T_sub_i values
can be covered in a 16 bit number. Alternatively T_sub_i can be derived from the four possible
The range of T_sub is 4000 ns - 5120 ns. These T_sub values
can be covered in a 16 bit number. Alternatively T_sub can be derived from the four possible
combinations of f_adc = 200M or 160M and R_os = 1 or 32/25, that can be represented with 2 bits.
......@@ -148,7 +152,8 @@ combinations of f_adc = 200M or 160M and R_os = 1 or 32/25, that can be represen
*******************************************************************************
Together the initial BSN, counting blocks and the order of the data within a block uniquely define the timing
of the data in a Station. However counting blocks is not sufficient to maintain the data timing, because:
of the data in a Station. However counting blocks is not sufficient to maintain the data timing, because
there can be gaps due to:
- The data flow at the SDP input may be stopped and restarted,
- at the external interfaces of the FPGAs in SDP it is possible that blocks of data get lost.
......@@ -172,7 +177,7 @@ FPGA in the SDP firmware has a BSN source, that all run synchronously within a S
Stations, because they have been started by the external PPS from the Timing Distributor (TD). The sync is a
periodic signal with period larger than the maximum latency of the data within the SDP, to ensure
that a sync at any FPGA refers to the same time instant. If somewhere in an FPGA the sync comes along, then
the BSN can be recreated by directly using the BSN that was held at the sync by the BSN source and start
the BSN can be recreated by directly using the BSN that was held at the sync by the local BSN source and start
continue counting blocks from there.
......
applications/lofar2/doc/prestudy/station2_tmp.txt 0 → 100644
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− 0
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Remaining texts that have not been used yet in official SDP detailed design documents
*******************************************************************************
* From station2_sdp_timing
*******************************************************************************
- It is not necessary to represent fine group delays of digital filters or analogue electronics and
cables in the BSN, because these delays are all accounted for after calibration.
. Course group delays and cable delay differences can be compensated for in steps to T_adc via the signal
input buffer of every ADC input in SDP.
. Fine group delay differences within a Station can be calibrated via the subband calibration weights.
- Group delay differences between Stations need to be calibrated at CEP, and can be compensated at CEP or
at Station via the input buffers and the subband calibration weights.
Key ideas:
- Use Ethernet CRC and DP CRC to ensure detection of packet errors and to ensure error free blocks
within FPGA firmware
RCU2 Subband Ring
PFB
data data
data ------> BSN --------> Move, -------> Packet
PPSH ------> source sync DSP sync encoding
BSN .........> BSN ring
Ring BF, XC
data data data
Packet --------> Validate --> Validate --> BSN --------> Move, --------> Packet
decoding sync CRC BSN aligner sync DSP sync encoding
ring BSN .......................................................> BSN output
applications/lofar2/doc/prestudy/station2_to_do_erko.txt
+ 12
− 0
View file @ d129e115
......@@ -59,6 +59,18 @@ Vijf principes:
- data buffer on output beamlets --> histogram
. buffer all beamlets per T_sub at sync
. buffer one beamlet for some T_sub time series after sync
- Created common_mem_bus and common_mem_master_mux to replace Qsys
. considered using Wishbone, but for our M&C using common_mem_bus is easier than wrapping a Wishbone bus
. add a common_arbiter to make a common_mem_master_arbiter using miso.waitrequest, however then it may
be necessary to reconsider wrapping a Wishbone bus.
- Add support generating MM bus by wiring common_mem_bus to named mosi/miso slaves or arrays of slaves
from yaml with ARGS
- g_sim
. define g_sim record
. use g_sim or consider sim models as a technology
- lofar2_unb2c structure with design_name revisions and node_<> per device: bsp, ring_(bf, xc, tb, so),
node_(bf, xc, tb, so, tdet, adc, fb), ddr4_(0,1) for tb, offload_10g
- Use GIT
- Understand AXI4 streaming (versus avalon, RL =0)
......
applications/ta2/designs/.gitignore 0 → 100644
+ 5
− 0
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*/*.aoco
*/*.aocr
*/*.aocx
*/*.sof
*/*.rbf
applications/ta2/designs/ta2_unb2b_qsfp_demo/Makefile 0 → 100644
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− 0
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CXX= g++ #-mcmodel=medium
CXXFLAGS= -std=c++11 -mavx2 -g -O3 -fopenmp #-DCL_ALTERA
AOC= aoc
AOCFLAGS= -v -g
#AOCRFLAGS+= -fp-relaxed
AOCRFLAGS+= -report
AOCRFLAGS+= -opt-arg=-allow-io-channel-autorun-kernel
#AOCRFLAGS+= -board=p385a_min_ax115_1710240
AOCOFLAGS+= -board=unb2b
#AOCOFLAGS+= -board=p385a_min_ax115
#AOCOFLAGS+= -board=p520_max_sg280l
#AOCOFLAGS= -board=a10gx_hostch
#AOCRFLAGS+= -board=s10gx_ea
AOCOFLAGS+= -I$(INTELOCLSDKROOT)/include/kernel_headers
#AOCFLAGS= -v -g -cl-opt-disable -cl-fast-relaxed-math -cl-mad-enable -fp-relaxed -report -board=a10gx_hostch
#AOCXFLAGS+= -high-effort
#AOCFLAGS+= -fast-compile
#AOCRFLAGS+= -profile=all
#AOCOFLAGS+= -march=emulator -DEMULATOR
#AOCRFLAGS+= -emulator-channel-depth-model=strict
#AOCXFLAGS+= -bsp-flow=base
AOCXFLAGS+= -bsp-flow=flat
ifneq ("$(SEED)", "")
AOCXFLAGS+= -seed=$(SEED)
endif
INCLUDES= $(shell aocl compile-config) #-I..
LDFLAGS= $(shell aocl link-config) #-ldl -lacl_emulator_kernel_rt #-lbfd
#INCLUDES= -I/var/scratch/package/altera_pro/18.0.0.219/hld/host/include
#LDFLAGS= -L/cm/shared/package/altera_pro/18.0.0.219/hld/board/nalla_pcie/linux64/lib -L/var/scratch/package/altera_pro/18.0.0.219/hld/host/linux64/lib -Wl,--no-as-needed -lalteracl -lnalla_pcie_mmd -lelf
#TMPDIR= /tmp/unb2b_LED_Demo_base
TMPDIR= $(RADIOHDL_BUILD_DIR)/unb2b/OpenCL/$(lastword $(subst /, ,$(dir $(abspath $1))))
CXXFLAGS+= $(INCLUDES)
CXXSOURCES= GridderTest.cc
CXXSOURCES= DegridderTest.cc
#CXXSOURCES+= FFT32Test.cc
#CXXSOURCES= IOChannelTest.cc
q:
OBJECTS= $(CXXSOURCES:%.cc=%.o)
DEPENDENCIES= $(CXXSOURCES:%.cc=%.d)
EXECUTABLES= $(CXXSOURCES:%.cc=%)
%.d: %.cc
-$(CXX) $(CXXFLAGS) -MM -MT $@ -MT ${@:%.d=%.o} $< -o $@
%.o: %.cc
$(CXX) -c $(CXXFLAGS) -o $@ $<
%.aoco: %.cl
(unset DISPLAY; mkdir -p $(TMPDIR)/$* && cp -a $< $(TMPDIR)/$* && cd $(TMPDIR)/$* && $(AOC) -c $(AOCOFLAGS) $< && cd - && cp -a $(TMPDIR)/$*/$@ .)
%.aocr: %.aoco
(unset DISPLAY; cp -a $< $(TMPDIR)/$* && cd $(TMPDIR)/$* && $(AOC) -rtl $(AOCRFLAGS) $< && cd - && cp -a $(TMPDIR)/$*/$@ .)
%.aocx: %.aocr
(unset DISPLAY; cp -a $< $(TMPDIR)/$* && cd $(TMPDIR)/$* && $(AOC) $(AOCXFLAGS) $< && cd - && cp -a $(TMPDIR)/$*/$@ .)
%.sof: %.aocx
(unset DISPLAY; cp -a $(TMPDIR)/$*/flat.sof ./$@)
%.rbf: %.sof
(unset DISPLAY; cp -a $(TMPDIR)/$*/flat.rbf ./$@)
#temp test
#%.aocx: %.aoco
# (unset DISPLAY; cp -a $< $(TMPDIR)/$* && cd $(TMPDIR)/$* && $(AOC) -rtl $(AOCRFLAGS) $(AOCXFLAGS) $< && cd - && cp -a $(TMPDIR)/$*/$@ .)
#%.build:
# test -f $@ || (unset DISPLAY; echo `hostname` && rm -rf $(TMPDIR)/$* && cp -a $(TMPDIR)/`basename $* $(lastword $(subst _, ,$*))`template $(TMPDIR)/$* && cd $(TMPDIR)/$* && mv *.aoco $*.aoco && mv *.aocr $*.aocr && mv *.cl $*.cl && mv *template $* && time $(AOC) $(AOCXFLAGS) -seed=$(lastword $(subst _, ,$*)) $*.aocr && fgrep MHz $*/quartus_sh_compile.log|tail -n 1) >$@ 2>&1
%.build:
test -f $@ || test -f /tmp/stop || (echo `hostname` && cp `basename $* _$(lastword $(subst _, ,$*))`.cl $*.cl && SEED=$(lastword $(subst _, ,$*)) time make -j1 $*.aocx && fgrep MHz $(TMPDIR)/$*/$*/quartus_sh_compile.log|tail -n 1) >$@ 2>&1
all:: $(EXECUTABLES)
GridderTest: GridderTest.o
$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
DegridderTest: DegridderTest.o
$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
FFT32Test: FFT32Test.o
$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
IOChannelTest: IOChannelTest.o
$(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -o $@
clean::
$(RM) a.out $(DEPENDENCIES) $(OBJECTS)
sleep.%::
$(subst ., ,$@)
ifeq (0, $(words $(findstring $(MAKECMDGOALS), clean)))
-include $(DEPENDENCIES)
endif
applications/ta2/designs/ta2_unb2b_qsfp_demo/qsfp_demo.cl 0 → 100644
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Source diff could not be displayed: it is too large. Options to address this: view the blob.
applications/ta2/libraries/ta2_unb2b_bsp/README.txt 0 → 100644
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SETUP ONCE
- Install Quartus 18.0.219 with arria10 dependencies.
- Make sure the directory /home/software/Altera/18.0.219 points to the Quartus Root directory.
This can be done by installing Quartus in this location or make a symbolic link to it.
- Aquire the RadioHDL library from SVN or other source.
- Export the environment variable $RADIOHDL in your .bashrc and source the setup script as follows:
export RADIOHDL=/path/to/RadioHDL/trunk
export RADIOHDL_WORK=${RADIOHDL}
. ${RADIOHDL}/tools/setup_radiohdl.sh
- Generate all IP by first navigating to $RADIOHDL/libraries/technology/ip_arria10_e1sg and then executing generate-all-ip.sh
- Run the python script: quartus_config by executing:
python $RADIOHDL/tools/oneclick/base/quartus_config.py -t unb2b
COMPILING OPENCL APPLICATION
- Make sure you have defined the required environment variables for OpenCL compilation with Uniboard2.
- With the provided makefile you can compile your application by executing:
make myApp.sof myApp.rbf
FLASH SOF TO FPGA
The quickest way to program the FPGA is to use a JTAG connection and program the FPGA with the Quartus programmer, writing the .sof file.
- To configure a jtagserver you can use the command:
jtagconfig -addserver <server name> <password>
For using dop36 to program the Uniboard2 in the lab, the command is:
jtagconfig --addserver dop36 BG132V051
- To program the FPGA use the following command:
quartus_pgm -c USB-BLASTERII -m jtag -o p\;my_app.sof@1
The above command will program FPGA 1 of Uniboard2 with my_app.sof.
FPGAs 2, 3, and 4 can also be programmed by changing the FPGA ID. For example
For FPGA 2 -> quartus_pgm -c USB-BLASTERII -m jtag -o p\;my_app.sof@2
For FPGA 3 -> quartus_pgm -c USB-BLASTERII -m jtag -o p\;my_app.sof@3
For FPGA 4 -> quartus_pgm -c USB-BLASTERII -m jtag -o p\;my_app.sof@4
Multiple FPGAs can be targeted simultaniously for example, programming FPGAs 1,2 and 4:
quartus_pgm -c USB-BLASTERII -m jtag -o p\;my_app.sof@1 -o p\;my_app.sof@2 -o p\;my_app.sof@4
FLASH RBF TO FPGA
If a JTAG connection is not available, the application can be written using the .rbf file over a 1GbE connection.
This is achieved by running the util_unb2.py script
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<?xml version="1.0"?>
<board_env version="18.0" name="ta2_unb2b_bsp">
<hardware dir="hardware" default="unb2b"></hardware>
<platform name="linux64">
<mmdlib>%b/linux64/lib/libaltera_a10_ref_mmd.so</mmdlib>
<linkflags>-L%b/linux64/lib</linkflags>
<linklibs>-laltera_a10_ref_mmd</linklibs>
<utilbindir>%b/linux64/libexec</utilbindir>
</platform>
<platform name="windows64">
<mmdlib>%b/windows64/bin/altera_a10_ref_mmd.dll</mmdlib>
<linkflags>/libpath:%b/windows64/lib</linkflags>
<linklibs>altera_a10_ref_mmd.lib</linklibs>
<utilbindir>%b/windows64/libexec</utilbindir>
</platform>
</board_env>
applications/ta2/libraries/ta2_unb2b_bsp/bringup/README.txt 0 → 100755
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(C) 1992-2018 Intel Corporation.
Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words
and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.
and/or other countries. Other marks and brands may be claimed as the property
of others. See Trademarks on intel.com for full list of Intel trademarks or
the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera)
Your use of Intel Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any output
files any of the foregoing (including device programming or simulation
files), and any associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License Subscription
Agreement, Intel MegaCore Function License Agreement, or other applicable
license agreement, including, without limitation, that your use is for the
sole purpose of programming logic devices manufactured by Intel and sold by
Intel or its authorized distributors. Please refer to the applicable
agreement for further details.
Initializing the A10 GX Development Kit for OpenCL Use
======================================================
The A10 GX Development Kit is targetted for generic FPGA development and
therefore is not shipped ready for use with OpenCL. An Intel FAE should
normally perform all bringup/initialization steps so that the A10 Dev Kit
works out of the box, meaning a user would need to only: plug the A10 dev kit
board into a machine's PCIe slot, run "aocl install", and then successfully
run "aocl diagnose".
In the event that an Intel FAE is unable to carry out the task, an end-user
(at their own risk) can follow the directions found in the document
"Configuring the Intel Arria 10 GX FPGA Development Kit for the Intel FPGA SDK for OpenCL"
which can be downloaded from here:
https://www.altera.com/documentation/tgy1490191698959.html
to prepare the board for OpenCL use.
********************************************************
* WARNING: This process requires hardware assembly and *
* familiarity with Quartus. In addition there is real *
* risk that the card be damaged during an attempt to *
* initialize it for OpenCL use. *
********************************************************
It is strongly advised that this initialization procedure is carried out by
an Intel FAE only. Service requests should be placed to carry out or assist
with the A10 Dev Kit initialization for OpenCL.
applications/ta2/libraries/ta2_unb2b_bsp/bringup/a10_ref_initialization.tgz 0 → 100755
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applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/board_spec.xml 0 → 100755
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<?xml version="1.0"?>
<board version="18.0" name="unb2b">
<compile name="flat" project="top" revision="flat" qsys_file="none" generic_kernel="1">
<generate cmd="quartus_sh -t scripts/pre_flow_pr.tcl flat"/>
<synthesize cmd="quartus_sh --flow compile top -c flat"/>
<auto_migrate platform_type="a10_ref" >
<include fixes=""/>
<exclude fixes="pre_skipbak,post_skipbak"/>
</auto_migrate>
</compile>
<device device_model="10ax115s2f45i2sges_dm.xml">
<used_resources>
<alms num="33433"/> <!-- (Total ALMs) - (ALMs available to kernel_system_inst) -->
<ffs num="133600"/>
<dsps num="0"/>
<rams num="179"/>
</used_resources>
</device>
<!-- Registers, 32 bit @ 125MHz -->
<global_mem name="REG" max_bandwidth="4000" interleaved_bytes="32">
<interface name="board" port="kernel_register_mem" type="slave" width="256" maxburst="1" address="0x000000000" size="0x000001000" latency_type="fixed"/>
</global_mem>
<channels>
<interface name="board" port="kernel_stream_src_1GbE" type="streamsource" width="40" chan_id="kernel_input_1GbE"/>
<interface name="board" port="kernel_stream_snk_1GbE" type="streamsink" width="40" chan_id="kernel_output_1GbE"/>
<interface name="board" port="kernel_stream_src_10GbE" type="streamsource" width="72" chan_id="kernel_input_10GbE"/>
<interface name="board" port="kernel_stream_snk_10GbE" type="streamsink" width="72" chan_id="kernel_output_10GbE"/>
<interface name="board" port="kernel_stream_src_40GbE" type="streamsource" width="264" chan_id="kernel_input_40GbE"/>
<interface name="board" port="kernel_stream_snk_40GbE" type="streamsink" width="264" chan_id="kernel_output_40GbE"/>
</channels>
<host>
<kernel_config start="0x00000000" size="0x0100000"/>
</host>
<interfaces>
<interface name="board" port="kernel_cra" type="master" width="64" misc="0"/>
<interface name="board" port="kernel_irq" type="irq" width="1"/>
<kernel_clk_reset clk="board.kernel_clk" clk2x="board.kernel_clk2x" reset="board.kernel_reset"/>
</interfaces>
</board>
applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/ctrl_unb2_board.tcl 0 → 100755
+ 49
− 0
View file @ d129e115
post_message "Running ctrl_unb2_board script"
set radiohdl_build $::env(RADIOHDL_BUILD_DIR)
#============================================================
# Files and basic settings
#============================================================
# All used HDL library *_lib.qip files in order with top level last
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/technology/technology_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_ram/ip_arria10_e1sg_ram_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_memory/tech_memory_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_fifo/ip_arria10_e1sg_fifo_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_fifo/tech_fifo_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_ddio/ip_arria10_e1sg_ddio_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_iobuf/tech_iobuf_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tst/tst_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/common/common_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/mm/mm_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_mult/ip_arria10_mult_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_complex_mult_rtl/ip_arria10_complex_mult_rtl_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_complex_mult_rtl_canonical/ip_arria10_complex_mult_rtl_canonical_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_complex_mult/ip_arria10_e1sg_complex_mult_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_mult_add4/ip_arria10_e1sg_mult_add4_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_mult_add2/ip_arria10_e1sg_mult_add2_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_mult/tech_mult_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/common_mult/common_mult_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/easics/easics_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/dp/dp_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ppsh/ppsh_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/i2c/i2c_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_tse_sgmii_lvds/ip_arria10_e1sg_tse_sgmii_lvds_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_tse/tech_tse_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/eth/eth_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_asmi_parallel/ip_arria10_e1sg_asmi_parallel_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_remote_update/ip_arria10_e1sg_remote_update_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_flash/tech_flash_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/remu/remu_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_clkbuf_global/ip_arria10_e1sg_clkbuf_global_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_clkbuf/tech_clkbuf_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_pll/tech_pll_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_fractional_pll_clk200/ip_arria10_e1sg_fractional_pll_clk200_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_fractional_pll_clk125/ip_arria10_e1sg_fractional_pll_clk125_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_fractional_pll/tech_fractional_pll_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/epcs/epcs_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_temp_sense/ip_arria10_e1sg_temp_sense_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_fpga_temp_sens/tech_fpga_temp_sens_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/ip_arria10_e1sg_voltage_sense/ip_arria10_e1sg_voltage_sense_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/tech_fpga_voltage_sens/tech_fpga_voltage_sens_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/fpga_sense/fpga_sense_lib.qip"
set_global_assignment -name QIP_FILE "$radiohdl_build/unb2b/quartus/unb2b_board/unb2b_board_lib.qip"
applications/ta2/libraries/ta2_unb2b_bsp/hardware/unb2b/device.tcl 0 → 100755
+ 65
− 0
View file @ d129e115
# (C) 1992-2018 Intel Corporation.
# Intel, the Intel logo, Intel, MegaCore, NIOS II, Quartus and TalkBack words
# and logos are trademarks of Intel Corporation or its subsidiaries in the U.S.
# and/or other countries. Other marks and brands may be claimed as the property
# of others. See Trademarks on intel.com for full list of Intel trademarks or
# the Trademarks & Brands Names Database (if Intel) or See www.Intel.com/legal (if Altera)
# Your use of Intel Corporation's design tools, logic functions and other
# software and tools, and its AMPP partner logic functions, and any output
# files any of the foregoing (including device programming or simulation
# files), and any associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License Subscription
# Agreement, Intel MegaCore Function License Agreement, or other applicable
# license agreement, including, without limitation, that your use is for the
# sole purpose of programming logic devices manufactured by Intel and sold by
# Intel or its authorized distributors. Please refer to the applicable
# agreement for further details.
# This file contains .qsf settings that are unique to this particular device
#############################################################
# Device
#############################################################
set_global_assignment -name FAMILY "Arria 10"
set_global_assignment -name DEVICE 10AX115U2F45E1SG
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "1.8 V"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
#set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
#set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE ANY
#set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 4
set_global_assignment -name ENABLE_OCT_DONE OFF
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
set_global_assignment -name ENABLE_NCE_PIN OFF
set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X4"
#set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "ACTIVE SERIAL X1"
set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE EPCQL1024
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name STRATIXIII_UPDATE_MODE REMOTE
set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON
#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
#set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
#set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
set_global_assignment -name CONFIGURATION_VCCIO_LEVEL 1.8V
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_12_5MHZ
set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_25MHZ
#set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHZ
set_global_assignment -name USER_START_UP_CLOCK OFF
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 1932
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