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Commit 942d8f38 authored by Eric Kooistra's avatar Eric Kooistra
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Aligned with official... 

Aligned with official https://support.astron.nl/confluence/display/STAT/WP-5+SDP. Added details for BSP development in Q1
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applications/lofar2/doc/prestudy/station2_sdp_firmware_planning.txt
+ 402
− 186
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...@@ -2,14 +2,16 @@ ...@@ -2,14 +2,16 @@
* Rules * Rules
******************************************************************************* *******************************************************************************
1) Continuously plan 4 sprint ahead 1) Continuously plan increment of 4 sprint ahead
After initial planning for thge whole project (at PDR) it remains necessary to keep on adapting After initial planning for thge whole project (at PDR) it remains necessary
/ fine tuning the planning per quarter, so about 4 sprints ahead. This concerns not only time to keep on adapting / fine tuning the planning per quarter, so about 4
but also expectations, interfaces and work sprints ahead. This concerns not only time but also expectations, interfaces
and work
2) Guard the architecture 2) Guard the architecture
New projects / functionality must be judges by an architect (team) to decide on how it will fir New projects / functionality must be judges by an architect (team) to decide
in the existing architecture, or how the architecture will be adapted. This may change the on how it will fit in the existing architecture, or how the architecture
requirements on the new project/ function. It also means that ad hoc solutions are not allowed. will be adapted. This may change the requirements on the new project/
function. It also means that ad hoc solutions are not allowed.
3) Complete set of documentation of finished product 3) Complete set of documentation of finished product
Important for maintenance and extensions. Important for maintenance and extensions.
...@@ -20,30 +22,35 @@ ...@@ -20,30 +22,35 @@
******************************************************************************* *******************************************************************************
1 year = 40 weeks = 1600 hours, so each Quarter has 10 weeks. 1 year = 40 weeks = 1600 hours, so each Quarter has 10 weeks.
1 week = 100% project allocation, bruto 40 hours, netto 40 * 0.8 = 32 hours = 4 days 1 week = 100% project allocation, bruto 40 hours, netto 40 * 0.8 = 32 hours =
4 days
sprint = 100% project allocation, bruto 3 weeks, netto 12 days. sprint = 100% project allocation, bruto 3 weeks, netto 12 days.
The week/hour estimates concern time that is booked on the project. For example if a tasks has The week/hour estimates concern time that is booked on the project. For
alloacted 1 week, then: example if a tasks has alloacted 1 week, then:
- 40 hours will be booked on the project - 40 hours will be booked on the project
- the lead time (doorlooptijd) wiil be about 1/0.8 = 1.25 longer - the lead time (doorlooptijd) wiil be about 1/0.8 = 1.25 longer
There are 52 / 3 = 17 sprints in a year, so about 4 sprints per Quarter. Hence each sprint can
contain about 10 / 4 = 2.5 weeks of booked work per person at 100% project allocation.
With e.g. 230 weeks and 3 persons allocated 100%, then the project lead time will be: There are 52 / 3 = 17 sprints in a year, so about 4 sprints per Quarter. Hence
each sprint can contain about 10 / 4 = 2.5 weeks of booked work per person at
100% project allocation.
With e.g. 230 weeks and 3 persons allocated 100%, then the project lead time
will be:
230 (booked weeks) / 40 (weeks/year) / 3 (persons) * 1.25 (netto) = 2.4 years 230 (booked weeks) / 40 (weeks/year) / 3 (persons) * 1.25 (netto) = 2.4 years
This then means that with the SDP work starting 1 jan 2020 it can complete mid 2022. This then means that with the SDP work starting 1 jan 2020 it can complete mid
2022.
******************************************************************************* *******************************************************************************
* L3 integration test platforms towards CDR * L3 integration test platforms towards CDR
******************************************************************************* *******************************************************************************
1) Laboratory tests 1) Lab Test Station (LTS) - First-light Mai 2020
Objectives: Verification of (parts of) individyual elements and their interfaces Objectives: Verification of (parts of) individyual elements and their
interfaces
- 1 UniBoard2 Rev 2 (use different FPGA on same UniBoard for FW, SW tests) - 1 UniBoard2 Rev 2 (use different FPGA on same UniBoard for FW, SW tests)
Setups for: Setups for:
- SW - SW
...@@ -53,16 +60,19 @@ Setups for: ...@@ -53,16 +60,19 @@ Setups for:
- Complete signal chain - Complete signal chain
2) Dwingeloo Test Station (DTS) - First-light Sep 2020 2) Dwingeloo Test Station (DTS) - First-light Sep 2020
Objectives: Verify that a complete signal chain using the first iteration of L3 hardware design Objectives: Verify that a complete signal chain using the first iteration of
shows no serious issues and that it can be reliably installed in a LOFAR station. L3 hardware design shows no serious issues and that it can be
reliably installed in a LOFAR station.
- 1 UniBoard2 Rev 2 - 1 UniBoard2 Rev 2
- First iteration of electronic boards --> 2 UniBoard2 Rev 3a - First iteration of electronic boards --> 2 UniBoard2 Rev 3a
3) Prototype Test Station (PTS) - First-light Mai 2021 3) Prototype Test Station (PTS) - First-light Mai 2021
Objectives: Verify Station L2 requirements through testing and analysis, and provide evidence to Objectives: Verify Station L2 requirements through testing and analysis, and
the CDR review panel that the designs ensure compliance with all L2 requirements. provide evidence to the CDR review panel that the designs ensure
compliance with all L2 requirements.
- Second iteration of electronic boards --> 4 UniBoard2 Rev 3b - Second iteration of electronic boards --> 4 UniBoard2 Rev 3b
- 4 UniBoard2 Rev 3b in two subracks (one for LBA with 32 RCU2, one for HBA with 32 RCU2) - 4 UniBoard2 Rev 3b in two subracks (one for LBA with 32 RCU2, one for HBA
with 32 RCU2)
- Output to CEP for correlation with other stations - Output to CEP for correlation with other stations
...@@ -72,16 +82,18 @@ Objectives: Verify Station L2 requirements through testing and analysis, and pro ...@@ -72,16 +82,18 @@ Objectives: Verify Station L2 requirements through testing and analysis, and pro
0) Station PDR close out 31 jan 2020 0) Station PDR close out 31 jan 2020
1) Station DDR ? 2020 1) Station DDR Dec 2020
2) Station CDR Dec 2021 2) Station CDR Dec 2021
Objectives: Compliance with all L2 requirements, all risks mitigated, ready for production Objectives: Compliance with all L2 requirements, all risks mitigated, ready
for production
Relevant project dates: Relevant project dates:
- 5-2020 Station DDR ? - 5-2020 Station DDR ?
- 9-2020 first light DTS (will use Rev 2, and 4 RCUs with JESD ADC) - 9-2020 first light DTS (will use Rev 2, and 4 RCUs with JESD ADC)
- 10-2020 Working UniBoard2 Rev 3a - 10-2020 Working UniBoard2 Rev 3a
- 5-2021 first light PTS (can use 2x Rev 3a, but goal is to use 4x Rev 3b, 32 RCU2_L, 32 RCU2_H) - 5-2021 first light PTS (can use 2x Rev 3a, but goal is to use 4x Rev 3b,
32 RCU2_L, 32 RCU2_H)
- 7-2021 Working UniBoard2 Rev 3b - 7-2021 Working UniBoard2 Rev 3b
- 12-2021 Station CDR - 12-2021 Station CDR
- 6-2022 Station rollout start - 6-2022 Station rollout start
...@@ -96,7 +108,8 @@ Includes design, implementation, verification on HW, technical commissioning. ...@@ -96,7 +108,8 @@ Includes design, implementation, verification on HW, technical commissioning.
v1 v2 v1 v2
Infrastructure Infrastructure
10 20 - Development environment using GIT, RadioHDL, updating existing components 10 20 - Development environment using GIT, RadioHDL, updating existing
components
20 . - BSP using Gemini Protocol, ARGS 20 . - BSP using Gemini Protocol, ARGS
10 . - Ethernet access (OSI 1-4) 10 . - Ethernet access (OSI 1-4)
10 20 - Ring access 10 20 - Ring access
...@@ -107,7 +120,8 @@ v1 v2 ...@@ -107,7 +120,8 @@ v1 v2
0 30 - Subband filterbank (oversampled) 0 30 - Subband filterbank (oversampled)
10 . - Beamformer 10 . - Beamformer
20 . - Subband correlator 20 . - Subband correlator
25 . - Transient buffer (DDR4 interface, subband select and DM >= 0, packet format, M&C, 25 . - Transient buffer (DDR4 interface, subband select and DM >= 0,
packet format, M&C,
RW access via M&C) RW access via M&C)
20 . - Transient detection 20 . - Transient detection
20 . - Subband offload 20 . - Subband offload
...@@ -119,23 +133,24 @@ v1 v2 ...@@ -119,23 +133,24 @@ v1 v2
5 - Design revisions and lab tests 5 - Design revisions and lab tests
15 - Technical commissioning 15 - Technical commissioning
v1 : 10 + 20 + 10 + 10 + 15 + 20 + 10 + 20 + 25 + 20 + 20 + 35 = 215 bruto weeks --> 215 / 40 v1 : 10 + 20 + 10 + 10 + 15 + 20 + 10 + 20 + 25 + 20 + 20 + 35 = 215 bruto
= 5.4 FTE ~ 3 people each 2 years weeks --> 215 / 40 = 5.4 FTE ~ 3 people each 2 years
v2 : 10 less for critically sampled PFB v2 : 10 less for critically sampled PFB
10 more for updating existing components 10 more for updating existing components
10 more for ring access 10 more for ring access
30 for oversampled PFB 30 for oversampled PFB
. consider unb2c test part of SDP FW integration and of SDP HW . consider unb2c test part of SDP FW integration and of SDP HW
15 technical commisioning relies on proper Systems Engineering, otherwise may become 15 technical commisioning relies on proper Systems Engineering,
50 weeks otherwise may become 50 weeks
==> EK, JH: v1 estimate of April 2019 is still valid as v2 on 10 Oct 2019. ==> EK, JH: v1 estimate of April 2019 is still valid as v2 on 10 Oct 2019.
v3 : v3 :
Infrastructure Infrastructure
20 - Development environment using GIT, RadioHDL, updating existing components 20 - Development environment using GIT, RadioHDL, updating existing
components
5 - unb2c FPGA pinning 5 - unb2c FPGA pinning
10 - unb2c FPGA interface test designs 10 - unb2c FPGA interface test designs
20 - Board Support Package using Gemini Protocol and ARGS 20 - Board Support Package using Gemini Protocol and ARGS
...@@ -159,10 +174,12 @@ v3 : ...@@ -159,10 +174,12 @@ v3 :
5 - Technical commissioning Prototype Station 5 - Technical commissioning Prototype Station
All: All:
20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 + 30 + 0 + 10 + 5 + 5 = 255 20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 + 30 +
0 + 10 + 5 + 5 = 255
No oversampled filterbank: No oversampled filterbank:
20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 + 0 + 10 + 5 + 5 = 225 20 + 5 + 10 + 20 + 20 + 10 + 15 + 10 + 20 + 10 + 25 + 20 + 20 +
0 + 10 + 5 + 5 = 225
...@@ -182,12 +199,13 @@ Changed tasks: ...@@ -182,12 +199,13 @@ Changed tasks:
Firmware FPGA images: Firmware FPGA images:
- the SDP has one main firmware design unb2c_sdp, - the SDP has one main firmware design unb2c_sdp,
- the integrated design of SDP is revision unb2c_sdp_station, - the integrated design of SDP is revision unb2c_sdp_station,
- per task there are revisions of unb2c_sdp that contain subsets of the SDP functionality, - per task there are revisions of unb2c_sdp that contain subsets of the SDP
functionality,
Deliverables (D) = an item, product : items that are needed for a milestone Deliverables (D) = an item, product : items that are needed for a milestone
Milestones (M) = a moment in time, achievement : 'cake moments' when you demonstrate or review Milestones (M) = a moment in time, achievement : 'cake moments' when you
deliverables as part of a larger system demonstrate or review deliverables as part of a larger system
- integration passed - integration passed
- review passed - review passed
...@@ -198,19 +216,21 @@ Below is the planning in weeks per task, the work includes: ...@@ -198,19 +216,21 @@ Below is the planning in weeks per task, the work includes:
- Firmware that runs on UniBoard2 - Firmware that runs on UniBoard2
weeks task description weeks task description
10 T5.1 Maintain firmware development environment (GIT, RadioHDL, HDL libraries) 10 T5.1 Maintain firmware development environment (GIT, RadioHDL, HDL
libraries)
30 T5.2a UniBoard2 board hardware 30 T5.2a UniBoard2 board hardware
10 T5.2b UniBoard2 test firmware (enable mass production of UniBoard2) 10 T5.2b UniBoard2 test firmware (enable mass production of UniBoard2)
20 T5.3a UniBoard2 board support package (BSP, M&C via Gemini Protocol, use ARGS for doc, 20 T5.3a UniBoard2 board support package (BSP, M&C via Gemini Protocol,
C, VHDL) use ARGS for doc, C, VHDL)
T5.3b SW driver for GP T5.3b SW driver for GP
10 T5.4 Network access via 10GbE (support ARP and ping) 10 T5.4 Network access via 10GbE (support ARP and ping)
20 T5.5 Ring access using test data and BSN monitor (support ring) 20 T5.5 Ring access using test data and BSN monitor (support ring)
20 T5.6 Detailed design SDP firmware (Required documents: SDP RS, FW detailed design, 20 T5.6 Detailed design SDP firmware (Required documents: SDP RS, FW
ICDs, FW manual) detailed design, ICDs, FW manual)
15 T5.7 ADC input and timestamp (RCU2 interface, capture timestamped data for offline 15 T5.7 ADC input and timestamp (RCU2 interface, capture timestamped
analysis) data for offline analysis)
10 T5.8 Subband filterbank (Fsub, critically sampled, calibrated subbands, SST) 10 T5.8 Subband filterbank (Fsub, critically sampled, calibrated
subbands, SST)
20 T5.9 Subband correlator (XC, one subband per 1 s integration) 20 T5.9 Subband correlator (XC, one subband per 1 s integration)
10 T5.10 Beamformer (BF, BST, beamlet output to CEP) 10 T5.10 Beamformer (BF, BST, beamlet output to CEP)
25 T5.11 Transient buffer (TB, ADC data, subband data) 25 T5.11 Transient buffer (TB, ADC data, subband data)
...@@ -221,11 +241,13 @@ Milestone : SDP ready for CDR: ...@@ -221,11 +241,13 @@ Milestone : SDP ready for CDR:
All major technical UniBoard2 hardware and SDP firmware risks are mitigated: All major technical UniBoard2 hardware and SDP firmware risks are mitigated:
- by design - by design
- SDP hardware and interfaces validated with at least two UniBoard2 using JTAG, firmware for BSP, - SDP hardware and interfaces validated with at least two UniBoard2 using
ring and ADC JTAG, firmware for BSP, ring and ADC
- Station validated using BF calibrated beamlet output to CEP and correlated with other Stations - Station validated using BF calibrated beamlet output to CEP and correlated
with other Stations
The remaining tasks concern completing the applications that the firmware needs to perform. The remaining tasks concern completing the applications that the firmware
needs to perform.
weeks task description weeks task description
20 T5.12 Transient detection (TDET) 20 T5.12 Transient detection (TDET)
...@@ -237,23 +259,24 @@ weeks task description ...@@ -237,23 +259,24 @@ weeks task description
Weeks Task Person Date Platform Deliverable description Weeks Task Person Date Platform Deliverable description
10 T5.1 Maintain firmware development environment (GIT, RadioHDL, 10 T5.1 Maintain firmware development
environment (GIT, RadioHDL,
ARGS, HDL libraries) ARGS, HDL libraries)
PD * HDL libraries in git/hdl PD * HDL libraries in git/hdl
PD * RadioHDL in git/radiohdl PD * RadioHDL in git/radiohdl
PD * ARGS in git/args PD * ARGS in git/args
PD - Maintain ARGS (e.g. for improved document generation) PD - Maintain ARGS (e.g. for improved document generation)
DS - HDL libraries regression test in git/hdl repository DS - HDL libraries regression test in git/hdl repository
EK - Code review procedure using GIT, branches and Jira EK - Code review procedure using GIT, branches and Jira
EK - Updated RadioHDL user guide EK - Updated RadioHDL user guide
EK - Updated RadioHDL programmers guide EK - Updated RadioHDL programmers guide
EK - Paper on RadioHDL EK - Paper on RadioHDL
EK - Updated ARGS user guide EK - Updated ARGS user guide
EK - Design document for ARGS HDL code generation EK - Design document for ARGS HDL code generation
EK - General HDL coding EK - General HDL coding
. Paper on RTL coding style . Paper on RTL coding style
. Global reset in sosi record . Global reset in sosi record
. Map between AXI bus and Avalon bus (both MM, ST) . Map between AXI bus and Avalon bus (both MM, ST)
25 T5.2a UniBoard2 board hardware 25 T5.2a UniBoard2 board hardware
1 GS 12-2019 D UniBoard2 Detailed Design document 1 GS 12-2019 D UniBoard2 Detailed Design document
...@@ -268,56 +291,75 @@ Weeks Task Person Date Platform Deliverable description ...@@ -268,56 +291,75 @@ Weeks Task Person Date Platform Deliverable description
3 GS 7-2021 D UniBoard2 production version Rev3b 3 GS 7-2021 D UniBoard2 production version Rev3b
GS,JH 7-2021 Lab,PTS M Working UniBoard2 Rev 3b GS,JH 7-2021 Lab,PTS M Working UniBoard2 Rev 3b
10 T5.2b UniBoard2 test firmware + lab tests to enable mass 10 T5.2b UniBoard2 test firmware + lab tests to
production of UniBoard2 enable mass production of UniBoard2
JH 2-2020 D unb2c_test_pinning (using 10GbE) JH 2-2020 D unb2c_test_pinning (using 10GbE)
JH 2-2020 D unb2c_test_pinning_jesd (using JESD204b) JH 2-2020 D unb2c_test_pinning_jesd (using
JH 2-2020 D unb2c_heater (verify speed grade using clk = 256 MHz) JESD204B)
JH 2-2020 - M Complete pinning + heater firmware package for unb2c JH 2-2020 D unb2c_heater (verify speed grade using
clk = 256 MHz)
Test designs unb2c_test_* can be prepared using UCP BSP, but JH 2-2020 - M Complete pinning + heater firmware
aim to use GP BSP at 7-2020. Converting from UCP to GP package for unb2c
involves instantiating new GP BSP VHDL and using peek/poke
via CSIRO GP driver. Test designs unb2c_test_* can be prepared
using UCP BSP, but aim to use GP BSP at
7-2020. Converting from UCP to GP
involves instantiating new GP BSP VHDL
and using
peek/poke via CSIRO GP driver.
JH 4-2020 D unb2c_test_ddr4 (both slots) JH 4-2020 D unb2c_test_ddr4 (both slots)
JH 4-2020 D unb2c_test_10GbE (front = QSFP + ring, back) JH 4-2020 D unb2c_test_10GbE (front = QSFP + ring,
JH 4-2020 D unb2c_test_adc (= lofar2_unb2b_adc_one_node for unb2c) back)
PD 6-2020 D unb2c_minimal_gp (BSP) (= unb2b_minimal_gp for unb2c) JH 4-2020 D unb2c_test_adc (=
. 1GbE (two revisions, one for each port) lofar2_unb2b_adc_one_node for unb2c)
PD 6-2020 D unb2c_minimal_gp (BSP) (=
unb2b_minimal_gp for unb2c)
. 1GbE (two revisions, one for each
port)
. PPS . PPS
. Flash . Flash
. internal FPGA monitor (temperature) . internal FPGA monitor (temperature)
JH 6-2020 M Complete test + BSP firmware package for unb2c HW JH 6-2020 M Complete test + BSP firmware package
for unb2c HW
20 T5.3a UniBoard2 FW board support package (BSP, M&C via Gemini
Protocol (GP), use ARGS for doc, C, VHDL) 20 T5.3a UniBoard2 FW board support package (BSP,
LH 2-2020 D Gemini LRU board for initial SW M&C tests M&C via Gemini Protocol (GP), use ARGS
for doc, C, VHDL)
LH 2-2020 D Gemini LRU board for initial SW M&C
tests
PD 5-2020 D unb2b_minimal_gp (BSP + M&C) PD 5-2020 D unb2b_minimal_gp (BSP + M&C)
PD 5-2020 Lab M Working BSP unb2b_minimal_gp + SW M&C PD 5-2020 Lab M Working BSP unb2b_minimal_gp + SW M&C
Aim is to automate using ARGS, fallback is to do by hand: Aim is to automate using ARGS, fallback
10-2020 D ARGS for VHDL slave generation (design in Task 5.1) is to do by hand:
10-2020 D ARGS for VHDL slave generation (design
in Task 5.1)
? T5.3b UniBoard2 SW driver ? T5.3b UniBoard2 SW driver
10-2020 d ARGS for SW driver generation 10-2020 d ARGS for SW driver generation
. CSIRO generates C header file for Gemini Protocol and . CSIRO generates C header file for
MM register map. Gemini Protocol and MM register map.
10 T5.4 Network access via 10GbE (support ARP request and ping 10 T5.4 Network access via 10GbE (support ARP
response) request and ping response)
RW 4-2020 D unb2c_network (10GbE + MAC statistics + ARP + ping + M&C) RW 4-2020 D unb2c_network (10GbE + MAC statistics
+ ARP + ping + M&C)
20 T5.5 Ring access, transport and alignment (using BG) 20 T5.5 Ring access, transport and alignment
(using BG)
D lofar2_unb2c_ring_sum D lofar2_unb2c_ring_sum
D lofar2_unb2c_ring_mux D lofar2_unb2c_ring_mux
. Control ring transport . Control ring transport
. Monitor ring transport, latency, alignment and timing . Monitor ring transport, latency,
alignment and timing
12-2020 Lab M Working ring + SW M&C 12-2020 Lab M Working ring + SW M&C
20 T5.6 Detailed design SDP (Required documents: SDP RS, FW detailed 20 T5.6 Detailed design SDP (Required documents:
SDP RS, FW detailed
design, ICDs, FW manual) design, ICDs, FW manual)
EK D SDP requirements specification (for DDR, CDR) EK D SDP requirements specification (for
EK D SDP architectural design document (for DDR, CDR) DDR, CDR)
EK D SDP architectural design document (for
DDR, CDR)
. toplevel structure of lofar2_unb2c . toplevel structure of lofar2_unb2c
. bsp . bsp
. timing (+ ICD STF-SDP) . timing (+ ICD STF-SDP)
...@@ -340,112 +382,137 @@ Weeks Task Person Date Platform Deliverable description ...@@ -340,112 +382,137 @@ Weeks Task Person Date Platform Deliverable description
EK d ICD RCU2S-SDP EK d ICD RCU2S-SDP
GS d ICD STF-SDP GS d ICD STF-SDP
GS D ICD SDP-STCA GS D ICD SDP-STCA
EK 6-2020 DDR M Complete SDP document package for Station DDR EK 6-2020 DDR M Complete SDP document package for DDR
all 12-2021 CDR M Complete SDP document package for Station CDR all 12-2021 CDR M Complete SDP document package for CDR
D Test & verification report per firmware deliverable D Test & verification report per firmware
. requirement + test case + result (readme.txt or doc) deliverable
. requirement + test case + result
15 T5.7 ADC input and timestamp (RCU2 interface, capture timestamped (readme.txt or doc)
data for offline analysis)
2-2020 Lab D lofar2_unb2b_adc_one_node (12 ADC + DB + M&C JESD + M&C) 15 T5.7 ADC input and timestamp (RCU2 interface,
. use data buffer (DB) to read captured samples via M&C capture timestamped data for offline
. on two nodes and power cycle to verify synchronisation analysis)
2-2020 Lab D lofar2_unb2b_adc_one_node (12 ADC + DB
+ M&C JESD + M&C)
. use data buffer (DB) to read captured
samples via M&C
. on two nodes and power cycle to
verify synchronisation
5-2020 Lab D lofar2_unb2b_adc_full 5-2020 Lab D lofar2_unb2b_adc_full
. waveform generator (WG) . waveform generator (WG)
. timestamp (ToD, BSN) . timestamp (ToD, BSN)
. delay buffer . delay buffer
. statistics (mean, power, histogram)) . statistics (mean, power, histogram))
JH 9-2020 DTS M Working ADC input and timestamp + SW M&C JH 9-2020 DTS M Working ADC input and timestamp + M&C
10 T5.8 Subband filterbank (Fsub, critically sampled, calibrated 10 T5.8 Subband filterbank (Fsub, critically
subbands, SST) sampled, calibrated subbands, SST)
6-2020 D lofar2_unb2c_filterbank_sst (12 ADC + SST + M&C) 6-2020 D lofar2_unb2c_filterbank_sst (12 ADC +
9-2020 D lofar2_unb2c_filterbank_full (+ calibration weights) SST + M&C)
9-2020 D lofar2_unb2c_filterbank_full (+
calibration weights)
9-2020 DTS M Working subband filterbank + SW M&C 9-2020 DTS M Working subband filterbank + SW M&C
. read and plot SST . read and plot SST
. control calibration weights . control calibration weights
15 T5.9 Subband correlator (XC, one subband per 1 s integration) 15 T5.9 Subband correlator (XC, one subband per
9-2020 D lofar2_unb2c_correlator_one_node (12 ADC + M&C) 1 s integration)
9-2020 D lofar2_unb2c_correlator_one_node (12
ADC + M&C)
D lofar2_unb2c_correlator_full (+ ring) D lofar2_unb2c_correlator_full (+ ring)
7-2021 PTS M Working Subband correlator + SW M&C 7-2021 PTS M Working Subband correlator + SW M&C
. control crosslet selection . control crosslet selection
. read and plot crosslet statistics (XST) . read and plot crosslet statistics
(XST)
15 T5.10 Beamformer (BF, BST, beamlet output to CEP) 15 T5.10 Beamformer (BF, BST, beamlet output to
9-2020 DTS D lofar2_unb2c_output_one_input (1 ADC + output via 10GbE) CEP)
9-2020 DTS D lofar2_unb2c_output_one_input (1 ADC +
output via 10GbE)
. select subbands from one input . select subbands from one input
. packetize subbands into packet . packetize subbands into packet
. control beamlet output (scaling, packetizing) . control beamlet output (scaling,
packetizing)
all 9-2020 DTS M Entire signal chain available at DTS all 9-2020 DTS M Entire signal chain available at DTS
. XC for one node . XC for one node
. BF output for one ADC input . BF output for one ADC input
D lofar2_unb2c_beamformer_output (12 ADC + BST + output via D lofar2_unb2c_beamformer_output (12 ADC
10GbE + M&C) + BST + output via 10GbE + M&C)
D lofar2_unb2c_beamformer_full (+ ring) D lofar2_unb2c_beamformer_full (+ ring)
7-2021 PTS M Working Station beamformer + SW M&C 7-2021 PTS M Working Station beamformer + SW M&C
. read and plot beamlet statistics (BST) . read and plot beamlet statistics
(BST)
25 T5.11 Transient buffer (TB, ADC data, subband data)
D lofar2_unb2c_transient_buffer_ddr4_access (direct read and 25 T5.11 Transient buffer (TB, ADC data, subband
write of DDR4 via M&C) data)
D lofar2_unb2c_transient_buffer_one_node (12 ADC + setup, D lofar2_unb2c_transient_buffer_ddr4_access
write ADC data, freeze, read via M&C) (direct read and write of DDR4 via M&C)
12-2020 Lab M Working Transient buffer and read DDR4 via M&C D lofar2_unb2c_transient_buffer_one_node
7-2021 Lab D lofar2_unb2c_transient_buffer_output (+ read out via 10GbE) (12 ADC + setup, write ADC data, freeze,
7-2021 PTS D lofar2_unb2c_transient_buffer_full (+ ring) read via M&C)
12-2021 PTS M Working Transient buffer and read via 10GbE + SW M&C 12-2020 Lab M Working Transient buffer and read DDR4
via M&C
7-2021 Lab D lofar2_unb2c_transient_buffer_output
(+ read out via 10GbE)
7-2021 PTS D lofar2_unb2c_transient_buffer_full (+
ring)
12-2021 PTS M Working Transient buffer and read via
10GbE + SW M&C
20 T5.12 Transient detection (TDET) 20 T5.12 Transient detection (TDET)
12-2021 PTS D lofar2_unb2c_transient_detection (12 ADC, detection and 12-2021 PTS D lofar2_unb2c_transient_detection (12
trigger + M&C) ADC, detection and trigger + M&C)
12-2021 Rollout M Working Transient detection + SW M&C 12-2021 Rollout M Working Transient detection + SW M&C
20 T5.13 Subband offload (SO) for AARTFAAC2.0 20 T5.13 Subband offload (SO) for AARTFAAC2.0
12-2020 Lab D lofar2_unb2c_subband_offload_output (12 ADC + packetized 12-2020 Lab D lofar2_unb2c_subband_offload_output (12
output via 10GbE + M&C) ADC + packetized output via 10GbE +
6-2022 PTS D lofar2_unb2c_subband_offload_full (+ ring) M&C)
6-2022 PTS D lofar2_unb2c_subband_offload_full (+
ring)
6-2022 Rollout M Working Subband offload + SW M&C 6-2022 Rollout M Working Subband offload + SW M&C
20 T5.14 Station test and verification 20 T5.14 Station test and verification
12-2021 PTS D lofar2_unb2c_sdp_station (all BF, XC, TD, TDET, SO) 12-2021 PTS D lofar2_unb2c_sdp_station (all BF, XC,
6-2022 Rollout M Operational Station Firmware (all BF, XC, TD, TDET, SO) TD, TDET, SO)
+ SW M&C 6-2022 Rollout M Operational Station Firmware (all BF,
XC, TD, TDET, SO) + SW M&C
SDP milestones: SDP milestones:
Weeks Task Person Date Platform Milestone description Person Date Platform Milestone description
JH 2-2020 - M Complete pinning + heater firmware package for unb2c JH 2-2020 - M Complete pinning + heater firmware package
GS 4-2020 M Design review UniBoard2 Rev 3a for unb2c
PD 5-2020 Lab M Working BSP unb2b_minimal_gp + SW M&C GS 4-2020 M Design review UniBoard2 Rev 3a
JH 6-2020 M Complete test + BSP firmware package for unb2c HW PD 5-2020 Lab M Working BSP unb2b_minimal_gp + SW M&C
JH 6-2020 M Complete test + BSP firmware package for unb2c HW
EK 6-2020 DDR M Complete SDP document package for Station DDR EK 6-2020 DDR M Complete SDP document package for Station DDR
JH 9-2020 DTS M Working ADC input and timestamp + SW M&C JH 9-2020 DTS M Working ADC input and timestamp + SW M&C
9-2020 DTS M Working subband filterbank + SW M&C 9-2020 DTS M Working subband filterbank + SW M&C
all 9-2020 DTS M Entire signal chain available at DTS all 9-2020 DTS M Entire signal chain available at DTS
. XC for one node . XC for one node
. BF output for one ADC input . BF output for one ADC input
GS,JH 10-2020 Lab M Working UniBoard2 Rev 3a GS,JH 10-2020 Lab M Working UniBoard2 Rev 3a
GS 12-2020 M UniBoard2 Rev 3b review GS 12-2020 M UniBoard2 Rev 3b review
12-2020 Lab M Working ring + SW M&C 12-2020 Lab M Working ring + SW M&C
12-2020 Lab M Working Transient buffer and read DDR4 via M&C 12-2020 Lab M Working Transient buffer and read DDR4 via M&C
GS,JH 7-2021 Lab,PTS M Working UniBoard2 Rev 3b GS,JH 7-2021 Lab,PTS M Working UniBoard2 Rev 3b
7-2021 PTS M Working Subband correlator + SW M&C 7-2021 PTS M Working Subband correlator + SW M&C
7-2021 PTS M Working Station beamformer + SW M&C 7-2021 PTS M Working Station beamformer + SW M&C
12-2021 PTS M Working Transient buffer and read via 10gbE + SW M&C 12-2021 PTS M Working Transient buffer and read via 10gbE + M&C
12-2021 PTS M Working Transient detection + SW M&C 12-2021 PTS M Working Transient detection + SW M&C
all 12-2021 CDR M Complete SDP document package for Station CDR all 12-2021 CDR M Complete SDP document package for Station CDR
6-2022 Rollout M Working Subband offload + SW M&C 6-2022 Rollout M Working Subband offload + SW M&C
6-2022 Rollout M Operational Station Firmware (all BF, XC, TD, TDET, SO) 6-2022 Rollout M Operational Station Firmware (all BF, XC, TD,
+ SW M&C TDET, SO) + SW M&C
******************************************************************************* *******************************************************************************
...@@ -454,14 +521,15 @@ Weeks Task Person Date Platform Milestone description ...@@ -454,14 +521,15 @@ Weeks Task Person Date Platform Milestone description
- PDR estimates (dec 2019) - PDR estimates (dec 2019)
SDP HW : Task 5.2a : 25 weeks SDP HW : Task 5.2a : 25 weeks
SDP FW : Task 5.1-5.13 : 10 + 10 + 20 + 10 + 20 + 20 + 15 + 10 + 15 + 15 + 25 + 20 + 20 = SDP FW : Task 5.1-5.13 : 10 + 10 + 20 + 10 + 20 + 20 + 15 + 10 + 15 + 15 +
25 + 20 + 20 =
210 weeks 210 weeks
Task 5.14 : 20 weeks Task 5.14 : 20 weeks
==> HW total 25 weeks ==> HW total 25 weeks
==> FW total 230 weeks ==> FW total 230 weeks
- AAD estimnates (okt 2018) - AAD estimnates (okt 2018)
AAD FW : FW Application : 4.8 FTE = 4.8 * 40 = 192 weeks AAD FW : FW Application : 4.8 FTE = 4.8 * 40 = 192 weeks
FW Commissioning : 35 weeks --> 192 + 35 = 230 weeks FW Commissioning : 35 weeks --> 192 + 35 = 230 weeks
. I/O 20 . I/O 20
...@@ -472,48 +540,196 @@ Weeks Task Person Date Platform Milestone description ...@@ -472,48 +540,196 @@ Weeks Task Person Date Platform Milestone description
. XC 20 . XC 20
. TBB 60 . TBB 60
. FW for control 40 . FW for control 40
Sum: 20 + 30 + 30 + 10 + 20 + 20 + 60 + 40 = 230 with critical Fsub Sum: 20 + 30 + 30 + 10 + 20 + 20 + 60 + 40 = 230 with critical
Fsub
weeks AAD task description weeks AAD task description
10 T5.1 Maintain FW development environment 10 T5.1 Maintain FW development environment
25 T5.2a UniBoard2 board hardware 25 T5.2a UniBoard2 board hardware
10 20 I/O T5.2b UniBoard2 test firmware (enable mass production of UniBoard2) 10 20 I/O T5.2b UniBoard2 test firmware (enable mass production)
20 30 BSP T5.3a UniBoard2 board support package 20 30 BSP T5.3a UniBoard2 board support package
T5.3b SW driver for GP T5.3b SW driver for GP
10 T5.4 Network access via 10GbE (support ARP and ping) 10 T5.4 Network access via 10GbE (support ARP and ping)
20 BF/TBB T5.5 Ring access 20 BF/TBB T5.5 Ring access
20 T5.6 Detailed design SDP firmware 20 T5.6 Detailed design SDP firmware
15 30 ADC T5.7 ADC input and timestamp 15 30 ADC T5.7 ADC input and timestamp
10 10 Fsub T5.8 Subband filterbank (Fsub, critically sampled, calibrated subbands, SST) 10 10 Fsub T5.8 Subband filterbank (Fsub, Ros=1, weights, SST)
15 T5.9 Subband correlator (XC, one subband per 1 s integration) 15 T5.9 Subband correlator (XC, one subband per 1 s)
15 20 BF T5.10 Beamformer 15 20 BF T5.10 Beamformer
25 60 TBB T5.11 Transient buffer (TB, ADC data, subband data) 25 60 TBB T5.11 Transient buffer (TB, ADC data, subband data)
20 TBB T5.12 Transient detection (TDET) 20 TBB T5.12 Transient detection (TDET)
20 T5.13 Subband offload (SO) for AARTFAAC2.0 20 T5.13 Subband offload (SO) for AARTFAAC2.0
20 35 Comm T5.14 Station test and verification (using unb2c_sdp_station) 20 35 Comm T5.14 Station test and verification (using
unb2c_sdp_station)
The AAD estimates for I/O + BSP + ADC + Fsub + BF + TBB + FW control =
The AAD estimates for I/O + BSP + ADC + Fsub + BF + TBB + FW control =
20 + 30 + 30 + 10 + 20 + 20 + 60 + 40 = 230 weeks with critical Fsub 20 + 30 + 30 + 10 + 20 + 20 + 60 + 40 = 230 weeks with critical Fsub
These tasks include detailed design and TBB includes TB + TDET. These tasks include detailed design and TBB includes TB + TDET.
JH,PD already spend about 30 weeks in 2019. JH,PD already spend about 30 weeks in 2019.
==> FW total 230 weeks, does not include ==> FW total 230 weeks, does not include
- PDR work on SDP in relation to rest if Station and LOFAR2.0 for ADD and SDP work package - PDR work on SDP in relation to rest if Station and LOFAR2.0 for ADD
management (EK spend about 30 weeks for this in 2019) and SDP work package management (EK spend about 30 weeks for this
in 2019)
- Subband offload for AARTFAAC2.0 (about 20 weeks) - Subband offload for AARTFAAC2.0 (about 20 weeks)
- Comparision - Comparision
The 'corrected' 2019 AAD estimate is: The 'corrected' 2019 AAD estimate is:
2019 AAD estimate = 2018 AAD estimate - (planned 2019 work JH,PD) 2019 AAD estimate = 2018 AAD estimate - (planned 2019 work JH,PD)
+ (unplanned AARTFAAC2.0) + (unplanned AARTFAAC2.0)
= 230 - 30 + 20 = 220 = 230 - 30 + 20 = 220
2019 PDR estimate = 230 2019 PDR estimate = 230
So the difference is -10 weeks, which means that the 2019 PDR is about -10 / 230 = 5 % more
time then the 2018 AAD estimate.
So the difference is -10 weeks, which means that the 2019 PDR is about -10
/ 230 = 5 % more time then the 2018 AAD estimate.
*******************************************************************************
* SDP effort estimates in LOFAR2.0 Station WP5 (since jan 2020)
*
* https://support.astron.nl/confluence/display/STAT/WP-5+SDP
*
*******************************************************************************
weeks hours name task description
10 400 PD/EK T5.1 Maintain FW development environment
30 1200 GS T5.2a UniBoard2 board hardware
10 400 JH T5.2b UniBoard2 test firmware (enable mass production)
20 800 PD T5.3a UniBoard2 board support package
LH T5.3b SW driver for GP
10 400 RW T5.4 Network access via 10GbE (support ARP and ping)
20 800 - T5.5 Ring access
20 800 EK T5.6 Detailed design SDP firmware
15 600 JH T5.7 ADC input and timestamp
10 400 - T5.8 Subband filterbank (Fsub, R_os = 1, weigths, SST)
20 800 - T5.9 Subband correlator (XC, one subband per 1 s)
10 400 - T5.10 Beamformer
25 1000 - T5.11 Transient buffer (TB, ADC data, subband data)
20 800 - T5.12 Transient detection (TDET)
+ +
--- ----
220 8800
20 (800) - T5.13 Subband offload (SO) for AARTFAAC2.0
20 800 - T5.14 Station test and verification after CDR (using
unb2c_sdp_station)
*******************************************************************************
* Q1 = Increment 1 Lab Test Station (LTS)
*******************************************************************************
Main deliverables
- EK: D19/20 SDP design documents for LTS
- JH: D25 unb2b_adc_full
- PD: D11 unb2b_minimal_gp (= BSP)
- EK: D41 ICD SC-SDP for unb2b_minimal_gp
- LH: D42 SDP OPC-UA server
- RW: D10 10GbE arp, ping
Current planning per person:
RW:
Q1: finish unb2c_network for 10GbE with ARP request and ping response on HW
GS: unb2c
- Production package proto unb2c (D9)
JH: ADC ingest and timing
sp1: finish unb2b_test_adc_one_node (D8,24) using revisions
. unb2b arria10 libraries working in simulation, including tech_jesd
sp2: unb2b_test_adc_full (D25), includes timing, DB, WG, statistics and M&C
sp3: lab test integration of unb2b_test_adc_full (D25)
sp4: finish unb2c pinning and heater designs (D3,4,5) for Uniboard2
production package (D9)
PD: BSP (= unb2b_minimal_gp)
sp1: ARP and ping on unb2b HW + use VHDL MM bus
sp2: Add Gemini Protocol (GP) firmware and read version in simulation
sp3: Gemini Protocol (GP) on hardware (D11)
sp4: lab test integration of unb2b_minimal_gp (D11)
EK: Designs Documentation
sp1: Design documents for SDP in confluence
. top level, timing and ADC
. BSP (= unb2b_minimal_gp)
. prestudy note on oversampled filterbank
sp2: Assist with new VHDL:
. BSN source with BSN offset
. synchronous SOSI reset
. ADC and processing clock domains
sp3: Design documents for SDP in confluence
. ring
. correlator
sp4: Prepare for Q2
LH: SDP-OPC-UA server
sp1: Investigate M&C software from CSIRO. Describe MM map of unb2b_minimal_gp
in ARGS yaml.
sp2: Investigate representation of MM map in OPC-UA. Draft design for SDP
OPC-UA server
sp3: Prototype of SDP OPC-UA server
sp4: lab test integration of SDP OPC-UA server with unb2b_minimal_gp
Other:
- synchronous sosi reset
- rename g_revision_id into g_stamp_revision (unb2b, unb2c) and add it to unb1
- remove g_technology from unb2b board designs, rely on c_technology_default
-------------------------------------------------------------------------------
-- BSP Detailed planning:
-------------------------------------------------------------------------------
BSP - PD
1) arp, ping
- extend eth1g module library
- create unb2b_arp_ping design library
. no eth1g files in this dir
. check clk delata-cycle assignments in ctrl_unb2b_board
. use eth from eth lib (so not from eth1g, as long as it can remain the same)
- unb2b_arp_ping + eth1g_master.vhd + tb_unb2b_arp_ping based on tb_eth.vhd
- reply arp and ping in eth1g_master
- toggle pout_wdi (used to be done by unb_osy)
- pass on other traffic to external master
- EK: fix g_sim = TRUE and g_sim_level = 1 in tb_eth.vhd (sim_tse.vhd)
- EK: create common_mem_wait_request_adapter.vhd, necessary to access TSE port
via the MM bus.
==> working unb2b_arp_ping in simulation
==> working unb2b_arp_ping on HW
2) gp_master = gemini protocol master
- create gp library
- extract gemini protocol master (gp_master) from CSIRO at Rx/Tx packet
interface
- simulate gp_master in tb_gp_master with rx MM request and tx MM response to
simulate a MM access via GP to a MM slave reg
==> working gp_master with tb_gp_master in simulation
- integrate gp_master + eth1g_master in mmm_unb2b_arp_ping_gp
==> working unb2b_arp_ping_gp in simulation
==> working unb2b_arp_ping_gp on HW
3) unb2b_minimal_gp
- create unb2b_minimal_gp design library (so not a revision of unb2b_minimal)
- integrate MM bus using common_mem_bus.vhd and common_mem_master_mux.vhd
- manually connect all ctrl_unb2b_minimal slaves to the MM bus
==> working unb2b_minimal_gp in simulation (at least compile, load, run 1 us)
==> working unb2b_minimal_gp on HW
4) MM bus from YAML
- use unb2b_minimal_gp reg map in YAML and use this to automaticly generate
mmm_<design_name> MM bus
*******************************************************************************
* Q2 = Increment 2
*******************************************************************************
- finish unb2c_test designs
- design document for SDP BF, BF output to CEP (D21)
- design document for SDP Transient buffer
- subband filterbank
- subband correlator on one node
- beamformer output to CEP
- ring (Cédric Dumez-Viou ?)
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