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Commit cf0e699c authored by Reinier van der Walle's avatar Reinier van der Walle
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Merge branch 'master' into L2SDP-497

parents e52a6020 a2e24900
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applications/lofar2/designs/lofar2_unb2b_sdp_station/lofar2_unb2b_sdp_station.mmap.gold
+ 518
− 515
View file @ cf0e699c
...@@ -18,518 +18,521 @@ number_of_columns = 13 ...@@ -18,518 +18,521 @@ number_of_columns = 13
# col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port # col 12: mm_peripheral_span (in MM words), if - then the span is not used or already defined on first line of MM port
# col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port # col 13: mm_port_span (in MM words), if - then the span is not used or already defined on first line of MM port
# #
# col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13 # col1 col2 col3 col4 col5 col6 col7 col8 col9 col10 col11 col12 col13
# ------------------------ ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- ----- # ---------------------------- ---- ---- ----- ---------------------------------------- ---------- ------ ----- ----------- ---------- ---------- ----- -----
ROM_SYSTEM_INFO 1 1 RAM data 0x00004000 32768 RO char8 b[31:0] b[7:0] - - ROM_SYSTEM_INFO 1 1 RAM data 0x00000000 32768 RO char8 b[31:0] b[7:0] - -
PIO_SYSTEM_INFO 1 1 REG info 0x00000000 1 RO uint32 b[31:0] - - - PIO_SYSTEM_INFO 1 1 REG info 0x00008000 1 RO uint32 b[31:0] - - -
- - - - info_gn_index 0x00000000 1 RO uint32 b[7:0] - - - - - - - info_gn_index 0x00008000 1 RO uint32 b[7:0] - - -
- - - - info_hw_version 0x00000000 1 RO uint32 b[9:8] - - - - - - - info_hw_version 0x00008000 1 RO uint32 b[9:8] - - -
- - - - info_cs_sim 0x00000000 1 RO uint32 b[10:10] - - - - - - - info_cs_sim 0x00008000 1 RO uint32 b[10:10] - - -
- - - - info_fw_version_major 0x00000000 1 RO uint32 b[19:16] - - - - - - - info_fw_version_major 0x00008000 1 RO uint32 b[19:16] - - -
- - - - info_fw_version_minor 0x00000000 1 RO uint32 b[23:20] - - - - - - - info_fw_version_minor 0x00008000 1 RO uint32 b[23:20] - - -
- - - - info_rom_version 0x00000000 1 RO uint32 b[26:24] - - - - - - - info_rom_version 0x00008000 1 RO uint32 b[26:24] - - -
- - - - info_technology 0x00000000 1 RO uint32 b[31:27] - - - - - - - info_technology 0x00008000 1 RO uint32 b[31:27] - - -
- - - - use_phy 0x00000001 1 RO uint32 b[7:0] - - - - - - - use_phy 0x00008001 1 RO uint32 b[7:0] - - -
- - - - design_name 0x00000002 52 RO char8 b[31:0] b[7:0] - - - - - - design_name 0x00008002 52 RO char8 b[31:0] b[7:0] - -
- - - - stamp_date 0x0000000f 1 RO uint32 b[31:0] - - - - - - - stamp_date 0x0000800f 1 RO uint32 b[31:0] - - -
- - - - stamp_time 0x00000010 1 RO uint32 b[31:0] - - - - - - - stamp_time 0x00008010 1 RO uint32 b[31:0] - - -
- - - - stamp_commit 0x00000011 3 RO uint32 b[31:0] - - - - - - - stamp_commit 0x00008011 3 RO uint32 b[31:0] - - -
- - - - design_note 0x00000014 52 RO char8 b[31:0] b[7:0] - - - - - - design_note 0x00008014 52 RO char8 b[31:0] b[7:0] - -
REG_WDI 1 1 REG wdi_override 0x00000c00 1 WO uint32 b[31:0] - - - REG_WDI 1 1 REG wdi_override 0x0000a000 1 WO uint32 b[31:0] - - -
REG_FPGA_TEMP_SENS 1 1 REG temp 0x0002d048 1 RO uint32 b[31:0] - - - REG_FPGA_TEMP_SENS 1 1 REG temp 0x0000c000 1 RO uint32 b[31:0] - - -
REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0002d030 6 RO uint32 b[31:0] - - - REG_FPGA_VOLTAGE_SENS 1 1 REG voltages 0x0000c000 6 RO uint32 b[31:0] - - -
RAM_SCRAP 1 1 RAM data 0x00000200 512 RW uint32 b[31:0] - - - RAM_SCRAP 1 1 RAM data 0x0000e000 512 RW uint32 b[31:0] - - -
AVS_ETH_0_TSE 1 1 REG status 0x00000400 1024 RO uint32 b[31:0] - - - AVS_ETH_0_TSE 1 1 REG status 0x00010000 1024 RO uint32 b[31:0] - - -
AVS_ETH_0_REG 1 1 REG status 0x0002d000 12 RO uint32 b[31:0] - - - AVS_ETH_0_REG 1 1 REG status 0x00010000 12 RO uint32 b[31:0] - - -
AVS_ETH_0_RAM 1 1 RAM data 0x00000800 1024 RW uint32 b[31:0] - - - AVS_ETH_0_RAM 1 1 RAM data 0x00010400 1024 RW uint32 b[31:0] - - -
PIO_PPS 1 1 REG capture_cnt 0x0002d06c 1 RO uint32 b[29:0] - - - PIO_PPS 1 1 REG capture_cnt 0x00012000 1 RO uint32 b[29:0] - - -
- - - - stable 0x0002d06c 1 RO uint32 b[30:30] - - - - - - - stable 0x00012000 1 RO uint32 b[30:30] - - -
- - - - toggle 0x0002d06c 1 RO uint32 b[31:31] - - - - - - - toggle 0x00012000 1 RO uint32 b[31:31] - - -
- - - - expected_cnt 0x0002d06d 1 RW uint32 b[27:0] - - - - - - - expected_cnt 0x00012001 1 RW uint32 b[27:0] - - -
- - - - edge 0x0002d06d 1 RW uint32 b[31:31] - - - - - - - edge 0x00012001 1 RW uint32 b[31:31] - - -
- - - - offset_cnt 0x0002d06e 1 RO uint32 b[27:0] - - - - - - - offset_cnt 0x00012002 1 RO uint32 b[27:0] - - -
REG_EPCS 1 1 REG addr 0x0002d050 1 WO uint32 b[23:0] - - - REG_EPCS 1 1 REG addr 0x00014000 1 WO uint32 b[23:0] - - -
- - - - rden 0x0002d051 1 WO uint32 b[0:0] - - - - - - - rden 0x00014001 1 WO uint32 b[0:0] - - -
- - - - read_bit 0x0002d052 1 WO uint32 b[0:0] - - - - - - - read_bit 0x00014002 1 WO uint32 b[0:0] - - -
- - - - write_bit 0x0002d053 1 WO uint32 b[0:0] - - - - - - - write_bit 0x00014003 1 WO uint32 b[0:0] - - -
- - - - sector_erase 0x0002d054 1 WO uint32 b[0:0] - - - - - - - sector_erase 0x00014004 1 WO uint32 b[0:0] - - -
- - - - busy 0x0002d055 1 RO uint32 b[0:0] - - - - - - - busy 0x00014005 1 RO uint32 b[0:0] - - -
- - - - unprotect 0x0002d056 1 WO uint32 b[31:0] - - - - - - - unprotect 0x00014006 1 WO uint32 b[31:0] - - -
REG_DPMM_CTRL 1 1 REG rd_usedw 0x0002d082 1 RO uint32 b[31:0] - - - REG_DPMM_CTRL 1 1 REG rd_usedw 0x00016000 1 RO uint32 b[31:0] - - -
REG_DPMM_DATA 1 1 FIFO data 0x0002d080 1 RO uint32 b[31:0] - - - REG_DPMM_DATA 1 1 FIFO data 0x00016400 1 RO uint32 b[31:0] - - -
REG_MMDP_CTRL 1 1 REG wr_usedw 0x0002d07e 1 RO uint32 b[31:0] - - - REG_MMDP_CTRL 1 1 REG wr_usedw 0x00018000 1 RO uint32 b[31:0] - - -
- - - - wr_availw 0x0002d07f 1 RO uint32 b[31:0] - - - - - - - wr_availw 0x00018001 1 RO uint32 b[31:0] - - -
REG_MMDP_DATA 1 1 FIFO data 0x0002d07c 1 WO uint32 b[31:0] - - - REG_MMDP_DATA 1 1 FIFO data 0x00018400 1 WO uint32 b[31:0] - - -
REG_REMU 1 1 REG reconfigure 0x0002d058 1 WO uint32 b[31:0] - - - REG_REMU 1 1 REG reconfigure 0x0001a000 1 WO uint32 b[31:0] - - -
- - - - param 0x0002d059 1 WO uint32 b[2:0] - - - - - - - param 0x0001a001 1 WO uint32 b[2:0] - - -
- - - - read_param 0x0002d05a 1 WO uint32 b[0:0] - - - - - - - read_param 0x0001a002 1 WO uint32 b[0:0] - - -
- - - - write_param 0x0002d05b 1 WO uint32 b[0:0] - - - - - - - write_param 0x0001a003 1 WO uint32 b[0:0] - - -
- - - - data_out 0x0002d05c 1 RO uint32 b[23:0] - - - - - - - data_out 0x0001a004 1 RO uint32 b[23:0] - - -
- - - - data_in 0x0002d05d 1 WO uint32 b[23:0] - - - - - - - data_in 0x0001a005 1 WO uint32 b[23:0] - - -
- - - - busy 0x0002d05e 1 RO uint32 b[0:0] - - - - - - - busy 0x0001a006 1 RO uint32 b[0:0] - - -
REG_SDP_INFO 1 1 REG block_period 0x0002d020 1 RO uint32 b[15:0] - - - REG_SDP_INFO 1 1 REG block_period 0x0001c000 1 RO uint32 b[15:0] - - -
- - - - n_rn 0x0002d021 1 RW uint32 b[7:0] - - - - - - - n_rn 0x0001c001 1 RW uint32 b[7:0] - - -
- - - - o_rn 0x0002d022 1 RW uint32 b[7:0] - - - - - - - o_rn 0x0001c002 1 RW uint32 b[7:0] - - -
- - - - n_si 0x0002d023 1 RW uint32 b[7:0] - - - - - - - n_si 0x0001c003 1 RW uint32 b[7:0] - - -
- - - - o_si 0x0002d024 1 RW uint32 b[7:0] - - - - - - - o_si 0x0001c004 1 RW uint32 b[7:0] - - -
- - - - beam_repositioning_flag 0x0002d025 1 RW uint32 b[0:0] - - - - - - - beam_repositioning_flag 0x0001c005 1 RW uint32 b[0:0] - - -
- - - - fsub_type 0x0002d026 1 RO uint32 b[0:0] - - - - - - - fsub_type 0x0001c006 1 RO uint32 b[0:0] - - -
- - - - f_adc 0x0002d027 1 RO uint32 b[0:0] - - - - - - - f_adc 0x0001c007 1 RO uint32 b[0:0] - - -
- - - - nyquist_zone_index 0x0002d028 1 RW uint32 b[1:0] - - - - - - - nyquist_zone_index 0x0001c008 1 RW uint32 b[1:0] - - -
- - - - observation_id 0x0002d029 1 RW uint32 b[31:0] - - - - - - - observation_id 0x0001c009 1 RW uint32 b[31:0] - - -
- - - - antenna_band_index 0x0002d02a 1 RO uint32 b[0:0] - - - - - - - antenna_band_index 0x0001c00a 1 RO uint32 b[0:0] - - -
- - - - station_id 0x0002d02b 1 RW uint32 b[15:0] - - - - - - - station_id 0x0001c00b 1 RW uint32 b[15:0] - - -
PIO_JESD_CTRL 1 1 REG enable 0x0002d072 1 RW uint32 b[30:0] - - - PIO_JESD_CTRL 1 1 REG enable 0x0001e000 1 RW uint32 b[30:0] - - -
- - - - reset 0x0002d072 1 RW uint32 b[31:31] - - - - - - - reset 0x0001e000 1 RW uint32 b[31:31] - - -
JESD204B 1 12 REG rx_dll_ctrl 0x0002c014 1 RW uint32 b[16:0] - - 256 JESD204B 1 12 REG rx_dll_ctrl 0x00020014 1 RW uint32 b[16:0] - - 256
- - - - rx_syncn_sysref_ctrl 0x0002c015 1 RW uint32 b[24:0] - - - - - - - rx_syncn_sysref_ctrl 0x00020015 1 RW uint32 b[24:0] - - -
- - - - rx_csr_sysref_always_on 0x0002c015 1 RW uint32 b[1:1] - - - - - - - rx_csr_sysref_always_on 0x00020015 1 RW uint32 b[1:1] - - -
- - - - rx_csr_rbd_offset 0x0002c015 1 RW uint32 b[10:3] - - - - - - - rx_csr_rbd_offset 0x00020015 1 RW uint32 b[10:3] - - -
- - - - rx_csr_lmfc_offset 0x0002c015 1 RW uint32 b[19:12] - - - - - - - rx_csr_lmfc_offset 0x00020015 1 RW uint32 b[19:12] - - -
- - - - rx_err0 0x0002c018 1 RW uint32 b[8:0] - - - - - - - rx_err0 0x00020018 1 RW uint32 b[8:0] - - -
- - - - rx_err1 0x0002c019 1 RW uint32 b[9:0] - - - - - - - rx_err1 0x00020019 1 RW uint32 b[9:0] - - -
- - - - csr_dev_syncn 0x0002c020 1 RO uint32 b[0:0] - - - - - - - csr_dev_syncn 0x00020020 1 RO uint32 b[0:0] - - -
- - - - csr_rbd_count 0x0002c020 1 RO uint32 b[10:3] - - - - - - - csr_rbd_count 0x00020020 1 RO uint32 b[10:3] - - -
- - - - rx_status1 0x0002c021 1 RW uint32 b[23:0] - - - - - - - rx_status1 0x00020021 1 RW uint32 b[23:0] - - -
- - - - rx_status2 0x0002c022 1 RW uint32 b[23:0] - - - - - - - rx_status2 0x00020022 1 RW uint32 b[23:0] - - -
- - - - rx_status3 0x0002c023 1 RW uint32 b[7:0] - - - - - - - rx_status3 0x00020023 1 RW uint32 b[7:0] - - -
- - - - rx_ilas_csr_l 0x0002c025 1 RW uint32 b[4:0] - - - - - - - rx_ilas_csr_l 0x00020025 1 RW uint32 b[4:0] - - -
- - - - rx_ilas_csr_f 0x0002c025 1 RW uint32 b[15:8] - - - - - - - rx_ilas_csr_f 0x00020025 1 RW uint32 b[15:8] - - -
- - - - rx_ilas_csr_k 0x0002c025 1 RW uint32 b[20:16] - - - - - - - rx_ilas_csr_k 0x00020025 1 RW uint32 b[20:16] - - -
- - - - rx_ilas_csr_m 0x0002c025 1 RW uint32 b[31:24] - - - - - - - rx_ilas_csr_m 0x00020025 1 RW uint32 b[31:24] - - -
- - - - rx_ilas_csr_n 0x0002c026 1 RW uint32 b[4:0] - - - - - - - rx_ilas_csr_n 0x00020026 1 RW uint32 b[4:0] - - -
- - - - rx_ilas_csr_cs 0x0002c026 1 RW uint32 b[7:6] - - - - - - - rx_ilas_csr_cs 0x00020026 1 RW uint32 b[7:6] - - -
- - - - rx_ilas_csr_np 0x0002c026 1 RW uint32 b[12:8] - - - - - - - rx_ilas_csr_np 0x00020026 1 RW uint32 b[12:8] - - -
- - - - rx_ilas_csr_subclassv 0x0002c026 1 RW uint32 b[15:13] - - - - - - - rx_ilas_csr_subclassv 0x00020026 1 RW uint32 b[15:13] - - -
- - - - rx_ilas_csr_s 0x0002c026 1 RW uint32 b[20:16] - - - - - - - rx_ilas_csr_s 0x00020026 1 RW uint32 b[20:16] - - -
- - - - rx_ilas_csr_jesdv 0x0002c026 1 RW uint32 b[23:21] - - - - - - - rx_ilas_csr_jesdv 0x00020026 1 RW uint32 b[23:21] - - -
- - - - rx_ilas_csr_cf 0x0002c026 1 RW uint32 b[28:24] - - - - - - - rx_ilas_csr_cf 0x00020026 1 RW uint32 b[28:24] - - -
- - - - rx_ilas_csr_hd 0x0002c026 1 RW uint32 b[31:31] - - - - - - - rx_ilas_csr_hd 0x00020026 1 RW uint32 b[31:31] - - -
- - - - rx_status4 0x0002c03c 1 RW uint32 b[15:0] - - - - - - - rx_status4 0x0002003c 1 RW uint32 b[15:0] - - -
- - - - rx_status5 0x0002c03d 1 RW uint32 b[15:0] - - - - - - - rx_status5 0x0002003d 1 RW uint32 b[15:0] - - -
- - - - rx_status6 0x0002c03e 1 RW uint32 b[23:0] - - - - - - - rx_status6 0x0002003e 1 RW uint32 b[23:0] - - -
- - - - rx_status7 0x0002c03f 1 RO uint32 b[31:0] - - - - - - - rx_status7 0x0002003f 1 RO uint32 b[31:0] - - -
REG_DP_SHIFTRAM 1 12 REG shift 0x00000c20 1 RW uint32 b[11:0] - - 2 REG_DP_SHIFTRAM 1 12 REG shift 0x00022000 1 RW uint32 b[11:0] - - 2
REG_BSN_SOURCE_V2 1 1 REG dp_on 0x0002d040 1 RW uint32 b[0:0] - - - REG_BSN_SOURCE_V2 1 1 REG dp_on 0x00024000 1 RW uint32 b[0:0] - - -
- - - - dp_on_pps 0x0002d040 1 RW uint32 b[1:1] - - - - - - - dp_on_pps 0x00024000 1 RW uint32 b[1:1] - - -
- - - - nof_clk_per_sync 0x0002d041 1 RW uint32 b[31:0] - - - - - - - nof_clk_per_sync 0x00024001 1 RW uint32 b[31:0] - - -
- - - - bsn_init 0x0002d042 1 RW uint64 b[31:0] b[31:0] - - - - - - bsn_init 0x00024002 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0002d043 - - - b[31:0] b[63:32] - - - - - - - 0x00024003 - - - b[31:0] b[63:32] - -
- - - - bsn_time_offset 0x0002d044 1 RW uint32 b[9:0] - - - - - - - bsn_time_offset 0x00024004 1 RW uint32 b[9:0] - - -
REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x0002d078 1 RW uint64 b[31:0] b[31:0] - - REG_BSN_SCHEDULER 1 1 REG scheduled_bsn 0x00026000 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x0002d079 - - - b[31:0] b[63:32] - - - - - - - 0x00026001 - - - b[31:0] b[63:32] - -
REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00000100 1 RO uint32 b[0:0] - - - REG_BSN_MONITOR_INPUT 1 1 REG xon_stable 0x00028000 1 RO uint32 b[0:0] - - -
- - - - ready_stable 0x00000100 1 RO uint32 b[1:1] - - - - - - - ready_stable 0x00028000 1 RO uint32 b[1:1] - - -
- - - - sync_timeout 0x00000100 1 RO uint32 b[2:2] - - - - - - - sync_timeout 0x00028000 1 RO uint32 b[2:2] - - -
- - - - bsn_at_sync 0x00000101 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_at_sync 0x00028001 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000102 - - - b[31:0] b[63:32] - - - - - - - 0x00028002 - - - b[31:0] b[63:32] - -
- - - - nof_sop 0x00000103 1 RO uint32 b[31:0] - - - - - - - nof_sop 0x00028003 1 RO uint32 b[31:0] - - -
- - - - nof_valid 0x00000104 1 RO uint32 b[31:0] - - - - - - - nof_valid 0x00028004 1 RO uint32 b[31:0] - - -
- - - - nof_err 0x00000105 1 RO uint32 b[31:0] - - - - - - - nof_err 0x00028005 1 RO uint32 b[31:0] - - -
- - - - bsn_first 0x00000106 1 RO uint64 b[31:0] b[31:0] - - - - - - bsn_first 0x00028006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000107 - - - b[31:0] b[63:32] - - - - - - - 0x00028007 - - - b[31:0] b[63:32] - -
- - - - bsn_first_cycle_cnt 0x00000108 1 RO uint32 b[31:0] - - - - - - - bsn_first_cycle_cnt 0x00028008 1 RO uint32 b[31:0] - - -
REG_WG 1 12 REG mode 0x00000d00 1 RW uint32 b[7:0] - - 4 REG_WG 1 12 REG mode 0x0002a000 1 RW uint32 b[7:0] - - 4
- - - - nof_samples 0x00000d00 1 RW uint32 b[31:16] - - - - - - - nof_samples 0x0002a000 1 RW uint32 b[31:16] - - -
- - - - phase 0x00000d01 1 RW uint32 b[15:0] - - - - - - - phase 0x0002a001 1 RW uint32 b[15:0] - - -
- - - - freq 0x00000d02 1 RW uint32 b[30:0] - - - - - - - freq 0x0002a002 1 RW uint32 b[30:0] - - -
- - - - ampl 0x00000d03 1 RW uint32 b[16:0] - - - - - - - ampl 0x0002a003 1 RW uint32 b[16:0] - - -
RAM_WG 1 12 RAM data 0x00020000 1024 RW uint32 b[17:0] - - 1024 RAM_WG 1 12 RAM data 0x0002c000 1024 RW uint32 b[17:0] - - 1024
REG_ADUH_MONITOR 1 12 REG mean_sum 0x00000d40 1 RO int64 b[31:0] b[31:0] - 4 RAM_ST_HISTOGRAM 1 12 RAM data 0x00030000 512 RW uint32 b[31:0] b[27:0] - 512
- - - - - 0x00000d41 - - - b[31:0] b[63:32] - - REG_ADUH_MONITOR 1 12 REG mean_sum 0x00032000 1 RO int64 b[31:0] b[31:0] - 4
- - - - power_sum 0x00000d42 1 RO int64 b[31:0] b[31:0] - - - - - - - 0x00032001 - - - b[31:0] b[63:32] - -
- - - - - 0x00000d43 - - - b[31:0] b[63:32] - - - - - - power_sum 0x00032002 1 RO int64 b[31:0] b[31:0] - -
REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00000020 1 RO uint32 b[31:0] - - 2 - - - - - 0x00032003 - - - b[31:0] b[63:32] - -
- - - - word_cnt 0x00000021 1 RO uint32 b[31:0] - - - REG_DIAG_DATA_BUFFER_BSN 1 12 REG sync_cnt 0x00034000 1 RO uint32 b[31:0] - - 2
RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00200000 1024 RW uint32 b[15:0] - - 1024 - - - - word_cnt 0x00034001 1 RO uint32 b[31:0] - - -
REG_SI 1 1 REG enable 0x0002d07a 1 RW uint32 b[0:0] - - - RAM_DIAG_DATA_BUFFER_BSN 1 12 RAM data 0x00038000 1024 RW uint32 b[15:0] - - 1024
RAM_FIL_COEFS 1 16 RAM data 0x00024000 1024 RW uint32 b[15:0] - - 1024 REG_SI 1 1 REG enable 0x0003c000 1 RW uint32 b[0:0] - - -
RAM_EQUALIZER_GAINS 1 6 RAM data 0x00006000 1024 RW cint16_ir b[31:0] - - 1024 RAM_FIL_COEFS 1 16 RAM data 0x00040000 1024 RW uint32 b[15:0] - - 1024
REG_DP_SELECTOR 1 1 REG input_select 0x0002d076 1 RW uint32 b[0:0] - - - RAM_EQUALIZER_GAINS 1 6 RAM data 0x00044000 1024 RW cint16_ir b[31:0] - - 1024
RAM_ST_SST 1 6 RAM data 0x00028000 1024 RW uint64 b[31:0] b[31:0] - 2048 REG_DP_SELECTOR 1 1 REG input_select 0x00046000 1 RW uint32 b[0:0] - - -
- - - - - 0x00028001 - - - b[21:0] b[53:32] - - RAM_ST_SST 1 6 RAM data 0x00048000 1024 RW uint64 b[31:0] b[31:0] - 2048
REG_STAT_ENABLE_SST 1 1 REG enable 0x0002d070 1 RW uint32 b[0:0] - - - - - - - - 0x00048001 - - - b[21:0] b[53:32] - -
REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x00000c40 1 RW uint64 b[31:0] b[31:0] - - REG_STAT_ENABLE_SST 1 1 REG enable 0x0004c000 1 RW uint32 b[0:0] - - -
- - - - - 0x00000c41 - - - b[31:0] b[63:32] - - REG_STAT_HDR_DAT_SST 1 1 REG bsn 0x0004e000 1 RW uint64 b[31:0] b[31:0] - -
- - - - sdp_block_period 0x00000c42 1 RW uint32 b[15:0] - - - - - - - - 0x0004e001 - - - b[31:0] b[63:32] - -
- - - - sdp_nof_statistics_per_packet 0x00000c43 1 RW uint32 b[15:0] - - - - - - - sdp_block_period 0x0004e002 1 RW uint32 b[15:0] - - -
- - - - sdp_nof_bytes_per_statistic 0x00000c44 1 RW uint32 b[7:0] - - - - - - - sdp_nof_statistics_per_packet 0x0004e003 1 RW uint32 b[15:0] - - -
- - - - sdp_nof_signal_inputs 0x00000c45 1 RW uint32 b[7:0] - - - - - - - sdp_nof_bytes_per_statistic 0x0004e004 1 RW uint32 b[7:0] - - -
- - - - sdp_data_id 0x00000c46 1 RW uint32 b[31:0] - - - - - - - sdp_nof_signal_inputs 0x0004e005 1 RW uint32 b[7:0] - - -
- - - - sdp_data_id_sst_signal_input_index 0x00000c46 1 RW uint32 b[7:0] - - - - - - - sdp_data_id 0x0004e006 1 RW uint32 b[31:0] - - -
- - - - sdp_data_id_sst_reserved 0x00000c46 1 RW uint32 b[31:8] - - - - - - - sdp_data_id_sst_signal_input_index 0x0004e006 1 RW uint32 b[7:0] - - -
- - - - sdp_integration_interval 0x00000c47 1 RW uint32 b[23:0] - - - - - - - sdp_data_id_sst_reserved 0x0004e006 1 RW uint32 b[31:8] - - -
- - - - sdp_reserved 0x00000c48 1 RW uint32 b[7:0] - - - - - - - sdp_integration_interval 0x0004e007 1 RW uint32 b[23:0] - - -
- - - - sdp_source_info_gn_index 0x00000c49 1 RW uint32 b[4:0] - - - - - - - sdp_reserved 0x0004e008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_reserved 0x00000c4a 1 RW uint32 b[7:5] - - - - - - - sdp_source_info_gn_index 0x0004e009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_subband_calibrated_flag 0x00000c4b 1 RW uint32 b[8:8] - - - - - - - sdp_source_info_reserved 0x0004e00a 1 RW uint32 b[7:5] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x00000c4c 1 RW uint32 b[9:9] - - - - - - - sdp_source_info_subband_calibrated_flag 0x0004e00b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_payload_error 0x00000c4d 1 RW uint32 b[10:10] - - - - - - - sdp_source_info_beam_repositioning_flag 0x0004e00c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_fsub_type 0x00000c4e 1 RW uint32 b[11:11] - - - - - - - sdp_source_info_payload_error 0x0004e00d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_f_adc 0x00000c4f 1 RW uint32 b[12:12] - - - - - - - sdp_source_info_fsub_type 0x0004e00e 1 RW uint32 b[11:11] - - -
- - - - sdp_source_info_nyquist_zone_index 0x00000c50 1 RW uint32 b[14:13] - - - - - - - sdp_source_info_f_adc 0x0004e00f 1 RW uint32 b[12:12] - - -
- - - - sdp_source_info_antenna_band_index 0x00000c51 1 RW uint32 b[15:15] - - - - - - - sdp_source_info_nyquist_zone_index 0x0004e010 1 RW uint32 b[14:13] - - -
- - - - sdp_station_id 0x00000c52 1 RW uint32 b[15:0] - - - - - - - sdp_source_info_antenna_band_index 0x0004e011 1 RW uint32 b[15:15] - - -
- - - - sdp_observation_id 0x00000c53 1 RW uint32 b[31:0] - - - - - - - sdp_station_id 0x0004e012 1 RW uint32 b[15:0] - - -
- - - - sdp_version_id 0x00000c54 1 RO uint32 b[7:0] - - - - - - - sdp_observation_id 0x0004e013 1 RW uint32 b[31:0] - - -
- - - - sdp_marker 0x00000c55 1 RO uint32 b[7:0] - - - - - - - sdp_version_id 0x0004e014 1 RO uint32 b[7:0] - - -
- - - - udp_checksum 0x00000c56 1 RW uint32 b[15:0] - - - - - - - sdp_marker 0x0004e015 1 RO uint32 b[7:0] - - -
- - - - udp_length 0x00000c57 1 RW uint32 b[15:0] - - - - - - - udp_checksum 0x0004e016 1 RW uint32 b[15:0] - - -
- - - - udp_destination_port 0x00000c58 1 RW uint32 b[15:0] - - - - - - - udp_length 0x0004e017 1 RW uint32 b[15:0] - - -
- - - - udp_source_port 0x00000c59 1 RW uint32 b[15:0] - - - - - - - udp_destination_port 0x0004e018 1 RW uint32 b[15:0] - - -
- - - - ip_destination_address 0x00000c5a 1 RW uint32 b[31:0] - - - - - - - udp_source_port 0x0004e019 1 RW uint32 b[15:0] - - -
- - - - ip_source_address 0x00000c5b 1 RW uint32 b[31:0] - - - - - - - ip_destination_address 0x0004e01a 1 RW uint32 b[31:0] - - -
- - - - ip_header_checksum 0x00000c5c 1 RW uint32 b[15:0] - - - - - - - ip_source_address 0x0004e01b 1 RW uint32 b[31:0] - - -
- - - - ip_protocol 0x00000c5d 1 RW uint32 b[7:0] - - - - - - - ip_header_checksum 0x0004e01c 1 RW uint32 b[15:0] - - -
- - - - ip_time_to_live 0x00000c5e 1 RW uint32 b[7:0] - - - - - - - ip_protocol 0x0004e01d 1 RW uint32 b[7:0] - - -
- - - - ip_fragment_offset 0x00000c5f 1 RW uint32 b[12:0] - - - - - - - ip_time_to_live 0x0004e01e 1 RW uint32 b[7:0] - - -
- - - - ip_flags 0x00000c60 1 RW uint32 b[2:0] - - - - - - - ip_fragment_offset 0x0004e01f 1 RW uint32 b[12:0] - - -
- - - - ip_identification 0x00000c61 1 RW uint32 b[15:0] - - - - - - - ip_flags 0x0004e020 1 RW uint32 b[2:0] - - -
- - - - ip_total_length 0x00000c62 1 RW uint32 b[15:0] - - - - - - - ip_identification 0x0004e021 1 RW uint32 b[15:0] - - -
- - - - ip_services 0x00000c63 1 RW uint32 b[7:0] - - - - - - - ip_total_length 0x0004e022 1 RW uint32 b[15:0] - - -
- - - - ip_header_length 0x00000c64 1 RW uint32 b[3:0] - - - - - - - ip_services 0x0004e023 1 RW uint32 b[7:0] - - -
- - - - ip_version 0x00000c65 1 RW uint32 b[3:0] - - - - - - - ip_header_length 0x0004e024 1 RW uint32 b[3:0] - - -
- - - - eth_type 0x00000c66 1 RO uint32 b[15:0] - - - - - - - ip_version 0x0004e025 1 RW uint32 b[3:0] - - -
- - - - eth_source_mac 0x00000c67 1 RO uint64 b[31:0] b[31:0] - - - - - - eth_type 0x0004e026 1 RO uint32 b[15:0] - - -
- - - - - 0x00000c68 - - - b[15:0] b[47:32] - - - - - - eth_source_mac 0x0004e027 1 RO uint64 b[31:0] b[31:0] - -
- - - - eth_destination_mac 0x00000c69 1 RW uint64 b[31:0] b[31:0] - - - - - - - 0x0004e028 - - - b[15:0] b[47:32] - -
- - - - - 0x00000c6a - - - b[15:0] b[47:32] - - - - - - eth_destination_mac 0x0004e029 1 RW uint64 b[31:0] b[31:0] - -
- - - - word_align 0x00000c6b 1 RW uint32 b[15:0] - - - - - - - - 0x0004e02a - - - b[15:0] b[47:32] - -
REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00000c10 1 RW uint32 b[0:0] - - - - - - - word_align 0x0004e02b 1 RW uint32 b[15:0] - - -
- - - - ctrl_interval_size 0x00000c11 1 RW uint32 b[31:0] - - - REG_BSN_SYNC_SCHEDULER_XSUB 1 1 REG ctrl_enable 0x00050000 1 RW uint32 b[0:0] - - -
- - - - ctrl_start_bsn 0x00000c12 1 RW uint64 b[31:0] b[31:0] - - - - - - ctrl_interval_size 0x00050001 1 RW uint32 b[30:0] - - -
- - - - - 0x00000c13 - - - b[31:0] b[63:32] - - - - - - ctrl_start_bsn 0x00050002 1 RW uint64 b[31:0] b[31:0] - -
- - - - mon_current_input_bsn 0x00000c14 1 RO uint64 b[31:0] b[31:0] - - - - - - - 0x00050003 - - - b[31:0] b[63:32] - -
- - - - - 0x00000c15 - - - b[31:0] b[63:32] - - - - - - mon_current_input_bsn 0x00050004 1 RO uint64 b[31:0] b[31:0] - -
- - - - mon_output_enable 0x00000c16 1 RO uint32 b[0:0] - - - - - - - - 0x00050005 - - - b[31:0] b[63:32] - -
- - - - mon_output_sync_bsn 0x00000c17 1 RO uint64 b[31:0] b[31:0] - - - - - - mon_input_bsn_at_sync 0x00050006 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00000c18 - - - b[31:0] b[63:32] - - - - - - - 0x00050007 - - - b[31:0] b[63:32] - -
- - - - block_size 0x00000c19 1 RO uint32 b[31:0] - - - - - - - mon_output_enable 0x00050008 1 RO uint32 b[0:0] - - -
RAM_ST_XSQ 1 9 RAM data 0x00018000 144 RW cint64_ir b[31:0] b[31:0] - 1028 - - - - mon_output_sync_bsn 0x00050009 1 RO uint64 b[31:0] b[31:0] - -
- - - - - 0x00018001 - - - b[31:0] b[63:32] - - - - - - - 0x0005000a - - - b[31:0] b[63:32] - -
REG_CROSSLETS_INFO 1 1 REG offset 0x0002d010 15 RW uint32 b[31:0] - - - - - - - block_size 0x0005000b 1 RO uint32 b[31:0] - - -
- - - - step 0x0002d01f 1 RW uint32 b[31:0] - - - RAM_ST_XSQ 1 9 RAM data 0x00054000 144 RW cint64_ir b[31:0] b[31:0] - 1024
REG_STAT_ENABLE_XST 1 1 REG enable 0x00000c02 1 RW uint32 b[0:0] - - - - - - - - 0x00054001 - - - b[31:0] b[63:32] - -
REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x00000040 1 RW uint64 b[31:0] b[31:0] - - REG_CROSSLETS_INFO 1 1 REG offset 0x00058000 15 RW uint32 b[31:0] - - -
- - - - - 0x00000041 - - - b[31:0] b[63:32] - - - - - - step 0x0005800f 1 RW uint32 b[31:0] - - -
- - - - block_period 0x00000042 1 RW uint32 b[15:0] - - - REG_STAT_ENABLE_XST 1 1 REG enable 0x0005a000 1 RW uint32 b[0:0] - - -
- - - - nof_statistics_per_packet 0x00000043 1 RW uint32 b[15:0] - - - REG_STAT_HDR_DAT_XST 1 1 REG bsn 0x0005c000 1 RW uint64 b[31:0] b[31:0] - -
- - - - nof_bytes_per_statistic 0x00000044 1 RW uint32 b[7:0] - - - - - - - - 0x0005c001 - - - b[31:0] b[63:32] - -
- - - - nof_signal_inputs 0x00000045 1 RW uint32 b[7:0] - - - - - - - block_period 0x0005c002 1 RW uint32 b[15:0] - - -
- - - - sdp_data_id 0x00000046 1 RW uint32 b[31:0] - - - - - - - nof_statistics_per_packet 0x0005c003 1 RW uint32 b[15:0] - - -
- - - - sdp_data_id_xst_signal_input_b_index 0x00000046 1 RW uint32 b[7:0] - - - - - - - nof_bytes_per_statistic 0x0005c004 1 RW uint32 b[7:0] - - -
- - - - sdp_data_id_xst_signal_input_a_index 0x00000046 1 RW uint32 b[15:8] - - - - - - - nof_signal_inputs 0x0005c005 1 RW uint32 b[7:0] - - -
- - - - sdp_data_id_xst_subband_index 0x00000046 1 RW uint32 b[24:16] - - - - - - - sdp_data_id 0x0005c006 1 RW uint32 b[31:0] - - -
- - - - sdp_data_id_xst_reserved 0x00000046 1 RW uint32 b[31:25] - - - - - - - sdp_data_id_xst_signal_input_b_index 0x0005c006 1 RW uint32 b[7:0] - - -
- - - - sdp_integration_interval 0x00000047 1 RW uint32 b[23:0] - - - - - - - sdp_data_id_xst_signal_input_a_index 0x0005c006 1 RW uint32 b[15:8] - - -
- - - - sdp_reserved 0x00000048 1 RW uint32 b[7:0] - - - - - - - sdp_data_id_xst_subband_index 0x0005c006 1 RW uint32 b[24:16] - - -
- - - - sdp_source_info_gn_index 0x00000049 1 RW uint32 b[4:0] - - - - - - - sdp_data_id_xst_reserved 0x0005c006 1 RW uint32 b[31:25] - - -
- - - - sdp_source_info_reserved 0x0000004a 1 RW uint32 b[7:5] - - - - - - - sdp_integration_interval 0x0005c007 1 RW uint32 b[23:0] - - -
- - - - sdp_source_info_subband_calibrated_flag 0x0000004b 1 RW uint32 b[8:8] - - - - - - - sdp_reserved 0x0005c008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0000004c 1 RW uint32 b[9:9] - - - - - - - sdp_source_info_gn_index 0x0005c009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_payload_error 0x0000004d 1 RW uint32 b[10:10] - - - - - - - sdp_source_info_reserved 0x0005c00a 1 RW uint32 b[7:5] - - -
- - - - sdp_source_info_fsub_type 0x0000004e 1 RW uint32 b[11:11] - - - - - - - sdp_source_info_subband_calibrated_flag 0x0005c00b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_f_adc 0x0000004f 1 RW uint32 b[12:12] - - - - - - - sdp_source_info_beam_repositioning_flag 0x0005c00c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_nyquist_zone_index 0x00000050 1 RW uint32 b[14:13] - - - - - - - sdp_source_info_payload_error 0x0005c00d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_antenna_band_index 0x00000051 1 RW uint32 b[15:15] - - - - - - - sdp_source_info_fsub_type 0x0005c00e 1 RW uint32 b[11:11] - - -
- - - - sdp_station_id 0x00000052 1 RW uint32 b[15:0] - - - - - - - sdp_source_info_f_adc 0x0005c00f 1 RW uint32 b[12:12] - - -
- - - - sdp_observation_id 0x00000053 1 RW uint32 b[31:0] - - - - - - - sdp_source_info_nyquist_zone_index 0x0005c010 1 RW uint32 b[14:13] - - -
- - - - sdp_version_id 0x00000054 1 RO uint32 b[7:0] - - - - - - - sdp_source_info_antenna_band_index 0x0005c011 1 RW uint32 b[15:15] - - -
- - - - sdp_marker 0x00000055 1 RO uint32 b[7:0] - - - - - - - sdp_station_id 0x0005c012 1 RW uint32 b[15:0] - - -
- - - - udp_checksum 0x00000056 1 RW uint32 b[15:0] - - - - - - - sdp_observation_id 0x0005c013 1 RW uint32 b[31:0] - - -
- - - - udp_length 0x00000057 1 RW uint32 b[15:0] - - - - - - - sdp_version_id 0x0005c014 1 RO uint32 b[7:0] - - -
- - - - udp_destination_port 0x00000058 1 RW uint32 b[15:0] - - - - - - - sdp_marker 0x0005c015 1 RO uint32 b[7:0] - - -
- - - - udp_source_port 0x00000059 1 RW uint32 b[15:0] - - - - - - - udp_checksum 0x0005c016 1 RW uint32 b[15:0] - - -
- - - - ip_destination_address 0x0000005a 1 RW uint32 b[31:0] - - - - - - - udp_length 0x0005c017 1 RW uint32 b[15:0] - - -
- - - - ip_source_address 0x0000005b 1 RW uint32 b[31:0] - - - - - - - udp_destination_port 0x0005c018 1 RW uint32 b[15:0] - - -
- - - - ip_header_checksum 0x0000005c 1 RW uint32 b[15:0] - - - - - - - udp_source_port 0x0005c019 1 RW uint32 b[15:0] - - -
- - - - ip_protocol 0x0000005d 1 RW uint32 b[7:0] - - - - - - - ip_destination_address 0x0005c01a 1 RW uint32 b[31:0] - - -
- - - - ip_time_to_live 0x0000005e 1 RW uint32 b[7:0] - - - - - - - ip_source_address 0x0005c01b 1 RW uint32 b[31:0] - - -
- - - - ip_fragment_offset 0x0000005f 1 RW uint32 b[12:0] - - - - - - - ip_header_checksum 0x0005c01c 1 RW uint32 b[15:0] - - -
- - - - ip_flags 0x00000060 1 RW uint32 b[2:0] - - - - - - - ip_protocol 0x0005c01d 1 RW uint32 b[7:0] - - -
- - - - ip_identification 0x00000061 1 RW uint32 b[15:0] - - - - - - - ip_time_to_live 0x0005c01e 1 RW uint32 b[7:0] - - -
- - - - ip_total_length 0x00000062 1 RW uint32 b[15:0] - - - - - - - ip_fragment_offset 0x0005c01f 1 RW uint32 b[12:0] - - -
- - - - ip_services 0x00000063 1 RW uint32 b[7:0] - - - - - - - ip_flags 0x0005c020 1 RW uint32 b[2:0] - - -
- - - - ip_header_length 0x00000064 1 RW uint32 b[3:0] - - - - - - - ip_identification 0x0005c021 1 RW uint32 b[15:0] - - -
- - - - ip_version 0x00000065 1 RW uint32 b[3:0] - - - - - - - ip_total_length 0x0005c022 1 RW uint32 b[15:0] - - -
- - - - eth_type 0x00000066 1 RO uint32 b[15:0] - - - - - - - ip_services 0x0005c023 1 RW uint32 b[7:0] - - -
- - - - eth_source_mac 0x00000067 1 RO uint64 b[31:0] b[31:0] - - - - - - ip_header_length 0x0005c024 1 RW uint32 b[3:0] - - -
- - - - - 0x00000068 - - - b[15:0] b[47:32] - - - - - - ip_version 0x0005c025 1 RW uint32 b[3:0] - - -
- - - - eth_destination_mac 0x00000069 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_type 0x0005c026 1 RO uint32 b[15:0] - - -
- - - - - 0x0000006a - - - b[15:0] b[47:32] - - - - - - eth_source_mac 0x0005c027 1 RO uint64 b[31:0] b[31:0] - -
- - - - word_align 0x0000006b 1 RW uint32 b[15:0] - - - - - - - - 0x0005c028 - - - b[15:0] b[47:32] - -
RAM_SS_SS_WIDE 2 6 RAM data 0x0001c000 976 RW uint32 b[9:0] - 8192 1024 - - - - eth_destination_mac 0x0005c029 1 RW uint64 b[31:0] b[31:0] - -
RAM_BF_WEIGHTS 2 12 RAM data 0x00010000 976 RW cint16_ir b[31:0] - 16384 1024 - - - - - 0x0005c02a - - - b[15:0] b[47:32] - -
REG_BF_SCALE 2 1 REG scale 0x0002d068 1 RW uint32 b[15:0] - 2 2 - - - - word_align 0x0005c02b 1 RW uint32 b[15:0] - - -
- - - - unused 0x0002d069 1 RW uint32 b[31:0] - - - RAM_SS_SS_WIDE 2 6 RAM data 0x0005e000 976 RW uint32 b[9:0] - 8192 1024
REG_HDR_DAT 2 1 REG bsn 0x00000c80 1 RW uint64 b[31:0] b[31:0] 64 64 RAM_BF_WEIGHTS 2 12 RAM data 0x00064000 976 RW cint16_ir b[31:0] - 16384 1024
- - - - - 0x00000c81 - - - b[31:0] b[63:32] - - REG_BF_SCALE 2 1 REG scale 0x0006c000 1 RW uint32 b[15:0] - 2 2
- - - - sdp_block_period 0x00000c82 1 RW uint32 b[15:0] - - - - - - - unused 0x0006c001 1 RW uint32 b[31:0] - - -
- - - - sdp_nof_beamlets_per_block 0x00000c83 1 RW uint32 b[15:0] - - - REG_HDR_DAT 2 1 REG bsn 0x0006e000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - sdp_nof_blocks_per_packet 0x00000c84 1 RW uint32 b[7:0] - - - - - - - - 0x0006e001 - - - b[31:0] b[63:32] - -
- - - - sdp_beamlet_index 0x00000c85 1 RW uint32 b[15:0] - - - - - - - sdp_block_period 0x0006e002 1 RW uint32 b[15:0] - - -
- - - - sdp_beamlet_scale 0x00000c86 1 RW uint32 b[15:0] - - - - - - - sdp_nof_beamlets_per_block 0x0006e003 1 RW uint32 b[15:0] - - -
- - - - sdp_reserved 0x00000c87 1 RW uint64 b[31:0] b[31:0] - - - - - - sdp_nof_blocks_per_packet 0x0006e004 1 RW uint32 b[7:0] - - -
- - - - - 0x00000c88 - - - b[7:0] b[39:32] - - - - - - sdp_beamlet_index 0x0006e005 1 RW uint32 b[15:0] - - -
- - - - sdp_source_info_gn_index 0x00000c89 1 RW uint32 b[4:0] - - - - - - - sdp_beamlet_scale 0x0006e006 1 RW uint32 b[15:0] - - -
- - - - sdp_source_info_beamlet_width 0x00000c8a 1 RW uint32 b[7:5] - - - - - - - sdp_reserved 0x0006e007 1 RW uint64 b[31:0] b[31:0] - -
- - - - sdp_source_info_repositioning_flag 0x00000c8b 1 RW uint32 b[9:9] - - - - - - - - 0x0006e008 - - - b[7:0] b[39:32] - -
- - - - sdp_source_info_payload_error 0x00000c8c 1 RW uint32 b[10:10] - - - - - - - sdp_source_info_gn_index 0x0006e009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_fsub_type 0x00000c8d 1 RW uint32 b[11:11] - - - - - - - sdp_source_info_beamlet_width 0x0006e00a 1 RW uint32 b[7:5] - - -
- - - - sdp_source_info_f_adc 0x00000c8e 1 RW uint32 b[12:12] - - - - - - - sdp_source_info_repositioning_flag 0x0006e00b 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_nyquist_zone_index 0x00000c8f 1 RW uint32 b[14:13] - - - - - - - sdp_source_info_payload_error 0x0006e00c 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_antenna_band_index 0x00000c90 1 RW uint32 b[15:15] - - - - - - - sdp_source_info_fsub_type 0x0006e00d 1 RW uint32 b[11:11] - - -
- - - - sdp_station_id 0x00000c91 1 RW uint32 b[15:0] - - - - - - - sdp_source_info_f_adc 0x0006e00e 1 RW uint32 b[12:12] - - -
- - - - sdp_observation_id 0x00000c92 1 RW uint32 b[31:0] - - - - - - - sdp_source_info_nyquist_zone_index 0x0006e00f 1 RW uint32 b[14:13] - - -
- - - - sdp_version_id 0x00000c93 1 RO uint32 b[7:0] - - - - - - - sdp_source_info_antenna_band_index 0x0006e010 1 RW uint32 b[15:15] - - -
- - - - sdp_marker 0x00000c94 1 RO uint32 b[7:0] - - - - - - - sdp_station_id 0x0006e011 1 RW uint32 b[15:0] - - -
- - - - udp_checksum 0x00000c95 1 RW uint32 b[15:0] - - - - - - - sdp_observation_id 0x0006e012 1 RW uint32 b[31:0] - - -
- - - - udp_length 0x00000c96 1 RW uint32 b[15:0] - - - - - - - sdp_version_id 0x0006e013 1 RO uint32 b[7:0] - - -
- - - - udp_destination_port 0x00000c97 1 RW uint32 b[15:0] - - - - - - - sdp_marker 0x0006e014 1 RO uint32 b[7:0] - - -
- - - - udp_source_port 0x00000c98 1 RW uint32 b[15:0] - - - - - - - udp_checksum 0x0006e015 1 RW uint32 b[15:0] - - -
- - - - ip_destination_address 0x00000c99 1 RW uint32 b[31:0] - - - - - - - udp_length 0x0006e016 1 RW uint32 b[15:0] - - -
- - - - ip_source_address 0x00000c9a 1 RW uint32 b[31:0] - - - - - - - udp_destination_port 0x0006e017 1 RW uint32 b[15:0] - - -
- - - - ip_header_checksum 0x00000c9b 1 RW uint32 b[15:0] - - - - - - - udp_source_port 0x0006e018 1 RW uint32 b[15:0] - - -
- - - - ip_protocol 0x00000c9c 1 RW uint32 b[7:0] - - - - - - - ip_destination_address 0x0006e019 1 RW uint32 b[31:0] - - -
- - - - ip_time_to_live 0x00000c9d 1 RW uint32 b[7:0] - - - - - - - ip_source_address 0x0006e01a 1 RW uint32 b[31:0] - - -
- - - - ip_fragment_offset 0x00000c9e 1 RW uint32 b[12:0] - - - - - - - ip_header_checksum 0x0006e01b 1 RW uint32 b[15:0] - - -
- - - - ip_flags 0x00000c9f 1 RW uint32 b[2:0] - - - - - - - ip_protocol 0x0006e01c 1 RW uint32 b[7:0] - - -
- - - - ip_identification 0x00000ca0 1 RW uint32 b[15:0] - - - - - - - ip_time_to_live 0x0006e01d 1 RW uint32 b[7:0] - - -
- - - - ip_total_length 0x00000ca1 1 RW uint32 b[15:0] - - - - - - - ip_fragment_offset 0x0006e01e 1 RW uint32 b[12:0] - - -
- - - - ip_services 0x00000ca2 1 RW uint32 b[7:0] - - - - - - - ip_flags 0x0006e01f 1 RW uint32 b[2:0] - - -
- - - - ip_header_length 0x00000ca3 1 RW uint32 b[3:0] - - - - - - - ip_identification 0x0006e020 1 RW uint32 b[15:0] - - -
- - - - ip_version 0x00000ca4 1 RW uint32 b[3:0] - - - - - - - ip_total_length 0x0006e021 1 RW uint32 b[15:0] - - -
- - - - eth_type 0x00000ca5 1 RO uint32 b[15:0] - - - - - - - ip_services 0x0006e022 1 RW uint32 b[7:0] - - -
- - - - eth_source_mac 0x00000ca6 1 RO uint64 b[31:0] b[31:0] - - - - - - ip_header_length 0x0006e023 1 RW uint32 b[3:0] - - -
- - - - - 0x00000ca7 - - - b[15:0] b[47:32] - - - - - - ip_version 0x0006e024 1 RW uint32 b[3:0] - - -
- - - - eth_destination_mac 0x00000ca8 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_type 0x0006e025 1 RO uint32 b[15:0] - - -
- - - - - 0x00000ca9 - - - b[15:0] b[47:32] - - - - - - eth_source_mac 0x0006e026 1 RO uint64 b[31:0] b[31:0] - -
REG_DP_XONOFF 2 1 REG enable_stream 0x0002d064 1 RW uint32 b[0:0] - 2 2 - - - - - 0x0006e027 - - - b[15:0] b[47:32] - -
RAM_ST_BST 2 1 RAM data 0x00001000 976 RW uint64 b[31:0] b[31:0] 2048 2048 - - - - eth_destination_mac 0x0006e028 1 RW uint64 b[31:0] b[31:0] - -
- - - - - 0x00001001 - - - b[21:0] b[53:32] - - - - - - - 0x0006e029 - - - b[15:0] b[47:32] - -
REG_STAT_ENABLE_BST 2 1 REG enable 0x0002d060 1 RW uint32 b[0:0] - 2 2 REG_DP_XONOFF 2 1 REG enable_stream 0x00070000 1 RW uint32 b[0:0] - 2 2
REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00000080 1 RW uint64 b[31:0] b[31:0] 64 64 RAM_ST_BST 2 1 RAM data 0x00072000 976 RW uint64 b[31:0] b[31:0] 2048 2048
- - - - - 0x00000081 - - - b[31:0] b[63:32] - - - - - - - 0x00072001 - - - b[21:0] b[53:32] - -
- - - - block_period 0x00000082 1 RW uint32 b[15:0] - - - REG_STAT_ENABLE_BST 2 1 REG enable 0x00074000 1 RW uint32 b[0:0] - 2 2
- - - - nof_statistics_per_packet 0x00000083 1 RW uint32 b[15:0] - - - REG_STAT_HDR_DAT_BST 2 1 REG bsn 0x00076000 1 RW uint64 b[31:0] b[31:0] 64 64
- - - - nof_bytes_per_statistic 0x00000084 1 RW uint32 b[7:0] - - - - - - - - 0x00076001 - - - b[31:0] b[63:32] - -
- - - - nof_signal_inputs 0x00000085 1 RW uint32 b[7:0] - - - - - - - block_period 0x00076002 1 RW uint32 b[15:0] - - -
- - - - sdp_data_id 0x00000086 1 RW uint32 b[31:0] - - - - - - - nof_statistics_per_packet 0x00076003 1 RW uint32 b[15:0] - - -
- - - - sdp_data_id_bst_beamlet_index 0x00000086 1 RW uint32 b[15:0] - - - - - - - nof_bytes_per_statistic 0x00076004 1 RW uint32 b[7:0] - - -
- - - - sdp_data_id_bst_reserved 0x00000086 1 RW uint32 b[31:16] - - - - - - - nof_signal_inputs 0x00076005 1 RW uint32 b[7:0] - - -
- - - - sdp_integration_interval 0x00000087 1 RW uint32 b[23:0] - - - - - - - sdp_data_id 0x00076006 1 RW uint32 b[31:0] - - -
- - - - sdp_reserved 0x00000088 1 RW uint32 b[7:0] - - - - - - - sdp_data_id_bst_beamlet_index 0x00076006 1 RW uint32 b[15:0] - - -
- - - - sdp_source_info_gn_index 0x00000089 1 RW uint32 b[4:0] - - - - - - - sdp_data_id_bst_reserved 0x00076006 1 RW uint32 b[31:16] - - -
- - - - sdp_source_info_reserved 0x0000008a 1 RW uint32 b[7:5] - - - - - - - sdp_integration_interval 0x00076007 1 RW uint32 b[23:0] - - -
- - - - sdp_source_info_subband_calibrated_flag 0x0000008b 1 RW uint32 b[8:8] - - - - - - - sdp_reserved 0x00076008 1 RW uint32 b[7:0] - - -
- - - - sdp_source_info_beam_repositioning_flag 0x0000008c 1 RW uint32 b[9:9] - - - - - - - sdp_source_info_gn_index 0x00076009 1 RW uint32 b[4:0] - - -
- - - - sdp_source_info_payload_error 0x0000008d 1 RW uint32 b[10:10] - - - - - - - sdp_source_info_reserved 0x0007600a 1 RW uint32 b[7:5] - - -
- - - - sdp_source_info_fsub_type 0x0000008e 1 RW uint32 b[11:11] - - - - - - - sdp_source_info_subband_calibrated_flag 0x0007600b 1 RW uint32 b[8:8] - - -
- - - - sdp_source_info_f_adc 0x0000008f 1 RW uint32 b[12:12] - - - - - - - sdp_source_info_beam_repositioning_flag 0x0007600c 1 RW uint32 b[9:9] - - -
- - - - sdp_source_info_nyquist_zone_index 0x00000090 1 RW uint32 b[14:13] - - - - - - - sdp_source_info_payload_error 0x0007600d 1 RW uint32 b[10:10] - - -
- - - - sdp_source_info_antenna_band_index 0x00000091 1 RW uint32 b[15:15] - - - - - - - sdp_source_info_fsub_type 0x0007600e 1 RW uint32 b[11:11] - - -
- - - - sdp_station_id 0x00000092 1 RW uint32 b[15:0] - - - - - - - sdp_source_info_f_adc 0x0007600f 1 RW uint32 b[12:12] - - -
- - - - sdp_observation_id 0x00000093 1 RW uint32 b[31:0] - - - - - - - sdp_source_info_nyquist_zone_index 0x00076010 1 RW uint32 b[14:13] - - -
- - - - sdp_version_id 0x00000094 1 RO uint32 b[7:0] - - - - - - - sdp_source_info_antenna_band_index 0x00076011 1 RW uint32 b[15:15] - - -
- - - - sdp_marker 0x00000095 1 RO uint32 b[7:0] - - - - - - - sdp_station_id 0x00076012 1 RW uint32 b[15:0] - - -
- - - - udp_checksum 0x00000096 1 RW uint32 b[15:0] - - - - - - - sdp_observation_id 0x00076013 1 RW uint32 b[31:0] - - -
- - - - udp_length 0x00000097 1 RW uint32 b[15:0] - - - - - - - sdp_version_id 0x00076014 1 RO uint32 b[7:0] - - -
- - - - udp_destination_port 0x00000098 1 RW uint32 b[15:0] - - - - - - - sdp_marker 0x00076015 1 RO uint32 b[7:0] - - -
- - - - udp_source_port 0x00000099 1 RW uint32 b[15:0] - - - - - - - udp_checksum 0x00076016 1 RW uint32 b[15:0] - - -
- - - - ip_destination_address 0x0000009a 1 RW uint32 b[31:0] - - - - - - - udp_length 0x00076017 1 RW uint32 b[15:0] - - -
- - - - ip_source_address 0x0000009b 1 RW uint32 b[31:0] - - - - - - - udp_destination_port 0x00076018 1 RW uint32 b[15:0] - - -
- - - - ip_header_checksum 0x0000009c 1 RW uint32 b[15:0] - - - - - - - udp_source_port 0x00076019 1 RW uint32 b[15:0] - - -
- - - - ip_protocol 0x0000009d 1 RW uint32 b[7:0] - - - - - - - ip_destination_address 0x0007601a 1 RW uint32 b[31:0] - - -
- - - - ip_time_to_live 0x0000009e 1 RW uint32 b[7:0] - - - - - - - ip_source_address 0x0007601b 1 RW uint32 b[31:0] - - -
- - - - ip_fragment_offset 0x0000009f 1 RW uint32 b[12:0] - - - - - - - ip_header_checksum 0x0007601c 1 RW uint32 b[15:0] - - -
- - - - ip_flags 0x000000a0 1 RW uint32 b[2:0] - - - - - - - ip_protocol 0x0007601d 1 RW uint32 b[7:0] - - -
- - - - ip_identification 0x000000a1 1 RW uint32 b[15:0] - - - - - - - ip_time_to_live 0x0007601e 1 RW uint32 b[7:0] - - -
- - - - ip_total_length 0x000000a2 1 RW uint32 b[15:0] - - - - - - - ip_fragment_offset 0x0007601f 1 RW uint32 b[12:0] - - -
- - - - ip_services 0x000000a3 1 RW uint32 b[7:0] - - - - - - - ip_flags 0x00076020 1 RW uint32 b[2:0] - - -
- - - - ip_header_length 0x000000a4 1 RW uint32 b[3:0] - - - - - - - ip_identification 0x00076021 1 RW uint32 b[15:0] - - -
- - - - ip_version 0x000000a5 1 RW uint32 b[3:0] - - - - - - - ip_total_length 0x00076022 1 RW uint32 b[15:0] - - -
- - - - eth_type 0x000000a6 1 RO uint32 b[15:0] - - - - - - - ip_services 0x00076023 1 RW uint32 b[7:0] - - -
- - - - eth_source_mac 0x000000a7 1 RO uint64 b[31:0] b[31:0] - - - - - - ip_header_length 0x00076024 1 RW uint32 b[3:0] - - -
- - - - - 0x000000a8 - - - b[15:0] b[47:32] - - - - - - ip_version 0x00076025 1 RW uint32 b[3:0] - - -
- - - - eth_destination_mac 0x000000a9 1 RW uint64 b[31:0] b[31:0] - - - - - - eth_type 0x00076026 1 RO uint32 b[15:0] - - -
- - - - - 0x000000aa - - - b[15:0] b[47:32] - - - - - - eth_source_mac 0x00076027 1 RO uint64 b[31:0] b[31:0] - -
- - - - word_align 0x000000ab 1 RW uint32 b[15:0] - - - - - - - - 0x00076028 - - - b[15:0] b[47:32] - -
REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00002000 1 RW uint32 b[0:0] - - - - - - - eth_destination_mac 0x00076029 1 RW uint64 b[31:0] b[31:0] - -
- - - - rx_transfer_status 0x00002001 1 RO uint32 b[0:0] - - - - - - - - 0x0007602a - - - b[15:0] b[47:32] - -
- - - - tx_transfer_control 0x00002002 1 RW uint32 b[0:0] - - - - - - - word_align 0x0007602b 1 RW uint32 b[15:0] - - -
- - - - rx_padcrc_control 0x00002040 1 RW uint32 b[1:0] - - - REG_NW_10GBE_MAC 1 1 REG rx_transfer_control 0x00078000 1 RW uint32 b[0:0] - - -
- - - - rx_crccheck_control 0x00002080 1 RW uint32 b[1:0] - - - - - - - rx_transfer_status 0x00078001 1 RO uint32 b[0:0] - - -
- - - - rx_pktovrflow_error 0x000020c0 1 RO uint64 b[3:0] b[35:32] - - - - - - tx_transfer_control 0x00078002 1 RW uint32 b[0:0] - - -
- - - - - 0x000020c1 - - - b[31:0] b[31:0] - - - - - - rx_padcrc_control 0x00078040 1 RW uint32 b[1:0] - - -
- - - - rx_pktovrflow_etherstatsdropevents 0x000020c2 1 RO uint64 b[3:0] b[35:32] - - - - - - rx_crccheck_control 0x00078080 1 RW uint32 b[1:0] - - -
- - - - - 0x000020c3 - - - b[31:0] b[31:0] - - - - - - rx_pktovrflow_error 0x000780c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_lane_decoder_preamble_control 0x00002100 1 RW uint32 b[0:0] - - - - - - - - 0x000780c1 - - - b[31:0] b[31:0] - -
- - - - rx_preamble_inserter_control 0x00002140 1 RW uint32 b[0:0] - - - - - - - rx_pktovrflow_etherstatsdropevents 0x000780c2 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_frame_control 0x00002800 1 RW uint32 b[19:0] - - - - - - - - 0x000780c3 - - - b[31:0] b[31:0] - -
- - - - rx_frame_maxlength 0x00002801 1 RW uint32 b[15:0] - - - - - - - rx_lane_decoder_preamble_control 0x00078100 1 RW uint32 b[0:0] - - -
- - - - rx_frame_addr0 0x00002802 1 RW uint32 b[15:0] - - - - - - - rx_preamble_inserter_control 0x00078140 1 RW uint32 b[0:0] - - -
- - - - rx_frame_addr1 0x00002803 1 RW uint32 b[15:0] - - - - - - - rx_frame_control 0x00078800 1 RW uint32 b[19:0] - - -
- - - - rx_frame_spaddr0_0 0x00002804 1 RW uint32 b[15:0] - - - - - - - rx_frame_maxlength 0x00078801 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr0_1 0x00002805 1 RW uint32 b[15:0] - - - - - - - rx_frame_addr0 0x00078802 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_0 0x00002806 1 RW uint32 b[15:0] - - - - - - - rx_frame_addr1 0x00078803 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr1_1 0x00002807 1 RW uint32 b[15:0] - - - - - - - rx_frame_spaddr0_0 0x00078804 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_0 0x00002808 1 RW uint32 b[15:0] - - - - - - - rx_frame_spaddr0_1 0x00078805 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr2_1 0x00002809 1 RW uint32 b[15:0] - - - - - - - rx_frame_spaddr1_0 0x00078806 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_0 0x0000280a 1 RW uint32 b[15:0] - - - - - - - rx_frame_spaddr1_1 0x00078807 1 RW uint32 b[15:0] - - -
- - - - rx_frame_spaddr3_1 0x0000280b 1 RW uint32 b[15:0] - - - - - - - rx_frame_spaddr2_0 0x00078808 1 RW uint32 b[15:0] - - -
- - - - rx_pfc_control 0x00002818 1 RW uint32 b[16:0] - - - - - - - rx_frame_spaddr2_1 0x00078809 1 RW uint32 b[15:0] - - -
- - - - rx_stats_clr 0x00002c00 1 RW uint32 b[0:0] - - - - - - - rx_frame_spaddr3_0 0x0007880a 1 RW uint32 b[15:0] - - -
- - - - rx_stats_framesok 0x00002c02 1 RO uint64 b[3:0] b[35:32] - - - - - - rx_frame_spaddr3_1 0x0007880b 1 RW uint32 b[15:0] - - -
- - - - - 0x00002c03 - - - b[31:0] b[31:0] - - - - - - rx_pfc_control 0x00078818 1 RW uint32 b[16:0] - - -
- - - - rx_stats_frameserr 0x00002c04 1 RO uint64 b[3:0] b[35:32] - - - - - - rx_stats_clr 0x00078c00 1 RW uint32 b[0:0] - - -
- - - - - 0x00002c05 - - - b[31:0] b[31:0] - - - - - - rx_stats_framesok 0x00078c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_framescrcerr 0x00002c06 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c03 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c07 - - - b[31:0] b[31:0] - - - - - - rx_stats_frameserr 0x00078c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_octetsok 0x00002c08 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c05 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c09 - - - b[31:0] b[31:0] - - - - - - rx_stats_framescrcerr 0x00078c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_pausemacctrl_frames 0x00002c0a 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c07 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c0b - - - b[31:0] b[31:0] - - - - - - rx_stats_octetsok 0x00078c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_iferrors 0x00002c0c 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c09 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c0d - - - b[31:0] b[31:0] - - - - - - rx_stats_pausemacctrl_frames 0x00078c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_unicast_framesok 0x00002c0e 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c0b - - - b[31:0] b[31:0] - -
- - - - - 0x00002c0f - - - b[31:0] b[31:0] - - - - - - rx_stats_iferrors 0x00078c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_unicast_frameserr 0x00002c10 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c0d - - - b[31:0] b[31:0] - -
- - - - - 0x00002c11 - - - b[31:0] b[31:0] - - - - - - rx_stats_unicast_framesok 0x00078c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_multicastframesok 0x00002c12 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c0f - - - b[31:0] b[31:0] - -
- - - - - 0x00002c13 - - - b[31:0] b[31:0] - - - - - - rx_stats_unicast_frameserr 0x00078c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_multicast_frameserr 0x00002c14 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c11 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c15 - - - b[31:0] b[31:0] - - - - - - rx_stats_multicastframesok 0x00078c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_broadcastframesok 0x00002c16 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c13 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c17 - - - b[31:0] b[31:0] - - - - - - rx_stats_multicast_frameserr 0x00078c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_broadcast_frameserr 0x00002c18 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c15 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c19 - - - b[31:0] b[31:0] - - - - - - rx_stats_broadcastframesok 0x00078c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstatsoctets 0x00002c1a 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c17 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c1b - - - b[31:0] b[31:0] - - - - - - rx_stats_broadcast_frameserr 0x00078c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstatspkts 0x00002c1c 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c19 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c1d - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstatsoctets 0x00078c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_undersizepkts 0x00002c1e 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c1b - - - b[31:0] b[31:0] - -
- - - - - 0x00002c1f - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstatspkts 0x00078c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_oversizepkts 0x00002c20 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c1d - - - b[31:0] b[31:0] - -
- - - - - 0x00002c21 - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_undersizepkts 0x00078c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_pkts64octets 0x00002c22 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c1f - - - b[31:0] b[31:0] - -
- - - - - 0x00002c23 - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_oversizepkts 0x00078c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_pkts65to127octets 0x00002c24 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c21 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c25 - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_pkts64octets 0x00078c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_pkts128to255octets 0x00002c26 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c23 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c27 - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_pkts65to127octets 0x00078c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_pkts256to511octets 0x00002c28 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c25 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c29 - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_pkts128to255octets 0x00078c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_pkts512to1023octets 0x00002c2a 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c27 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c2b - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_pkts256to511octets 0x00078c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstat_pkts1024to1518octets 0x00002c2c 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c29 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c2d - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_pkts512to1023octets 0x00078c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_pkts1519toxoctets 0x00002c2e 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c2b - - - b[31:0] b[31:0] - -
- - - - - 0x00002c2f - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstat_pkts1024to1518octets 0x00078c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_fragments 0x00002c30 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c2d - - - b[31:0] b[31:0] - -
- - - - - 0x00002c31 - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_pkts1519toxoctets 0x00078c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstats_jabbers 0x00002c32 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c2f - - - b[31:0] b[31:0] - -
- - - - - 0x00002c33 - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_fragments 0x00078c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_etherstatscrcerr 0x00002c34 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c31 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c35 - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstats_jabbers 0x00078c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_unicastmacctrlframes 0x00002c36 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c33 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c37 - - - b[31:0] b[31:0] - - - - - - rx_stats_etherstatscrcerr 0x00078c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_multicastmac_ctrlframes 0x00002c38 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c35 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c39 - - - b[31:0] b[31:0] - - - - - - rx_stats_unicastmacctrlframes 0x00078c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_broadcastmac_ctrlframes 0x00002c3a 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c37 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c3b - - - b[31:0] b[31:0] - - - - - - rx_stats_multicastmac_ctrlframes 0x00078c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - rx_stats_pfcmacctrlframes 0x00002c3c 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00078c39 - - - b[31:0] b[31:0] - -
- - - - - 0x00002c3d - - - b[31:0] b[31:0] - - - - - - rx_stats_broadcastmac_ctrlframes 0x00078c3a 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_transfer_status 0x00003001 1 RO uint32 b[0:0] - - - - - - - - 0x00078c3b - - - b[31:0] b[31:0] - -
- - - - tx_padins_control 0x00003040 1 RW uint32 b[0:0] - - - - - - - rx_stats_pfcmacctrlframes 0x00078c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_crcins_control 0x00003080 1 RW uint32 b[1:0] - - - - - - - - 0x00078c3d - - - b[31:0] b[31:0] - -
- - - - tx_pktunderflow_error 0x000030c0 1 RO uint64 b[3:0] b[35:32] - - - - - - tx_transfer_status 0x00079001 1 RO uint32 b[0:0] - - -
- - - - - 0x000030c1 - - - b[31:0] b[31:0] - - - - - - tx_padins_control 0x00079040 1 RW uint32 b[0:0] - - -
- - - - tx_preamble_control 0x00003100 1 RW uint32 b[0:0] - - - - - - - tx_crcins_control 0x00079080 1 RW uint32 b[1:0] - - -
- - - - tx_pauseframe_control 0x00003140 1 RW uint32 b[1:0] - - - - - - - tx_pktunderflow_error 0x000790c0 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_pauseframe_quanta 0x00003141 1 RW uint32 b[15:0] - - - - - - - - 0x000790c1 - - - b[31:0] b[31:0] - -
- - - - tx_pauseframe_enable 0x00003142 1 RW uint32 b[0:0] - - - - - - - tx_preamble_control 0x00079100 1 RW uint32 b[0:0] - - -
- - - - pfc_pause_quanta_0 0x00003180 1 RW uint32 b[31:0] - - - - - - - tx_pauseframe_control 0x00079140 1 RW uint32 b[1:0] - - -
- - - - pfc_pause_quanta_1 0x00003181 1 RW uint32 b[31:0] - - - - - - - tx_pauseframe_quanta 0x00079141 1 RW uint32 b[15:0] - - -
- - - - pfc_pause_quanta_2 0x00003182 1 RW uint32 b[31:0] - - - - - - - tx_pauseframe_enable 0x00079142 1 RW uint32 b[0:0] - - -
- - - - pfc_pause_quanta_3 0x00003183 1 RW uint32 b[31:0] - - - - - - - pfc_pause_quanta_0 0x00079180 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_4 0x00003184 1 RW uint32 b[31:0] - - - - - - - pfc_pause_quanta_1 0x00079181 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_5 0x00003185 1 RW uint32 b[31:0] - - - - - - - pfc_pause_quanta_2 0x00079182 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_6 0x00003186 1 RW uint32 b[31:0] - - - - - - - pfc_pause_quanta_3 0x00079183 1 RW uint32 b[31:0] - - -
- - - - pfc_pause_quanta_7 0x00003187 1 RW uint32 b[31:0] - - - - - - - pfc_pause_quanta_4 0x00079184 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_0 0x00003190 1 RW uint32 b[31:0] - - - - - - - pfc_pause_quanta_5 0x00079185 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_1 0x00003191 1 RW uint32 b[31:0] - - - - - - - pfc_pause_quanta_6 0x00079186 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_2 0x00003192 1 RW uint32 b[31:0] - - - - - - - pfc_pause_quanta_7 0x00079187 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_3 0x00003193 1 RW uint32 b[31:0] - - - - - - - pfc_holdoff_quanta_0 0x00079190 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_4 0x00003194 1 RW uint32 b[31:0] - - - - - - - pfc_holdoff_quanta_1 0x00079191 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_5 0x00003195 1 RW uint32 b[31:0] - - - - - - - pfc_holdoff_quanta_2 0x00079192 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_6 0x00003196 1 RW uint32 b[31:0] - - - - - - - pfc_holdoff_quanta_3 0x00079193 1 RW uint32 b[31:0] - - -
- - - - pfc_holdoff_quanta_7 0x00003197 1 RW uint32 b[31:0] - - - - - - - pfc_holdoff_quanta_4 0x00079194 1 RW uint32 b[31:0] - - -
- - - - tx_pfc_priority_enable 0x000031a0 1 RW uint32 b[7:0] - - - - - - - pfc_holdoff_quanta_5 0x00079195 1 RW uint32 b[31:0] - - -
- - - - tx_addrins_control 0x00003200 1 RW uint32 b[0:0] - - - - - - - pfc_holdoff_quanta_6 0x00079196 1 RW uint32 b[31:0] - - -
- - - - tx_addrins_macaddr0 0x00003201 1 RW uint32 b[31:0] - - - - - - - pfc_holdoff_quanta_7 0x00079197 1 RW uint32 b[31:0] - - -
- - - - tx_addrins_macaddr1 0x00003202 1 RW uint32 b[15:0] - - - - - - - tx_pfc_priority_enable 0x000791a0 1 RW uint32 b[7:0] - - -
- - - - tx_frame_maxlength 0x00003801 1 RW uint32 b[15:0] - - - - - - - tx_addrins_control 0x00079200 1 RW uint32 b[0:0] - - -
- - - - tx_stats_clr 0x00003c00 1 RW uint32 b[0:0] - - - - - - - tx_addrins_macaddr0 0x00079201 1 RW uint32 b[31:0] - - -
- - - - tx_stats_framesok 0x00003c02 1 RO uint64 b[3:0] b[35:32] - - - - - - tx_addrins_macaddr1 0x00079202 1 RW uint32 b[15:0] - - -
- - - - - 0x00003c03 - - - b[31:0] b[31:0] - - - - - - tx_frame_maxlength 0x00079801 1 RW uint32 b[15:0] - - -
- - - - tx_stats_frameserr 0x00003c04 1 RO uint64 b[3:0] b[35:32] - - - - - - tx_stats_clr 0x00079c00 1 RW uint32 b[0:0] - - -
- - - - - 0x00003c05 - - - b[31:0] b[31:0] - - - - - - tx_stats_framesok 0x00079c02 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_framescrcerr 0x00003c06 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c03 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c07 - - - b[31:0] b[31:0] - - - - - - tx_stats_frameserr 0x00079c04 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_octetsok 0x00003c08 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c05 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c09 - - - b[31:0] b[31:0] - - - - - - tx_stats_framescrcerr 0x00079c06 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_pausemacctrl_frames 0x00003c0a 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c07 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c0b - - - b[31:0] b[31:0] - - - - - - tx_stats_octetsok 0x00079c08 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_iferrors 0x00003c0c 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c09 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c0d - - - b[31:0] b[31:0] - - - - - - tx_stats_pausemacctrl_frames 0x00079c0a 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_unicast_framesok 0x00003c0e 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c0b - - - b[31:0] b[31:0] - -
- - - - - 0x00003c0f - - - b[31:0] b[31:0] - - - - - - tx_stats_iferrors 0x00079c0c 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_unicast_frameserr 0x00003c10 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c0d - - - b[31:0] b[31:0] - -
- - - - - 0x00003c11 - - - b[31:0] b[31:0] - - - - - - tx_stats_unicast_framesok 0x00079c0e 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_multicastframesok 0x00003c12 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c0f - - - b[31:0] b[31:0] - -
- - - - - 0x00003c13 - - - b[31:0] b[31:0] - - - - - - tx_stats_unicast_frameserr 0x00079c10 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_multicast_frameserr 0x00003c14 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c11 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c15 - - - b[31:0] b[31:0] - - - - - - tx_stats_multicastframesok 0x00079c12 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_broadcastframesok 0x00003c16 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c13 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c17 - - - b[31:0] b[31:0] - - - - - - tx_stats_multicast_frameserr 0x00079c14 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_broadcast_frameserr 0x00003c18 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c15 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c19 - - - b[31:0] b[31:0] - - - - - - tx_stats_broadcastframesok 0x00079c16 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstatsoctets 0x00003c1a 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c17 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c1b - - - b[31:0] b[31:0] - - - - - - tx_stats_broadcast_frameserr 0x00079c18 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstatspkts 0x00003c1c 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c19 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c1d - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstatsoctets 0x00079c1a 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_undersizepkts 0x00003c1e 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c1b - - - b[31:0] b[31:0] - -
- - - - - 0x00003c1f - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstatspkts 0x00079c1c 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_oversizepkts 0x00003c20 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c1d - - - b[31:0] b[31:0] - -
- - - - - 0x00003c21 - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_undersizepkts 0x00079c1e 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_pkts64octets 0x00003c22 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c1f - - - b[31:0] b[31:0] - -
- - - - - 0x00003c23 - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_oversizepkts 0x00079c20 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_pkts65to127octets 0x00003c24 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c21 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c25 - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_pkts64octets 0x00079c22 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_pkts128to255octets 0x00003c26 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c23 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c27 - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_pkts65to127octets 0x00079c24 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_pkts256to511octets 0x00003c28 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c25 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c29 - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_pkts128to255octets 0x00079c26 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_pkts512to1023octets 0x00003c2a 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c27 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c2b - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_pkts256to511octets 0x00079c28 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstat_pkts1024to1518octets 0x00003c2c 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c29 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c2d - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_pkts512to1023octets 0x00079c2a 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_pkts1519toxoctets 0x00003c2e 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c2b - - - b[31:0] b[31:0] - -
- - - - - 0x00003c2f - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstat_pkts1024to1518octets 0x00079c2c 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_fragments 0x00003c30 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c2d - - - b[31:0] b[31:0] - -
- - - - - 0x00003c31 - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_pkts1519toxoctets 0x00079c2e 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstats_jabbers 0x00003c32 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c2f - - - b[31:0] b[31:0] - -
- - - - - 0x00003c33 - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_fragments 0x00079c30 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_etherstatscrcerr 0x00003c34 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c31 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c35 - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstats_jabbers 0x00079c32 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_unicastmacctrlframes 0x00003c36 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c33 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c37 - - - b[31:0] b[31:0] - - - - - - tx_stats_etherstatscrcerr 0x00079c34 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_multicastmac_ctrlframes 0x00003c38 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c35 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c39 - - - b[31:0] b[31:0] - - - - - - tx_stats_unicastmacctrlframes 0x00079c36 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_broadcastmac_ctrlframes 0x00003c3a 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c37 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c3b - - - b[31:0] b[31:0] - - - - - - tx_stats_multicastmac_ctrlframes 0x00079c38 1 RO uint64 b[3:0] b[35:32] - -
- - - - tx_stats_pfcmacctrlframes 0x00003c3c 1 RO uint64 b[3:0] b[35:32] - - - - - - - 0x00079c39 - - - b[31:0] b[31:0] - -
- - - - - 0x00003c3d - - - b[31:0] b[31:0] - - - - - - tx_stats_broadcastmac_ctrlframes 0x00079c3a 1 RO uint64 b[3:0] b[35:32] - -
REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0002d074 1 RO uint32 b[0:0] - - - - - - - - 0x00079c3b - - - b[31:0] b[31:0] - -
- - - - xgmii_tx_ready 0x0002d074 1 RO uint32 b[1:1] - - - - - - - tx_stats_pfcmacctrlframes 0x00079c3c 1 RO uint64 b[3:0] b[35:32] - -
- - - - xgmii_link_status 0x0002d074 1 RO uint32 b[3:2] - - - - - - - - 0x00079c3d - - - b[31:0] b[31:0] - -
\ No newline at end of file REG_NW_10GBE_ETH10G 1 1 REG tx_snk_out_xon 0x0007a000 1 RO uint32 b[0:0] - - -
- - - - xgmii_tx_ready 0x0007a000 1 RO uint32 b[1:1] - - -
- - - - xgmii_link_status 0x0007a000 1 RO uint32 b[3:2] - - -
\ No newline at end of file
applications/lofar2/libraries/sdp/src/vhdl/sdp_statistics_offload.vhd
+ 2
− 2
View file @ cf0e699c
...@@ -137,7 +137,7 @@ ARCHITECTURE str OF sdp_statistics_offload IS ...@@ -137,7 +137,7 @@ ARCHITECTURE str OF sdp_statistics_offload IS
integration_interval : NATURAL; integration_interval : NATURAL;
END RECORD; END RECORD;
CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0'), 0, '0', 0, 1); -- integration interval should start at 1 as it is a total count and not an index count. CONSTANT c_reg_rst : t_reg := (0, 0, '0', (OTHERS => '0'), (OTHERS => '0'), 0, '0', 0, 0);
SIGNAL r : t_reg; SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg; SIGNAL nxt_r : t_reg;
...@@ -207,7 +207,7 @@ BEGIN ...@@ -207,7 +207,7 @@ BEGIN
-- Count number of sop's in a sync interval and get payload errors and keep them till next sync. -- Count number of sop's in a sync interval and get payload errors and keep them till next sync.
IF in_sosi.sync = '1' THEN IF in_sosi.sync = '1' THEN
v.integration_interval := r.interval_cnt; v.integration_interval := r.interval_cnt + 1; -- count = index + 1
v.interval_cnt := 0; v.interval_cnt := 0;
v.payload_err := '0'; v.payload_err := '0';
ELSE ELSE
......
applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_statistics_offload.vhd
+ 7
− 4
View file @ cf0e699c
...@@ -48,10 +48,10 @@ USE work.sdp_pkg.ALL; ...@@ -48,10 +48,10 @@ USE work.sdp_pkg.ALL;
ENTITY tb_sdp_statistics_offload IS ENTITY tb_sdp_statistics_offload IS
GENERIC ( GENERIC (
g_statistics_type : STRING := "SST"; g_statistics_type : STRING := "XST";
g_offload_time : NATURAL := 500; g_offload_time : NATURAL := 500;
g_beamset_id : NATURAL := 0; g_beamset_id : NATURAL := 0;
g_P_sq : NATURAL := c_sdp_P_sq g_P_sq : NATURAL := 1 --c_sdp_P_sq
); );
END tb_sdp_statistics_offload; END tb_sdp_statistics_offload;
...@@ -326,12 +326,15 @@ BEGIN ...@@ -326,12 +326,15 @@ BEGIN
REPORT "wrong sdp_block_period" SEVERITY ERROR; REPORT "wrong sdp_block_period" SEVERITY ERROR;
-- Check variable header info. -- Check variable header info.
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_integration_interval") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_integration_interval")) = TO_UVEC(c_nof_block_per_sync, 24)
REPORT "wrong sdp_integration_interval" SEVERITY ERROR;
IF g_statistics_type = "SST" THEN IF g_statistics_type = "SST" THEN
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")) = TO_UVEC(rx_block_cnt + c_sdp_S_pn * gn_index, 32) ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")) = TO_UVEC(rx_block_cnt + c_sdp_S_pn * gn_index, 32)
REPORT "wront SST sdp_data_id" SEVERITY ERROR; REPORT "wrong SST sdp_data_id" SEVERITY ERROR;
ELSIF g_statistics_type = "BST" THEN ELSIF g_statistics_type = "BST" THEN
ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")) = TO_UVEC(c_beamlet_id, 32) ASSERT rx_hdr_fields_raw(field_hi(c_sdp_stat_hdr_field_arr, "sdp_data_id") DOWNTO field_lo(c_sdp_stat_hdr_field_arr, "sdp_data_id")) = TO_UVEC(c_beamlet_id, 32)
REPORT "wront BST sdp_data_id" SEVERITY ERROR; REPORT "wrong BST sdp_data_id" SEVERITY ERROR;
--ELSIF g_statistics_type = "XST" THEN --TODO: RW define check --ELSIF g_statistics_type = "XST" THEN --TODO: RW define check
END IF; END IF;
END IF; END IF;
......
libraries/base/common/src/vhdl/common_mem_pkg.vhd
+ 74
− 42
View file @ cf0e699c
...@@ -18,6 +18,34 @@ ...@@ -18,6 +18,34 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>. -- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
--
-- Author: E. Kooistra, D. vd Schuur
-- Purpose: Simple memory access (for MM control interface)
-- Description:
--
-- Assume the MM bus is for a 32 bit processor, therefore on the processor
-- side of a memory peripheral typcially use c_word_w = 32 for the address
-- and data fields in the MM bus records. However the MM bus can also be used
-- on the user side of a memory peripheral and there the data width should
-- not be limited by the processor type but rather by the maximum user data
-- width on the streaming interface.
--
-- The std_logic_vector widths in the record need to be defined, because in
-- a record they can not be unconstrained. A signal that needs less address
-- or data width simply leaves the unused MSbits at 'X'. The actually used
-- width of a memory gets set via a generic record type t_c_mem.
--
-- The alternative is to not put the std_logic_vector elements in the record,
-- and declare them seperately, however then the compact representation that
-- records provide gets lost, because the record then only contains wr_en and
-- rd_en. Another alternative is to define the address as a integer and the
-- data as an integer. However this limits their range to 32 bit numbers,
-- which can be too few for data.
-- Do not change these widths, because c_word_w just fits in a VHDL INTEGER
-- Should wider address range or data width be needed, then define a new
-- record type eg. t_mem_ctlr or t_mem_bus for that with
-- sufficient widths.
LIBRARY IEEE; LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_1164.ALL;
...@@ -25,34 +53,6 @@ USE IEEE.NUMERIC_STD.ALL; ...@@ -25,34 +53,6 @@ USE IEEE.NUMERIC_STD.ALL;
USE work.common_pkg.ALL; USE work.common_pkg.ALL;
PACKAGE common_mem_pkg IS PACKAGE common_mem_pkg IS
------------------------------------------------------------------------------
-- Simple memory access (for MM control interface)
------------------------------------------------------------------------------
-- Assume the MM bus is for a 32 bit processor, therefore on the processor
-- side of a memory peripheral typcially use c_word_w = 32 for the address
-- and data fields in the MM bus records. However the MM bus can also be used
-- on the user side of a memory peripheral and there the data width should
-- not be limited by the processor type but rather by the maximum user data
-- width on the streaming interface.
--
-- The std_logic_vector widths in the record need to be defined, because in
-- a record they can not be unconstrained. A signal that needs less address
-- or data width simply leaves the unused MSbits at 'X'. The actually used
-- width of a memory gets set via a generic record type t_c_mem.
--
-- The alternative is to not put the std_logic_vector elements in the record,
-- and declare them seperately, however then the compact representation that
-- records provide gets lost, because the record then only contains wr_en and
-- rd_en. Another alternative is to define the address as a integer and the
-- data as an integer. However this limits their range to 32 bit numbers,
-- which can be too few for data.
-- Do not change these widths, because c_word_w just fits in a VHDL INTEGER
-- Should wider address range or data width be needed, then define a new
-- record type eg. t_mem_ctlr or t_mem_bus for that with
-- sufficient widths.
-- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed -- Choose smallest maximum slv lengths that fit all use cases, because unconstrained record fields slv is not allowed
CONSTANT c_mem_address_w : NATURAL := 32; -- address range (suits 32-bit processor) CONSTANT c_mem_address_w : NATURAL := 32; -- address range (suits 32-bit processor)
...@@ -80,9 +80,24 @@ PACKAGE common_mem_pkg IS ...@@ -80,9 +80,24 @@ PACKAGE common_mem_pkg IS
TYPE t_mem_miso_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_miso; TYPE t_mem_miso_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_miso;
TYPE t_mem_mosi_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_mosi; TYPE t_mem_mosi_arr IS ARRAY (INTEGER RANGE <>) OF t_mem_mosi;
-- MOSI/MISO subtypes
SUBTYPE t_mem_copi IS t_mem_mosi; -- Controller Out Peripheral In
SUBTYPE t_mem_cipo IS t_mem_miso; -- Peripheral In Controller Out
CONSTANT c_mem_cipo_rst : t_mem_cipo := c_mem_miso_rst;
CONSTANT c_mem_copi_rst : t_mem_copi := c_mem_mosi_rst;
SUBTYPE t_mem_cipo_arr IS t_mem_miso_arr;
SUBTYPE t_mem_copi_arr IS t_mem_mosi_arr;
-- Reset only the control fields of the MM record -- Reset only the control fields of the MM record
FUNCTION RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) RETURN t_mem_mosi; FUNCTION RESET_MEM_MOSI_CTRL(mosi : t_mem_mosi) RETURN t_mem_mosi; -- deprecated, use RESET_MEM_COPI_CTRL() instead
FUNCTION RESET_MEM_MISO_CTRL(miso : t_mem_miso) RETURN t_mem_miso; FUNCTION RESET_MEM_COPI_CTRL(copi : t_mem_copi) RETURN t_mem_copi;
FUNCTION RESET_MEM_COPI_CTRL(copi_arr : t_mem_copi_arr) RETURN t_mem_copi_arr;
FUNCTION RESET_MEM_MISO_CTRL(miso : t_mem_miso) RETURN t_mem_miso; -- deprecated, use RESET_MEM_CIPO_CTRL() instead
FUNCTION RESET_MEM_CIPO_CTRL(cipo : t_mem_cipo) RETURN t_mem_cipo;
FUNCTION RESET_MEM_CIPO_CTRL(cipo_arr : t_mem_cipo_arr) RETURN t_mem_cipo_arr;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width -- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR; -- unsigned, use integer to support 32 bit range
...@@ -94,17 +109,6 @@ PACKAGE common_mem_pkg IS ...@@ -94,17 +109,6 @@ PACKAGE common_mem_pkg IS
FUNCTION RESIZE_MEM_UDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned FUNCTION RESIZE_MEM_UDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- unsigned
FUNCTION RESIZE_MEM_SDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- sign extended FUNCTION RESIZE_MEM_SDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- sign extended
FUNCTION RESIZE_MEM_XDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- set unused MSBits to 'X' FUNCTION RESIZE_MEM_XDATA( vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- set unused MSBits to 'X'
-- MOSI/MISO subtypes
SUBTYPE t_mem_copi IS t_mem_mosi; -- Controller Out Peripheral In
SUBTYPE t_mem_cipo IS t_mem_miso; -- Peripheral In Controller Out
CONSTANT c_mem_cipo_rst : t_mem_cipo := c_mem_miso_rst;
CONSTANT c_mem_copi_rst : t_mem_copi := c_mem_mosi_rst;
SUBTYPE t_mem_cipo_arr IS t_mem_miso_arr;
SUBTYPE t_mem_copi_arr IS t_mem_mosi_arr;
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Burst memory access (for DDR access interface) -- Burst memory access (for DDR access interface)
...@@ -191,7 +195,21 @@ PACKAGE BODY common_mem_pkg IS ...@@ -191,7 +195,21 @@ PACKAGE BODY common_mem_pkg IS
v_mosi.wr := '0'; v_mosi.wr := '0';
RETURN v_mosi; RETURN v_mosi;
END RESET_MEM_MOSI_CTRL; END RESET_MEM_MOSI_CTRL;
FUNCTION RESET_MEM_COPI_CTRL(copi : t_mem_copi) RETURN t_mem_copi IS
BEGIN
RETURN RESET_MEM_MOSI_CTRL(copi);
END;
FUNCTION RESET_MEM_COPI_CTRL(copi_arr : t_mem_copi_arr) RETURN t_mem_copi_arr IS
VARIABLE v_copi_arr : t_mem_copi_arr(copi_arr'RANGE) := copi_arr;
BEGIN
FOR I IN copi_arr'RANGE LOOP
v_copi_arr(I) := RESET_MEM_COPI_CTRL(copi_arr(I));
END LOOP;
RETURN v_copi_arr;
END;
FUNCTION RESET_MEM_MISO_CTRL(miso : t_mem_miso) RETURN t_mem_miso IS FUNCTION RESET_MEM_MISO_CTRL(miso : t_mem_miso) RETURN t_mem_miso IS
VARIABLE v_miso : t_mem_miso := miso; VARIABLE v_miso : t_mem_miso := miso;
BEGIN BEGIN
...@@ -200,6 +218,20 @@ PACKAGE BODY common_mem_pkg IS ...@@ -200,6 +218,20 @@ PACKAGE BODY common_mem_pkg IS
RETURN v_miso; RETURN v_miso;
END RESET_MEM_MISO_CTRL; END RESET_MEM_MISO_CTRL;
FUNCTION RESET_MEM_CIPO_CTRL(cipo : t_mem_cipo) RETURN t_mem_cipo IS
BEGIN
RETURN RESET_MEM_MISO_CTRL(cipo);
END RESET_MEM_CIPO_CTRL;
FUNCTION RESET_MEM_CIPO_CTRL(cipo_arr : t_mem_cipo_arr) RETURN t_mem_cipo_arr IS
VARIABLE v_cipo_arr : t_mem_cipo_arr(cipo_arr'RANGE) := cipo_arr;
BEGIN
FOR I IN cipo_arr'RANGE LOOP
v_cipo_arr(I) := RESET_MEM_CIPO_CTRL(cipo_arr(I));
END LOOP;
RETURN v_cipo_arr;
END RESET_MEM_CIPO_CTRL;
-- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width -- Resize functions to fit an integer or an SLV in the corresponding t_mem_miso or t_mem_mosi field width
FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR IS FUNCTION TO_MEM_ADDRESS(n : INTEGER) RETURN STD_LOGIC_VECTOR IS
BEGIN BEGIN
......
libraries/base/common/src/vhdl/common_pkg.vhd
+ 20
− 4
View file @ cf0e699c
...@@ -18,13 +18,10 @@ ...@@ -18,13 +18,10 @@
-- along with this program. If not, see <http://www.gnu.org/licenses/>. -- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- --
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
-- Author: -- Author:
-- . Eric Kooistra -- . Eric Kooistra
-- Purpose: -- Purpose:
-- . Collection of commonly used base funtions -- . Collection of commonly used base funtions
-- Interface:
-- . [n/a]
-- Description: -- Description:
-- . This is a package containing generic constants and functions. -- . This is a package containing generic constants and functions.
-- . More information can be found in the comments near the code. -- . More information can be found in the comments near the code.
...@@ -415,7 +412,10 @@ PACKAGE common_pkg IS ...@@ -415,7 +412,10 @@ PACKAGE common_pkg IS
FUNCTION SUB_SVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH FUNCTION SUB_SVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec - r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH
FUNCTION ADD_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH FUNCTION ADD_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec + r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
FUNCTION SUB_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH FUNCTION SUB_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec - r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH
FUNCTION MULT_SVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec * r_vec, treat slv operands as signed, slv output width is l_vec'LENGTH + r_vec'LENGTH
FUNCTION MULT_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR; -- l_vec * r_vec, treat slv operands as unsigned, slv output width is l_vec'LENGTH + r_vec'LENGTH
FUNCTION COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im FUNCTION COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER; -- Calculate real part of complex multiplication: a_re*b_re - a_im*b_im
FUNCTION COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im FUNCTION COMPLEX_MULT_IMAG(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER; -- Calculate imag part of complex multiplication: a_im*b_re + a_re*b_im
...@@ -2019,6 +2019,22 @@ PACKAGE BODY common_pkg IS ...@@ -2019,6 +2019,22 @@ PACKAGE BODY common_pkg IS
BEGIN BEGIN
RETURN SUB_UVEC(l_vec, r_vec, l_vec'LENGTH); RETURN SUB_UVEC(l_vec, r_vec, l_vec'LENGTH);
END; END;
FUNCTION MULT_SVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT c_product_w : NATURAL := l_vec'LENGTH + r_vec'LENGTH;
VARIABLE v_product : STD_LOGIC_VECTOR(c_product_w-1 DOWNTO 0);
BEGIN
v_product := STD_LOGIC_VECTOR(SIGNED(l_vec) * SIGNED(r_vec));
RETURN v_product;
END;
FUNCTION MULT_UVEC(l_vec : STD_LOGIC_VECTOR; r_vec : STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS
CONSTANT c_product_w : NATURAL := l_vec'LENGTH + r_vec'LENGTH;
VARIABLE v_product : STD_LOGIC_VECTOR(c_product_w-1 DOWNTO 0);
BEGIN
v_product := STD_LOGIC_VECTOR(UNSIGNED(l_vec) * UNSIGNED(r_vec));
RETURN v_product;
END;
FUNCTION COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER IS FUNCTION COMPLEX_MULT_REAL(a_re, a_im, b_re, b_im : INTEGER) RETURN INTEGER IS
BEGIN BEGIN
......
libraries/base/common_mult/hdllib.cfg
+ 2
− 1
View file @ cf0e699c
...@@ -18,10 +18,11 @@ test_bench_files = ...@@ -18,10 +18,11 @@ test_bench_files =
tb/vhdl/tb_common_complex_mult.vhd tb/vhdl/tb_common_complex_mult.vhd
tb/vhdl/tb_tb_common_mult.vhd tb/vhdl/tb_tb_common_mult.vhd
tb/vhdl/tb_tb_common_complex_mult.vhd
regression_test_vhdl = regression_test_vhdl =
tb/vhdl/tb_common_mult_add2.vhd tb/vhdl/tb_common_mult_add2.vhd
tb/vhdl/tb_common_complex_mult.vhd tb/vhdl/tb_tb_common_complex_mult.vhd
tb/vhdl/tb_tb_common_mult.vhd tb/vhdl/tb_tb_common_mult.vhd
......
libraries/base/common_mult/src/vhdl/common_complex_mult.vhd
+ 0
− 4
View file @ cf0e699c
...@@ -47,8 +47,6 @@ USE technology_lib.technology_select_pkg.ALL; ...@@ -47,8 +47,6 @@ USE technology_lib.technology_select_pkg.ALL;
ENTITY common_complex_mult IS ENTITY common_complex_mult IS
GENERIC ( GENERIC (
g_sim : BOOLEAN := FALSE;
g_sim_level : NATURAL := 0; -- 0: Simulate variant passed via g_variant for given g_technology
g_technology : NATURAL := c_tech_select_default; g_technology : NATURAL := c_tech_select_default;
g_variant : STRING := "IP"; g_variant : STRING := "IP";
g_in_a_w : POSITIVE; g_in_a_w : POSITIVE;
...@@ -111,8 +109,6 @@ BEGIN ...@@ -111,8 +109,6 @@ BEGIN
u_complex_mult : ENTITY tech_mult_lib.tech_complex_mult u_complex_mult : ENTITY tech_mult_lib.tech_complex_mult
GENERIC MAP( GENERIC MAP(
g_sim => g_sim,
g_sim_level => g_sim_level,
g_technology => g_technology, g_technology => g_technology,
g_variant => g_variant, g_variant => g_variant,
g_in_a_w => g_in_a_w, g_in_a_w => g_in_a_w,
......
libraries/base/common_mult/tb/vhdl/tb_common_complex_mult.vhd
+ 117
− 100
View file @ cf0e699c
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
-- p_verify verifies that the instances of common_complex_mult all yield the -- p_verify verifies that the instances of common_complex_mult all yield the
-- expected results and ASSERTs an ERROR in case they differ. -- expected results and ASSERTs an ERROR in case they differ.
-- Usage: -- Usage:
-- > as 10 -- > as 12
-- > run -all -- signal tb_end will stop the simulation by stopping the clk -- > run -all -- signal tb_end will stop the simulation by stopping the clk
LIBRARY IEEE, common_lib, technology_lib, tech_mult_lib, ip_stratixiv_mult_lib; LIBRARY IEEE, common_lib, technology_lib, tech_mult_lib, ip_stratixiv_mult_lib;
...@@ -32,14 +32,15 @@ USE IEEE.numeric_std.ALL; ...@@ -32,14 +32,15 @@ USE IEEE.numeric_std.ALL;
USE technology_lib.technology_select_pkg.ALL; USE technology_lib.technology_select_pkg.ALL;
USE common_lib.common_pkg.ALL; USE common_lib.common_pkg.ALL;
USE common_lib.common_lfsr_sequences_pkg.ALL; USE common_lib.common_lfsr_sequences_pkg.ALL;
USE common_lib.common_str_pkg.ALL;
USE common_lib.tb_common_pkg.ALL; USE common_lib.tb_common_pkg.ALL;
ENTITY tb_common_complex_mult IS ENTITY tb_common_complex_mult IS
GENERIC ( GENERIC (
g_in_dat_w : NATURAL := 4; g_variant : STRING := "IP"; -- "RTL" or "IP"
g_out_dat_w : NATURAL := 8; -- g_in_dat_w*2 for multiply and +1 for adder g_in_dat_w : NATURAL := 18;
g_conjugate_b : BOOLEAN := FALSE; -- When FALSE p = a * b, else p = a * conj(b) g_conjugate_b : BOOLEAN := TRUE; -- When FALSE p = a * b, else p = a * conj(b)
g_pipeline_input : NATURAL := 1; g_pipeline_input : NATURAL := 1;
g_pipeline_product : NATURAL := 0; g_pipeline_product : NATURAL := 0;
g_pipeline_adder : NATURAL := 1; g_pipeline_adder : NATURAL := 1;
...@@ -53,9 +54,14 @@ ARCHITECTURE tb OF tb_common_complex_mult IS ...@@ -53,9 +54,14 @@ ARCHITECTURE tb OF tb_common_complex_mult IS
CONSTANT clk_period : TIME := 10 ns; CONSTANT clk_period : TIME := 10 ns;
CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output; CONSTANT c_pipeline : NATURAL := g_pipeline_input + g_pipeline_product + g_pipeline_adder + g_pipeline_output;
-- g_in_dat_w*2 for multiply and +1 for adder to fit largest im product value
CONSTANT c_out_dat_w : NATURAL := g_in_dat_w * 2 + 1;
CONSTANT c_max : INTEGER := 2**(g_in_dat_w-1)-1; CONSTANT c_max : INTEGER := 2**(g_in_dat_w-1)-1;
CONSTANT c_min : INTEGER := -2**(g_in_dat_w-1); CONSTANT c_min : INTEGER := -2**(g_in_dat_w-1);
CONSTANT c_small : INTEGER := smallest(5, c_max);
CONSTANT c_technology : NATURAL := c_tech_select_default; CONSTANT c_technology : NATURAL := c_tech_select_default;
SIGNAL tb_end : STD_LOGIC := '0'; SIGNAL tb_end : STD_LOGIC := '0';
...@@ -64,25 +70,32 @@ ARCHITECTURE tb OF tb_common_complex_mult IS ...@@ -64,25 +70,32 @@ ARCHITECTURE tb OF tb_common_complex_mult IS
SIGNAL random : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences SIGNAL random : STD_LOGIC_VECTOR(14 DOWNTO 0) := (OTHERS=>'0'); -- use different lengths to have different random sequences
-- Input
SIGNAL in_ar : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0); SIGNAL in_ar : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_ai : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0); SIGNAL in_ai : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_br : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0); SIGNAL in_br : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_bi : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0); SIGNAL in_bi : STD_LOGIC_VECTOR(g_in_dat_w-1 DOWNTO 0);
SIGNAL in_val : STD_LOGIC; -- in_val is only passed on to out_val SIGNAL in_val : STD_LOGIC; -- in_val is only passed on to out_val, not used by multiplier itself
SIGNAL result_val_expected : STD_LOGIC;
SIGNAL result_val_rtl : STD_LOGIC;
SIGNAL result_val_ip : STD_LOGIC;
SIGNAL out_result_re : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- combinatorial result
SIGNAL out_result_im : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_re_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0); -- pipelined results
SIGNAL result_re_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_re_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_im_expected : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_im_rtl : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
SIGNAL result_im_ip : STD_LOGIC_VECTOR(g_out_dat_w-1 DOWNTO 0);
-- Results
-- . expected valid and DUT valid, only depends on in_val and c_pipeline
SIGNAL result_val_expected : STD_LOGIC;
SIGNAL result_val_dut : STD_LOGIC;
-- . product result
SIGNAL ref_result_re : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0); -- combinatorial result
SIGNAL ref_result_im : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0);
SIGNAL result_re_expected : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0); -- pipelined results
SIGNAL result_re_dut : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0);
SIGNAL result_im_expected : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0);
SIGNAL result_im_dut : STD_LOGIC_VECTOR(c_out_dat_w-1 DOWNTO 0);
-- Debug signals to view constant values in wave window
SIGNAL dbg_variant : STRING(g_variant'RANGE) := g_variant;
SIGNAL dbg_in_dat_w : NATURAL := g_in_dat_w;
SIGNAL dbg_conjugate_b : BOOLEAN := g_conjugate_b;
SIGNAL dbg_pipeline : NATURAL := c_pipeline;
BEGIN BEGIN
...@@ -101,34 +114,36 @@ BEGIN ...@@ -101,34 +114,36 @@ BEGIN
in_ai <= TO_SVEC(0, g_in_dat_w); in_ai <= TO_SVEC(0, g_in_dat_w);
in_bi <= TO_SVEC(0, g_in_dat_w); in_bi <= TO_SVEC(0, g_in_dat_w);
WAIT UNTIL rising_edge(clk); WAIT UNTIL rising_edge(clk);
FOR I IN 0 TO 9 LOOP proc_common_wait_some_cycles(clk, 10);
WAIT UNTIL rising_edge(clk);
END LOOP;
rst <= '0'; rst <= '0';
FOR I IN 0 TO 9 LOOP proc_common_wait_some_cycles(clk, 10);
WAIT UNTIL rising_edge(clk);
END LOOP;
-- Some special combinations -- Some more special combinations with max and min
in_ar <= TO_SVEC(2, g_in_dat_w);
in_ai <= TO_SVEC(4, g_in_dat_w);
in_br <= TO_SVEC(3, g_in_dat_w);
in_bi <= TO_SVEC(5, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC( c_max, g_in_dat_w); -- p*p - p*p + j ( p*p + p*p) = 0 + j 2pp or p*p + p*p + j (-p*p + p*p) = 2pp + j 0 in_ar <= TO_SVEC( c_max, g_in_dat_w); -- p*p - p*p + j ( p*p + p*p) = 0 + j 2pp or p*p + p*p + j (-p*p + p*p) = 2pp + j 0
in_ai <= TO_SVEC( c_max, g_in_dat_w); in_ai <= TO_SVEC( c_max, g_in_dat_w);
in_br <= TO_SVEC( c_max, g_in_dat_w); in_br <= TO_SVEC( c_max, g_in_dat_w);
in_bi <= TO_SVEC( c_max, g_in_dat_w); in_bi <= TO_SVEC( c_max, g_in_dat_w);
WAIT UNTIL rising_edge(clk); WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC( c_min, g_in_dat_w);
in_ai <= TO_SVEC( c_min, g_in_dat_w); -- Skip (c_min + j*c_min) * (c_min + j*c_min), because that just does not fit in 2*g_in_dat_w bits of complex multiplier
in_br <= TO_SVEC( c_min, g_in_dat_w); --in_ar <= TO_SVEC( c_min, g_in_dat_w);
in_bi <= TO_SVEC( c_min, g_in_dat_w); --in_ai <= TO_SVEC( c_min, g_in_dat_w);
WAIT UNTIL rising_edge(clk); --in_br <= TO_SVEC( c_min, g_in_dat_w);
in_ar <= TO_SVEC( c_max, g_in_dat_w); --in_bi <= TO_SVEC( c_min, g_in_dat_w);
in_ai <= TO_SVEC( c_max, g_in_dat_w); --WAIT UNTIL rising_edge(clk);
in_br <= TO_SVEC( c_min, g_in_dat_w);
in_bi <= TO_SVEC( c_min, g_in_dat_w); IF dbg_conjugate_b = FALSE THEN
in_ar <= TO_SVEC( c_max, g_in_dat_w);
in_ai <= TO_SVEC( c_max, g_in_dat_w);
in_br <= TO_SVEC( c_min, g_in_dat_w);
in_bi <= TO_SVEC( c_min, g_in_dat_w);
ELSE
in_ar <= TO_SVEC( c_min, g_in_dat_w);
in_ai <= TO_SVEC( c_min, g_in_dat_w);
in_br <= TO_SVEC( c_max, g_in_dat_w);
in_bi <= TO_SVEC( c_max, g_in_dat_w);
END IF;
WAIT UNTIL rising_edge(clk); WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC( c_max, g_in_dat_w); in_ar <= TO_SVEC( c_max, g_in_dat_w);
in_ai <= TO_SVEC( c_max, g_in_dat_w); in_ai <= TO_SVEC( c_max, g_in_dat_w);
...@@ -140,51 +155,85 @@ BEGIN ...@@ -140,51 +155,85 @@ BEGIN
in_br <= TO_SVEC(-c_max, g_in_dat_w); in_br <= TO_SVEC(-c_max, g_in_dat_w);
in_bi <= TO_SVEC(-c_max, g_in_dat_w); in_bi <= TO_SVEC(-c_max, g_in_dat_w);
WAIT UNTIL rising_edge(clk); WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC(0, g_in_dat_w);
in_br <= TO_SVEC(0, g_in_dat_w);
in_ai <= TO_SVEC(0, g_in_dat_w);
in_bi <= TO_SVEC(0, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
proc_common_wait_some_cycles(clk, 10);
FOR I IN 0 TO 49 LOOP -- Some special combinations close to max, min
WAIT UNTIL rising_edge(clk); in_ar <= TO_SVEC( c_max, g_in_dat_w);
END LOOP; in_ai <= TO_SVEC( c_max-1, g_in_dat_w);
in_br <= TO_SVEC( c_max-2, g_in_dat_w);
in_bi <= TO_SVEC( c_max-3, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC( c_min, g_in_dat_w);
in_ai <= TO_SVEC( c_min+1, g_in_dat_w);
in_br <= TO_SVEC( c_min+2, g_in_dat_w);
in_bi <= TO_SVEC( c_min+3, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC( c_max, g_in_dat_w);
in_ai <= TO_SVEC( c_max-1, g_in_dat_w);
in_br <= TO_SVEC( c_min+2, g_in_dat_w);
in_bi <= TO_SVEC( c_min+3, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC( c_max, g_in_dat_w);
in_ai <= TO_SVEC( c_max-1, g_in_dat_w);
in_br <= TO_SVEC(-c_max+2, g_in_dat_w);
in_bi <= TO_SVEC(-c_max+3, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC( c_min, g_in_dat_w);
in_ai <= TO_SVEC( c_min+1, g_in_dat_w);
in_br <= TO_SVEC(-c_max+2, g_in_dat_w);
in_bi <= TO_SVEC(-c_max+3, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
in_ar <= TO_SVEC(0, g_in_dat_w);
in_br <= TO_SVEC(0, g_in_dat_w);
in_ai <= TO_SVEC(0, g_in_dat_w);
in_bi <= TO_SVEC(0, g_in_dat_w);
WAIT UNTIL rising_edge(clk);
proc_common_wait_some_cycles(clk, 100);
-- All combinations -- Try all small combinations
FOR I IN -c_max TO c_max LOOP FOR I IN -c_small TO c_small LOOP
FOR J IN -c_max TO c_max LOOP FOR J IN -c_small TO c_small LOOP
FOR K IN -c_max TO c_max LOOP FOR K IN -c_small TO c_small LOOP
FOR L IN -c_max TO c_max LOOP FOR L IN -c_small TO c_small LOOP
in_ar <= TO_SVEC(I, g_in_dat_w); in_ar <= TO_SVEC(I, g_in_dat_w);
in_ai <= TO_SVEC(K, g_in_dat_w); in_ai <= TO_SVEC(K, g_in_dat_w);
in_br <= TO_SVEC(J, g_in_dat_w); in_br <= TO_SVEC(J, g_in_dat_w);
in_bi <= TO_SVEC(L, g_in_dat_w); in_bi <= TO_SVEC(L, g_in_dat_w);
WAIT UNTIL rising_edge(clk); WAIT UNTIL rising_edge(clk);
END LOOP; END LOOP;
proc_common_wait_some_cycles(clk, 10);
END LOOP; END LOOP;
proc_common_wait_some_cycles(clk, 100);
END LOOP; END LOOP;
END LOOP; proc_common_wait_some_cycles(clk, 1000);
FOR I IN 0 TO 49 LOOP
WAIT UNTIL rising_edge(clk);
END LOOP; END LOOP;
tb_end <= '1'; tb_end <= '1';
WAIT; WAIT;
END PROCESS; END PROCESS;
-- Expected combinatorial complex multiply out_result -- Expected combinatorial complex multiply ref_result
out_result_re <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "RE", g_out_dat_w); ref_result_re <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "RE", c_out_dat_w);
out_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", g_out_dat_w); ref_result_im <= func_complex_multiply(in_ar, in_ai, in_br, in_bi, g_conjugate_b, "IM", c_out_dat_w);
u_result_re : ENTITY common_lib.common_pipeline u_result_re : ENTITY common_lib.common_pipeline
GENERIC MAP ( GENERIC MAP (
g_representation => "SIGNED", g_representation => "SIGNED",
g_pipeline => c_pipeline, g_pipeline => c_pipeline,
g_reset_value => 0, g_reset_value => 0,
g_in_dat_w => g_out_dat_w, g_in_dat_w => c_out_dat_w,
g_out_dat_w => g_out_dat_w g_out_dat_w => c_out_dat_w
) )
PORT MAP ( PORT MAP (
rst => rst, rst => rst,
clk => clk, clk => clk,
clken => '1', clken => '1',
in_dat => out_result_re, in_dat => ref_result_re,
out_dat => result_re_expected out_dat => result_re_expected
); );
...@@ -193,14 +242,14 @@ BEGIN ...@@ -193,14 +242,14 @@ BEGIN
g_representation => "SIGNED", g_representation => "SIGNED",
g_pipeline => c_pipeline, g_pipeline => c_pipeline,
g_reset_value => 0, g_reset_value => 0,
g_in_dat_w => g_out_dat_w, g_in_dat_w => c_out_dat_w,
g_out_dat_w => g_out_dat_w g_out_dat_w => c_out_dat_w
) )
PORT MAP ( PORT MAP (
rst => rst, rst => rst,
clk => clk, clk => clk,
clken => '1', clken => '1',
in_dat => out_result_im, in_dat => ref_result_im,
out_dat => result_im_expected out_dat => result_im_expected
); );
...@@ -217,40 +266,13 @@ BEGIN ...@@ -217,40 +266,13 @@ BEGIN
out_dat => result_val_expected out_dat => result_val_expected
); );
u_dut_rtl : ENTITY work.common_complex_mult u_dut : ENTITY work.common_complex_mult
GENERIC MAP (
g_technology => c_technology,
g_variant => "RTL",
g_in_a_w => g_in_dat_w,
g_in_b_w => g_in_dat_w,
g_out_p_w => g_out_dat_w,
g_conjugate_b => g_conjugate_b,
g_pipeline_input => g_pipeline_input,
g_pipeline_product => g_pipeline_product,
g_pipeline_adder => g_pipeline_adder,
g_pipeline_output => g_pipeline_output
)
PORT MAP (
rst => rst,
clk => clk,
clken => '1',
in_ar => in_ar,
in_ai => in_ai,
in_br => in_br,
in_bi => in_bi,
in_val => in_val,
out_pr => result_re_rtl,
out_pi => result_im_rtl,
out_val => result_val_rtl
);
u_dut_ip : ENTITY work.common_complex_mult
GENERIC MAP ( GENERIC MAP (
g_technology => c_technology, g_technology => c_technology,
g_variant => "IP", g_variant => g_variant,
g_in_a_w => g_in_dat_w, g_in_a_w => g_in_dat_w,
g_in_b_w => g_in_dat_w, g_in_b_w => g_in_dat_w,
g_out_p_w => g_out_dat_w, g_out_p_w => c_out_dat_w,
g_conjugate_b => g_conjugate_b, g_conjugate_b => g_conjugate_b,
g_pipeline_input => g_pipeline_input, g_pipeline_input => g_pipeline_input,
g_pipeline_product => g_pipeline_product, g_pipeline_product => g_pipeline_product,
...@@ -266,23 +288,18 @@ BEGIN ...@@ -266,23 +288,18 @@ BEGIN
in_br => in_br, in_br => in_br,
in_bi => in_bi, in_bi => in_bi,
in_val => in_val, in_val => in_val,
out_pr => result_re_ip, out_pr => result_re_dut,
out_pi => result_im_ip, out_pi => result_im_dut,
out_val => result_val_ip out_val => result_val_dut
); );
p_verify : PROCESS(rst, clk) p_verify : PROCESS(rst, clk)
BEGIN BEGIN
IF rst='0' THEN IF rst='0' THEN
IF rising_edge(clk) THEN IF rising_edge(clk) THEN
ASSERT result_re_rtl = result_re_expected REPORT "Error: RE wrong RTL result" SEVERITY ERROR; ASSERT result_re_dut = result_re_expected REPORT "Error: RE wrong result, " & slv_to_str(result_re_dut) & " /= " & slv_to_str(result_re_expected) SEVERITY ERROR;
ASSERT result_im_rtl = result_im_expected REPORT "Error: IM wrong RTL result" SEVERITY ERROR; ASSERT result_im_dut = result_im_expected REPORT "Error: IM wrong result, " & slv_to_str(result_im_dut) & " /= " & slv_to_str(result_im_expected) SEVERITY ERROR;
ASSERT result_val_rtl = result_val_expected REPORT "Error: VAL wrong RTL result" SEVERITY ERROR; ASSERT result_val_dut = result_val_expected REPORT "Error: VAL wrong result" SEVERITY ERROR;
ASSERT result_re_ip = result_re_expected REPORT "Error: RE wrong IP result" SEVERITY ERROR;
ASSERT result_im_ip = result_im_expected REPORT "Error: IM wrong IP result" SEVERITY ERROR;
ASSERT result_val_ip = result_val_expected REPORT "Error: VAL wrong IP result" SEVERITY ERROR;
END IF; END IF;
END IF; END IF;
END PROCESS; END PROCESS;
......
libraries/base/common_mult/tb/vhdl/tb_tb_common_complex_mult.vhd 0 → 100644
+ 63
− 0
View file @ cf0e699c
-- --------------------------------------------------------------------------
-- Copyright 2020
-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- --------------------------------------------------------------------------
-- --------------------------------------------------------------------------
-- Author: E. Kooistra
-- Purpose: Multi tb for variants of common_complex_mult
-- Description:
-- Usage:
-- > as 3
-- > run -all
-- --------------------------------------------------------------------------
LIBRARY IEEE, technology_lib;
USE IEEE.std_logic_1164.ALL;
USE technology_lib.technology_pkg.ALL;
USE technology_lib.technology_select_pkg.ALL;
ENTITY tb_tb_common_complex_mult IS
END tb_tb_common_complex_mult;
ARCHITECTURE tb OF tb_tb_common_complex_mult IS
SIGNAL tb_end : STD_LOGIC := '0'; -- declare tb_end to avoid 'No objects found' error on 'when -label tb_end'
BEGIN
-- g_variant : STRING := "IP";
-- g_in_dat_w : NATURAL := 4;
-- g_conjugate_b : BOOLEAN := FALSE; -- When FALSE p = a * b, else p = a * conj(b)
-- g_pipeline_input : NATURAL := 1;
-- g_pipeline_product : NATURAL := 0;
-- g_pipeline_adder : NATURAL := 1;
-- g_pipeline_output : NATURAL := 1
-- IP variants
u_ip_18b : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 18, FALSE, 1, 0, 1, 1);
u_ip_18b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 18, TRUE, 1, 0, 1, 1);
gen_27b : IF c_tech_select_default /= c_tech_stratixiv GENERATE
u_ip_27b : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, FALSE, 1, 0, 1, 1);
u_ip_27b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("IP", 27, TRUE, 1, 0, 1, 1);
END GENERATE;
-- RTL variants
u_rtl_18b : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 18, FALSE, 1, 0, 1, 1);
u_rtl_27b : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 27, FALSE, 1, 0, 1, 1);
u_rtl_18b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 18, TRUE, 1, 0, 1, 1);
u_rtl_27b_conj : ENTITY work.tb_common_complex_mult GENERIC MAP ("RTL", 27, TRUE, 1, 0, 1, 1);
END tb;
libraries/base/dp/dp.peripheral.yaml
+ 20
− 10
View file @ cf0e699c
...@@ -216,26 +216,37 @@ peripherals: ...@@ -216,26 +216,37 @@ peripherals:
mm_port_description: "" mm_port_description: ""
fields: fields:
- - field_name: ctrl_enable - - field_name: ctrl_enable
field_description: "Enable the output when 1, disable the output when 0. To first disable output to re-enable output." field_description:
address_offset: 0 * MM_BUS_SIZE # = 0x0 "Enable the output when 1, disable the output when 0. First disable output to re-enable output."
address_offset: 0 * MM_BUS_SIZE
mm_width: 1 mm_width: 1
access_mode: RW access_mode: RW
- - field_name: ctrl_interval_size - - field_name: ctrl_interval_size
field_description: "Number of samples in output sync interval" field_description:
address_offset: 1 * MM_BUS_SIZE # = 0x4 "Number of samples in output sync interval. For example, for sample rate 200 MHz
this implies a maximum sync interval period of 2**31 * 5 ns = 10.7 s (because
VHDL NATURAL range is 0 - 2**31-1)"
address_offset: 1 * MM_BUS_SIZE
mm_width: 31
access_mode: RW access_mode: RW
- - field_name: ctrl_start_bsn - - field_name: ctrl_start_bsn
field_description: field_description:
"Schedule start BSN for the output. The start BSN needs to be in the future, "Schedule start BSN for the output. The start BSN needs to be in the future,
if the start BSN is in the past or if the input stream is not active, then if the start BSN is in the past or if the input stream is not active, then
ctrl_enable = '1' will have no effect." ctrl_enable = '1' will have no effect."
address_offset: 2 * MM_BUS_SIZE # = 0x8 address_offset: 2 * MM_BUS_SIZE
user_width: 64 user_width: 64
radix: uint64 radix: uint64
access_mode: RW access_mode: RW
- - field_name: mon_current_input_bsn - - field_name: mon_current_input_bsn
field_description: "Current input BSN. This can be read to determine a start BSN in the future." field_description: "Current input BSN. This can be read to determine a start BSN in the future."
address_offset: 4 * MM_BUS_SIZE # = 0x10 address_offset: 4 * MM_BUS_SIZE
user_width: 64
radix: uint64
access_mode: RO
- - field_name: mon_input_bsn_at_sync
field_description: "Input BSN at input sync. This can be read to compare with mon_output_sync_bsn."
address_offset: 6 * MM_BUS_SIZE
user_width: 64 user_width: 64
radix: uint64 radix: uint64
access_mode: RO access_mode: RO
...@@ -244,21 +255,20 @@ peripherals: ...@@ -244,21 +255,20 @@ peripherals:
"Is 1 when output is enabled, 0 when output is disabled. The output stream gets "Is 1 when output is enabled, 0 when output is disabled. The output stream gets
enabled when ctrl_enable is set '1' and when the BSN of the input stream has enabled when ctrl_enable is set '1' and when the BSN of the input stream has
reached the ctrl_start_bsn." reached the ctrl_start_bsn."
address_offset: 6 * MM_BUS_SIZE # = 0x18 address_offset: 8 * MM_BUS_SIZE
mm_width: 1 mm_width: 1
access_mode: RO access_mode: RO
- - field_name: mon_output_sync_bsn - - field_name: mon_output_sync_bsn
field_description: "Output BSN at sync. This yields the number of blocks per output sync interval." field_description: "Output BSN at sync. This yields the number of blocks per output sync interval."
address_offset: 7 * MM_BUS_SIZE # = 0x1C address_offset: 9 * MM_BUS_SIZE
user_width: 64 user_width: 64
radix: uint64 radix: uint64
access_mode: RO access_mode: RO
- - field_name: block_size - - field_name: block_size
field_description: "Number of samples per BSN block, same for input stream and output stream." field_description: "Number of samples per BSN block, same for input stream and output stream."
address_offset: 9 * MM_BUS_SIZE # = 0x24 address_offset: 11 * MM_BUS_SIZE
access_mode: RO access_mode: RO
- peripheral_name: dp_bsn_monitor # pi_dp_bsn_monitor.py - peripheral_name: dp_bsn_monitor # pi_dp_bsn_monitor.py
peripheral_description: "Monitor the Block Sequence Number (BSN) status of streaming data." peripheral_description: "Monitor the Block Sequence Number (BSN) status of streaming data."
parameters: parameters:
......
libraries/base/dp/hdllib.cfg
+ 6
− 7
View file @ cf0e699c
...@@ -82,6 +82,12 @@ synth_files = ...@@ -82,6 +82,12 @@ synth_files =
src/vhdl/dp_block_from_mm.vhd src/vhdl/dp_block_from_mm.vhd
src/vhdl/dp_block_from_mm_dc.vhd src/vhdl/dp_block_from_mm_dc.vhd
src/vhdl/dp_block_to_mm.vhd src/vhdl/dp_block_to_mm.vhd
src/vhdl/dp_bsn_monitor.vhd
src/vhdl/dp_bsn_monitor_reg.vhd
src/vhdl/mms_dp_bsn_monitor.vhd
src/vhdl/dp_bsn_monitor_v2.vhd
src/vhdl/dp_bsn_monitor_reg_v2.vhd
src/vhdl/mms_dp_bsn_monitor_v2.vhd
src/vhdl/dp_bsn_source.vhd src/vhdl/dp_bsn_source.vhd
src/vhdl/dp_bsn_source_v2.vhd src/vhdl/dp_bsn_source_v2.vhd
src/vhdl/dp_bsn_source_reg.vhd src/vhdl/dp_bsn_source_reg.vhd
...@@ -115,12 +121,6 @@ synth_files = ...@@ -115,12 +121,6 @@ synth_files =
src/vhdl/dp_packet_dec_channel_lo.vhd src/vhdl/dp_packet_dec_channel_lo.vhd
src/vhdl/dp_gap.vhd src/vhdl/dp_gap.vhd
src/vhdl/dp_mon.vhd src/vhdl/dp_mon.vhd
src/vhdl/dp_bsn_monitor.vhd
src/vhdl/dp_bsn_monitor_reg.vhd
src/vhdl/mms_dp_bsn_monitor.vhd
src/vhdl/dp_bsn_monitor_v2.vhd
src/vhdl/dp_bsn_monitor_reg_v2.vhd
src/vhdl/mms_dp_bsn_monitor_v2.vhd
src/vhdl/dp_distribute.vhd src/vhdl/dp_distribute.vhd
src/vhdl/dp_ram_from_mm.vhd src/vhdl/dp_ram_from_mm.vhd
src/vhdl/dp_ram_from_mm_reg.vhd src/vhdl/dp_ram_from_mm_reg.vhd
...@@ -364,7 +364,6 @@ regression_test_vhdl = ...@@ -364,7 +364,6 @@ regression_test_vhdl =
tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd tb/vhdl/tb_tb_dp_block_gen_valid_arr.vhd
tb/vhdl/tb_tb_dp_block_from_mm.vhd tb/vhdl/tb_tb_dp_block_from_mm.vhd
tb/vhdl/tb_tb_dp_block_validate_channel.vhd tb/vhdl/tb_tb_dp_block_validate_channel.vhd
tb/vhdl/tb_tb_dp_bsn_align.vhd
tb/vhdl/tb_tb_dp_bsn_source_v2.vhd tb/vhdl/tb_tb_dp_bsn_source_v2.vhd
tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd tb/vhdl/tb_tb_dp_bsn_sync_scheduler.vhd
tb/vhdl/tb_tb_dp_concat.vhd tb/vhdl/tb_tb_dp_concat.vhd
......
libraries/base/dp/src/vhdl/dp_block_from_mm.vhd
+ 20
− 5
View file @ cf0e699c
...@@ -37,6 +37,8 @@ ENTITY dp_block_from_mm IS ...@@ -37,6 +37,8 @@ ENTITY dp_block_from_mm IS
g_data_size : NATURAL; g_data_size : NATURAL;
g_step_size : NATURAL; g_step_size : NATURAL;
g_nof_data : NATURAL; g_nof_data : NATURAL;
g_data_w : NATURAL := c_word_w;
g_mm_rd_latency : NATURAL := 1; -- default 1 from rd_en to rd_val, use 2 to ease timing closure
g_reverse_word_order : BOOLEAN := FALSE g_reverse_word_order : BOOLEAN := FALSE
); );
PORT ( PORT (
...@@ -70,8 +72,15 @@ ARCHITECTURE rtl OF dp_block_from_mm IS ...@@ -70,8 +72,15 @@ ARCHITECTURE rtl OF dp_block_from_mm IS
SIGNAL r : t_reg; SIGNAL r : t_reg;
SIGNAL nxt_r : t_reg; SIGNAL nxt_r : t_reg;
SIGNAL mm_address : NATURAL := 0; SIGNAL mm_address : NATURAL := 0;
SIGNAL last_mm_address : NATURAL := 0; SIGNAL last_mm_address : NATURAL := 0;
SIGNAL r_sop_p : STD_LOGIC;
SIGNAL r_eop_p : STD_LOGIC;
SIGNAL out_sop : STD_LOGIC;
SIGNAL out_eop : STD_LOGIC;
BEGIN BEGIN
last_mm_address <= g_step_size * (g_nof_data - 1) + g_data_size + start_address - 1; last_mm_address <= g_step_size * (g_nof_data - 1) + g_data_size + start_address - 1;
...@@ -79,15 +88,21 @@ BEGIN ...@@ -79,15 +88,21 @@ BEGIN
mm_mosi.address <= TO_MEM_ADDRESS(mm_address); mm_mosi.address <= TO_MEM_ADDRESS(mm_address);
u_sosi : PROCESS(r, mm_miso) -- Take care of g_mm_rd_latency for out_sosi.sop and out_sosi.eop
r_sop_p <= r.sop WHEN rising_edge(clk);
r_eop_p <= r.eop WHEN rising_edge(clk);
out_sop <= r.sop WHEN g_mm_rd_latency = 1 ELSE r_sop_p;
out_eop <= r.eop WHEN g_mm_rd_latency = 1 ELSE r_eop_p;
u_sosi : PROCESS(r, mm_miso, out_sop, out_eop)
BEGIN BEGIN
out_sosi <= c_dp_sosi_rst; -- To avoid Modelsim warnings on conversion to integer from unused fields. out_sosi <= c_dp_sosi_rst; -- To avoid Modelsim warnings on conversion to integer from unused fields.
out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(c_word_w-1 DOWNTO 0)); out_sosi.data <= RESIZE_DP_DATA(mm_miso.rddata(g_data_w-1 DOWNTO 0));
out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1) out_sosi.valid <= mm_miso.rdval; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so same as the ready latency (RL = 1)
out_sosi.sop <= r.sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop out_sosi.sop <= out_sop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.sop can be used for output sop
out_sosi.eop <= r.eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop out_sosi.eop <= out_eop; -- read latency from mm_mosi.rd to mm_miso.rdval is 1, so r.eop can be used for output eop
END PROCESS; END PROCESS;
mm_done <= r.eop; mm_done <= r.eop;
p_reg : PROCESS(rst, clk) p_reg : PROCESS(rst, clk)
......
libraries/base/dp/src/vhdl/dp_bsn_sync_scheduler.vhd
+ 35
− 8
View file @ cf0e699c
...@@ -38,7 +38,7 @@ ...@@ -38,7 +38,7 @@
-- * ctrl_enable: -- * ctrl_enable:
-- The output is enabled at the ctrl_start_bsn when ctrl_enable = '1' and the -- The output is enabled at the ctrl_start_bsn when ctrl_enable = '1' and the
-- output is disable after an in_sosi.eop when ctrl_enable = '0'. If the -- output is disable after an in_sosi.eop when ctrl_enable = '0'. If the
-- output is diabled, then the sosai control fields are forced to '0', the -- output is diabled, then the sosi control fields are forced to '0', the
-- other sosi fields of the in_sosi are passed on to the out_sosi. -- other sosi fields of the in_sosi are passed on to the out_sosi.
-- * mon_current_input_bsn: -- * mon_current_input_bsn:
-- The user can read mon_current_input_bsn to determine a suitable -- The user can read mon_current_input_bsn to determine a suitable
...@@ -195,13 +195,19 @@ BEGIN ...@@ -195,13 +195,19 @@ BEGIN
output_start <= '0'; output_start <= '0';
output_sync <= '0'; output_sync <= '0';
---------------------------------------------------------------------------
-- Detect ctrl_enable rising event -- Detect ctrl_enable rising event
---------------------------------------------------------------------------
IF ctrl_enable = '1' AND ctrl_enable_evt = '1' THEN IF ctrl_enable = '1' AND ctrl_enable_evt = '1' THEN
v.enable_init := '1'; v.enable_init := '1';
END IF; END IF;
-- Initialization: calculate number of blocks per output sync interval ---------------------------------------------------------------------------
-- . use r.enable_init instead of v.enable_init to easy timing closure and -- Initialization:
-- calculate number of blocks per output sync interval, start with
-- nof_blk_max in first sync interval
---------------------------------------------------------------------------
-- . use r.enable_init instead of v.enable_init to ease timing closure and
-- because functionally it makes no difference. -- because functionally it makes no difference.
IF r.enable_init = '1' THEN IF r.enable_init = '1' THEN
-- Assume ctrl_start_bsn is scheduled more than nof_blk block clk cycles -- Assume ctrl_start_bsn is scheduled more than nof_blk block clk cycles
...@@ -239,7 +245,9 @@ BEGIN ...@@ -239,7 +245,9 @@ BEGIN
v.blk_cnt := 0; v.blk_cnt := 0;
END IF; END IF;
-- Enable / disable control ---------------------------------------------------------------------------
-- Enable / re-enable / disable control
---------------------------------------------------------------------------
IF ctrl_enable = '0' THEN IF ctrl_enable = '0' THEN
-- Disable output when ctrl_enable requests disable. -- Disable output when ctrl_enable requests disable.
v.enable := '0'; v.enable := '0';
...@@ -260,6 +268,12 @@ BEGIN ...@@ -260,6 +268,12 @@ BEGIN
END IF; END IF;
END IF; END IF;
---------------------------------------------------------------------------
-- Output enable / disable
-- . enable at start_bsn and issue output_start pulse for first output
-- sync interval
-- . disable after input block has finished.
---------------------------------------------------------------------------
-- Hold input eop to detect when input has finished a block and to detect -- Hold input eop to detect when input has finished a block and to detect
-- gaps between in_sosi.eop and in_sosi.sop -- gaps between in_sosi.eop and in_sosi.sop
IF in_sosi.sop = '1' THEN IF in_sosi.sop = '1' THEN
...@@ -269,7 +283,9 @@ BEGIN ...@@ -269,7 +283,9 @@ BEGIN
v.hold_eop := '1'; v.hold_eop := '1';
END IF; END IF;
IF v.enable = '1' THEN -- . use r.enable instead of v.enable to ease timing closure and because
-- functionally it makes no difference.
IF r.enable = '1' THEN
-- Output enable at in_sosi.sop start_bsn -- Output enable at in_sosi.sop start_bsn
IF in_sosi.sop = '1' THEN IF in_sosi.sop = '1' THEN
IF UNSIGNED(in_sosi.bsn) = UNSIGNED(r.start_bsn) THEN IF UNSIGNED(in_sosi.bsn) = UNSIGNED(r.start_bsn) THEN
...@@ -285,6 +301,9 @@ BEGIN ...@@ -285,6 +301,9 @@ BEGIN
END IF; END IF;
END IF; END IF;
---------------------------------------------------------------------------
-- Issue output_sync at output_sync_bsn and request next output_sync_bsn
---------------------------------------------------------------------------
-- Generate output sync interval based on input BSN and ctrl_interval_size -- Generate output sync interval based on input BSN and ctrl_interval_size
IF v.output_enable = '1' THEN IF v.output_enable = '1' THEN
IF in_sosi.sop = '1' THEN IF in_sosi.sop = '1' THEN
...@@ -300,7 +319,9 @@ BEGIN ...@@ -300,7 +319,9 @@ BEGIN
END IF; END IF;
END IF; END IF;
-- Determine BSN for next output sync ---------------------------------------------------------------------------
-- Determine BSN for next output_sync (= output_sync_bsn)
---------------------------------------------------------------------------
IF r.update_bsn = '1' THEN IF r.update_bsn = '1' THEN
-- Similar code as in proc_dp_verify_sync(), the difference is that: -- Similar code as in proc_dp_verify_sync(), the difference is that:
-- . Here r.extra is number of extra samples in nof_blk_max compared to -- . Here r.extra is number of extra samples in nof_blk_max compared to
...@@ -321,8 +342,9 @@ BEGIN ...@@ -321,8 +342,9 @@ BEGIN
-- Assume output_sync_bsn is in future -- Assume output_sync_bsn is in future
v.update_bsn := '0'; v.update_bsn := '0';
-- else: last r.input_bsn will be used to keep update_bsn active for -- If output_sync_bsn is still in past, due to lost input blocks, then
-- more clk cycles to catch up for lost input blocks. -- last r.input_bsn will be used to keep update_bsn active for more clk
-- cycles to catch up for lost input blocks.
END IF; END IF;
-- Hold input bsn -- Hold input bsn
...@@ -346,7 +368,10 @@ BEGIN ...@@ -346,7 +368,10 @@ BEGIN
nxt_r <= v; nxt_r <= v;
END PROCESS; END PROCESS;
-----------------------------------------------------------------------------
-- Output in_sosi with programmed sync interval or disable the output -- Output in_sosi with programmed sync interval or disable the output
-----------------------------------------------------------------------------
-- . note this is part of p_comb, but using a separate process is fine too.
p_output_sosi : PROCESS(in_sosi, nxt_r, output_sync) p_output_sosi : PROCESS(in_sosi, nxt_r, output_sync)
BEGIN BEGIN
output_sosi <= in_sosi; output_sosi <= in_sosi;
...@@ -360,7 +385,9 @@ BEGIN ...@@ -360,7 +385,9 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
-----------------------------------------------------------------------------
-- Pipeline output to avoid timing closure problems due to use of nxt_r.output_enable -- Pipeline output to avoid timing closure problems due to use of nxt_r.output_enable
-----------------------------------------------------------------------------
u_out_sosi : ENTITY work.dp_pipeline u_out_sosi : ENTITY work.dp_pipeline
GENERIC MAP ( GENERIC MAP (
g_pipeline => g_pipeline g_pipeline => g_pipeline
......
libraries/base/dp/src/vhdl/mms_dp_gain_arr.vhd
+ 0
− 2
View file @ cf0e699c
...@@ -240,8 +240,6 @@ BEGIN ...@@ -240,8 +240,6 @@ BEGIN
gen_nof_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE gen_nof_streams : FOR I IN 0 TO g_nof_streams-1 GENERATE
u_common_complex_mult : ENTITY common_mult_lib.common_complex_mult u_common_complex_mult : ENTITY common_mult_lib.common_complex_mult
GENERIC MAP ( GENERIC MAP (
g_sim => FALSE,
g_sim_level => 0, -- 0: Simulate variant passed via g_variant for given g_technology
g_technology => g_technology, g_technology => g_technology,
g_variant => "IP", g_variant => "IP",
g_in_a_w => g_gain_w, g_in_a_w => g_gain_w,
......
libraries/base/dp/tb/vhdl/tb_dp_bsn_sync_scheduler.vhd
+ 17
− 3
View file @ cf0e699c
...@@ -78,8 +78,8 @@ ENTITY tb_dp_bsn_sync_scheduler IS ...@@ -78,8 +78,8 @@ ENTITY tb_dp_bsn_sync_scheduler IS
-- Input sync period and sosi ctrl -- Input sync period and sosi ctrl
g_nof_input_sync : NATURAL := 10; g_nof_input_sync : NATURAL := 10;
g_nof_block_per_input_sync : NATURAL := 17; g_nof_block_per_input_sync : NATURAL := 17;
g_block_size : NATURAL := 10; g_block_size : NATURAL := 2;
g_input_gap_size : NATURAL := 3; g_input_gap_size : NATURAL := 0;
-- Output sync period -- Output sync period
g_nof_samples_per_output_sync : NATURAL := 45 -- 45 / g_block_size = 4.5 g_nof_samples_per_output_sync : NATURAL := 45 -- 45 / g_block_size = 4.5
...@@ -161,6 +161,8 @@ ARCHITECTURE tb OF tb_dp_bsn_sync_scheduler IS ...@@ -161,6 +161,8 @@ ARCHITECTURE tb OF tb_dp_bsn_sync_scheduler IS
SIGNAL prev_out_enable : STD_LOGIC := '0'; SIGNAL prev_out_enable : STD_LOGIC := '0';
SIGNAL pending_out_disable : STD_LOGIC := '0'; SIGNAL pending_out_disable : STD_LOGIC := '0';
SIGNAL expected_out_enable : STD_LOGIC := '0'; SIGNAL expected_out_enable : STD_LOGIC := '0';
SIGNAL expected_out_enable1 : STD_LOGIC := '0';
SIGNAL expected_out_enable2 : STD_LOGIC := '0';
SIGNAL expecting_out_start : STD_LOGIC := '0'; SIGNAL expecting_out_start : STD_LOGIC := '0';
SIGNAL hold_out_eop : STD_LOGIC := '0'; SIGNAL hold_out_eop : STD_LOGIC := '0';
SIGNAL hold_out_sop : STD_LOGIC := '0'; SIGNAL hold_out_sop : STD_LOGIC := '0';
...@@ -388,6 +390,9 @@ BEGIN ...@@ -388,6 +390,9 @@ BEGIN
END IF; END IF;
END PROCESS; END PROCESS;
expected_out_enable1 <= expected_out_enable WHEN rising_edge(clk);
expected_out_enable2 <= expected_out_enable1 WHEN rising_edge(clk);
p_verify_out_enable : PROCESS(clk) p_verify_out_enable : PROCESS(clk)
BEGIN BEGIN
-- Use registered values to compare, to avoid combinatorial differences -- Use registered values to compare, to avoid combinatorial differences
...@@ -397,7 +402,16 @@ BEGIN ...@@ -397,7 +402,16 @@ BEGIN
IF rising_edge(clk) THEN IF rising_edge(clk) THEN
IF out_enable /= expected_out_enable THEN IF out_enable /= expected_out_enable THEN
IF out_enable = '1' THEN IF out_enable = '1' THEN
REPORT "Unexpected enabled out_enable" SEVERITY ERROR; IF g_block_size > 2 THEN
REPORT "Unexpected enabled out_enable" SEVERITY ERROR;
ELSIF out_enable /= expected_out_enable2 THEN
-- For g_block_size = 2 the use of r.enable (instead of v.enable)
-- in dp_bsn_sync_scheduler.vhd causes that the output can stay
-- enabled 2 cycles longer, which is ok. Using v.enable does
-- avoid this need to use expected_out_enable2, but for timing
-- closure it is preferred to use r.enable.
REPORT "Unexpected enabled out_enable2" SEVERITY ERROR;
END IF;
ELSE ELSE
REPORT "Unexpected disabled out_enable" SEVERITY ERROR; REPORT "Unexpected disabled out_enable" SEVERITY ERROR;
END IF; END IF;
......
libraries/dsp/iquv/src/vhdl/iquv.vhd
+ 0
− 3
View file @ cf0e699c
...@@ -181,7 +181,6 @@ BEGIN ...@@ -181,7 +181,6 @@ BEGIN
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- u_CmplxMul_xx : ENTITY common_mult_lib.common_complex_mult -- u_CmplxMul_xx : ENTITY common_mult_lib.common_complex_mult
-- GENERIC MAP ( -- GENERIC MAP (
-- g_sim => g_sim,
-- g_technology => g_technology, -- g_technology => g_technology,
-- g_in_a_w => g_in_data_w, -- g_in_a_w => g_in_data_w,
-- g_in_b_w => g_in_data_w, -- g_in_b_w => g_in_data_w,
...@@ -203,7 +202,6 @@ BEGIN ...@@ -203,7 +202,6 @@ BEGIN
u_CmplxMul_xy : ENTITY common_mult_lib.common_complex_mult u_CmplxMul_xy : ENTITY common_mult_lib.common_complex_mult
GENERIC MAP ( GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology, g_technology => g_technology,
g_variant => g_variant, g_variant => g_variant,
g_in_a_w => g_in_data_w, g_in_a_w => g_in_data_w,
...@@ -226,7 +224,6 @@ BEGIN ...@@ -226,7 +224,6 @@ BEGIN
u_CmplxMul_xxyy : ENTITY common_mult_lib.common_complex_mult u_CmplxMul_xxyy : ENTITY common_mult_lib.common_complex_mult
GENERIC MAP ( GENERIC MAP (
g_sim => g_sim,
g_technology => g_technology, g_technology => g_technology,
g_variant => g_variant, g_variant => g_variant,
g_in_a_w => g_in_data_w, g_in_a_w => g_in_data_w,
......
libraries/dsp/st/st.peripheral.yaml
+ 1
− 1
View file @ cf0e699c
...@@ -151,7 +151,7 @@ peripherals: ...@@ -151,7 +151,7 @@ peripherals:
# from sdp_pkg.vhd: # from sdp_pkg.vhd:
# . c_sdp_ram_st_xsq_addr_w = ceil_log2(P_sq) + ceil_log2(N_crosslets * X_sq * c_nof_complex * (c_longword_sz/c_word_sz) # . c_sdp_ram_st_xsq_addr_w = ceil_log2(P_sq) + ceil_log2(N_crosslets * X_sq * c_nof_complex * (c_longword_sz/c_word_sz)
# . c_sdp_X_sq = S_pn**2 = g_nof_signal_inputs**2 # . c_sdp_X_sq = S_pn**2 = g_nof_signal_inputs**2
mm_port_span: ceil_pow2(g_nof_streams) + ceil_pow2(g_nof_crosslets * g_nof_signal_inputs**2 * c_nof_complex * g_stat_data_sz) * MM_BUS_SIZE mm_port_span: ceil_pow2(g_nof_crosslets * g_nof_signal_inputs**2 * c_nof_complex * g_stat_data_sz) * MM_BUS_SIZE
mm_port_description: | mm_port_description: |
"The crosslets statistics per PN are stored in g_nof_streams blocks "The crosslets statistics per PN are stored in g_nof_streams blocks
of each nof_stat values per block (= per X_sq correlator cell). The of each nof_stat values per block (= per X_sq correlator cell). The
......
libraries/technology/ip_arria10_e1sg/altera_libraries/altmult_complex_180/compile_ip.tcl
+ 3
− 0
View file @ cf0e699c
...@@ -34,3 +34,6 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e ...@@ -34,3 +34,6 @@ set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e
vmap altmult_complex_180 ./work/ vmap altmult_complex_180 ./work/
vcom "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.vhd" vcom "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_altmult_complex_180_nkpx3mi.vhd"
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
vcom "$IP_DIR/../altmult_complex_180/sim/ip_arria10_e1sg_complex_mult_27b_altmult_complex_180_ylvsosy.vhd"
libraries/technology/ip_arria10_e1sg/complex_mult/compile_ip.tcl
+ 3
− 0
View file @ cf0e699c
...@@ -31,3 +31,6 @@ ...@@ -31,3 +31,6 @@
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim" set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult/sim"
vcom "$IP_DIR/ip_arria10_e1sg_complex_mult.vhd" vcom "$IP_DIR/ip_arria10_e1sg_complex_mult.vhd"
set IP_DIR "$env(RADIOHDL_BUILD_DIR)/$env(BUILDSET)/qsys-generate/ip_arria10_e1sg_complex_mult_27b/sim"
vcom "$IP_DIR/ip_arria10_e1sg_complex_mult_27b.vhd"
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