JESD outputs data on upper 14 bits instead of lower 14 bits

applications/lofar2/libraries/sdp/src/vhdl/node_sdp_adc_input_and_timing.vhd

@@ -204,13 +204,16 @@ BEGIN
   -- . the input valid is always '1', even when there is no data 
   -----------------------------------------------------------------------------
   
-  gen_force_valid : FOR I IN 0 TO c_sdp_S_pn-1 GENERATE
-    p_sosi : PROCESS(rx_sosi_arr)
-    BEGIN
-      dp_shiftram_snk_in_arr(I)       <= rx_sosi_arr(I);
-      dp_shiftram_snk_in_arr(I).valid <= '1';
-    END PROCESS;
-  END GENERATE;
+  p_dp_shiftram_snk_in_arr : PROCESS(rx_sosi_arr)
+  BEGIN
+    dp_shiftram_snk_in_arr <= rx_sosi_arr;
+    FOR I IN 0 TO c_sdp_S_pn-1 LOOP
+      -- ADC data is stored in the upper 14 bits of the jesd rx_sosi.
+      dp_shiftram_snk_in_arr(I).data    <= RESIZE_DP_SDATA(rx_sosi_arr(I).data(c_sdp_W_adc_jesd-1 DOWNTO (c_sdp_W_adc_jesd - c_sdp_W_adc) ));
+      -- Force valid.
+      dp_shiftram_snk_in_arr(I).valid   <= '1';
+    END LOOP;
+  END PROCESS;
 
 
   u_dp_shiftram : ENTITY dp_lib.dp_shiftram