Copied from ip_arria10_e2sg/ram/. Changed technology name to ip_ agi027_xxxx...

Copied from ip_arria10_e2sg/ram/. Changed technology name to ip_ agi027_xxxx for hdl_lib_name, hdl_library_clause_name, hdl_lib_uses_synth, hdl_lib_technology and synth_files, and in synth_files= *true_dual_port_ram_dual_clock.vhd to *true_dual_port_ram_single_clock.vhd.

libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg

+hdl_lib_name = ip_agi027_xxxx_ram
+hdl_library_clause_name = ip_agi027_xxxx_ram_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+    ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd
+    ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd
+    ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd
+    
+    ip_agi027_xxxx_ram_cr_cw.vhd
+    ip_agi027_xxxx_ram_rw_rw.vhd
+    ip_agi027_xxxx_ram_r_w.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+