From cc702dccff6fb8351af9794a393d018e9ef663ad Mon Sep 17 00:00:00 2001
From: David Brouwer <dbrouwer@astron.nl>
Date: Thu, 2 Nov 2023 10:46:04 +0100
Subject: [PATCH] Copied from ip_arria10_e2sg/ram/. Changed technology name to
 ip_ agi027_xxxx for hdl_lib_name, hdl_library_clause_name,
 hdl_lib_uses_synth, hdl_lib_technology and synth_files, and in synth_files=
 *true_dual_port_ram_dual_clock.vhd to *true_dual_port_ram_single_clock.vhd.

---
 .../technology/ip_agi027_xxxx/ram/hdllib.cfg  | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg

diff --git a/libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg b/libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg
new file mode 100644
index 0000000000..cde0c8fedc
--- /dev/null
+++ b/libraries/technology/ip_agi027_xxxx/ram/hdllib.cfg
@@ -0,0 +1,23 @@
+hdl_lib_name = ip_agi027_xxxx_ram
+hdl_library_clause_name = ip_agi027_xxxx_ram_lib
+hdl_lib_uses_synth = technology
+hdl_lib_uses_sim = 
+hdl_lib_technology = ip_agi027_xxxx
+
+synth_files =
+    ip_agi027_xxxx_true_dual_port_ram_single_clock.vhd
+    ip_agi027_xxxx_simple_dual_port_ram_dual_clock.vhd
+    ip_agi027_xxxx_simple_dual_port_ram_single_clock.vhd
+    
+    ip_agi027_xxxx_ram_cr_cw.vhd
+    ip_agi027_xxxx_ram_rw_rw.vhd
+    ip_agi027_xxxx_ram_r_w.vhd
+    
+test_bench_files =
+
+
+[modelsim_project_file]
+
+
+[quartus_project_file]
+
-- 
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