1e fix run

applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd

@@ -386,7 +386,7 @@ begin
     ---------------------------------------------------------------------------
     -- Write FPGA_bf_ring_nof_transport_hops_RW = ring_lane_info.transport_nof_hops
     v_span := 2**c_addr_w_reg_ring_lane_info_bf;
-    for RN in 0 to c_last_rn LOOP
+    for RN in 0 to c_last_rn loop
       v_offset := 1 + RN * v_span;
       v_transport_nof_hops := 1;
       if RN = c_last_rn then
@@ -398,7 +398,7 @@ begin
     proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_dp_clk_period,
                                                 c_common_cross_clock_domain_latency * 2);
     -- Readback FPGA_bf_ring_nof_transport_hops_R
-    for RN in 0 to c_last_rn LOOP
+    for RN in 0 to c_last_rn loop
       v_offset := 1 + RN * v_span;
       proc_mem_mm_bus_rd(v_offset, mm_clk, reg_ring_lane_info_bf_cipo, reg_ring_lane_info_bf_copi);
       proc_mem_mm_bus_rd_latency(1, mm_clk);
@@ -416,7 +416,7 @@ begin
     ---------------------------------------------------------------------------
     v_span := 2**c_sdp_reg_bsn_monitor_v2_addr_w;
     -- Read FPGA_bf_ring_rx_latency_R
-    for RN in 0 to c_last_rn LOOP
+    for RN in 0 to c_last_rn loop
       v_offset := 6 + RN * v_span;
       proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_cipo, reg_bsn_monitor_v2_ring_rx_bf_copi);
       proc_mem_mm_bus_rd_latency(1, mm_clk);
@@ -424,7 +424,7 @@ begin
     end loop;
     -- Read FPGA_bf_rx_align_latency_R, for both c_sdp_P_sum = 2 inputs per RN
     v_span_node := true_log_pow2(c_sdp_P_sum) * v_span;
-    for RN in 0 to c_last_rn LOOP
+    for RN in 0 to c_last_rn loop
       for P in 0 to c_sdp_P_sum - 1 loop
         v_offset := 6 + RN * v_span_node + P * v_span;
         proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_bf_rx_align_cipo, reg_bsn_monitor_v2_bf_rx_align_copi);
@@ -433,14 +433,14 @@ begin
       end loop;
     end loop;
     -- Read FPGA_bf_aligned_latency_R
-    for RN in 0 to c_last_rn LOOP
+    for RN in 0 to c_last_rn loop
       v_offset := 6 + RN * v_span;
       proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_bf_aligned_cipo, reg_bsn_monitor_v2_bf_aligned_copi);
       proc_mem_mm_bus_rd_latency(1, mm_clk);
       FPGA_bf_aligned_latency_R(RN) <= TO_SINT(reg_bsn_monitor_v2_bf_aligned_cipo.rddata(c_word_w - 1 downto 0));
     end loop;
     -- Read FPGA_bf_ring_tx_latency_R
-    for RN in 0 to c_last_rn LOOP
+    for RN in 0 to c_last_rn loop
       v_offset := 6 + RN * v_span;
       proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_cipo, reg_bsn_monitor_v2_ring_tx_bf_copi);
       proc_mem_mm_bus_rd_latency(1, mm_clk);
@@ -469,7 +469,7 @@ begin
                  int_to_str(FPGA_bf_rx_align_latency_R(RN)(1)) & " )        " &
                  int_to_str(FPGA_bf_aligned_latency_R(RN)) & "            " &
                  int_to_str(FPGA_bf_ring_tx_latency_R(RN)));
-    end Loop;
+    end loop;
 
     tb_end <= '1';
     wait;
@@ -610,7 +610,7 @@ begin
   ------------------------------------------------------------------------------
   p_verify_bf_sum : process(dp_clk)
   begin
-    for RN in 0 to c_last_rn Loop
+    for RN in 0 to c_last_rn loop
       if bf_sum_sosi_arr(RN).valid = '1' then
         assert TO_SINT(bf_sum_sosi_arr(RN).re) = (RN + 1) * c_local_bf_re report "Wrong BF re sum at node " & int_to_str(RN) severity error;
         assert TO_SINT(bf_sum_sosi_arr(RN).im) = (RN + 1) * c_local_bf_im report "Wrong BF im sum at node " & int_to_str(RN) severity error;

applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd

@@ -613,7 +613,7 @@ begin
                 int_to_str(FPGA_xst_ring_rx_latency_R(RN)(U), c_col_w);
       end loop;
       print_str(v_line);
-    end Loop;
+    end loop;
     print_str("");
 
     print_str("FPGA_xst_ring_tx_latency_R:");
@@ -629,7 +629,7 @@ begin
                 int_to_str(FPGA_xst_ring_tx_latency_R(RN)(U), c_col_w);
       end loop;
       print_str(v_line);
-    end Loop;
+    end loop;
     print_str("");
 
     print_str("FPGA_xst_rx_align_latency_R:");
@@ -645,13 +645,13 @@ begin
                 int_to_str(FPGA_xst_rx_align_latency_R(RN)(U), c_col_w);
       end loop;
       print_str(v_line);
-    end Loop;
+    end loop;
     print_str("");
 
     print_str("FPGA_xst_aligned_latency_R:");
     for RN in 0 to c_last_rn loop
       print_str(int_to_str(RN) & ": " & int_to_str(FPGA_xst_aligned_latency_R(RN)));
-    end Loop;
+    end loop;
     print_str("");
 
     tb_end <= '1';
@@ -829,7 +829,7 @@ begin
   p_verify_crosslets : process(dp_clk)
   begin
     -- Verify that data /= 0, so no lost data = 0 insertion
-    for RN in 0 to c_last_rn Loop
+    for RN in 0 to c_last_rn loop
       for P in 0 to c_P_sq - 1 loop
         if x_sosi_2arr(RN)(P).valid = '1' then
           assert TO_SINT(x_sosi_2arr(RN)(P).re) /= 0 report "Wrong crosslet re at node " & int_to_str(RN) severity error;