diff --git a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
index 5f59cf66fdc9ff4b49f7238087e7732de7b8b691..a68ec72956363a465162dc6454205e187040d8ab 100644
--- a/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
+++ b/applications/lofar1/RSP/pfs/src/vhdl/pfs_tapsbuf(rtl).vhd
@@ -14,13 +14,13 @@ begin
---------------------------------------------------------------
process (clk)
begin
- if (clk'event and clk = '1') then
- if (wren = '1') then
- RAM (conv_integer(wraddr)) <= wrdata;
- end if;
- read_addrb <= rdaddr;
+ if (clk'event and clk = '1') then
+ if (wren = '1') then
+ RAM (conv_integer(wraddr)) <= wrdata;
+ end if;
+ read_addrb <= rdaddr;
rddata <= RAM(conv_integer(read_addrb));
- end if;
+ end if;
end process;
---------------------------------------------------------------
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
index 5cc1a7bc4af02db5ba94db771d8050b1368fda87..4cacb6ce6f6848ef9d7e2e3e70ca30345b0e05ca 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_beamformer_remote_ring.vhd
@@ -386,7 +386,7 @@ begin
---------------------------------------------------------------------------
-- Write FPGA_bf_ring_nof_transport_hops_RW = ring_lane_info.transport_nof_hops
v_span := 2**c_addr_w_reg_ring_lane_info_bf;
- for RN in 0 to c_last_rn LOOP
+ for RN in 0 to c_last_rn loop
v_offset := 1 + RN * v_span;
v_transport_nof_hops := 1;
if RN = c_last_rn then
@@ -398,7 +398,7 @@ begin
proc_common_wait_cross_clock_domain_latency(c_mm_clk_period, c_dp_clk_period,
c_common_cross_clock_domain_latency * 2);
-- Readback FPGA_bf_ring_nof_transport_hops_R
- for RN in 0 to c_last_rn LOOP
+ for RN in 0 to c_last_rn loop
v_offset := 1 + RN * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_ring_lane_info_bf_cipo, reg_ring_lane_info_bf_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
@@ -416,7 +416,7 @@ begin
---------------------------------------------------------------------------
v_span := 2**c_sdp_reg_bsn_monitor_v2_addr_w;
-- Read FPGA_bf_ring_rx_latency_R
- for RN in 0 to c_last_rn LOOP
+ for RN in 0 to c_last_rn loop
v_offset := 6 + RN * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_ring_rx_bf_cipo, reg_bsn_monitor_v2_ring_rx_bf_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
@@ -424,7 +424,7 @@ begin
end loop;
-- Read FPGA_bf_rx_align_latency_R, for both c_sdp_P_sum = 2 inputs per RN
v_span_node := true_log_pow2(c_sdp_P_sum) * v_span;
- for RN in 0 to c_last_rn LOOP
+ for RN in 0 to c_last_rn loop
for P in 0 to c_sdp_P_sum - 1 loop
v_offset := 6 + RN * v_span_node + P * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_bf_rx_align_cipo, reg_bsn_monitor_v2_bf_rx_align_copi);
@@ -433,14 +433,14 @@ begin
end loop;
end loop;
-- Read FPGA_bf_aligned_latency_R
- for RN in 0 to c_last_rn LOOP
+ for RN in 0 to c_last_rn loop
v_offset := 6 + RN * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_bf_aligned_cipo, reg_bsn_monitor_v2_bf_aligned_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
FPGA_bf_aligned_latency_R(RN) <= TO_SINT(reg_bsn_monitor_v2_bf_aligned_cipo.rddata(c_word_w - 1 downto 0));
end loop;
-- Read FPGA_bf_ring_tx_latency_R
- for RN in 0 to c_last_rn LOOP
+ for RN in 0 to c_last_rn loop
v_offset := 6 + RN * v_span;
proc_mem_mm_bus_rd(v_offset, mm_clk, reg_bsn_monitor_v2_ring_tx_bf_cipo, reg_bsn_monitor_v2_ring_tx_bf_copi);
proc_mem_mm_bus_rd_latency(1, mm_clk);
@@ -469,7 +469,7 @@ begin
int_to_str(FPGA_bf_rx_align_latency_R(RN)(1)) & " ) " &
int_to_str(FPGA_bf_aligned_latency_R(RN)) & " " &
int_to_str(FPGA_bf_ring_tx_latency_R(RN)));
- end Loop;
+ end loop;
tb_end <= '1';
wait;
@@ -610,7 +610,7 @@ begin
------------------------------------------------------------------------------
p_verify_bf_sum : process(dp_clk)
begin
- for RN in 0 to c_last_rn Loop
+ for RN in 0 to c_last_rn loop
if bf_sum_sosi_arr(RN).valid = '1' then
assert TO_SINT(bf_sum_sosi_arr(RN).re) = (RN + 1) * c_local_bf_re report "Wrong BF re sum at node " & int_to_str(RN) severity error;
assert TO_SINT(bf_sum_sosi_arr(RN).im) = (RN + 1) * c_local_bf_im report "Wrong BF im sum at node " & int_to_str(RN) severity error;
diff --git a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
index f3ec0216b7663de1707e007a9dad35c9ae598afc..a94a8c33fa9fefb538aa1158f31a43f804e34b91 100644
--- a/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
+++ b/applications/lofar2/libraries/sdp/tb/vhdl/tb_sdp_crosslets_remote_ring.vhd
@@ -613,7 +613,7 @@ begin
int_to_str(FPGA_xst_ring_rx_latency_R(RN)(U), c_col_w);
end loop;
print_str(v_line);
- end Loop;
+ end loop;
print_str("");
print_str("FPGA_xst_ring_tx_latency_R:");
@@ -629,7 +629,7 @@ begin
int_to_str(FPGA_xst_ring_tx_latency_R(RN)(U), c_col_w);
end loop;
print_str(v_line);
- end Loop;
+ end loop;
print_str("");
print_str("FPGA_xst_rx_align_latency_R:");
@@ -645,13 +645,13 @@ begin
int_to_str(FPGA_xst_rx_align_latency_R(RN)(U), c_col_w);
end loop;
print_str(v_line);
- end Loop;
+ end loop;
print_str("");
print_str("FPGA_xst_aligned_latency_R:");
for RN in 0 to c_last_rn loop
print_str(int_to_str(RN) & ": " & int_to_str(FPGA_xst_aligned_latency_R(RN)));
- end Loop;
+ end loop;
print_str("");
tb_end <= '1';
@@ -829,7 +829,7 @@ begin
p_verify_crosslets : process(dp_clk)
begin
-- Verify that data /= 0, so no lost data = 0 insertion
- for RN in 0 to c_last_rn Loop
+ for RN in 0 to c_last_rn loop
for P in 0 to c_P_sq - 1 loop
if x_sosi_2arr(RN)(P).valid = '1' then
assert TO_SINT(x_sosi_2arr(RN)(P).re) /= 0 report "Wrong crosslet re at node " & int_to_str(RN) severity error;
diff --git a/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd b/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd
index 905fe77cabb4212ad3c36883ef568ab13f7b68f2..8fff1d5c72cf3d4b6b4affd8509aabec72ffd2fc 100644
--- a/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd
+++ b/applications/rdma_demo/libraries/rdma_generator/tb/vhdl/tb_rdma_generator.vhd
@@ -82,7 +82,7 @@ end tb_rdma_generator;
architecture tb of tb_rdma_generator is
-- use to distinguish logging from tb instances in tb_tb
- constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : ";
+ constant c_tb_str : string := "tb-" & natural'image(g_tb_index) & " : ";
constant mm_clk_period : time := 10 ns; -- 100 MHz
constant c_nof_st_clk_per_s : natural := 200 * 10**6;
@@ -261,7 +261,7 @@ begin
proc_mem_mm_bus_wr(v_offset + 16#10#, TO_SINT(c_eth_tester_ip_dst_addr),
mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
proc_mem_mm_bus_wr(v_offset + 16#18#, TO_SINT(c_eth_tester_eth_dst_mac(31 downto 0)),
- mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
+ mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
proc_mem_mm_bus_wr(v_offset + 16#19#, TO_UINT(c_eth_tester_eth_dst_mac(47 downto 32)),
mm_clk, reg_hdr_dat_cipo, reg_hdr_dat_copi);
end loop;
@@ -275,7 +275,7 @@ begin
proc_mem_mm_bus_wr(I * 2, bg_ctrl_arr(I).samples_per_packet, mm_clk, reg_dp_split_copi);
-- Prepare the BG
- proc_mem_mm_bus_wr(v_offset + 1, ceil_div(bg_ctrl_arr(I).samples_per_packet, g_nof_octet_generate),
+ proc_mem_mm_bus_wr(v_offset + 1, ceil_div(bg_ctrl_arr(I).samples_per_packet, g_nof_octet_generate),
mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 2, bg_ctrl_arr(I).blocks_per_sync, mm_clk, reg_bg_ctrl_copi);
proc_mem_mm_bus_wr(v_offset + 3, bg_ctrl_arr(I).gapsize, mm_clk, reg_bg_ctrl_copi);
@@ -432,17 +432,17 @@ begin
-- the ETH data rate < 1 Gbps and no BG block flow control.
-- Verify, only log when wrong
if I = 0 then
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_first report
c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx report
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_first_tx report
c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
else
- assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report
+ assert tx_mon_nof_sop_arr(I) = c_mon_nof_sop_others report
c_tb_str & "Wrong tx nof_sop for stream (" & natural'image(I) & ")" severity ERROR;
- assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx report
+ assert tx_mon_nof_valid_arr(I) = c_mon_nof_valid_others_tx report
c_tb_str & "Wrong tx nof_valid for stream (" & natural'image(I) & ")" severity ERROR;
end if;
- assert tx_mon_latency_arr(I) = c_tx_exp_latency report
+ assert tx_mon_latency_arr(I) = c_tx_exp_latency report
c_tb_str & "Wrong tx latency for stream (" & natural'image(I) & ")" severity ERROR;
-- For short block lengths the Rx latency appears to become less, the
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser.vhd b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser.vhd
index e142a25e85f2577455418ee0a466ad0269090f94..ab7609135554f20fa28ccffd828a16a20ee1fbf1 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser.vhd
@@ -21,7 +21,7 @@
-- Purpose: Packetizes an incoming data stream as RDMA "WRITE" packets.
-- Description: see https://support.astron.nl/confluence/x/urT-Bg
-- Note: Due to the extra headers being prepended and the latency
--- that is introduced, a gap size of 10 clock cycles between
+-- that is introduced, a gap size of 10 clock cycles between
-- packets is necessary.
library IEEE, common_lib, dp_lib, eth_lib, rdma_icrc_external_lib;
use IEEE.std_logic_1164.all;
@@ -64,7 +64,7 @@ architecture str of rdma_packetiser is
constant c_nof_byte : natural := 64;
constant c_data_w : natural := c_nof_byte * c_byte_w;
constant c_max_packet_size : natural := ceil_div(9000, c_nof_byte);
- -- dp_offload_tx_v3 needs 8 clock cycles (minimum) to prepend headers
+ -- dp_offload_tx_v3 needs 8 clock cycles (minimum) to prepend headers
-- even if the header is < 8 words
constant c_latency_dp_offload_tx : natural := 8;
constant c_dp_fifo_latency : natural := 3;
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd
index 5699ea65e28cce9e00aaf33eeaaec8e4aa97ad58..17b213f76fd0d07cf0741f40613e6f48aef389a4 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_assemble_header.vhd
@@ -108,7 +108,7 @@ architecture str of rdma_packetiser_assemble_header is
constant c_ip_udp_app_mid_hdr_len : natural := c_network_ip_header_len + c_udp_app_mid_hdr_len;
constant c_ip_udp_app_last_hdr_len : natural := c_network_ip_header_len + c_udp_app_last_hdr_len;
constant c_ip_udp_app_wo_hdr_len : natural := c_network_ip_header_len + c_udp_app_wo_hdr_len;
- constant c_nof_offload : natural := 4;
+ constant c_nof_offload : natural := 4;
type t_state is (s_first, s_middle, s_last);
type t_reg is record -- record to keep the registers organized.
@@ -167,13 +167,13 @@ architecture str of rdma_packetiser_assemble_header is
signal dp_pipeline_src_out : t_dp_sosi := c_dp_sosi_rst;
begin
- immediate_data <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "immediate_data" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "immediate_data" ));
- use_immediate <= sl(hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_use_immediate" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_use_immediate" )));
- use_msg_cnt_as_immediate <= sl(hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_use_msg_cnt_as_immediate") downto field_lo(c_rdma_packetiser_mm_field_arr, "config_use_msg_cnt_as_immediate")));
- nof_packets_in_msg <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_nof_packets_in_msg" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_nof_packets_in_msg" ));
- nof_msg <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_nof_msg" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_nof_msg" ));
- dma_len <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ));
- start_address <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_start_address" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_start_address" ));
+ immediate_data <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "immediate_data" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "immediate_data" ));
+ use_immediate <= sl(hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_use_immediate" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_use_immediate" )));
+ use_msg_cnt_as_immediate <= sl(hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_use_msg_cnt_as_immediate") downto field_lo(c_rdma_packetiser_mm_field_arr, "config_use_msg_cnt_as_immediate")));
+ nof_packets_in_msg <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_nof_packets_in_msg" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_nof_packets_in_msg" ));
+ nof_msg <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_nof_msg" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_nof_msg" ));
+ dma_len <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ));
+ start_address <= hdr_fields_slv_out_mm(field_hi(c_rdma_packetiser_mm_field_arr, "config_start_address" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "config_start_address" ));
-- State machine to derive RDMA header fields.
q <= d when rising_edge(dp_clk);
@@ -260,7 +260,7 @@ begin
end process;
-------------------------------------------------------------------------------
- -- Wire the header fields
+ -- Wire the header fields
-------------------------------------------------------------------------------
hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "ip_total_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "ip_total_length" )) <= TO_UVEC(q.ip_total_length, 16);
hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "udp_total_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "udp_total_length" )) <= TO_UVEC(q.udp_total_length, 16);
@@ -270,7 +270,7 @@ begin
hdr_fields_slv_in(field_hi(c_rdma_packetiser_mm_field_arr, "reth_dma_length" ) downto field_lo(c_rdma_packetiser_mm_field_arr, "reth_dma_length" )) <= std_logic_vector(q.dma_len);
-------------------------------------------------------------------------------
- -- demux to guide the incoming stream to the correct eth_ip_offload_tx
+ -- demux to guide the incoming stream to the correct eth_ip_offload_tx
-------------------------------------------------------------------------------
u_dp_demux : entity dp_lib.dp_demux
generic map (
@@ -285,10 +285,10 @@ begin
clk => dp_clk,
sel_ctrl => q.sel_ctrl,
-
+
snk_in => snk_in,
snk_out => snk_out,
-
+
src_out_arr => dp_demux_src_out_arr,
src_in_arr => dp_demux_src_in_arr
);
@@ -307,31 +307,31 @@ begin
p_wire_headers : process(hdr_fields_slv_out_mm, use_msg_cnt_as_immediate, q)
begin
-- set headers.
- eth_hdr <= field_select_subset(c_rdma_packetiser_eth_hdr_field_arr,
- c_rdma_packetiser_mm_field_arr,
+ eth_hdr <= field_select_subset(c_rdma_packetiser_eth_hdr_field_arr,
+ c_rdma_packetiser_mm_field_arr,
hdr_fields_slv_out_mm);
- hdr_fields_slv_in_first <= field_select_subset(c_rdma_packetiser_first_hdr_field_arr,
- c_rdma_packetiser_mm_field_arr,
+ hdr_fields_slv_in_first <= field_select_subset(c_rdma_packetiser_first_hdr_field_arr,
+ c_rdma_packetiser_mm_field_arr,
hdr_fields_slv_out_mm);
- hdr_fields_slv_in_mid <= field_select_subset(c_rdma_packetiser_mid_hdr_field_arr,
- c_rdma_packetiser_mm_field_arr,
+ hdr_fields_slv_in_mid <= field_select_subset(c_rdma_packetiser_mid_hdr_field_arr,
+ c_rdma_packetiser_mm_field_arr,
hdr_fields_slv_out_mm);
- hdr_fields_slv_in_last <= field_select_subset(c_rdma_packetiser_last_hdr_field_arr,
- c_rdma_packetiser_mm_field_arr,
+ hdr_fields_slv_in_last <= field_select_subset(c_rdma_packetiser_last_hdr_field_arr,
+ c_rdma_packetiser_mm_field_arr,
hdr_fields_slv_out_mm);
- hdr_fields_slv_in_wo <= field_select_subset(c_rdma_packetiser_wo_hdr_field_arr,
- c_rdma_packetiser_mm_field_arr,
+ hdr_fields_slv_in_wo <= field_select_subset(c_rdma_packetiser_wo_hdr_field_arr,
+ c_rdma_packetiser_mm_field_arr,
hdr_fields_slv_out_mm);
if use_msg_cnt_as_immediate = '1' then -- set immediate data to msg_cnt when use_msg_cnt_as_immediate = '1'
- hdr_fields_slv_in_last(field_hi(c_rdma_packetiser_last_hdr_field_arr, "immediate_data") downto
+ hdr_fields_slv_in_last(field_hi(c_rdma_packetiser_last_hdr_field_arr, "immediate_data") downto
field_lo(c_rdma_packetiser_last_hdr_field_arr, "immediate_data")) <= TO_UVEC(q.msg_cnt, 32);
- hdr_fields_slv_in_wo( field_hi(c_rdma_packetiser_wo_hdr_field_arr, "immediate_data") downto
+ hdr_fields_slv_in_wo( field_hi(c_rdma_packetiser_wo_hdr_field_arr, "immediate_data") downto
field_lo(c_rdma_packetiser_wo_hdr_field_arr, "immediate_data")) <= TO_UVEC(q.msg_cnt, 32);
end if;
end process;
-------------------------------------------------------------------------------
- -- Header for first packets or write only without immediate data
+ -- Header for first packets or write only without immediate data
-------------------------------------------------------------------------------
u_eth_ip_offload_first : entity eth_lib.eth_ip_offload_tx
generic map (
@@ -393,11 +393,11 @@ begin
snk_out_arr(0) => eth_ip_offload_last_snk_out,
src_out_arr(0) => eth_ip_offload_last_src_out,
src_in_arr(0) => eth_ip_offload_last_src_in,
- hdr_fields_in_arr(0) => hdr_fields_slv_in_last
+ hdr_fields_in_arr(0) => hdr_fields_slv_in_last
);
-------------------------------------------------------------------------------
- -- Header for write only packets with immediate data
+ -- Header for write only packets with immediate data
-------------------------------------------------------------------------------
u_eth_ip_offload_wo : entity eth_lib.eth_ip_offload_tx
generic map (
@@ -445,8 +445,8 @@ begin
mm_clk => mm_clk,
dp_rst => dp_rst,
dp_clk => dp_clk,
- reg_hdr_dat_mosi => reg_hdr_dat_copi,
- reg_hdr_dat_miso => reg_hdr_dat_cipo,
+ reg_hdr_dat_mosi => reg_hdr_dat_copi,
+ reg_hdr_dat_miso => reg_hdr_dat_cipo,
snk_in_arr(0) => dp_pipeline_src_out,
hdr_fields_in_arr(0) => hdr_fields_slv_in,
hdr_fields_out_arr(0) => hdr_fields_slv_out_mm
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
index 0b1a9ec103b92ae5a10fb34379c16857b50c3228..e2c6d16f5e0f7ef3450f598c51922611bd784aa9 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/src/vhdl/rdma_packetiser_pkg.vhd
@@ -95,7 +95,7 @@ package rdma_packetiser_pkg is
constant c_rdma_packetiser_mm_field_arr : t_common_field_arr(
c_rdma_packetiser_mm_nof_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ),
( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), -- fixed
@@ -146,7 +146,7 @@ package rdma_packetiser_pkg is
constant c_rdma_packetiser_reg_mm_dat_addr_w : natural := ceil_log2(field_nof_words(c_rdma_packetiser_mm_field_arr, c_word_w));
constant c_rdma_packetiser_reg_mm_dat_addr_span : natural := 2**c_rdma_packetiser_reg_mm_dat_addr_w;
- -- ETH header
+ -- ETH header
-- Handeled seperate from the other headers as the ethernet header must be excluded from the icrc checksum computation.
constant c_rdma_packetiser_eth_hdr_nof_fields : natural := 3 ;
constant c_rdma_packetiser_eth_hdr_field_sel : std_logic_vector(c_rdma_packetiser_eth_hdr_nof_fields - 1 downto 0) := (others => '0');
@@ -154,7 +154,7 @@ package rdma_packetiser_pkg is
constant c_rdma_packetiser_eth_hdr_field_arr : t_common_field_arr(
c_rdma_packetiser_eth_hdr_nof_fields - 1 downto 0) := (
( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(0) ),
- ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
+ ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ),
( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") )
);
@@ -195,11 +195,11 @@ package rdma_packetiser_pkg is
( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
- ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
+ ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
- ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) )
+ ( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) )
);
@@ -240,7 +240,7 @@ package rdma_packetiser_pkg is
( field_name_pad("bth_dest_qp" ), "RW", 16, field_default(0) ),
( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
- ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) )
+ ( field_name_pad("bth_psn" ), "RW", 32, field_default(0) )
);
-- RoCEv2 header for last packets with immediate data
@@ -323,12 +323,12 @@ package rdma_packetiser_pkg is
( field_name_pad("bth_ack_req" ), "RW", 1, field_default(0) ),
( field_name_pad("bth_reserved_b" ), "RW", 7, field_default(0) ),
( field_name_pad("bth_psn" ), "RW", 32, field_default(0) ),
-
+
( field_name_pad("reth_virtual_address"), "RW", 64, field_default(0) ),
( field_name_pad("reth_r_key" ), "RW", 32, field_default(0) ),
( field_name_pad("reth_dma_length" ), "RW", 32, field_default(0) ),
- ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
+ ( field_name_pad("immediate_data" ), "RW", 32, field_default(0) )
);
constant c_rdma_packetiser_bth_len : natural := 12; -- octets
@@ -399,7 +399,7 @@ package body rdma_packetiser_pkg is
v.bth.ack_req := hdr_fields_raw(field_hi(c_hdr_field_arr, "bth_ack_req") downto field_lo(c_hdr_field_arr, "bth_ack_req"));
v.bth.reserved_b := hdr_fields_raw(field_hi(c_hdr_field_arr, "bth_reserved_b") downto field_lo(c_hdr_field_arr, "bth_reserved_b"));
v.bth.psn := hdr_fields_raw(field_hi(c_hdr_field_arr, "bth_psn") downto field_lo(c_hdr_field_arr, "bth_psn"));
-
+
-- reth header (optional)
v.reth := ((others => '0'), (others => '0'),(others => '0'));
if field_exists(c_hdr_field_arr, "reth_virtual_address") then -- reth header exists
@@ -421,7 +421,7 @@ package body rdma_packetiser_pkg is
constant c_field_len : natural := field_slv_len(field_arr);
variable v : std_logic_vector(c_field_len-1 downto 0) := (others => '0');
constant c_hdr_field_arr : t_common_field_arr := field_arr;
- begin
+ begin
-- eth header (optional)
if field_exists(c_hdr_field_arr, "eth_dst_mac") then -- eth header exists
v(field_hi(c_hdr_field_arr, "eth_dst_mac") downto field_lo(c_hdr_field_arr, "eth_dst_mac")) := hdr_fields.eth.dst_mac;
@@ -429,7 +429,7 @@ package body rdma_packetiser_pkg is
v(field_hi(c_hdr_field_arr, "eth_type") downto field_lo(c_hdr_field_arr, "eth_type")) := hdr_fields.eth.eth_type;
end if;
- -- ip header
+ -- ip header
v(field_hi(c_hdr_field_arr, "ip_version") downto field_lo(c_hdr_field_arr, "ip_version")) := hdr_fields.ip.version;
v(field_hi(c_hdr_field_arr, "ip_header_length") downto field_lo(c_hdr_field_arr, "ip_header_length")) := hdr_fields.ip.header_length;
v(field_hi(c_hdr_field_arr, "ip_services") downto field_lo(c_hdr_field_arr, "ip_services")) := hdr_fields.ip.services;
@@ -443,13 +443,13 @@ package body rdma_packetiser_pkg is
v(field_hi(c_hdr_field_arr, "ip_src_addr") downto field_lo(c_hdr_field_arr, "ip_src_addr")) := hdr_fields.ip.src_ip_addr;
v(field_hi(c_hdr_field_arr, "ip_dst_addr") downto field_lo(c_hdr_field_arr, "ip_dst_addr")) := hdr_fields.ip.dst_ip_addr;
- -- udp header
+ -- udp header
v(field_hi(c_hdr_field_arr, "udp_src_port") downto field_lo(c_hdr_field_arr, "udp_src_port")) := hdr_fields.udp.src_port;
v(field_hi(c_hdr_field_arr, "udp_dst_port") downto field_lo(c_hdr_field_arr, "udp_dst_port")) := hdr_fields.udp.dst_port;
v(field_hi(c_hdr_field_arr, "udp_total_length") downto field_lo(c_hdr_field_arr, "udp_total_length")) := hdr_fields.udp.total_length;
v(field_hi(c_hdr_field_arr, "udp_checksum") downto field_lo(c_hdr_field_arr, "udp_checksum")) := hdr_fields.udp.checksum;
- -- bth header
+ -- bth header
v(field_hi(c_hdr_field_arr, "bth_opcode") downto field_lo(c_hdr_field_arr, "bth_opcode")) := hdr_fields.bth.opcode;
v(field_hi(c_hdr_field_arr, "bth_se") downto field_lo(c_hdr_field_arr, "bth_se")) := hdr_fields.bth.se;
v(field_hi(c_hdr_field_arr, "bth_m") downto field_lo(c_hdr_field_arr, "bth_m")) := hdr_fields.bth.m;
@@ -463,7 +463,7 @@ package body rdma_packetiser_pkg is
v(field_hi(c_hdr_field_arr, "bth_ack_req") downto field_lo(c_hdr_field_arr, "bth_ack_req")) := hdr_fields.bth.ack_req;
v(field_hi(c_hdr_field_arr, "bth_reserved_b") downto field_lo(c_hdr_field_arr, "bth_reserved_b")) := hdr_fields.bth.reserved_b;
v(field_hi(c_hdr_field_arr, "bth_psn") downto field_lo(c_hdr_field_arr, "bth_psn")) := hdr_fields.bth.psn;
-
+
-- reth header
v(field_hi(c_hdr_field_arr, "reth_virtual_address") downto field_lo(c_hdr_field_arr, "reth_virtual_address")) := hdr_fields.reth.virtual_address;
v(field_hi(c_hdr_field_arr, "reth_r_key") downto field_lo(c_hdr_field_arr, "reth_r_key")) := hdr_fields.reth.r_key;
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
index 89f38bc41bdfe0ee7b576bd72aa38a48da6393b1..480a928a3fcb52df8dce3e90bf519bc040b759b4 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_rdma_packetiser_assemble_header.vhd
@@ -195,7 +195,7 @@ begin
-- calculate expected lengths
v_exp_udp_total_length := c_network_udp_header_len + c_rdma_packetiser_bth_len + to_uint(block_len) + c_rdma_packetiser_icrc_len;
v_exp_reth_virtual_address := (others => '0');
- v_exp_reth_dma_length := 0;
+ v_exp_reth_dma_length := 0;
if v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_first or
v_exp_bth_opcode = c_rdma_packetiser_opcode_uc_write_only or
@@ -254,7 +254,7 @@ begin
v_m := v_p / g_nof_packets_in_msg;
proc_common_wait_some_cycles(dp_clk, 1);
-
+
-- assert when header is not as expected.
assert rx_rdma_header = exp_rdma_header report "Wrong rx_rdma_header" severity error;
assert rx_rdma_header.ip.total_length = exp_rdma_header.ip.total_length report "Wrong rx_rdma_header.ip.total_length value" severity error;
@@ -288,7 +288,7 @@ begin
snk_in => snk_in,
snk_out => snk_out,
-
+
src_out => src_out,
src_in => src_in,
@@ -296,7 +296,7 @@ begin
);
-------------------------------------------------------------------------------
- -- Header for first packets or write only without immediate data
+ -- Header for first packets or write only without immediate data
-------------------------------------------------------------------------------
u_dp_offload_first: entity dp_lib.dp_offload_rx
generic map (
@@ -353,7 +353,7 @@ begin
);
-------------------------------------------------------------------------------
- -- Header for write only packets with immediate data
+ -- Header for write only packets with immediate data
-------------------------------------------------------------------------------
u_dp_offload_wo: entity dp_lib.dp_offload_rx
generic map (
diff --git a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd
index 2a800a776a368365f0f07dfd6609436e0cccb3ba..9527eeef22627f1535e8ee934886f5315c722d1a 100644
--- a/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd
+++ b/applications/rdma_demo/libraries/rdma_packetiser/tb/vhdl/tb_tb_rdma_packetiser_assemble_header.vhd
@@ -53,11 +53,11 @@ begin
u_lo_addr : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_low_start_addr, 4, 5);
u_hi_addr : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_high_start_addr, 4, 5);
u_no_mid : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_high_start_addr, 2, 5);
- u_wr_only : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_high_start_addr, 1, 5);
+ u_wr_only : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 50, 15, c_high_start_addr, 1, 5);
u_large : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 10, 2000, c_low_start_addr, 3, 1);
u_no_imm_cnt : entity work.tb_rdma_packetiser_assemble_header generic map( 32, false, true, 50, 15, c_low_start_addr, 4, 5);
u_no_cnt : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, false, 50, 15, c_low_start_addr, 4, 5);
u_no_imm : entity work.tb_rdma_packetiser_assemble_header generic map( 32, false, false, 50, 7, c_high_start_addr, 3, 5);
- u_wide : entity work.tb_rdma_packetiser_assemble_header generic map( 1024, true, true, 50, 6, c_low_start_addr, 1, 5);
- u_many : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 600, 7, c_low_start_addr, 100, 5);
+ u_wide : entity work.tb_rdma_packetiser_assemble_header generic map( 1024, true, true, 50, 6, c_low_start_addr, 1, 5);
+ u_many : entity work.tb_rdma_packetiser_assemble_header generic map( 32, true, true, 600, 7, c_low_start_addr, 100, 5);
end tb;
diff --git a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
index 24a8174ff6cb64308949e445ebd127229d2e1b41..598bfdf53b57e2d42ec99b8a0ba8fcb26a8c4f36 100644
--- a/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
+++ b/boards/uniboard2/designs/unb2_pinning/src/vhdl/unb2_pinning.vhd
@@ -510,16 +510,16 @@ begin
if local_i_clk'event and local_i_clk = '1' then
local_i_be <= (others => '1');
if local_i_ready = '1' then
- local_i_read <= not local_i_read;
+ local_i_read <= not local_i_read;
local_i_write <= local_i_read_data_valid;
local_i_address <= local_i_address + 1;
- if local_i_read_data_valid = '1' then
+ if local_i_read_data_valid = '1' then
local_i_writedata <= not local_i_readdata;
- else
- local_i_writedata <= (others => '1');
+ else
+ local_i_writedata <= (others => '1');
end if;
end if;
- end if;
+ end if;
end if;
end process;
@@ -578,16 +578,16 @@ begin
if local_ii_clk'event and local_ii_clk = '1' then
local_ii_be <= (others => '1');
if local_ii_ready = '1' then
- local_ii_read <= not local_ii_read;
+ local_ii_read <= not local_ii_read;
local_ii_write <= local_ii_read_data_valid;
local_ii_address <= local_ii_address + 1;
- if local_ii_read_data_valid = '1' then
+ if local_ii_read_data_valid = '1' then
local_ii_writedata <= not local_ii_readdata;
- else
- local_ii_writedata <= (others => '1');
+ else
+ local_ii_writedata <= (others => '1');
end if;
end if;
- end if;
+ end if;
end if;
end process;
@@ -656,7 +656,7 @@ begin
rx_cdr_refclk0 => sa_clk,
tx_serial_data => tx_serial_data_front,
rx_serial_data => rx_serial_data_front,
- tx_coreclkin => tx_serdesclk_front, -- write side clock for tx fifo
+ tx_coreclkin => tx_serdesclk_front, -- write side clock for tx fifo
rx_coreclkin => tx_serdesclk_front,
tx_clkout => tx_serdesclk_front,
rx_clkout => open,
@@ -729,7 +729,7 @@ begin
rx_cdr_refclk0 => sb_clk,
tx_serial_data => tx_serial_data_back(47 downto 24),
rx_serial_data => rx_serial_data_back(47 downto 24),
- tx_coreclkin => tx_serdesclk_back(47 downto 24), -- write side clock for tx fifo
+ tx_coreclkin => tx_serdesclk_back(47 downto 24), -- write side clock for tx fifo
rx_coreclkin => tx_serdesclk_back(47 downto 24),
tx_clkout => tx_serdesclk_back(47 downto 24),
rx_clkout => open,
@@ -793,7 +793,7 @@ begin
rx_cdr_refclk0 => bck_ref_clk,
tx_serial_data => tx_serial_data_back(23 downto 0),
rx_serial_data => rx_serial_data_back(23 downto 0),
- tx_coreclkin => tx_serdesclk_back(23 downto 0), -- write side clock for tx fifo
+ tx_coreclkin => tx_serdesclk_back(23 downto 0), -- write side clock for tx fifo
rx_coreclkin => tx_serdesclk_back(23 downto 0),
tx_clkout => tx_serdesclk_back(23 downto 0),
rx_clkout => open,
diff --git a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
index 8f346a6f27cd7e3c42e7cd900c8702cbe0dceea8..b75ee3b644282236ab8033310c593bbf3400f058 100644
--- a/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
+++ b/boards/uniboard2/designs/unb2_singlemac/src/vhdl/unb2_singlemac.vhd
@@ -348,7 +348,7 @@ begin
locked => sys_locked,
outclk_0 => mm_clk, -- 100MHz
outclk_1 => sys_clk, -- 300MHz
- outclk_2 => clk_125 -- 125MHz for 1ge
+ outclk_2 => clk_125 -- 125MHz for 1ge
);
-- bidirectional and misc
@@ -392,7 +392,7 @@ begin
toggle_count <= toggle_count + 1;
else
toggle_count <= (others => '0');
- led_state <= not led_state;
+ led_state <= not led_state;
end if;
end if;
end if;
@@ -406,7 +406,7 @@ begin
else
toggle_count1 <= (others => '0');
testio_out(2) <= not testio_out(2);
- pout_wdi <= not pout_wdi;
+ pout_wdi <= not pout_wdi;
end if;
end if;
end process;
diff --git a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
index 0e6ff5436b8694a8ac2b36a829ca58f4d2925381..80d8c6cc7218c08a1158b925b290cbc22c037177 100644
--- a/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
+++ b/boards/uniboard2/designs/unb2_test/src/vhdl/mmm_unb2_test.vhd
@@ -758,21 +758,21 @@ begin
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
index f2b16a715495109a68ad8c1939b70094532de969..8c34e863e2342a6bbe66911fe5dc103e15cfffc0 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew/ddr4_micron46_mbIIskew_inst.vhd
@@ -1,90 +1,90 @@
- component ddr4_micron46_mbIIskew is
- port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
- );
- end component ddr4_micron46_mbIIskew;
+ component ddr4_micron46_mbIIskew is
+ port (
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic; -- readdatavalid
+ mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
+ mmr_slave_read_0 : in std_logic := 'X'; -- read
+ mmr_slave_write_0 : in std_logic := 'X'; -- write
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
+ mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
+ emif_usr_clk : out std_logic; -- clk
+ emif_usr_reset_n : out std_logic; -- reset_n
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic -- local_cal_fail
+ );
+ end component ddr4_micron46_mbIIskew;
- u0 : component ddr4_micron46_mbIIskew
- port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
- mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
- mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
- mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+ u0 : component ddr4_micron46_mbIIskew
+ port map (
+ amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
+ amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
+ amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
+ amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
+ mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
+ mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
+ mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
+ mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
+ mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
+ mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
+ mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
+ mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
+ mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
+ mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
+ mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
+ mem_a => CONNECTED_TO_mem_a, -- .mem_a
+ mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
+ mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
+ mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
+ mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
+ mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
+ mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
+ mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
+ mem_par => CONNECTED_TO_mem_par, -- .mem_par
+ mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
+ mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
+ mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
+ oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
+ local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ );
diff --git a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
index c028fced708026eff114f3297a08f0c515850074..b405106f3ab75d1c6f4622b05e02bd728fe84c33 100644
--- a/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
+++ b/boards/uniboard2a/designs/altera_ref_designs/ddr4/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew/ddr4_micron46_mbIskew_inst.vhd
@@ -1,90 +1,90 @@
- component ddr4_micron46_mbIskew is
- port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
- );
- end component ddr4_micron46_mbIskew;
+ component ddr4_micron46_mbIskew is
+ port (
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic; -- readdatavalid
+ mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
+ mmr_slave_read_0 : in std_logic := 'X'; -- read
+ mmr_slave_write_0 : in std_logic := 'X'; -- write
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
+ mmr_slave_readdatavalid_0 : out std_logic; -- readdatavalid
+ emif_usr_clk : out std_logic; -- clk
+ emif_usr_reset_n : out std_logic; -- reset_n
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic -- local_cal_fail
+ );
+ end component ddr4_micron46_mbIskew;
- u0 : component ddr4_micron46_mbIskew
- port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
- mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
- mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
- mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+ u0 : component ddr4_micron46_mbIskew
+ port map (
+ amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
+ amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
+ amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
+ amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
+ mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
+ mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
+ mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
+ mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
+ mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
+ mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
+ mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
+ mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
+ mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0, -- .readdatavalid
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
+ mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
+ mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
+ mem_a => CONNECTED_TO_mem_a, -- .mem_a
+ mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
+ mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
+ mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
+ mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
+ mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
+ mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
+ mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
+ mem_par => CONNECTED_TO_mem_par, -- .mem_par
+ mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
+ mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
+ mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
+ oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
+ local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ );
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
index 262091355adb479dc226846baa15fb29cc297e0e..ed36a9a7daa389bf1e542ab32f11add8c4e54457 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/mmm_unb2a_test.vhd
@@ -784,21 +784,21 @@ begin
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
diff --git a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
index 1a5006c92d75968729f9fc849d656f8f42f90f68..95b0f768f13711445f2f07be22ec2378f3ea7144 100644
--- a/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
+++ b/boards/uniboard2a/designs/unb2a_test/src/vhdl/qsys_unb2a_test_pkg.vhd
@@ -29,7 +29,7 @@ package qsys_unb2a_test_pkg is
-----------------------------------------------------------------------------
component qsys_unb2a_test is
- port (
+ port (
avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 1188b1f4a3a8c3bda14f3b6fb3aaf6912e8d9d4f..63b9a4eac3f8c5286e4c22e7c5d6ba61ad1ca40f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,18 +1,18 @@
- component altjesd_ss_RX_corepll is
- port (
- locked : out std_logic; -- export
- outclk_0 : out std_logic; -- clk
- outclk_1 : out std_logic; -- clk
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X' -- reset
- );
- end component altjesd_ss_RX_corepll;
+ component altjesd_ss_RX_corepll is
+ port (
+ locked : out std_logic; -- export
+ outclk_0 : out std_logic; -- clk
+ outclk_1 : out std_logic; -- clk
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X' -- reset
+ );
+ end component altjesd_ss_RX_corepll;
- u0 : component altjesd_ss_RX_corepll
- port map (
- locked => CONNECTED_TO_locked, -- locked.export
- outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
- outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
- refclk => CONNECTED_TO_refclk, -- refclk.clk
- rst => CONNECTED_TO_rst -- reset.reset
- );
+ u0 : component altjesd_ss_RX_corepll
+ port map (
+ locked => CONNECTED_TO_locked, -- locked.export
+ outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
+ outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
+ refclk => CONNECTED_TO_refclk, -- refclk.clk
+ rst => CONNECTED_TO_rst -- reset.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 4d125d7d6b09eb801f54521d54896e4cd0d3f452..151469f9ea5ad6202d813b7837e88cd36ec84839 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_frame_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_frame_reset;
+ component altjesd_ss_RX_frame_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+ end component altjesd_ss_RX_frame_reset;
- u0 : component altjesd_ss_RX_frame_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+ u0 : component altjesd_ss_RX_frame_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 2fdfadb51af42decdc595af06f6653c82f64f67b..a2d2bd6b6e8367d16a7033b23352468912e69240 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_link_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_link_reset;
+ component altjesd_ss_RX_link_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+ end component altjesd_ss_RX_link_reset;
- u0 : component altjesd_ss_RX_link_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+ u0 : component altjesd_ss_RX_link_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index f5e2ba1f77a9a3ef8e6ec47a9929ad820950c0a3..55a61ea70d8b1e675806ba2799f926c728f4f61d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -1,162 +1,162 @@
- component altjesd_ss_RX_reset_seq is
- generic (
- NUM_OUTPUTS : integer := 3;
- ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
- ENABLE_ASSERTION_SEQUENCE : integer := 0;
- ENABLE_DEASSERTION_SEQUENCE : integer := 0;
- MIN_ASRT_TIME : integer := 0;
- ASRT_DELAY0 : integer := 0;
- DSRT_DELAY0 : integer := 0;
- ASRT_REMAP0 : integer := 0;
- DSRT_REMAP0 : integer := 0;
- DSRT_QUALCNT_0 : integer := 0;
- ASRT_DELAY1 : integer := 0;
- DSRT_DELAY1 : integer := 0;
- ASRT_REMAP1 : integer := 1;
- DSRT_REMAP1 : integer := 1;
- DSRT_QUALCNT_1 : integer := 0;
- ASRT_DELAY2 : integer := 0;
- DSRT_DELAY2 : integer := 0;
- ASRT_REMAP2 : integer := 2;
- DSRT_REMAP2 : integer := 2;
- DSRT_QUALCNT_2 : integer := 0;
- ASRT_DELAY3 : integer := 0;
- DSRT_DELAY3 : integer := 0;
- ASRT_REMAP3 : integer := 3;
- DSRT_REMAP3 : integer := 3;
- DSRT_QUALCNT_3 : integer := 0;
- ASRT_DELAY4 : integer := 0;
- DSRT_DELAY4 : integer := 0;
- ASRT_REMAP4 : integer := 4;
- DSRT_REMAP4 : integer := 4;
- DSRT_QUALCNT_4 : integer := 0;
- ASRT_DELAY5 : integer := 0;
- DSRT_DELAY5 : integer := 0;
- ASRT_REMAP5 : integer := 5;
- DSRT_REMAP5 : integer := 5;
- DSRT_QUALCNT_5 : integer := 0;
- ASRT_DELAY6 : integer := 0;
- DSRT_DELAY6 : integer := 0;
- ASRT_REMAP6 : integer := 6;
- DSRT_REMAP6 : integer := 6;
- DSRT_QUALCNT_6 : integer := 0;
- ASRT_DELAY7 : integer := 0;
- DSRT_DELAY7 : integer := 0;
- ASRT_REMAP7 : integer := 7;
- DSRT_REMAP7 : integer := 7;
- DSRT_QUALCNT_7 : integer := 0;
- ASRT_DELAY8 : integer := 0;
- DSRT_DELAY8 : integer := 0;
- ASRT_REMAP8 : integer := 8;
- DSRT_REMAP8 : integer := 8;
- DSRT_QUALCNT_8 : integer := 0;
- ASRT_DELAY9 : integer := 0;
- DSRT_DELAY9 : integer := 0;
- ASRT_REMAP9 : integer := 9;
- DSRT_REMAP9 : integer := 9;
- DSRT_QUALCNT_9 : integer := 0
- );
- port (
- av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_read : in std_logic := 'X'; -- read
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_write : in std_logic := 'X'; -- write
- irq : out std_logic; -- irq
- clk : in std_logic := 'X'; -- clk
- csr_reset : in std_logic := 'X'; -- reset
- reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- reset_in0 : in std_logic := 'X'; -- reset
- reset_out0 : out std_logic; -- reset
- reset_out1 : out std_logic; -- reset
- reset_out2 : out std_logic; -- reset
- reset_out3 : out std_logic; -- reset
- reset_out4 : out std_logic; -- reset
- reset_out5 : out std_logic; -- reset
- reset_out6 : out std_logic; -- reset
- reset_out7 : out std_logic -- reset
- );
- end component altjesd_ss_RX_reset_seq;
+ component altjesd_ss_RX_reset_seq is
+ generic (
+ NUM_OUTPUTS : integer := 3;
+ ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
+ ENABLE_ASSERTION_SEQUENCE : integer := 0;
+ ENABLE_DEASSERTION_SEQUENCE : integer := 0;
+ MIN_ASRT_TIME : integer := 0;
+ ASRT_DELAY0 : integer := 0;
+ DSRT_DELAY0 : integer := 0;
+ ASRT_REMAP0 : integer := 0;
+ DSRT_REMAP0 : integer := 0;
+ DSRT_QUALCNT_0 : integer := 0;
+ ASRT_DELAY1 : integer := 0;
+ DSRT_DELAY1 : integer := 0;
+ ASRT_REMAP1 : integer := 1;
+ DSRT_REMAP1 : integer := 1;
+ DSRT_QUALCNT_1 : integer := 0;
+ ASRT_DELAY2 : integer := 0;
+ DSRT_DELAY2 : integer := 0;
+ ASRT_REMAP2 : integer := 2;
+ DSRT_REMAP2 : integer := 2;
+ DSRT_QUALCNT_2 : integer := 0;
+ ASRT_DELAY3 : integer := 0;
+ DSRT_DELAY3 : integer := 0;
+ ASRT_REMAP3 : integer := 3;
+ DSRT_REMAP3 : integer := 3;
+ DSRT_QUALCNT_3 : integer := 0;
+ ASRT_DELAY4 : integer := 0;
+ DSRT_DELAY4 : integer := 0;
+ ASRT_REMAP4 : integer := 4;
+ DSRT_REMAP4 : integer := 4;
+ DSRT_QUALCNT_4 : integer := 0;
+ ASRT_DELAY5 : integer := 0;
+ DSRT_DELAY5 : integer := 0;
+ ASRT_REMAP5 : integer := 5;
+ DSRT_REMAP5 : integer := 5;
+ DSRT_QUALCNT_5 : integer := 0;
+ ASRT_DELAY6 : integer := 0;
+ DSRT_DELAY6 : integer := 0;
+ ASRT_REMAP6 : integer := 6;
+ DSRT_REMAP6 : integer := 6;
+ DSRT_QUALCNT_6 : integer := 0;
+ ASRT_DELAY7 : integer := 0;
+ DSRT_DELAY7 : integer := 0;
+ ASRT_REMAP7 : integer := 7;
+ DSRT_REMAP7 : integer := 7;
+ DSRT_QUALCNT_7 : integer := 0;
+ ASRT_DELAY8 : integer := 0;
+ DSRT_DELAY8 : integer := 0;
+ ASRT_REMAP8 : integer := 8;
+ DSRT_REMAP8 : integer := 8;
+ DSRT_QUALCNT_8 : integer := 0;
+ ASRT_DELAY9 : integer := 0;
+ DSRT_DELAY9 : integer := 0;
+ ASRT_REMAP9 : integer := 9;
+ DSRT_REMAP9 : integer := 9;
+ DSRT_QUALCNT_9 : integer := 0
+ );
+ port (
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_write : in std_logic := 'X'; -- write
+ irq : out std_logic; -- irq
+ clk : in std_logic := 'X'; -- clk
+ csr_reset : in std_logic := 'X'; -- reset
+ reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ reset_in0 : in std_logic := 'X'; -- reset
+ reset_out0 : out std_logic; -- reset
+ reset_out1 : out std_logic; -- reset
+ reset_out2 : out std_logic; -- reset
+ reset_out3 : out std_logic; -- reset
+ reset_out4 : out std_logic; -- reset
+ reset_out5 : out std_logic; -- reset
+ reset_out6 : out std_logic; -- reset
+ reset_out7 : out std_logic -- reset
+ );
+ end component altjesd_ss_RX_reset_seq;
- u0 : component altjesd_ss_RX_reset_seq
- generic map (
- NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
- ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
- ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
- ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
- MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
- ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
- DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
- ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
- DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
- DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
- ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
- DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
- ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
- DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
- DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
- ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
- DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
- ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
- DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
- DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
- ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
- DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
- ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
- DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
- DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
- ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
- DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
- ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
- DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
- DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
- ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
- DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
- ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
- DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
- DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
- ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
- DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
- ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
- DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
- DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
- ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
- DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
- ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
- DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
- DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
- ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
- DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
- ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
- DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
- DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
- ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
- DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
- ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
- DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
- DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
- )
- port map (
- av_address => CONNECTED_TO_av_address, -- av_csr.address
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_read => CONNECTED_TO_av_read, -- .read
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_write => CONNECTED_TO_av_write, -- .write
- irq => CONNECTED_TO_irq, -- av_csr_irq.irq
- clk => CONNECTED_TO_clk, -- clk.clk
- csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
- reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
- reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
- reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
- reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
- reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
- reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
- reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
- reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
- reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
- reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
- reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
- reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
- );
+ u0 : component altjesd_ss_RX_reset_seq
+ generic map (
+ NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
+ ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
+ ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
+ ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
+ MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
+ ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
+ DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
+ ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
+ DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
+ DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
+ ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
+ DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
+ ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
+ DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
+ DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
+ ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
+ DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
+ ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
+ DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
+ DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
+ ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
+ DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
+ ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
+ DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
+ DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
+ ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
+ DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
+ ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
+ DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
+ DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
+ ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
+ DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
+ ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
+ DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
+ DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
+ ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
+ DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
+ ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
+ DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
+ DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
+ ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
+ DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
+ ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
+ DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
+ DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
+ ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
+ DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
+ ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
+ DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
+ DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
+ ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
+ DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
+ ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
+ DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
+ DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
+ )
+ port map (
+ av_address => CONNECTED_TO_av_address, -- av_csr.address
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_read => CONNECTED_TO_av_read, -- .read
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_write => CONNECTED_TO_av_write, -- .write
+ irq => CONNECTED_TO_irq, -- av_csr_irq.irq
+ clk => CONNECTED_TO_clk, -- clk.clk
+ csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
+ reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
+ reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
+ reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
+ reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
+ reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
+ reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
+ reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
+ reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
+ reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
+ reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
+ reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
+ reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index e49f93a337e01a20a39b99a717881d143e0d0970..b6d3bb0ce6607b0321184959d1f71178117f2f2d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,24 +1,24 @@
- component altjesd_ss_RX_xcvr_reset_control is
- port (
- clock : in std_logic := 'X'; -- clk
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
- );
- end component altjesd_ss_RX_xcvr_reset_control;
+ component altjesd_ss_RX_xcvr_reset_control is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
+ );
+ end component altjesd_ss_RX_xcvr_reset_control;
- u0 : component altjesd_ss_RX_xcvr_reset_control
- port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
- );
+ u0 : component altjesd_ss_RX_xcvr_reset_control
+ port map (
+ clock => CONNECTED_TO_clock, -- clock.clk
+ pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
+ reset => CONNECTED_TO_reset, -- reset.reset
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index af64e251092b8abe7083a94e7070e5407b77a322..bffa8692a2f502c59e6d94c0ccb1689bded5dfd2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,16 +1,16 @@
- component device_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component device_clk;
+ component device_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+ end component device_clk;
- u0 : component device_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ u0 : component device_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 26992b63a4edbecaa5e2a236b47a7c62d9e417d4..7514bc689dce666498f170d34e8de952a97dc3ff 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,16 +1,16 @@
- component frame_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component frame_clk;
+ component frame_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+ end component frame_clk;
- u0 : component frame_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ u0 : component frame_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 745dc1937c6fff32fda95a03e5bd47b88e8206b7..7798e03252582378dcf368ea5842eea9029d3bd9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,100 +1,100 @@
- component jesd is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component jesd;
+ component jesd is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+ end component jesd;
- u0 : component jesd
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+ u0 : component jesd
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index acbc33a2d1959920765b1866572b908d153acbc2..663d98ae67df528bdcb2143626722f2e2e96b0f4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,16 +1,16 @@
- component link_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component link_clk;
+ component link_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+ end component link_clk;
- u0 : component link_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ u0 : component link_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index 42aae3ddf073f5dfbfee338c2139ed38675a6a2a..b27913d51cba176742e7ee9bd382d3e9fcec3b29 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_0 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_0;
+ component qsys_unb2b_minimal_avs_common_mm_0 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_avs_common_mm_0;
- u0 : component qsys_unb2b_minimal_avs_common_mm_0
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_avs_common_mm_0
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index 4ddaf7fa7d6f6d85a966525b9dd908dbdae955a3..12174ecf49ee84a11fc47c86b50a537127c91bbf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_1 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_1;
+ component qsys_unb2b_minimal_avs_common_mm_1 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_avs_common_mm_1;
- u0 : component qsys_unb2b_minimal_avs_common_mm_1
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_avs_common_mm_1
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 06df7d37f4b4ceeb07d517f45c42b0cfa1cac3f2..2d7c8108d11a3175bcb7a3cfc62cf273e06ffc2f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,84 +1,84 @@
- component qsys_unb2b_minimal_avs_eth_0 is
- port (
- coe_clk_export : out std_logic; -- export
- ins_interrupt_irq : out std_logic; -- irq
- coe_irq_export : in std_logic := 'X'; -- export
- csi_mm_clk : in std_logic := 'X'; -- clk
- csi_mm_reset : in std_logic := 'X'; -- reset
- mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_ram_write : in std_logic := 'X'; -- write
- mms_ram_read : in std_logic := 'X'; -- read
- mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
- mms_reg_write : in std_logic := 'X'; -- write
- mms_reg_read : in std_logic := 'X'; -- read
- mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_tse_write : in std_logic := 'X'; -- write
- mms_tse_read : in std_logic := 'X'; -- read
- mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_waitrequest : out std_logic; -- waitrequest
- coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
- coe_ram_read_export : out std_logic; -- export
- coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_write_export : out std_logic; -- export
- coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
- coe_reg_read_export : out std_logic; -- export
- coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reg_write_export : out std_logic; -- export
- coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reset_export : out std_logic; -- export
- coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
- coe_tse_read_export : out std_logic; -- export
- coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_waitrequest_export : in std_logic := 'X'; -- export
- coe_tse_write_export : out std_logic; -- export
- coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_eth_0;
+ component qsys_unb2b_minimal_avs_eth_0 is
+ port (
+ coe_clk_export : out std_logic; -- export
+ ins_interrupt_irq : out std_logic; -- irq
+ coe_irq_export : in std_logic := 'X'; -- export
+ csi_mm_clk : in std_logic := 'X'; -- clk
+ csi_mm_reset : in std_logic := 'X'; -- reset
+ mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_ram_write : in std_logic := 'X'; -- write
+ mms_ram_read : in std_logic := 'X'; -- read
+ mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
+ mms_reg_write : in std_logic := 'X'; -- write
+ mms_reg_read : in std_logic := 'X'; -- read
+ mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_tse_write : in std_logic := 'X'; -- write
+ mms_tse_read : in std_logic := 'X'; -- read
+ mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_waitrequest : out std_logic; -- waitrequest
+ coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_ram_read_export : out std_logic; -- export
+ coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_write_export : out std_logic; -- export
+ coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ coe_reg_read_export : out std_logic; -- export
+ coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reg_write_export : out std_logic; -- export
+ coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export : out std_logic; -- export
+ coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_tse_read_export : out std_logic; -- export
+ coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_tse_waitrequest_export : in std_logic := 'X'; -- export
+ coe_tse_write_export : out std_logic; -- export
+ coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_avs_eth_0;
- u0 : component qsys_unb2b_minimal_avs_eth_0
- port map (
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
- coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
- csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
- csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
- mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
- mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
- mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
- mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
- mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
- mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
- mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
- mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
- mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
- mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
- mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
- mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
- mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
- mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
- mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
- mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
- coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
- coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
- coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
- coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
- coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
- coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
- coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
- coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
- coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
- coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
- coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
- coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
- coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
- coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
- coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
- );
+ u0 : component qsys_unb2b_minimal_avs_eth_0
+ port map (
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
+ coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
+ csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
+ csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
+ mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
+ mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
+ mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
+ mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
+ mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
+ mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
+ mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
+ mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
+ mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
+ mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
+ mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
+ mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
+ mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
+ mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
+ mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
+ mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
+ coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
+ coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
+ coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
+ coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
+ coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
+ coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
+ coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
+ coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
+ coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
+ coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
+ coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
+ coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
+ coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
+ coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
+ coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index fafd41bbfa80eae91afc0da3d18e2f4b799f6a95..b717623c7cc1c3984c781cc836d9bc13c93bebea 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,16 +1,16 @@
- component qsys_unb2b_minimal_clk_0 is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component qsys_unb2b_minimal_clk_0;
+ component qsys_unb2b_minimal_clk_0 is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+ end component qsys_unb2b_minimal_clk_0;
- u0 : component qsys_unb2b_minimal_clk_0
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ u0 : component qsys_unb2b_minimal_clk_0
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 38fce9676fd1136ba002d70216e0ae804269cd9f..4b049df7a095757aba476bf10632411ebc1e23bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,60 +1,60 @@
- component qsys_unb2b_minimal_cpu_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(19 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
- );
- end component qsys_unb2b_minimal_cpu_0;
+ component qsys_unb2b_minimal_cpu_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ dummy_ci_port : out std_logic; -- readra
+ d_address : out std_logic_vector(19 downto 0); -- address
+ d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ d_read : out std_logic; -- read
+ d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ d_waitrequest : in std_logic := 'X'; -- waitrequest
+ d_write : out std_logic; -- write
+ d_writedata : out std_logic_vector(31 downto 0); -- writedata
+ debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
+ debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
+ debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
+ debug_mem_slave_read : in std_logic := 'X'; -- read
+ debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
+ debug_mem_slave_waitrequest : out std_logic; -- waitrequest
+ debug_mem_slave_write : in std_logic := 'X'; -- write
+ debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ debug_reset_request : out std_logic; -- reset
+ i_address : out std_logic_vector(17 downto 0); -- address
+ i_read : out std_logic; -- read
+ i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ i_waitrequest : in std_logic := 'X'; -- waitrequest
+ irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_req : in std_logic := 'X' -- reset_req
+ );
+ end component qsys_unb2b_minimal_cpu_0;
- u0 : component qsys_unb2b_minimal_cpu_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
- d_address => CONNECTED_TO_d_address, -- data_master.address
- d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
- d_read => CONNECTED_TO_d_read, -- .read
- d_readdata => CONNECTED_TO_d_readdata, -- .readdata
- d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
- d_write => CONNECTED_TO_d_write, -- .write
- d_writedata => CONNECTED_TO_d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
- debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
- i_address => CONNECTED_TO_i_address, -- instruction_master.address
- i_read => CONNECTED_TO_i_read, -- .read
- i_readdata => CONNECTED_TO_i_readdata, -- .readdata
- i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- reset_req => CONNECTED_TO_reset_req -- .reset_req
- );
+ u0 : component qsys_unb2b_minimal_cpu_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
+ d_address => CONNECTED_TO_d_address, -- data_master.address
+ d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
+ d_read => CONNECTED_TO_d_read, -- .read
+ d_readdata => CONNECTED_TO_d_readdata, -- .readdata
+ d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
+ d_write => CONNECTED_TO_d_write, -- .write
+ d_writedata => CONNECTED_TO_d_writedata, -- .writedata
+ debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
+ debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
+ debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
+ debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
+ debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
+ debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
+ debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
+ debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
+ debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
+ debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
+ i_address => CONNECTED_TO_i_address, -- instruction_master.address
+ i_read => CONNECTED_TO_i_read, -- .read
+ i_readdata => CONNECTED_TO_i_readdata, -- .readdata
+ i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ reset_req => CONNECTED_TO_reset_req -- .reset_req
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c76f427acbe4d282fd1db94d2af4ffdce37d9027..f1383bb2be99d5fbcfdb238fc6d9168d81663e8d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,100 +1,100 @@
- component qsys_unb2b_minimal_jesd204 is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component qsys_unb2b_minimal_jesd204;
+ component qsys_unb2b_minimal_jesd204 is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+ end component qsys_unb2b_minimal_jesd204;
- u0 : component qsys_unb2b_minimal_jesd204
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+ u0 : component qsys_unb2b_minimal_jesd204
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index bc11c57e416cd6de852d448d82730d0e93d92791..3567f678e64f9732e4715dd34785b34131be83a2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_jtag_uart_0 is
- port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
- );
- end component qsys_unb2b_minimal_jtag_uart_0;
+ component qsys_unb2b_minimal_jtag_uart_0 is
+ port (
+ av_chipselect : in std_logic := 'X'; -- chipselect
+ av_address : in std_logic := 'X'; -- address
+ av_read_n : in std_logic := 'X'; -- read_n
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_write_n : in std_logic := 'X'; -- write_n
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_waitrequest : out std_logic; -- waitrequest
+ clk : in std_logic := 'X'; -- clk
+ av_irq : out std_logic; -- irq
+ rst_n : in std_logic := 'X' -- reset_n
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0;
- u0 : component qsys_unb2b_minimal_jtag_uart_0
- port map (
- av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => CONNECTED_TO_av_address, -- .address
- av_read_n => CONNECTED_TO_av_read_n, -- .read_n
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_write_n => CONNECTED_TO_av_write_n, -- .write_n
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
- clk => CONNECTED_TO_clk, -- clk.clk
- av_irq => CONNECTED_TO_av_irq, -- irq.irq
- rst_n => CONNECTED_TO_rst_n -- reset.reset_n
- );
+ u0 : component qsys_unb2b_minimal_jtag_uart_0
+ port map (
+ av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
+ av_address => CONNECTED_TO_av_address, -- .address
+ av_read_n => CONNECTED_TO_av_read_n, -- .read_n
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_write_n => CONNECTED_TO_av_write_n, -- .write_n
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
+ clk => CONNECTED_TO_clk, -- clk.clk
+ av_irq => CONNECTED_TO_av_irq, -- irq.irq
+ rst_n => CONNECTED_TO_rst_n -- reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index f453120efc4f037dc4efbc07b42a93186450fe1d..0d06cbc9cae02b57e8a7ff4817a0c6df89c5acd0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_onchip_memory2_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
- );
- end component qsys_unb2b_minimal_onchip_memory2_0;
+ component qsys_unb2b_minimal_onchip_memory2_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ reset_req : in std_logic := 'X'; -- reset_req
+ address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
+ clken : in std_logic := 'X'; -- clken
+ chipselect : in std_logic := 'X'; -- chipselect
+ write : in std_logic := 'X'; -- write
+ readdata : out std_logic_vector(31 downto 0); -- readdata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
+ );
+ end component qsys_unb2b_minimal_onchip_memory2_0;
- u0 : component qsys_unb2b_minimal_onchip_memory2_0
- port map (
- clk => CONNECTED_TO_clk, -- clk1.clk
- reset => CONNECTED_TO_reset, -- reset1.reset
- reset_req => CONNECTED_TO_reset_req, -- .reset_req
- address => CONNECTED_TO_address, -- s1.address
- clken => CONNECTED_TO_clken, -- .clken
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write => CONNECTED_TO_write, -- .write
- readdata => CONNECTED_TO_readdata, -- .readdata
- writedata => CONNECTED_TO_writedata, -- .writedata
- byteenable => CONNECTED_TO_byteenable -- .byteenable
- );
+ u0 : component qsys_unb2b_minimal_onchip_memory2_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk1.clk
+ reset => CONNECTED_TO_reset, -- reset1.reset
+ reset_req => CONNECTED_TO_reset_req, -- .reset_req
+ address => CONNECTED_TO_address, -- s1.address
+ clken => CONNECTED_TO_clken, -- .clken
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write => CONNECTED_TO_write, -- .write
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ byteenable => CONNECTED_TO_byteenable -- .byteenable
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 580187433d6ad3516adc8f3613297cd106f122a7..04740d0db75fc3b705ba549ac5fde6008f898c8c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_pps is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_pps;
+ component qsys_unb2b_minimal_pio_pps is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_pio_pps;
- u0 : component qsys_unb2b_minimal_pio_pps
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_pio_pps
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index b05a01d44469adf2ce2a5524f755a45e93ee3b55..871bc6d3263e6e4d8feb155f6f304fc8a80a3af5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_system_info;
+ component qsys_unb2b_minimal_pio_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_pio_system_info;
- u0 : component qsys_unb2b_minimal_pio_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_pio_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 4639e141f52b87b436009b6f01944420186ed973..9f0f3e87a85a8b699eec8f520148c81fc6bb8e63 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_pio_wdi is
- port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
- );
- end component qsys_unb2b_minimal_pio_wdi;
+ component qsys_unb2b_minimal_pio_wdi is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ out_port : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ write_n : in std_logic := 'X'; -- write_n
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ chipselect : in std_logic := 'X'; -- chipselect
+ readdata : out std_logic_vector(31 downto 0) -- readdata
+ );
+ end component qsys_unb2b_minimal_pio_wdi;
- u0 : component qsys_unb2b_minimal_pio_wdi
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- out_port => CONNECTED_TO_out_port, -- external_connection.export
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- write_n => CONNECTED_TO_write_n, -- .write_n
- writedata => CONNECTED_TO_writedata, -- .writedata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- readdata => CONNECTED_TO_readdata -- .readdata
- );
+ u0 : component qsys_unb2b_minimal_pio_wdi
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ out_port => CONNECTED_TO_out_port, -- external_connection.export
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ write_n => CONNECTED_TO_write_n, -- .write_n
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ readdata => CONNECTED_TO_readdata -- .readdata
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index ec324643910e8ec28eea3841bf69396535f66ce8..a64854d5352fc652203949432c5b9f0f33131046 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_ctrl;
+ component qsys_unb2b_minimal_reg_dpmm_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_dpmm_ctrl;
- u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 902a48132b9b35e040acf2ea2bdc5803e567864e..06282c4a21f00a3201b0691428c71902a4464b28 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_data;
+ component qsys_unb2b_minimal_reg_dpmm_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_dpmm_data;
- u0 : component qsys_unb2b_minimal_reg_dpmm_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_dpmm_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index b7e771b662f1b2279fb0a2605ad86648a3821987..497d0469c292994e6de0e909ea0d0921fdf05a42 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_epcs is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_epcs;
+ component qsys_unb2b_minimal_reg_epcs is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_epcs;
- u0 : component qsys_unb2b_minimal_reg_epcs
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_epcs
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 170f85ed587a093a331bd7da8153feb63a78358e..b6735293936fec25bc7bf9127d59b0ad3d07ecce 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_temp_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_temp_sens;
+ component qsys_unb2b_minimal_reg_fpga_temp_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_fpga_temp_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 495dae0b21c808c2f09bc98a269f98a22332116b..43d217b96822d4ba769c181b52c1cf53b50fc68e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_voltage_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
+ component qsys_unb2b_minimal_reg_fpga_voltage_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index e099a81cd1f19acfb178d8108c3a40c275935b38..25fd2f1508fd4b47c24182576fb0807704107fc0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_ctrl;
+ component qsys_unb2b_minimal_reg_mmdp_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_mmdp_ctrl;
- u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index d25eb92a9c789a0a393083008b9dd982889f184e..8a41c8392d54030f95da390e61418de2c67b90c8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_data;
+ component qsys_unb2b_minimal_reg_mmdp_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_mmdp_data;
- u0 : component qsys_unb2b_minimal_reg_mmdp_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_mmdp_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 837cb45819d6d993ab0e2ec2cd835b1f69bd1365..74cabd7563f8877d842ff92522d2d0aa2f53c952 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_remu is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_remu;
+ component qsys_unb2b_minimal_reg_remu is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_remu;
- u0 : component qsys_unb2b_minimal_reg_remu
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_remu
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index b97ef222ecfeac9b9cdc0609f289add83696334d..c0dc7de22245a6bd61f6476ca3b5c298c6e524c3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_pmbus is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_pmbus;
+ component qsys_unb2b_minimal_reg_unb_pmbus is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_unb_pmbus;
- u0 : component qsys_unb2b_minimal_reg_unb_pmbus
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_unb_pmbus
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index 1871be2f741a5f58a41c9f333411b3b210fec9e6..22effc2f2409107eda24580155339ceecde4cecb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_sens;
+ component qsys_unb2b_minimal_reg_unb_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_unb_sens;
- u0 : component qsys_unb2b_minimal_reg_unb_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_unb_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 229a2d315e14744572cd30efdc1e44a03cb55744..039ee2a813502fae87e99b929262dda1203cdcf3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_wdi is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_wdi;
+ component qsys_unb2b_minimal_reg_wdi is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_wdi;
- u0 : component qsys_unb2b_minimal_reg_wdi
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_wdi
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index ae35f2bd1988023e11957c39257a521354f840f8..21cd10c8b208554725ed607a34187388b7dd1e13 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_rom_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_rom_system_info;
+ component qsys_unb2b_minimal_rom_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_rom_system_info;
- u0 : component qsys_unb2b_minimal_rom_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_rom_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index ff04a90d2be254067a63715a1ab244263a405a8f..b56940d1e977f236b500a9831b59df657403a2aa 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node0/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_timer_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
- );
- end component qsys_unb2b_minimal_timer_0;
+ component qsys_unb2b_minimal_timer_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ irq : out std_logic; -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
+ writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
+ readdata : out std_logic_vector(15 downto 0); -- readdata
+ chipselect : in std_logic := 'X'; -- chipselect
+ write_n : in std_logic := 'X' -- write_n
+ );
+ end component qsys_unb2b_minimal_timer_0;
- u0 : component qsys_unb2b_minimal_timer_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- writedata => CONNECTED_TO_writedata, -- .writedata
- readdata => CONNECTED_TO_readdata, -- .readdata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write_n => CONNECTED_TO_write_n -- .write_n
- );
+ u0 : component qsys_unb2b_minimal_timer_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write_n => CONNECTED_TO_write_n -- .write_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
index 1188b1f4a3a8c3bda14f3b6fb3aaf6912e8d9d4f..63b9a4eac3f8c5286e4c22e7c5d6ba61ad1ca40f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_corepll/altjesd_ss_RX_corepll_inst.vhd
@@ -1,18 +1,18 @@
- component altjesd_ss_RX_corepll is
- port (
- locked : out std_logic; -- export
- outclk_0 : out std_logic; -- clk
- outclk_1 : out std_logic; -- clk
- refclk : in std_logic := 'X'; -- clk
- rst : in std_logic := 'X' -- reset
- );
- end component altjesd_ss_RX_corepll;
+ component altjesd_ss_RX_corepll is
+ port (
+ locked : out std_logic; -- export
+ outclk_0 : out std_logic; -- clk
+ outclk_1 : out std_logic; -- clk
+ refclk : in std_logic := 'X'; -- clk
+ rst : in std_logic := 'X' -- reset
+ );
+ end component altjesd_ss_RX_corepll;
- u0 : component altjesd_ss_RX_corepll
- port map (
- locked => CONNECTED_TO_locked, -- locked.export
- outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
- outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
- refclk => CONNECTED_TO_refclk, -- refclk.clk
- rst => CONNECTED_TO_rst -- reset.reset
- );
+ u0 : component altjesd_ss_RX_corepll
+ port map (
+ locked => CONNECTED_TO_locked, -- locked.export
+ outclk_0 => CONNECTED_TO_outclk_0, -- outclk0.clk
+ outclk_1 => CONNECTED_TO_outclk_1, -- outclk1.clk
+ refclk => CONNECTED_TO_refclk, -- refclk.clk
+ rst => CONNECTED_TO_rst -- reset.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
index 4d125d7d6b09eb801f54521d54896e4cd0d3f452..151469f9ea5ad6202d813b7837e88cd36ec84839 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_frame_reset/altjesd_ss_RX_frame_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_frame_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_frame_reset;
+ component altjesd_ss_RX_frame_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+ end component altjesd_ss_RX_frame_reset;
- u0 : component altjesd_ss_RX_frame_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+ u0 : component altjesd_ss_RX_frame_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
index 2fdfadb51af42decdc595af06f6653c82f64f67b..a2d2bd6b6e8367d16a7033b23352468912e69240 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_link_reset/altjesd_ss_RX_link_reset_inst.vhd
@@ -1,14 +1,14 @@
- component altjesd_ss_RX_link_reset is
- port (
- clk : in std_logic := 'X'; -- clk
- in_reset_n : in std_logic := 'X'; -- reset_n
- out_reset_n : out std_logic -- reset_n
- );
- end component altjesd_ss_RX_link_reset;
+ component altjesd_ss_RX_link_reset is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ in_reset_n : in std_logic := 'X'; -- reset_n
+ out_reset_n : out std_logic -- reset_n
+ );
+ end component altjesd_ss_RX_link_reset;
- u0 : component altjesd_ss_RX_link_reset
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
- out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
- );
+ u0 : component altjesd_ss_RX_link_reset
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ in_reset_n => CONNECTED_TO_in_reset_n, -- in_reset.reset_n
+ out_reset_n => CONNECTED_TO_out_reset_n -- out_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
index f5e2ba1f77a9a3ef8e6ec47a9929ad820950c0a3..55a61ea70d8b1e675806ba2799f926c728f4f61d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_reset_seq/altjesd_ss_RX_reset_seq_inst.vhd
@@ -1,162 +1,162 @@
- component altjesd_ss_RX_reset_seq is
- generic (
- NUM_OUTPUTS : integer := 3;
- ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
- ENABLE_ASSERTION_SEQUENCE : integer := 0;
- ENABLE_DEASSERTION_SEQUENCE : integer := 0;
- MIN_ASRT_TIME : integer := 0;
- ASRT_DELAY0 : integer := 0;
- DSRT_DELAY0 : integer := 0;
- ASRT_REMAP0 : integer := 0;
- DSRT_REMAP0 : integer := 0;
- DSRT_QUALCNT_0 : integer := 0;
- ASRT_DELAY1 : integer := 0;
- DSRT_DELAY1 : integer := 0;
- ASRT_REMAP1 : integer := 1;
- DSRT_REMAP1 : integer := 1;
- DSRT_QUALCNT_1 : integer := 0;
- ASRT_DELAY2 : integer := 0;
- DSRT_DELAY2 : integer := 0;
- ASRT_REMAP2 : integer := 2;
- DSRT_REMAP2 : integer := 2;
- DSRT_QUALCNT_2 : integer := 0;
- ASRT_DELAY3 : integer := 0;
- DSRT_DELAY3 : integer := 0;
- ASRT_REMAP3 : integer := 3;
- DSRT_REMAP3 : integer := 3;
- DSRT_QUALCNT_3 : integer := 0;
- ASRT_DELAY4 : integer := 0;
- DSRT_DELAY4 : integer := 0;
- ASRT_REMAP4 : integer := 4;
- DSRT_REMAP4 : integer := 4;
- DSRT_QUALCNT_4 : integer := 0;
- ASRT_DELAY5 : integer := 0;
- DSRT_DELAY5 : integer := 0;
- ASRT_REMAP5 : integer := 5;
- DSRT_REMAP5 : integer := 5;
- DSRT_QUALCNT_5 : integer := 0;
- ASRT_DELAY6 : integer := 0;
- DSRT_DELAY6 : integer := 0;
- ASRT_REMAP6 : integer := 6;
- DSRT_REMAP6 : integer := 6;
- DSRT_QUALCNT_6 : integer := 0;
- ASRT_DELAY7 : integer := 0;
- DSRT_DELAY7 : integer := 0;
- ASRT_REMAP7 : integer := 7;
- DSRT_REMAP7 : integer := 7;
- DSRT_QUALCNT_7 : integer := 0;
- ASRT_DELAY8 : integer := 0;
- DSRT_DELAY8 : integer := 0;
- ASRT_REMAP8 : integer := 8;
- DSRT_REMAP8 : integer := 8;
- DSRT_QUALCNT_8 : integer := 0;
- ASRT_DELAY9 : integer := 0;
- DSRT_DELAY9 : integer := 0;
- ASRT_REMAP9 : integer := 9;
- DSRT_REMAP9 : integer := 9;
- DSRT_QUALCNT_9 : integer := 0
- );
- port (
- av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_read : in std_logic := 'X'; -- read
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_write : in std_logic := 'X'; -- write
- irq : out std_logic; -- irq
- clk : in std_logic := 'X'; -- clk
- csr_reset : in std_logic := 'X'; -- reset
- reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
- reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
- reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
- reset_in0 : in std_logic := 'X'; -- reset
- reset_out0 : out std_logic; -- reset
- reset_out1 : out std_logic; -- reset
- reset_out2 : out std_logic; -- reset
- reset_out3 : out std_logic; -- reset
- reset_out4 : out std_logic; -- reset
- reset_out5 : out std_logic; -- reset
- reset_out6 : out std_logic; -- reset
- reset_out7 : out std_logic -- reset
- );
- end component altjesd_ss_RX_reset_seq;
+ component altjesd_ss_RX_reset_seq is
+ generic (
+ NUM_OUTPUTS : integer := 3;
+ ENABLE_DEASSERTION_INPUT_QUAL : integer := 0;
+ ENABLE_ASSERTION_SEQUENCE : integer := 0;
+ ENABLE_DEASSERTION_SEQUENCE : integer := 0;
+ MIN_ASRT_TIME : integer := 0;
+ ASRT_DELAY0 : integer := 0;
+ DSRT_DELAY0 : integer := 0;
+ ASRT_REMAP0 : integer := 0;
+ DSRT_REMAP0 : integer := 0;
+ DSRT_QUALCNT_0 : integer := 0;
+ ASRT_DELAY1 : integer := 0;
+ DSRT_DELAY1 : integer := 0;
+ ASRT_REMAP1 : integer := 1;
+ DSRT_REMAP1 : integer := 1;
+ DSRT_QUALCNT_1 : integer := 0;
+ ASRT_DELAY2 : integer := 0;
+ DSRT_DELAY2 : integer := 0;
+ ASRT_REMAP2 : integer := 2;
+ DSRT_REMAP2 : integer := 2;
+ DSRT_QUALCNT_2 : integer := 0;
+ ASRT_DELAY3 : integer := 0;
+ DSRT_DELAY3 : integer := 0;
+ ASRT_REMAP3 : integer := 3;
+ DSRT_REMAP3 : integer := 3;
+ DSRT_QUALCNT_3 : integer := 0;
+ ASRT_DELAY4 : integer := 0;
+ DSRT_DELAY4 : integer := 0;
+ ASRT_REMAP4 : integer := 4;
+ DSRT_REMAP4 : integer := 4;
+ DSRT_QUALCNT_4 : integer := 0;
+ ASRT_DELAY5 : integer := 0;
+ DSRT_DELAY5 : integer := 0;
+ ASRT_REMAP5 : integer := 5;
+ DSRT_REMAP5 : integer := 5;
+ DSRT_QUALCNT_5 : integer := 0;
+ ASRT_DELAY6 : integer := 0;
+ DSRT_DELAY6 : integer := 0;
+ ASRT_REMAP6 : integer := 6;
+ DSRT_REMAP6 : integer := 6;
+ DSRT_QUALCNT_6 : integer := 0;
+ ASRT_DELAY7 : integer := 0;
+ DSRT_DELAY7 : integer := 0;
+ ASRT_REMAP7 : integer := 7;
+ DSRT_REMAP7 : integer := 7;
+ DSRT_QUALCNT_7 : integer := 0;
+ ASRT_DELAY8 : integer := 0;
+ DSRT_DELAY8 : integer := 0;
+ ASRT_REMAP8 : integer := 8;
+ DSRT_REMAP8 : integer := 8;
+ DSRT_QUALCNT_8 : integer := 0;
+ ASRT_DELAY9 : integer := 0;
+ DSRT_DELAY9 : integer := 0;
+ ASRT_REMAP9 : integer := 9;
+ DSRT_REMAP9 : integer := 9;
+ DSRT_QUALCNT_9 : integer := 0
+ );
+ port (
+ av_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_read : in std_logic := 'X'; -- read
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_write : in std_logic := 'X'; -- write
+ irq : out std_logic; -- irq
+ clk : in std_logic := 'X'; -- clk
+ csr_reset : in std_logic := 'X'; -- reset
+ reset1_dsrt_qual : in std_logic := 'X'; -- reset1_dsrt_qual
+ reset2_dsrt_qual : in std_logic := 'X'; -- reset2_dsrt_qual
+ reset5_dsrt_qual : in std_logic := 'X'; -- reset5_dsrt_qual
+ reset_in0 : in std_logic := 'X'; -- reset
+ reset_out0 : out std_logic; -- reset
+ reset_out1 : out std_logic; -- reset
+ reset_out2 : out std_logic; -- reset
+ reset_out3 : out std_logic; -- reset
+ reset_out4 : out std_logic; -- reset
+ reset_out5 : out std_logic; -- reset
+ reset_out6 : out std_logic; -- reset
+ reset_out7 : out std_logic -- reset
+ );
+ end component altjesd_ss_RX_reset_seq;
- u0 : component altjesd_ss_RX_reset_seq
- generic map (
- NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
- ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
- ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
- ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
- MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
- ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
- DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
- ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
- DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
- DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
- ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
- DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
- ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
- DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
- DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
- ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
- DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
- ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
- DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
- DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
- ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
- DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
- ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
- DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
- DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
- ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
- DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
- ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
- DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
- DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
- ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
- DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
- ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
- DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
- DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
- ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
- DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
- ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
- DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
- DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
- ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
- DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
- ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
- DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
- DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
- ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
- DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
- ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
- DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
- DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
- ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
- DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
- ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
- DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
- DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
- )
- port map (
- av_address => CONNECTED_TO_av_address, -- av_csr.address
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_read => CONNECTED_TO_av_read, -- .read
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_write => CONNECTED_TO_av_write, -- .write
- irq => CONNECTED_TO_irq, -- av_csr_irq.irq
- clk => CONNECTED_TO_clk, -- clk.clk
- csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
- reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
- reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
- reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
- reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
- reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
- reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
- reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
- reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
- reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
- reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
- reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
- reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
- );
+ u0 : component altjesd_ss_RX_reset_seq
+ generic map (
+ NUM_OUTPUTS => INTEGER_VALUE_FOR_NUM_OUTPUTS,
+ ENABLE_DEASSERTION_INPUT_QUAL => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_INPUT_QUAL,
+ ENABLE_ASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_ASSERTION_SEQUENCE,
+ ENABLE_DEASSERTION_SEQUENCE => INTEGER_VALUE_FOR_ENABLE_DEASSERTION_SEQUENCE,
+ MIN_ASRT_TIME => INTEGER_VALUE_FOR_MIN_ASRT_TIME,
+ ASRT_DELAY0 => INTEGER_VALUE_FOR_ASRT_DELAY0,
+ DSRT_DELAY0 => INTEGER_VALUE_FOR_DSRT_DELAY0,
+ ASRT_REMAP0 => INTEGER_VALUE_FOR_ASRT_REMAP0,
+ DSRT_REMAP0 => INTEGER_VALUE_FOR_DSRT_REMAP0,
+ DSRT_QUALCNT_0 => INTEGER_VALUE_FOR_DSRT_QUALCNT_0,
+ ASRT_DELAY1 => INTEGER_VALUE_FOR_ASRT_DELAY1,
+ DSRT_DELAY1 => INTEGER_VALUE_FOR_DSRT_DELAY1,
+ ASRT_REMAP1 => INTEGER_VALUE_FOR_ASRT_REMAP1,
+ DSRT_REMAP1 => INTEGER_VALUE_FOR_DSRT_REMAP1,
+ DSRT_QUALCNT_1 => INTEGER_VALUE_FOR_DSRT_QUALCNT_1,
+ ASRT_DELAY2 => INTEGER_VALUE_FOR_ASRT_DELAY2,
+ DSRT_DELAY2 => INTEGER_VALUE_FOR_DSRT_DELAY2,
+ ASRT_REMAP2 => INTEGER_VALUE_FOR_ASRT_REMAP2,
+ DSRT_REMAP2 => INTEGER_VALUE_FOR_DSRT_REMAP2,
+ DSRT_QUALCNT_2 => INTEGER_VALUE_FOR_DSRT_QUALCNT_2,
+ ASRT_DELAY3 => INTEGER_VALUE_FOR_ASRT_DELAY3,
+ DSRT_DELAY3 => INTEGER_VALUE_FOR_DSRT_DELAY3,
+ ASRT_REMAP3 => INTEGER_VALUE_FOR_ASRT_REMAP3,
+ DSRT_REMAP3 => INTEGER_VALUE_FOR_DSRT_REMAP3,
+ DSRT_QUALCNT_3 => INTEGER_VALUE_FOR_DSRT_QUALCNT_3,
+ ASRT_DELAY4 => INTEGER_VALUE_FOR_ASRT_DELAY4,
+ DSRT_DELAY4 => INTEGER_VALUE_FOR_DSRT_DELAY4,
+ ASRT_REMAP4 => INTEGER_VALUE_FOR_ASRT_REMAP4,
+ DSRT_REMAP4 => INTEGER_VALUE_FOR_DSRT_REMAP4,
+ DSRT_QUALCNT_4 => INTEGER_VALUE_FOR_DSRT_QUALCNT_4,
+ ASRT_DELAY5 => INTEGER_VALUE_FOR_ASRT_DELAY5,
+ DSRT_DELAY5 => INTEGER_VALUE_FOR_DSRT_DELAY5,
+ ASRT_REMAP5 => INTEGER_VALUE_FOR_ASRT_REMAP5,
+ DSRT_REMAP5 => INTEGER_VALUE_FOR_DSRT_REMAP5,
+ DSRT_QUALCNT_5 => INTEGER_VALUE_FOR_DSRT_QUALCNT_5,
+ ASRT_DELAY6 => INTEGER_VALUE_FOR_ASRT_DELAY6,
+ DSRT_DELAY6 => INTEGER_VALUE_FOR_DSRT_DELAY6,
+ ASRT_REMAP6 => INTEGER_VALUE_FOR_ASRT_REMAP6,
+ DSRT_REMAP6 => INTEGER_VALUE_FOR_DSRT_REMAP6,
+ DSRT_QUALCNT_6 => INTEGER_VALUE_FOR_DSRT_QUALCNT_6,
+ ASRT_DELAY7 => INTEGER_VALUE_FOR_ASRT_DELAY7,
+ DSRT_DELAY7 => INTEGER_VALUE_FOR_DSRT_DELAY7,
+ ASRT_REMAP7 => INTEGER_VALUE_FOR_ASRT_REMAP7,
+ DSRT_REMAP7 => INTEGER_VALUE_FOR_DSRT_REMAP7,
+ DSRT_QUALCNT_7 => INTEGER_VALUE_FOR_DSRT_QUALCNT_7,
+ ASRT_DELAY8 => INTEGER_VALUE_FOR_ASRT_DELAY8,
+ DSRT_DELAY8 => INTEGER_VALUE_FOR_DSRT_DELAY8,
+ ASRT_REMAP8 => INTEGER_VALUE_FOR_ASRT_REMAP8,
+ DSRT_REMAP8 => INTEGER_VALUE_FOR_DSRT_REMAP8,
+ DSRT_QUALCNT_8 => INTEGER_VALUE_FOR_DSRT_QUALCNT_8,
+ ASRT_DELAY9 => INTEGER_VALUE_FOR_ASRT_DELAY9,
+ DSRT_DELAY9 => INTEGER_VALUE_FOR_DSRT_DELAY9,
+ ASRT_REMAP9 => INTEGER_VALUE_FOR_ASRT_REMAP9,
+ DSRT_REMAP9 => INTEGER_VALUE_FOR_DSRT_REMAP9,
+ DSRT_QUALCNT_9 => INTEGER_VALUE_FOR_DSRT_QUALCNT_9
+ )
+ port map (
+ av_address => CONNECTED_TO_av_address, -- av_csr.address
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_read => CONNECTED_TO_av_read, -- .read
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_write => CONNECTED_TO_av_write, -- .write
+ irq => CONNECTED_TO_irq, -- av_csr_irq.irq
+ clk => CONNECTED_TO_clk, -- clk.clk
+ csr_reset => CONNECTED_TO_csr_reset, -- csr_reset.reset
+ reset1_dsrt_qual => CONNECTED_TO_reset1_dsrt_qual, -- reset1_dsrt_qual.reset1_dsrt_qual
+ reset2_dsrt_qual => CONNECTED_TO_reset2_dsrt_qual, -- reset2_dsrt_qual.reset2_dsrt_qual
+ reset5_dsrt_qual => CONNECTED_TO_reset5_dsrt_qual, -- reset5_dsrt_qual.reset5_dsrt_qual
+ reset_in0 => CONNECTED_TO_reset_in0, -- reset_in0.reset
+ reset_out0 => CONNECTED_TO_reset_out0, -- reset_out0.reset
+ reset_out1 => CONNECTED_TO_reset_out1, -- reset_out1.reset
+ reset_out2 => CONNECTED_TO_reset_out2, -- reset_out2.reset
+ reset_out3 => CONNECTED_TO_reset_out3, -- reset_out3.reset
+ reset_out4 => CONNECTED_TO_reset_out4, -- reset_out4.reset
+ reset_out5 => CONNECTED_TO_reset_out5, -- reset_out5.reset
+ reset_out6 => CONNECTED_TO_reset_out6, -- reset_out6.reset
+ reset_out7 => CONNECTED_TO_reset_out7 -- reset_out7.reset
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
index e49f93a337e01a20a39b99a717881d143e0d0970..b6d3bb0ce6607b0321184959d1f71178117f2f2d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/altjesd_ss_RX_xcvr_reset_control/altjesd_ss_RX_xcvr_reset_control_inst.vhd
@@ -1,24 +1,24 @@
- component altjesd_ss_RX_xcvr_reset_control is
- port (
- clock : in std_logic := 'X'; -- clk
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
- );
- end component altjesd_ss_RX_xcvr_reset_control;
+ component altjesd_ss_RX_xcvr_reset_control is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(0 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(0 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(0 downto 0) -- rx_ready
+ );
+ end component altjesd_ss_RX_xcvr_reset_control;
- u0 : component altjesd_ss_RX_xcvr_reset_control
- port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
- );
+ u0 : component altjesd_ss_RX_xcvr_reset_control
+ port map (
+ clock => CONNECTED_TO_clock, -- clock.clk
+ pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
+ reset => CONNECTED_TO_reset, -- reset.reset
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => CONNECTED_TO_rx_ready -- rx_ready.rx_ready
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
index af64e251092b8abe7083a94e7070e5407b77a322..bffa8692a2f502c59e6d94c0ccb1689bded5dfd2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/device_clk/device_clk_inst.vhd
@@ -1,16 +1,16 @@
- component device_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component device_clk;
+ component device_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+ end component device_clk;
- u0 : component device_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ u0 : component device_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
index 26992b63a4edbecaa5e2a236b47a7c62d9e417d4..7514bc689dce666498f170d34e8de952a97dc3ff 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/frame_clk/frame_clk_inst.vhd
@@ -1,16 +1,16 @@
- component frame_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component frame_clk;
+ component frame_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+ end component frame_clk;
- u0 : component frame_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ u0 : component frame_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
index 745dc1937c6fff32fda95a03e5bd47b88e8206b7..7798e03252582378dcf368ea5842eea9029d3bd9 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/jesd/jesd_inst.vhd
@@ -1,100 +1,100 @@
- component jesd is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component jesd;
+ component jesd is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+ end component jesd;
- u0 : component jesd
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+ u0 : component jesd
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
index acbc33a2d1959920765b1866572b908d153acbc2..663d98ae67df528bdcb2143626722f2e2e96b0f4 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/link_clk/link_clk_inst.vhd
@@ -1,16 +1,16 @@
- component link_clk is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component link_clk;
+ component link_clk is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+ end component link_clk;
- u0 : component link_clk
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ u0 : component link_clk
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
index 42aae3ddf073f5dfbfee338c2139ed38675a6a2a..b27913d51cba176742e7ee9bd382d3e9fcec3b29 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_0/qsys_unb2b_minimal_avs_common_mm_0_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_0 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_0;
+ component qsys_unb2b_minimal_avs_common_mm_0 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_avs_common_mm_0;
- u0 : component qsys_unb2b_minimal_avs_common_mm_0
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_avs_common_mm_0
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
index 4ddaf7fa7d6f6d85a966525b9dd908dbdae955a3..12174ecf49ee84a11fc47c86b50a537127c91bbf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_common_mm_1/qsys_unb2b_minimal_avs_common_mm_1_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_avs_common_mm_1 is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_common_mm_1;
+ component qsys_unb2b_minimal_avs_common_mm_1 is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_avs_common_mm_1;
- u0 : component qsys_unb2b_minimal_avs_common_mm_1
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_avs_common_mm_1
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
index 06df7d37f4b4ceeb07d517f45c42b0cfa1cac3f2..2d7c8108d11a3175bcb7a3cfc62cf273e06ffc2f 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_avs_eth_0/qsys_unb2b_minimal_avs_eth_0_inst.vhd
@@ -1,84 +1,84 @@
- component qsys_unb2b_minimal_avs_eth_0 is
- port (
- coe_clk_export : out std_logic; -- export
- ins_interrupt_irq : out std_logic; -- irq
- coe_irq_export : in std_logic := 'X'; -- export
- csi_mm_clk : in std_logic := 'X'; -- clk
- csi_mm_reset : in std_logic := 'X'; -- reset
- mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_ram_write : in std_logic := 'X'; -- write
- mms_ram_read : in std_logic := 'X'; -- read
- mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
- mms_reg_write : in std_logic := 'X'; -- write
- mms_reg_read : in std_logic := 'X'; -- read
- mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mms_tse_write : in std_logic := 'X'; -- write
- mms_tse_read : in std_logic := 'X'; -- read
- mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
- mms_tse_waitrequest : out std_logic; -- waitrequest
- coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
- coe_ram_read_export : out std_logic; -- export
- coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_ram_write_export : out std_logic; -- export
- coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
- coe_reg_read_export : out std_logic; -- export
- coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_reg_write_export : out std_logic; -- export
- coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
- coe_reset_export : out std_logic; -- export
- coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
- coe_tse_read_export : out std_logic; -- export
- coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- coe_tse_waitrequest_export : in std_logic := 'X'; -- export
- coe_tse_write_export : out std_logic; -- export
- coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
- );
- end component qsys_unb2b_minimal_avs_eth_0;
+ component qsys_unb2b_minimal_avs_eth_0 is
+ port (
+ coe_clk_export : out std_logic; -- export
+ ins_interrupt_irq : out std_logic; -- irq
+ coe_irq_export : in std_logic := 'X'; -- export
+ csi_mm_clk : in std_logic := 'X'; -- clk
+ csi_mm_reset : in std_logic := 'X'; -- reset
+ mms_ram_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_ram_write : in std_logic := 'X'; -- write
+ mms_ram_read : in std_logic := 'X'; -- read
+ mms_ram_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_ram_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_reg_address : in std_logic_vector(3 downto 0) := (others => 'X'); -- address
+ mms_reg_write : in std_logic := 'X'; -- write
+ mms_reg_read : in std_logic := 'X'; -- read
+ mms_reg_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_reg_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mms_tse_write : in std_logic := 'X'; -- write
+ mms_tse_read : in std_logic := 'X'; -- read
+ mms_tse_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mms_tse_readdata : out std_logic_vector(31 downto 0); -- readdata
+ mms_tse_waitrequest : out std_logic; -- waitrequest
+ coe_ram_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_ram_read_export : out std_logic; -- export
+ coe_ram_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_ram_write_export : out std_logic; -- export
+ coe_ram_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reg_address_export : out std_logic_vector(3 downto 0); -- export
+ coe_reg_read_export : out std_logic; -- export
+ coe_reg_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_reg_write_export : out std_logic; -- export
+ coe_reg_writedata_export : out std_logic_vector(31 downto 0); -- export
+ coe_reset_export : out std_logic; -- export
+ coe_tse_address_export : out std_logic_vector(9 downto 0); -- export
+ coe_tse_read_export : out std_logic; -- export
+ coe_tse_readdata_export : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ coe_tse_waitrequest_export : in std_logic := 'X'; -- export
+ coe_tse_write_export : out std_logic; -- export
+ coe_tse_writedata_export : out std_logic_vector(31 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_avs_eth_0;
- u0 : component qsys_unb2b_minimal_avs_eth_0
- port map (
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
- coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
- csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
- csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
- mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
- mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
- mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
- mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
- mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
- mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
- mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
- mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
- mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
- mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
- mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
- mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
- mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
- mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
- mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
- mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
- coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
- coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
- coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
- coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
- coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
- coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
- coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
- coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
- coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
- coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
- coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
- coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
- coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
- coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
- coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
- );
+ u0 : component qsys_unb2b_minimal_avs_eth_0
+ port map (
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ ins_interrupt_irq => CONNECTED_TO_ins_interrupt_irq, -- interrupt.irq
+ coe_irq_export => CONNECTED_TO_coe_irq_export, -- irq.export
+ csi_mm_clk => CONNECTED_TO_csi_mm_clk, -- mm.clk
+ csi_mm_reset => CONNECTED_TO_csi_mm_reset, -- mm_reset.reset
+ mms_ram_address => CONNECTED_TO_mms_ram_address, -- mms_ram.address
+ mms_ram_write => CONNECTED_TO_mms_ram_write, -- .write
+ mms_ram_read => CONNECTED_TO_mms_ram_read, -- .read
+ mms_ram_writedata => CONNECTED_TO_mms_ram_writedata, -- .writedata
+ mms_ram_readdata => CONNECTED_TO_mms_ram_readdata, -- .readdata
+ mms_reg_address => CONNECTED_TO_mms_reg_address, -- mms_reg.address
+ mms_reg_write => CONNECTED_TO_mms_reg_write, -- .write
+ mms_reg_read => CONNECTED_TO_mms_reg_read, -- .read
+ mms_reg_writedata => CONNECTED_TO_mms_reg_writedata, -- .writedata
+ mms_reg_readdata => CONNECTED_TO_mms_reg_readdata, -- .readdata
+ mms_tse_address => CONNECTED_TO_mms_tse_address, -- mms_tse.address
+ mms_tse_write => CONNECTED_TO_mms_tse_write, -- .write
+ mms_tse_read => CONNECTED_TO_mms_tse_read, -- .read
+ mms_tse_writedata => CONNECTED_TO_mms_tse_writedata, -- .writedata
+ mms_tse_readdata => CONNECTED_TO_mms_tse_readdata, -- .readdata
+ mms_tse_waitrequest => CONNECTED_TO_mms_tse_waitrequest, -- .waitrequest
+ coe_ram_address_export => CONNECTED_TO_coe_ram_address_export, -- ram_address.export
+ coe_ram_read_export => CONNECTED_TO_coe_ram_read_export, -- ram_read.export
+ coe_ram_readdata_export => CONNECTED_TO_coe_ram_readdata_export, -- ram_readdata.export
+ coe_ram_write_export => CONNECTED_TO_coe_ram_write_export, -- ram_write.export
+ coe_ram_writedata_export => CONNECTED_TO_coe_ram_writedata_export, -- ram_writedata.export
+ coe_reg_address_export => CONNECTED_TO_coe_reg_address_export, -- reg_address.export
+ coe_reg_read_export => CONNECTED_TO_coe_reg_read_export, -- reg_read.export
+ coe_reg_readdata_export => CONNECTED_TO_coe_reg_readdata_export, -- reg_readdata.export
+ coe_reg_write_export => CONNECTED_TO_coe_reg_write_export, -- reg_write.export
+ coe_reg_writedata_export => CONNECTED_TO_coe_reg_writedata_export, -- reg_writedata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ coe_tse_address_export => CONNECTED_TO_coe_tse_address_export, -- tse_address.export
+ coe_tse_read_export => CONNECTED_TO_coe_tse_read_export, -- tse_read.export
+ coe_tse_readdata_export => CONNECTED_TO_coe_tse_readdata_export, -- tse_readdata.export
+ coe_tse_waitrequest_export => CONNECTED_TO_coe_tse_waitrequest_export, -- tse_waitrequest.export
+ coe_tse_write_export => CONNECTED_TO_coe_tse_write_export, -- tse_write.export
+ coe_tse_writedata_export => CONNECTED_TO_coe_tse_writedata_export -- tse_writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
index fafd41bbfa80eae91afc0da3d18e2f4b799f6a95..b717623c7cc1c3984c781cc836d9bc13c93bebea 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_clk_0/qsys_unb2b_minimal_clk_0_inst.vhd
@@ -1,16 +1,16 @@
- component qsys_unb2b_minimal_clk_0 is
- port (
- clk_out : out std_logic; -- clk
- in_clk : in std_logic := 'X'; -- clk
- reset_n : in std_logic := 'X'; -- reset_n
- reset_n_out : out std_logic -- reset_n
- );
- end component qsys_unb2b_minimal_clk_0;
+ component qsys_unb2b_minimal_clk_0 is
+ port (
+ clk_out : out std_logic; -- clk
+ in_clk : in std_logic := 'X'; -- clk
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_n_out : out std_logic -- reset_n
+ );
+ end component qsys_unb2b_minimal_clk_0;
- u0 : component qsys_unb2b_minimal_clk_0
- port map (
- clk_out => CONNECTED_TO_clk_out, -- clk.clk
- in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
- reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
- reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
- );
+ u0 : component qsys_unb2b_minimal_clk_0
+ port map (
+ clk_out => CONNECTED_TO_clk_out, -- clk.clk
+ in_clk => CONNECTED_TO_in_clk, -- clk_in.clk
+ reset_n => CONNECTED_TO_reset_n, -- clk_in_reset.reset_n
+ reset_n_out => CONNECTED_TO_reset_n_out -- clk_reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
index 38fce9676fd1136ba002d70216e0ae804269cd9f..4b049df7a095757aba476bf10632411ebc1e23bf 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_cpu_0/qsys_unb2b_minimal_cpu_0_inst.vhd
@@ -1,60 +1,60 @@
- component qsys_unb2b_minimal_cpu_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- dummy_ci_port : out std_logic; -- readra
- d_address : out std_logic_vector(19 downto 0); -- address
- d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
- d_read : out std_logic; -- read
- d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- d_waitrequest : in std_logic := 'X'; -- waitrequest
- d_write : out std_logic; -- write
- d_writedata : out std_logic_vector(31 downto 0); -- writedata
- debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
- debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
- debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
- debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
- debug_mem_slave_read : in std_logic := 'X'; -- read
- debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
- debug_mem_slave_waitrequest : out std_logic; -- waitrequest
- debug_mem_slave_write : in std_logic := 'X'; -- write
- debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- debug_reset_request : out std_logic; -- reset
- i_address : out std_logic_vector(17 downto 0); -- address
- i_read : out std_logic; -- read
- i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
- i_waitrequest : in std_logic := 'X'; -- waitrequest
- irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- reset_req : in std_logic := 'X' -- reset_req
- );
- end component qsys_unb2b_minimal_cpu_0;
+ component qsys_unb2b_minimal_cpu_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ dummy_ci_port : out std_logic; -- readra
+ d_address : out std_logic_vector(19 downto 0); -- address
+ d_byteenable : out std_logic_vector(3 downto 0); -- byteenable
+ d_read : out std_logic; -- read
+ d_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ d_waitrequest : in std_logic := 'X'; -- waitrequest
+ d_write : out std_logic; -- write
+ d_writedata : out std_logic_vector(31 downto 0); -- writedata
+ debug_mem_slave_debugaccess_to_roms : out std_logic; -- debugaccess
+ debug_mem_slave_address : in std_logic_vector(8 downto 0) := (others => 'X'); -- address
+ debug_mem_slave_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable
+ debug_mem_slave_debugaccess : in std_logic := 'X'; -- debugaccess
+ debug_mem_slave_read : in std_logic := 'X'; -- read
+ debug_mem_slave_readdata : out std_logic_vector(31 downto 0); -- readdata
+ debug_mem_slave_waitrequest : out std_logic; -- waitrequest
+ debug_mem_slave_write : in std_logic := 'X'; -- write
+ debug_mem_slave_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ debug_reset_request : out std_logic; -- reset
+ i_address : out std_logic_vector(17 downto 0); -- address
+ i_read : out std_logic; -- read
+ i_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
+ i_waitrequest : in std_logic := 'X'; -- waitrequest
+ irq : in std_logic_vector(31 downto 0) := (others => 'X'); -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ reset_req : in std_logic := 'X' -- reset_req
+ );
+ end component qsys_unb2b_minimal_cpu_0;
- u0 : component qsys_unb2b_minimal_cpu_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
- d_address => CONNECTED_TO_d_address, -- data_master.address
- d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
- d_read => CONNECTED_TO_d_read, -- .read
- d_readdata => CONNECTED_TO_d_readdata, -- .readdata
- d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
- d_write => CONNECTED_TO_d_write, -- .write
- d_writedata => CONNECTED_TO_d_writedata, -- .writedata
- debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
- debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
- debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
- debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
- debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
- debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
- debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
- debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
- debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
- debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
- i_address => CONNECTED_TO_i_address, -- instruction_master.address
- i_read => CONNECTED_TO_i_read, -- .read
- i_readdata => CONNECTED_TO_i_readdata, -- .readdata
- i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- reset_req => CONNECTED_TO_reset_req -- .reset_req
- );
+ u0 : component qsys_unb2b_minimal_cpu_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ dummy_ci_port => CONNECTED_TO_dummy_ci_port, -- custom_instruction_master.readra
+ d_address => CONNECTED_TO_d_address, -- data_master.address
+ d_byteenable => CONNECTED_TO_d_byteenable, -- .byteenable
+ d_read => CONNECTED_TO_d_read, -- .read
+ d_readdata => CONNECTED_TO_d_readdata, -- .readdata
+ d_waitrequest => CONNECTED_TO_d_waitrequest, -- .waitrequest
+ d_write => CONNECTED_TO_d_write, -- .write
+ d_writedata => CONNECTED_TO_d_writedata, -- .writedata
+ debug_mem_slave_debugaccess_to_roms => CONNECTED_TO_debug_mem_slave_debugaccess_to_roms, -- .debugaccess
+ debug_mem_slave_address => CONNECTED_TO_debug_mem_slave_address, -- debug_mem_slave.address
+ debug_mem_slave_byteenable => CONNECTED_TO_debug_mem_slave_byteenable, -- .byteenable
+ debug_mem_slave_debugaccess => CONNECTED_TO_debug_mem_slave_debugaccess, -- .debugaccess
+ debug_mem_slave_read => CONNECTED_TO_debug_mem_slave_read, -- .read
+ debug_mem_slave_readdata => CONNECTED_TO_debug_mem_slave_readdata, -- .readdata
+ debug_mem_slave_waitrequest => CONNECTED_TO_debug_mem_slave_waitrequest, -- .waitrequest
+ debug_mem_slave_write => CONNECTED_TO_debug_mem_slave_write, -- .write
+ debug_mem_slave_writedata => CONNECTED_TO_debug_mem_slave_writedata, -- .writedata
+ debug_reset_request => CONNECTED_TO_debug_reset_request, -- debug_reset_request.reset
+ i_address => CONNECTED_TO_i_address, -- instruction_master.address
+ i_read => CONNECTED_TO_i_read, -- .read
+ i_readdata => CONNECTED_TO_i_readdata, -- .readdata
+ i_waitrequest => CONNECTED_TO_i_waitrequest, -- .waitrequest
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ reset_req => CONNECTED_TO_reset_req -- .reset_req
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
index c76f427acbe4d282fd1db94d2af4ffdce37d9027..f1383bb2be99d5fbcfdb238fc6d9168d81663e8d 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jesd204/qsys_unb2b_minimal_jesd204_inst.vhd
@@ -1,100 +1,100 @@
- component qsys_unb2b_minimal_jesd204 is
- port (
- alldev_lane_aligned : in std_logic := 'X'; -- export
- csr_cf : out std_logic_vector(4 downto 0); -- export
- csr_cs : out std_logic_vector(1 downto 0); -- export
- csr_f : out std_logic_vector(7 downto 0); -- export
- csr_hd : out std_logic; -- export
- csr_k : out std_logic_vector(4 downto 0); -- export
- csr_l : out std_logic_vector(4 downto 0); -- export
- csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
- csr_m : out std_logic_vector(7 downto 0); -- export
- csr_n : out std_logic_vector(4 downto 0); -- export
- csr_np : out std_logic_vector(4 downto 0); -- export
- csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
- csr_s : out std_logic_vector(4 downto 0); -- export
- dev_lane_aligned : out std_logic; -- export
- dev_sync_n : out std_logic; -- export
- jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
- jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
- jesd204_rx_avs_read : in std_logic := 'X'; -- read
- jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
- jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
- jesd204_rx_avs_write : in std_logic := 'X'; -- write
- jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
- jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
- jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
- jesd204_rx_frame_error : in std_logic := 'X'; -- export
- jesd204_rx_int : out std_logic; -- irq
- jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
- jesd204_rx_link_valid : out std_logic; -- valid
- jesd204_rx_link_ready : in std_logic := 'X'; -- ready
- pll_ref_clk : in std_logic := 'X'; -- clk
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
- rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
- rxlink_clk : in std_logic := 'X'; -- clk
- rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
- rxphy_clk : out std_logic_vector(0 downto 0); -- export
- sof : out std_logic_vector(3 downto 0); -- export
- somf : out std_logic_vector(3 downto 0); -- export
- sysref : in std_logic := 'X' -- export
- );
- end component qsys_unb2b_minimal_jesd204;
+ component qsys_unb2b_minimal_jesd204 is
+ port (
+ alldev_lane_aligned : in std_logic := 'X'; -- export
+ csr_cf : out std_logic_vector(4 downto 0); -- export
+ csr_cs : out std_logic_vector(1 downto 0); -- export
+ csr_f : out std_logic_vector(7 downto 0); -- export
+ csr_hd : out std_logic; -- export
+ csr_k : out std_logic_vector(4 downto 0); -- export
+ csr_l : out std_logic_vector(4 downto 0); -- export
+ csr_lane_powerdown : out std_logic_vector(0 downto 0); -- export
+ csr_m : out std_logic_vector(7 downto 0); -- export
+ csr_n : out std_logic_vector(4 downto 0); -- export
+ csr_np : out std_logic_vector(4 downto 0); -- export
+ csr_rx_testmode : out std_logic_vector(3 downto 0); -- export
+ csr_s : out std_logic_vector(4 downto 0); -- export
+ dev_lane_aligned : out std_logic; -- export
+ dev_sync_n : out std_logic; -- export
+ jesd204_rx_avs_chipselect : in std_logic := 'X'; -- chipselect
+ jesd204_rx_avs_address : in std_logic_vector(7 downto 0) := (others => 'X'); -- address
+ jesd204_rx_avs_read : in std_logic := 'X'; -- read
+ jesd204_rx_avs_readdata : out std_logic_vector(31 downto 0); -- readdata
+ jesd204_rx_avs_waitrequest : out std_logic; -- waitrequest
+ jesd204_rx_avs_write : in std_logic := 'X'; -- write
+ jesd204_rx_avs_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ jesd204_rx_avs_clk : in std_logic := 'X'; -- clk
+ jesd204_rx_avs_rst_n : in std_logic := 'X'; -- reset_n
+ jesd204_rx_dlb_data : in std_logic_vector(31 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_data_valid : in std_logic_vector(0 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_disperr : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_errdetect : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_dlb_kchar_data : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
+ jesd204_rx_frame_error : in std_logic := 'X'; -- export
+ jesd204_rx_int : out std_logic; -- irq
+ jesd204_rx_link_data : out std_logic_vector(31 downto 0); -- data
+ jesd204_rx_link_valid : out std_logic; -- valid
+ jesd204_rx_link_ready : in std_logic := 'X'; -- ready
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_digitalreset
+ rx_islockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => 'X'); -- rx_serial_data
+ rxlink_clk : in std_logic := 'X'; -- clk
+ rxlink_rst_n_reset_n : in std_logic := 'X'; -- reset_n
+ rxphy_clk : out std_logic_vector(0 downto 0); -- export
+ sof : out std_logic_vector(3 downto 0); -- export
+ somf : out std_logic_vector(3 downto 0); -- export
+ sysref : in std_logic := 'X' -- export
+ );
+ end component qsys_unb2b_minimal_jesd204;
- u0 : component qsys_unb2b_minimal_jesd204
- port map (
- alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
- csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
- csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
- csr_f => CONNECTED_TO_csr_f, -- csr_f.export
- csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
- csr_k => CONNECTED_TO_csr_k, -- csr_k.export
- csr_l => CONNECTED_TO_csr_l, -- csr_l.export
- csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
- csr_m => CONNECTED_TO_csr_m, -- csr_m.export
- csr_n => CONNECTED_TO_csr_n, -- csr_n.export
- csr_np => CONNECTED_TO_csr_np, -- csr_np.export
- csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
- csr_s => CONNECTED_TO_csr_s, -- csr_s.export
- dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
- dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
- jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
- jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
- jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
- jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
- jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
- jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
- jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
- jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
- jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
- jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
- jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
- jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
- jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
- jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
- jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
- jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
- jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
- jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
- jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
- rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
- rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
- rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
- rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
- sof => CONNECTED_TO_sof, -- sof.export
- somf => CONNECTED_TO_somf, -- somf.export
- sysref => CONNECTED_TO_sysref -- sysref.export
- );
+ u0 : component qsys_unb2b_minimal_jesd204
+ port map (
+ alldev_lane_aligned => CONNECTED_TO_alldev_lane_aligned, -- alldev_lane_aligned.export
+ csr_cf => CONNECTED_TO_csr_cf, -- csr_cf.export
+ csr_cs => CONNECTED_TO_csr_cs, -- csr_cs.export
+ csr_f => CONNECTED_TO_csr_f, -- csr_f.export
+ csr_hd => CONNECTED_TO_csr_hd, -- csr_hd.export
+ csr_k => CONNECTED_TO_csr_k, -- csr_k.export
+ csr_l => CONNECTED_TO_csr_l, -- csr_l.export
+ csr_lane_powerdown => CONNECTED_TO_csr_lane_powerdown, -- csr_lane_powerdown.export
+ csr_m => CONNECTED_TO_csr_m, -- csr_m.export
+ csr_n => CONNECTED_TO_csr_n, -- csr_n.export
+ csr_np => CONNECTED_TO_csr_np, -- csr_np.export
+ csr_rx_testmode => CONNECTED_TO_csr_rx_testmode, -- csr_rx_testmode.export
+ csr_s => CONNECTED_TO_csr_s, -- csr_s.export
+ dev_lane_aligned => CONNECTED_TO_dev_lane_aligned, -- dev_lane_aligned.export
+ dev_sync_n => CONNECTED_TO_dev_sync_n, -- dev_sync_n.export
+ jesd204_rx_avs_chipselect => CONNECTED_TO_jesd204_rx_avs_chipselect, -- jesd204_rx_avs.chipselect
+ jesd204_rx_avs_address => CONNECTED_TO_jesd204_rx_avs_address, -- .address
+ jesd204_rx_avs_read => CONNECTED_TO_jesd204_rx_avs_read, -- .read
+ jesd204_rx_avs_readdata => CONNECTED_TO_jesd204_rx_avs_readdata, -- .readdata
+ jesd204_rx_avs_waitrequest => CONNECTED_TO_jesd204_rx_avs_waitrequest, -- .waitrequest
+ jesd204_rx_avs_write => CONNECTED_TO_jesd204_rx_avs_write, -- .write
+ jesd204_rx_avs_writedata => CONNECTED_TO_jesd204_rx_avs_writedata, -- .writedata
+ jesd204_rx_avs_clk => CONNECTED_TO_jesd204_rx_avs_clk, -- jesd204_rx_avs_clk.clk
+ jesd204_rx_avs_rst_n => CONNECTED_TO_jesd204_rx_avs_rst_n, -- jesd204_rx_avs_rst_n.reset_n
+ jesd204_rx_dlb_data => CONNECTED_TO_jesd204_rx_dlb_data, -- jesd204_rx_dlb_data.export
+ jesd204_rx_dlb_data_valid => CONNECTED_TO_jesd204_rx_dlb_data_valid, -- jesd204_rx_dlb_data_valid.export
+ jesd204_rx_dlb_disperr => CONNECTED_TO_jesd204_rx_dlb_disperr, -- jesd204_rx_dlb_disperr.export
+ jesd204_rx_dlb_errdetect => CONNECTED_TO_jesd204_rx_dlb_errdetect, -- jesd204_rx_dlb_errdetect.export
+ jesd204_rx_dlb_kchar_data => CONNECTED_TO_jesd204_rx_dlb_kchar_data, -- jesd204_rx_dlb_kchar_data.export
+ jesd204_rx_frame_error => CONNECTED_TO_jesd204_rx_frame_error, -- jesd204_rx_frame_error.export
+ jesd204_rx_int => CONNECTED_TO_jesd204_rx_int, -- jesd204_rx_int.irq
+ jesd204_rx_link_data => CONNECTED_TO_jesd204_rx_link_data, -- jesd204_rx_link.data
+ jesd204_rx_link_valid => CONNECTED_TO_jesd204_rx_link_valid, -- .valid
+ jesd204_rx_link_ready => CONNECTED_TO_jesd204_rx_link_ready, -- .ready
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_islockedtodata => CONNECTED_TO_rx_islockedtodata, -- rx_islockedtodata.rx_is_lockedtodata
+ rx_serial_data => CONNECTED_TO_rx_serial_data, -- rx_serial_data.rx_serial_data
+ rxlink_clk => CONNECTED_TO_rxlink_clk, -- rxlink_clk.clk
+ rxlink_rst_n_reset_n => CONNECTED_TO_rxlink_rst_n_reset_n, -- rxlink_rst_n.reset_n
+ rxphy_clk => CONNECTED_TO_rxphy_clk, -- rxphy_clk.export
+ sof => CONNECTED_TO_sof, -- sof.export
+ somf => CONNECTED_TO_somf, -- somf.export
+ sysref => CONNECTED_TO_sysref -- sysref.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
index bc11c57e416cd6de852d448d82730d0e93d92791..3567f678e64f9732e4715dd34785b34131be83a2 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_jtag_uart_0/qsys_unb2b_minimal_jtag_uart_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_jtag_uart_0 is
- port (
- av_chipselect : in std_logic := 'X'; -- chipselect
- av_address : in std_logic := 'X'; -- address
- av_read_n : in std_logic := 'X'; -- read_n
- av_readdata : out std_logic_vector(31 downto 0); -- readdata
- av_write_n : in std_logic := 'X'; -- write_n
- av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- av_waitrequest : out std_logic; -- waitrequest
- clk : in std_logic := 'X'; -- clk
- av_irq : out std_logic; -- irq
- rst_n : in std_logic := 'X' -- reset_n
- );
- end component qsys_unb2b_minimal_jtag_uart_0;
+ component qsys_unb2b_minimal_jtag_uart_0 is
+ port (
+ av_chipselect : in std_logic := 'X'; -- chipselect
+ av_address : in std_logic := 'X'; -- address
+ av_read_n : in std_logic := 'X'; -- read_n
+ av_readdata : out std_logic_vector(31 downto 0); -- readdata
+ av_write_n : in std_logic := 'X'; -- write_n
+ av_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ av_waitrequest : out std_logic; -- waitrequest
+ clk : in std_logic := 'X'; -- clk
+ av_irq : out std_logic; -- irq
+ rst_n : in std_logic := 'X' -- reset_n
+ );
+ end component qsys_unb2b_minimal_jtag_uart_0;
- u0 : component qsys_unb2b_minimal_jtag_uart_0
- port map (
- av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
- av_address => CONNECTED_TO_av_address, -- .address
- av_read_n => CONNECTED_TO_av_read_n, -- .read_n
- av_readdata => CONNECTED_TO_av_readdata, -- .readdata
- av_write_n => CONNECTED_TO_av_write_n, -- .write_n
- av_writedata => CONNECTED_TO_av_writedata, -- .writedata
- av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
- clk => CONNECTED_TO_clk, -- clk.clk
- av_irq => CONNECTED_TO_av_irq, -- irq.irq
- rst_n => CONNECTED_TO_rst_n -- reset.reset_n
- );
+ u0 : component qsys_unb2b_minimal_jtag_uart_0
+ port map (
+ av_chipselect => CONNECTED_TO_av_chipselect, -- avalon_jtag_slave.chipselect
+ av_address => CONNECTED_TO_av_address, -- .address
+ av_read_n => CONNECTED_TO_av_read_n, -- .read_n
+ av_readdata => CONNECTED_TO_av_readdata, -- .readdata
+ av_write_n => CONNECTED_TO_av_write_n, -- .write_n
+ av_writedata => CONNECTED_TO_av_writedata, -- .writedata
+ av_waitrequest => CONNECTED_TO_av_waitrequest, -- .waitrequest
+ clk => CONNECTED_TO_clk, -- clk.clk
+ av_irq => CONNECTED_TO_av_irq, -- irq.irq
+ rst_n => CONNECTED_TO_rst_n -- reset.reset_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
index f453120efc4f037dc4efbc07b42a93186450fe1d..0d06cbc9cae02b57e8a7ff4817a0c6df89c5acd0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_onchip_memory2_0/qsys_unb2b_minimal_onchip_memory2_0_inst.vhd
@@ -1,28 +1,28 @@
- component qsys_unb2b_minimal_onchip_memory2_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- reset : in std_logic := 'X'; -- reset
- reset_req : in std_logic := 'X'; -- reset_req
- address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
- clken : in std_logic := 'X'; -- clken
- chipselect : in std_logic := 'X'; -- chipselect
- write : in std_logic := 'X'; -- write
- readdata : out std_logic_vector(31 downto 0); -- readdata
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
- );
- end component qsys_unb2b_minimal_onchip_memory2_0;
+ component qsys_unb2b_minimal_onchip_memory2_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ reset : in std_logic := 'X'; -- reset
+ reset_req : in std_logic := 'X'; -- reset_req
+ address : in std_logic_vector(14 downto 0) := (others => 'X'); -- address
+ clken : in std_logic := 'X'; -- clken
+ chipselect : in std_logic := 'X'; -- chipselect
+ write : in std_logic := 'X'; -- write
+ readdata : out std_logic_vector(31 downto 0); -- readdata
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ byteenable : in std_logic_vector(3 downto 0) := (others => 'X') -- byteenable
+ );
+ end component qsys_unb2b_minimal_onchip_memory2_0;
- u0 : component qsys_unb2b_minimal_onchip_memory2_0
- port map (
- clk => CONNECTED_TO_clk, -- clk1.clk
- reset => CONNECTED_TO_reset, -- reset1.reset
- reset_req => CONNECTED_TO_reset_req, -- .reset_req
- address => CONNECTED_TO_address, -- s1.address
- clken => CONNECTED_TO_clken, -- .clken
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write => CONNECTED_TO_write, -- .write
- readdata => CONNECTED_TO_readdata, -- .readdata
- writedata => CONNECTED_TO_writedata, -- .writedata
- byteenable => CONNECTED_TO_byteenable -- .byteenable
- );
+ u0 : component qsys_unb2b_minimal_onchip_memory2_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk1.clk
+ reset => CONNECTED_TO_reset, -- reset1.reset
+ reset_req => CONNECTED_TO_reset_req, -- .reset_req
+ address => CONNECTED_TO_address, -- s1.address
+ clken => CONNECTED_TO_clken, -- .clken
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write => CONNECTED_TO_write, -- .write
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ byteenable => CONNECTED_TO_byteenable -- .byteenable
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
index 580187433d6ad3516adc8f3613297cd106f122a7..04740d0db75fc3b705ba549ac5fde6008f898c8c 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_pps/qsys_unb2b_minimal_pio_pps_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_pps is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_pps;
+ component qsys_unb2b_minimal_pio_pps is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_pio_pps;
- u0 : component qsys_unb2b_minimal_pio_pps
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_pio_pps
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
index b05a01d44469adf2ce2a5524f755a45e93ee3b55..871bc6d3263e6e4d8feb155f6f304fc8a80a3af5 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_system_info/qsys_unb2b_minimal_pio_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_pio_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_pio_system_info;
+ component qsys_unb2b_minimal_pio_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_pio_system_info;
- u0 : component qsys_unb2b_minimal_pio_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_pio_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
index 4639e141f52b87b436009b6f01944420186ed973..9f0f3e87a85a8b699eec8f520148c81fc6bb8e63 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_pio_wdi/qsys_unb2b_minimal_pio_wdi_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_pio_wdi is
- port (
- clk : in std_logic := 'X'; -- clk
- out_port : out std_logic; -- export
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
- write_n : in std_logic := 'X'; -- write_n
- writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- chipselect : in std_logic := 'X'; -- chipselect
- readdata : out std_logic_vector(31 downto 0) -- readdata
- );
- end component qsys_unb2b_minimal_pio_wdi;
+ component qsys_unb2b_minimal_pio_wdi is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ out_port : out std_logic; -- export
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(1 downto 0) := (others => 'X'); -- address
+ write_n : in std_logic := 'X'; -- write_n
+ writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ chipselect : in std_logic := 'X'; -- chipselect
+ readdata : out std_logic_vector(31 downto 0) -- readdata
+ );
+ end component qsys_unb2b_minimal_pio_wdi;
- u0 : component qsys_unb2b_minimal_pio_wdi
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- out_port => CONNECTED_TO_out_port, -- external_connection.export
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- write_n => CONNECTED_TO_write_n, -- .write_n
- writedata => CONNECTED_TO_writedata, -- .writedata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- readdata => CONNECTED_TO_readdata -- .readdata
- );
+ u0 : component qsys_unb2b_minimal_pio_wdi
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ out_port => CONNECTED_TO_out_port, -- external_connection.export
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ write_n => CONNECTED_TO_write_n, -- .write_n
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ readdata => CONNECTED_TO_readdata -- .readdata
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
index ec324643910e8ec28eea3841bf69396535f66ce8..a64854d5352fc652203949432c5b9f0f33131046 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_ctrl/qsys_unb2b_minimal_reg_dpmm_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_ctrl;
+ component qsys_unb2b_minimal_reg_dpmm_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_dpmm_ctrl;
- u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_dpmm_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
index 902a48132b9b35e040acf2ea2bdc5803e567864e..06282c4a21f00a3201b0691428c71902a4464b28 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_dpmm_data/qsys_unb2b_minimal_reg_dpmm_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_dpmm_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_dpmm_data;
+ component qsys_unb2b_minimal_reg_dpmm_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_dpmm_data;
- u0 : component qsys_unb2b_minimal_reg_dpmm_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_dpmm_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
index b7e771b662f1b2279fb0a2605ad86648a3821987..497d0469c292994e6de0e909ea0d0921fdf05a42 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_epcs/qsys_unb2b_minimal_reg_epcs_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_epcs is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_epcs;
+ component qsys_unb2b_minimal_reg_epcs is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_epcs;
- u0 : component qsys_unb2b_minimal_reg_epcs
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_epcs
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
index 170f85ed587a093a331bd7da8153feb63a78358e..b6735293936fec25bc7bf9127d59b0ad3d07ecce 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_temp_sens/qsys_unb2b_minimal_reg_fpga_temp_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_temp_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_temp_sens;
+ component qsys_unb2b_minimal_reg_fpga_temp_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_fpga_temp_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_fpga_temp_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
index 495dae0b21c808c2f09bc98a269f98a22332116b..43d217b96822d4ba769c181b52c1cf53b50fc68e 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_fpga_voltage_sens/qsys_unb2b_minimal_reg_fpga_voltage_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_fpga_voltage_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
+ component qsys_unb2b_minimal_reg_fpga_voltage_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_fpga_voltage_sens;
- u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_fpga_voltage_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
index e099a81cd1f19acfb178d8108c3a40c275935b38..25fd2f1508fd4b47c24182576fb0807704107fc0 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_ctrl/qsys_unb2b_minimal_reg_mmdp_ctrl_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_ctrl is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_ctrl;
+ component qsys_unb2b_minimal_reg_mmdp_ctrl is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_mmdp_ctrl;
- u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_mmdp_ctrl
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
index d25eb92a9c789a0a393083008b9dd982889f184e..8a41c8392d54030f95da390e61418de2c67b90c8 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_mmdp_data/qsys_unb2b_minimal_reg_mmdp_data_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_mmdp_data is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_mmdp_data;
+ component qsys_unb2b_minimal_reg_mmdp_data is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_mmdp_data;
- u0 : component qsys_unb2b_minimal_reg_mmdp_data
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_mmdp_data
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
index 837cb45819d6d993ab0e2ec2cd835b1f69bd1365..74cabd7563f8877d842ff92522d2d0aa2f53c952 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_remu/qsys_unb2b_minimal_reg_remu_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_remu is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_remu;
+ component qsys_unb2b_minimal_reg_remu is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_remu;
- u0 : component qsys_unb2b_minimal_reg_remu
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_remu
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
index b97ef222ecfeac9b9cdc0609f289add83696334d..c0dc7de22245a6bd61f6476ca3b5c298c6e524c3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_pmbus/qsys_unb2b_minimal_reg_unb_pmbus_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_pmbus is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_pmbus;
+ component qsys_unb2b_minimal_reg_unb_pmbus is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_unb_pmbus;
- u0 : component qsys_unb2b_minimal_reg_unb_pmbus
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_unb_pmbus
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
index 1871be2f741a5f58a41c9f333411b3b210fec9e6..22effc2f2409107eda24580155339ceecde4cecb 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_unb_sens/qsys_unb2b_minimal_reg_unb_sens_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_unb_sens is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_unb_sens;
+ component qsys_unb2b_minimal_reg_unb_sens is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_unb_sens;
- u0 : component qsys_unb2b_minimal_reg_unb_sens
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_unb_sens
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
index 229a2d315e14744572cd30efdc1e44a03cb55744..039ee2a813502fae87e99b929262dda1203cdcf3 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_reg_wdi/qsys_unb2b_minimal_reg_wdi_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_reg_wdi is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_reg_wdi;
+ component qsys_unb2b_minimal_reg_wdi is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_reg_wdi;
- u0 : component qsys_unb2b_minimal_reg_wdi
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_reg_wdi
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
index ae35f2bd1988023e11957c39257a521354f840f8..21cd10c8b208554725ed607a34187388b7dd1e13 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_rom_system_info/qsys_unb2b_minimal_rom_system_info_inst.vhd
@@ -1,44 +1,44 @@
- component qsys_unb2b_minimal_rom_system_info is
- generic (
- g_adr_w : natural := 5;
- g_dat_w : natural := 32
- );
- port (
- coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
- coe_clk_export : out std_logic; -- export
- avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
- avs_mem_write : in std_logic := 'X'; -- write
- avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
- avs_mem_read : in std_logic := 'X'; -- read
- avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
- coe_read_export : out std_logic; -- export
- coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
- coe_reset_export : out std_logic; -- export
- csi_system_clk : in std_logic := 'X'; -- clk
- csi_system_reset : in std_logic := 'X'; -- reset
- coe_write_export : out std_logic; -- export
- coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
- );
- end component qsys_unb2b_minimal_rom_system_info;
+ component qsys_unb2b_minimal_rom_system_info is
+ generic (
+ g_adr_w : natural := 5;
+ g_dat_w : natural := 32
+ );
+ port (
+ coe_address_export : out std_logic_vector(g_adr_w - 1 downto 0); -- export
+ coe_clk_export : out std_logic; -- export
+ avs_mem_address : in std_logic_vector(g_adr_w - 1 downto 0) := (others => 'X'); -- address
+ avs_mem_write : in std_logic := 'X'; -- write
+ avs_mem_writedata : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- writedata
+ avs_mem_read : in std_logic := 'X'; -- read
+ avs_mem_readdata : out std_logic_vector(g_dat_w - 1 downto 0); -- readdata
+ coe_read_export : out std_logic; -- export
+ coe_readdata_export : in std_logic_vector(g_dat_w - 1 downto 0) := (others => 'X'); -- export
+ coe_reset_export : out std_logic; -- export
+ csi_system_clk : in std_logic := 'X'; -- clk
+ csi_system_reset : in std_logic := 'X'; -- reset
+ coe_write_export : out std_logic; -- export
+ coe_writedata_export : out std_logic_vector(g_dat_w - 1 downto 0) -- export
+ );
+ end component qsys_unb2b_minimal_rom_system_info;
- u0 : component qsys_unb2b_minimal_rom_system_info
- generic map (
- g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
- g_dat_w => NATURAL_VALUE_FOR_g_dat_w
- )
- port map (
- coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
- coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
- avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
- avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
- avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
- avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
- avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
- coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
- coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
- coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
- csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
- csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
- coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
- coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
- );
+ u0 : component qsys_unb2b_minimal_rom_system_info
+ generic map (
+ g_adr_w => NATURAL_VALUE_FOR_g_adr_w,
+ g_dat_w => NATURAL_VALUE_FOR_g_dat_w
+ )
+ port map (
+ coe_address_export => CONNECTED_TO_coe_address_export, -- address.export
+ coe_clk_export => CONNECTED_TO_coe_clk_export, -- clk.export
+ avs_mem_address => CONNECTED_TO_avs_mem_address, -- mem.address
+ avs_mem_write => CONNECTED_TO_avs_mem_write, -- .write
+ avs_mem_writedata => CONNECTED_TO_avs_mem_writedata, -- .writedata
+ avs_mem_read => CONNECTED_TO_avs_mem_read, -- .read
+ avs_mem_readdata => CONNECTED_TO_avs_mem_readdata, -- .readdata
+ coe_read_export => CONNECTED_TO_coe_read_export, -- read.export
+ coe_readdata_export => CONNECTED_TO_coe_readdata_export, -- readdata.export
+ coe_reset_export => CONNECTED_TO_coe_reset_export, -- reset.export
+ csi_system_clk => CONNECTED_TO_csi_system_clk, -- system.clk
+ csi_system_reset => CONNECTED_TO_csi_system_reset, -- system_reset.reset
+ coe_write_export => CONNECTED_TO_coe_write_export, -- write.export
+ coe_writedata_export => CONNECTED_TO_coe_writedata_export -- writedata.export
+ );
diff --git a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
index ff04a90d2be254067a63715a1ab244263a405a8f..b56940d1e977f236b500a9831b59df657403a2aa 100644
--- a/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
+++ b/boards/uniboard2b/designs/unb2b_jesd/revisions/unb2b_jesd_node3/quartus/ip/qsys_unb2b_minimal/qsys_unb2b_minimal_timer_0/qsys_unb2b_minimal_timer_0_inst.vhd
@@ -1,24 +1,24 @@
- component qsys_unb2b_minimal_timer_0 is
- port (
- clk : in std_logic := 'X'; -- clk
- irq : out std_logic; -- irq
- reset_n : in std_logic := 'X'; -- reset_n
- address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
- writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
- readdata : out std_logic_vector(15 downto 0); -- readdata
- chipselect : in std_logic := 'X'; -- chipselect
- write_n : in std_logic := 'X' -- write_n
- );
- end component qsys_unb2b_minimal_timer_0;
+ component qsys_unb2b_minimal_timer_0 is
+ port (
+ clk : in std_logic := 'X'; -- clk
+ irq : out std_logic; -- irq
+ reset_n : in std_logic := 'X'; -- reset_n
+ address : in std_logic_vector(2 downto 0) := (others => 'X'); -- address
+ writedata : in std_logic_vector(15 downto 0) := (others => 'X'); -- writedata
+ readdata : out std_logic_vector(15 downto 0); -- readdata
+ chipselect : in std_logic := 'X'; -- chipselect
+ write_n : in std_logic := 'X' -- write_n
+ );
+ end component qsys_unb2b_minimal_timer_0;
- u0 : component qsys_unb2b_minimal_timer_0
- port map (
- clk => CONNECTED_TO_clk, -- clk.clk
- irq => CONNECTED_TO_irq, -- irq.irq
- reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
- address => CONNECTED_TO_address, -- s1.address
- writedata => CONNECTED_TO_writedata, -- .writedata
- readdata => CONNECTED_TO_readdata, -- .readdata
- chipselect => CONNECTED_TO_chipselect, -- .chipselect
- write_n => CONNECTED_TO_write_n -- .write_n
- );
+ u0 : component qsys_unb2b_minimal_timer_0
+ port map (
+ clk => CONNECTED_TO_clk, -- clk.clk
+ irq => CONNECTED_TO_irq, -- irq.irq
+ reset_n => CONNECTED_TO_reset_n, -- reset.reset_n
+ address => CONNECTED_TO_address, -- s1.address
+ writedata => CONNECTED_TO_writedata, -- .writedata
+ readdata => CONNECTED_TO_readdata, -- .readdata
+ chipselect => CONNECTED_TO_chipselect, -- .chipselect
+ write_n => CONNECTED_TO_write_n -- .write_n
+ );
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
index ab0300e724b7bb8f55b4b891a838ca736862dc05..40bb71ce7c74c29ed7d99ca88af5e1a65a334375 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/mmm_unb2b_test.vhd
@@ -770,21 +770,21 @@ begin
reg_io_ddr_MB_II_write_export => reg_io_ddr_MB_II_mosi.wr,
reg_io_ddr_MB_II_writedata_export => reg_io_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
- reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
- reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
-
- reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
- reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
- reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
- reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
- reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_I_address_export => reg_diag_tx_seq_ddr_MB_I_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_write_export => reg_diag_tx_seq_ddr_MB_I_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_I_writedata_export => reg_diag_tx_seq_ddr_MB_I_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_I_read_export => reg_diag_tx_seq_ddr_MB_I_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_I_readdata_export => reg_diag_tx_seq_ddr_MB_I_miso.rddata(c_word_w - 1 downto 0),
+
+ reg_diag_tx_seq_ddr_MB_II_reset_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_clk_export => OPEN,
+ reg_diag_tx_seq_ddr_MB_II_address_export => reg_diag_tx_seq_ddr_MB_II_mosi.address(c_unb2b_board_peripherals_mm_reg_default.reg_diag_tx_seq_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_write_export => reg_diag_tx_seq_ddr_MB_II_mosi.wr,
+ reg_diag_tx_seq_ddr_MB_II_writedata_export => reg_diag_tx_seq_ddr_MB_II_mosi.wrdata(c_word_w - 1 downto 0),
+ reg_diag_tx_seq_ddr_MB_II_read_export => reg_diag_tx_seq_ddr_MB_II_mosi.rd,
+ reg_diag_tx_seq_ddr_MB_II_readdata_export => reg_diag_tx_seq_ddr_MB_II_miso.rddata(c_word_w - 1 downto 0),
reg_diag_rx_seq_ddr_MB_I_reset_export => OPEN,
reg_diag_rx_seq_ddr_MB_I_clk_export => OPEN,
diff --git a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
index 02021567e290a50a5b46eff215147816e76578ef..87d90d128065ed496f60333ad851e9bd571c54a4 100644
--- a/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
+++ b/boards/uniboard2b/designs/unb2b_test/src/vhdl/qsys_unb2b_test_pkg.vhd
@@ -29,7 +29,7 @@ package qsys_unb2b_test_pkg is
-----------------------------------------------------------------------------
component qsys_unb2b_test is
- port (
+ port (
avs_eth_0_clk_export : out std_logic; -- avs_eth_0_clk.export
avs_eth_0_irq_export : in std_logic := '0'; -- avs_eth_0_irq.export
avs_eth_0_ram_address_export : out std_logic_vector(9 downto 0); -- avs_eth_0_ram_address.export
diff --git a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
index e03a41f2c78e62ca008bdf75cae34dd0db7d034a..7f89b84367a86f6a00aa7bc63949714275561b36 100644
--- a/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
+++ b/boards/uniboard2c/designs/unb2c_test/src/vhdl/unb2c_test.vhd
@@ -442,7 +442,7 @@ architecture str of unb2c_test is
-- DDR calibration_ok signals are set to '0' by default such that the corresponding
-- LED is turned OFF when no IP is instantiated. This is prefered over turning it on
-- as that would indicate a (false) correct calibration.
- signal ddr_I_cal_ok : std_logic := '0';
+ signal ddr_I_cal_ok : std_logic := '0';
signal ddr_II_cal_ok : std_logic := '0';
-- UDP streaming ports for 1GbE I and 1GbE II
@@ -1242,13 +1242,13 @@ begin
red_led_arr => qsfp_red_led_arr,
QSFP_LED => QSFP_LED
);
-
+
u_front_led : entity unb2c_board_lib.unb2c_board_qsfp_leds_v2
generic map (
g_sim => g_sim,
g_factory_image => g_factory_image,
g_nof_qsfp => c_unb2c_board_tr_qsfp.nof_bus,
- g_mm_pulse_us => 1000 / (10**9 / c_mm_clk_freq),
+ g_mm_pulse_us => 1000 / (10**9 / c_mm_clk_freq),
g_dp_pulse_us => 1000 / (10**9 / c_dp_clk_freq)
)
port map (
diff --git a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
index a26751236aab0e7203dc36a06fd6758f5faf50dc..a70a149bd08d3dee249b442ad835ac716ceec948 100644
--- a/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
+++ b/boards/uniboard2c/lattice_jtag/UNB2_JTAG_SCANBRIDGE/source/jtag_top(str).vhd
@@ -29,7 +29,7 @@ architecture str of jtag_top is
-- enter the number of BSCAN2 blocks to create. This is the only place that
-- needs to be modified to control the number of local scan ports created.
generic (
- bscan_ports : positive := 2
+ bscan_ports : positive := 2
);
port (
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
index 95690420b5adb0782501ae08dc35d1589c62b575..094c7c988bbd3d8caef01f0c2e655b4ec962b72f 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_cr_cw.vhd
@@ -17,12 +17,12 @@
-- limitations under the License.
--
-- -----------------------------------------------------------------------------
---
--- Author:
+--
+-- Author:
-- D.F. Brouwer
--- Purpose:
+-- Purpose:
-- Multi page memory with seperate clock and address per port with single wr
--- and single rd
+-- and single rd
-- Description:
-- When *_next_page pulses then the next access will occur in the next page.
-- Remarks:
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
index d14ab4d07069cedabc5651e88af6f4872c6a05aa..a8f4d13706a31577e34c2816de7b5581c775d75e 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_crw_crw.vhd
@@ -17,8 +17,8 @@
-- limitations under the License.
--
-- -----------------------------------------------------------------------------
---
--- Author:
+--
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
diff --git a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
index d2b9efe3d437d393991b3f245b49e9c766c05021..9a18427a808ded6f8026c59d3937f63d628ff755 100644
--- a/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_paged_ram_rw_rw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
diff --git a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
index fd000548f0186c359e4deba7fe5733ce1bffe4a8..379adf5e473d43345d75b2a04f5030af9d3715c2 100644
--- a/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_cr_cw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
index 8b6378b009e61ee9c440b40663208e1eda98169e..970478e94a08b8125ba0849b1eecf92650ba4b04 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cr.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
index cac8b4dc12fd5eaffa27a67c1a36e7478d93f1fe..9839b2b66fab1aa5ee65369ed8863b0d1d99df59 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
index e151c5c1272866d1a18278de84539a88cfccee2f..24995bd132327c72663831de36e5c1c3fb0d38e1 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_crw_ratio.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
diff --git a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
index 5500773ade6e05181785f6f13456065973a659e8..d98e3af03c2b7b8bf7987e3969609ce396c7f3fe 100644
--- a/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_crw_cw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
diff --git a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
index baaf775ae82726a66abac3fd7480c55282ae57f3..f39c7c87f5fc2ea9b34f6d3720a4e7f4d1570292 100644
--- a/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
+++ b/libraries/base/common/src/vhdl/common_ram_rw_rw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- -
-- Changed by:
-- D.F. Brouwer
@@ -96,7 +96,7 @@ begin
)
port map (
clock => clk,
- enable => clken,
+ enable => clken,
wren_a => wr_en_a,
wren_b => wr_en_b,
data_a => wr_dat_a,
diff --git a/libraries/base/common/src/vhdl/common_str_pkg.vhd b/libraries/base/common/src/vhdl/common_str_pkg.vhd
index 8aad8788922126a200c54d4bbfc735cb55ef384f..b56337e78f3b30c3c87bcf1a2ebc97076aceb26c 100644
--- a/libraries/base/common/src/vhdl/common_str_pkg.vhd
+++ b/libraries/base/common/src/vhdl/common_str_pkg.vhd
@@ -117,13 +117,13 @@ package body common_str_pkg is
function time_to_str(in_time : time) return string is
constant c_max_len_time : natural := 20;
- variable v_line : LINE;
- variable v_str : string(1 to c_max_len_time) := (others => ' ');
+ variable v_line : LINE;
+ variable v_str : string(1 to c_max_len_time) := (others => ' ');
begin
write(v_line, in_time);
- v_str(v_line.ALL'range) := v_line.all;
- deallocate(v_line);
- return v_str;
+ v_str(v_line.ALL'range) := v_line.all;
+ deallocate(v_line);
+ return v_str;
end;
function str_to_time(in_str : string) return time is
@@ -223,7 +223,7 @@ package body common_str_pkg is
when 'X' => v_result := "XXXX";
when 'z' => v_result := "ZZZZ";
when 'Z' => v_result := "ZZZZ";
- when others => v_result := "0000";
+ when others => v_result := "0000";
end case;
return v_result;
end hex_nibble_to_slv;
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
index 05e526c6838c9c5742008eeaac54cc7af1a214df..57a6912714b1c996da6cc73880c0f835a5f8c444 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_cr_cw.vhd
@@ -18,9 +18,9 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
--- Purpose:
+-- Purpose:
-- Test bench for common_paged_ram_cr_cw
-- Reference:
-- Based on tb_common_paged_ram_crw_crw.vhd
diff --git a/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd b/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
index 2de05fffb45fc79828ab8ff58ced5d5406787234..3527267b3d8a012ba12aea623e42e07c6345fb36 100644
--- a/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
+++ b/libraries/base/common/tb/vhdl/tb_common_paged_ram_rw_rw.vhd
@@ -18,9 +18,9 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
--- Purpose:
+-- Purpose:
-- Test bench for common_paged_ram_rw_rw
-- Reference:
-- Based on tb_common_paged_ram_crw_crw.vhd
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
index fe450e22c104ff81613d9c0de21b3d25672d2217..64f0ef268b00f6fc96f91956c86b2be42b49c891 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter.vhd
@@ -29,7 +29,7 @@ use common_lib.common_field_pkg.all;
entity dp_offload_rx_filter is
generic (
- g_bypass : boolean := false;
+ g_bypass : boolean := false;
g_nof_streams : positive := 1;
g_data_w : natural;
g_hdr_field_arr : t_common_field_arr;
diff --git a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
index d091171e52e44be574bade197cb2ce51d162e2b2..f3c4567456ed12046d06e6140eaad19abb70019c 100644
--- a/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
+++ b/libraries/base/dp/src/vhdl/dp_offload_rx_filter_mm.vhd
@@ -66,9 +66,9 @@ architecture str of dp_offload_rx_filter_mm is
constant c_field_slv_out_w : natural := field_slv_out_len(field_arr_set_mode(g_hdr_field_arr , "RW"));
- constant c_nof_ena : natural := 4;
- constant c_reg_w : natural := c_nof_ena * c_word_w;
- constant c_adr_w : natural := ceil_log2(c_nof_ena);
+ constant c_nof_ena : natural := 4;
+ constant c_reg_w : natural := c_nof_ena * c_word_w;
+ constant c_adr_w : natural := ceil_log2(c_nof_ena);
constant c_ena_reg : t_c_mem := (1, c_adr_w, 32, c_nof_ena, '0');
subtype eth_dst_mac_range is natural range field_hi(g_hdr_field_arr, "eth_dst_mac" ) downto field_lo(g_hdr_field_arr, "eth_dst_mac");
@@ -85,13 +85,13 @@ architecture str of dp_offload_rx_filter_mm is
signal mult_streams_mosi_arr : t_mem_mosi_arr(g_nof_streams - 1 downto 0);
signal mult_streams_miso_arr : t_mem_miso_arr(g_nof_streams - 1 downto 0);
- signal common_mosi_arr : t_mem_mosi_arr(1 downto 0);
- signal common_miso_arr : t_mem_miso_arr(1 downto 0);
+ signal common_mosi_arr : t_mem_mosi_arr(1 downto 0);
+ signal common_miso_arr : t_mem_miso_arr(1 downto 0);
type t_bool_arr is array (integer range <>) of boolean;
type t_reg_sig_arr is array (integer range <>) of std_logic_vector(c_reg_w - 1 downto 0);
- signal reg_ena_sig : t_reg_sig_arr(g_nof_streams - 1 downto 0);
+ signal reg_ena_sig : t_reg_sig_arr(g_nof_streams - 1 downto 0);
signal eth_dst_mac_ena : t_bool_arr(g_nof_streams - 1 downto 0);
signal ip_dst_addr_ena : t_bool_arr(g_nof_streams - 1 downto 0);
@@ -165,9 +165,9 @@ begin
end if;
end process;
- -------------------------------------------
- -- mm_fields for MM access to each field --
- -------------------------------------------
+ -------------------------------------------
+ -- mm_fields for MM access to each field --
+ -------------------------------------------
u_mult_mem_mux : entity common_lib.common_mem_mux
generic map (
g_nof_mosi => g_nof_streams,
@@ -194,33 +194,33 @@ begin
);
eth_dst_mac_ena(i) <= is_true(reg_ena_sig(i)(0));
- ip_dst_addr_ena(i) <= is_true(reg_ena_sig(i)(32));
- ip_total_length_ena(i) <= is_true(reg_ena_sig(i)(64));
- udp_dst_port_ena(i) <= is_true(reg_ena_sig(i)(96));
+ ip_dst_addr_ena(i) <= is_true(reg_ena_sig(i)(32));
+ ip_total_length_ena(i) <= is_true(reg_ena_sig(i)(64));
+ udp_dst_port_ena(i) <= is_true(reg_ena_sig(i)(96));
cr : entity common_lib.common_reg_r_w_dc
- generic map(
- g_reg => c_ena_reg
- )
- port map(
- -- Clocks and reset
- mm_rst => mm_rst, -- reset synchronous with mm_clk
- mm_clk => mm_clk, -- memory-mapped bus clock
- st_rst => dp_rst, -- reset synchronous with st_clk
- st_clk => dp_clk, -- other clock domain clock
-
- -- Memory Mapped Slave in mm_clk domain
- sla_in => common_mosi_arr(1), -- IN t_mem_mosi; -- actual ranges defined by g_reg
- sla_out => common_miso_arr(1), -- OUT t_mem_miso; -- actual ranges defined by g_reg
-
- -- MM registers in st_clk domain
- reg_wr_arr => OPEN,
- reg_rd_arr => OPEN,
- in_new => OPEN,
- in_reg => reg_ena_sig(i),
- out_reg => reg_ena_sig(i),
- out_new => open
- );
+ generic map(
+ g_reg => c_ena_reg
+ )
+ port map(
+ -- Clocks and reset
+ mm_rst => mm_rst, -- reset synchronous with mm_clk
+ mm_clk => mm_clk, -- memory-mapped bus clock
+ st_rst => dp_rst, -- reset synchronous with st_clk
+ st_clk => dp_clk, -- other clock domain clock
+
+ -- Memory Mapped Slave in mm_clk domain
+ sla_in => common_mosi_arr(1), -- IN t_mem_mosi; -- actual ranges defined by g_reg
+ sla_out => common_miso_arr(1), -- OUT t_mem_miso; -- actual ranges defined by g_reg
+
+ -- MM registers in st_clk domain
+ reg_wr_arr => OPEN,
+ reg_rd_arr => OPEN,
+ in_new => OPEN,
+ in_reg => reg_ena_sig(i),
+ out_reg => reg_ena_sig(i),
+ out_new => open
+ );
u_mm_fields_slv: entity mm_lib.mm_fields
generic map(
diff --git a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
index 2de0853cc9f7d0b773b10ae9a3b8dd7e0e7944e0..2719bd8d00b80b75538d8847563b05ed71cfddaf 100644
--- a/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
+++ b/libraries/base/dp/src/vhdl/dp_packet_merge.vhd
@@ -95,7 +95,7 @@ architecture rtl of dp_packet_merge is
src_out : t_dp_sosi;
end record;
- constant c_reg_rst : t_reg := (0, 0, 0, '0', '0', (others =>'0'), '0', c_dp_sosi_rst);
+ constant c_reg_rst : t_reg := (0, 0, 0, '0', '0', (others => '0'), '0', c_dp_sosi_rst);
signal r, nxt_r : t_reg;
begin
diff --git a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
index 4cca345bbd35100172c94b8936b40d15d0071eff..cec6ea4536f2372b1e08364bd77a68c4174152a8 100644
--- a/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
+++ b/libraries/base/dp/tb/vhdl/tb_dp_offload_rx_filter.vhd
@@ -52,7 +52,7 @@ end tb_dp_offload_rx_filter;
architecture tb of tb_dp_offload_rx_filter is
constant c_nof_stream : natural := 1;
- constant c_data_w : natural := 64;
+ constant c_data_w : natural := 64;
constant c_correct_mac : std_logic_vector(47 downto 0) := x"FFABCDABCDFF";
constant c_correct_ip : std_logic_vector(31 downto 0) := x"12345678";
@@ -64,7 +64,7 @@ architecture tb of tb_dp_offload_rx_filter is
constant c_wrong_length : natural := 60;
constant c_wrong_port : natural := 4001;
- constant c_nof_packets : natural := 5;
+ constant c_nof_packets : natural := 5;
constant c_nof_hdr_fields : natural := 3 + 12 + 4 + 9 + 1;
constant c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields - 1 downto 0) := ( ( field_name_pad("eth_dst_mac" ), " ", 48, field_default(0) ),
@@ -102,15 +102,15 @@ architecture tb of tb_dp_offload_rx_filter is
----------------------------------------------------------------------------
constant c_dp_clk_period : time := 5 ns;
constant c_nof_streams : positive := 1;
- constant hdr_fields_rst : t_slv_1024_arr(c_nof_streams - 1 downto 0) := (others => (others => '0'));
+ constant hdr_fields_rst : t_slv_1024_arr(c_nof_streams - 1 downto 0) := (others => (others => '0'));
signal dp_rst : std_logic;
signal dp_clk : std_logic := '0';
signal tb_end : std_logic := '0';
- signal toggle : boolean := false;
- signal counter : natural := 0;
+ signal toggle : boolean := false;
+ signal counter : natural := 0;
- signal in_sosi : t_dp_sosi := c_dp_sosi_rst;
+ signal in_sosi : t_dp_sosi := c_dp_sosi_rst;
signal snk_in_arr : t_dp_sosi_arr(c_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
signal snk_out_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0);
signal src_in_arr : t_dp_siso_arr(c_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
@@ -167,20 +167,20 @@ begin
p_special_stimuli : process(in_sosi.sop)
begin
- if in_sosi.sop = '1' then
- counter <= counter + 1;
- if toggle then
- hdr_fields_out_arr <= hdr_fields_in_arr;
- else
- hdr_fields_out_arr <= hdr_fields_wrong_arr;
- end if;
- toggle <= not toggle;
+ if in_sosi.sop = '1' then
+ counter <= counter + 1;
+ if toggle then
+ hdr_fields_out_arr <= hdr_fields_in_arr;
+ else
+ hdr_fields_out_arr <= hdr_fields_wrong_arr;
+ end if;
+ toggle <= not toggle;
else
- hdr_fields_out_arr <= hdr_fields_rst;
+ hdr_fields_out_arr <= hdr_fields_rst;
end if;
- if c_nof_packets + 1 <= counter then
- tb_end <= '1';
+ if c_nof_packets + 1 <= counter then
+ tb_end <= '1';
end if;
end process;
diff --git a/libraries/base/util/src/vhdl/util_heater.vhd b/libraries/base/util/src/vhdl/util_heater.vhd
index 14ca41286efd16db50f0d613e97bf8184b1e6667..170e9ea3629e00dd04c08322cd6290e246525b15 100644
--- a/libraries/base/util/src/vhdl/util_heater.vhd
+++ b/libraries/base/util/src/vhdl/util_heater.vhd
@@ -158,13 +158,13 @@ begin
rst => mm_rst,
clk => mm_clk,
-- control side
- wr_en => sla_in.wr,
- wr_adr => sla_in.address(c_mm_reg.adr_w - 1 downto 0),
- wr_dat => sla_in.wrdata(c_mm_reg.dat_w - 1 downto 0),
- rd_en => sla_in.rd,
- rd_adr => sla_in.address(c_mm_reg.adr_w - 1 downto 0),
- rd_dat => sla_out.rddata(c_mm_reg.dat_w - 1 downto 0),
- rd_val => OPEN,
+ wr_en => sla_in.wr,
+ wr_adr => sla_in.address(c_mm_reg.adr_w - 1 downto 0),
+ wr_dat => sla_in.wrdata(c_mm_reg.dat_w - 1 downto 0),
+ rd_en => sla_in.rd,
+ rd_adr => sla_in.address(c_mm_reg.adr_w - 1 downto 0),
+ rd_dat => sla_out.rddata(c_mm_reg.dat_w - 1 downto 0),
+ rd_val => OPEN,
-- data side
out_reg => mm_reg_en,
in_reg => mm_reg_xor
diff --git a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
index 36d0e53f0d279d8a5c60b57a5345f9e9dc68d65d..2bf2ac6eed13a88a0b68343cbd2732f7024be09e 100644
--- a/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_reorder_sepa_pipe.vhd
@@ -243,7 +243,7 @@ begin
v.rd_en := '0';
case r.state is
- when s_idle =>
+ when s_idle =>
if(next_page = '1') then -- Both counters are reset on page turn.
v.rd_en := '1';
v.switch := '0';
@@ -257,7 +257,7 @@ begin
end if;
end if;
- when s_run_separate =>
+ when s_run_separate =>
v.rd_en := '1';
if(r.switch = '0') then
v.switch := '1';
@@ -293,9 +293,9 @@ begin
v.count_up := r.count_up + 1;
end if;
- when others =>
- v.state := s_idle;
- end case;
+ when others =>
+ v.state := s_idle;
+ end case;
if(rst = '1') then
v.switch := '0';
diff --git a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
index c31e4c188132f18303c3fd9219c07a213af1e46d..de528f689e40a6be6dae7c3cb339612a6ce39182 100644
--- a/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
+++ b/libraries/dsp/fft/src/vhdl/fft_wide_unit_control.vhd
@@ -231,15 +231,15 @@ begin
end if;
case r.state is
- when s_idle =>
- if(in_val = '1') then -- Wait for the first data to arrive
- v.packet_cnt := 0; -- Reset the packet counter
- v.state := s_run;
- end if;
+ when s_idle =>
+ if(in_val = '1') then -- Wait for the first data to arrive
+ v.packet_cnt := 0; -- Reset the packet counter
+ v.state := s_run;
+ end if;
- when s_run =>
- v.val_dly(0) := '1'; -- Assert the valid signal (Stream starts)
- v.packet_cnt := r.packet_cnt + 1; -- Increment the packet-counter when in s_run-state
+ when s_run =>
+ v.val_dly(0) := '1'; -- Assert the valid signal (Stream starts)
+ v.packet_cnt := r.packet_cnt + 1; -- Increment the packet-counter when in s_run-state
if(r.packet_cnt = 0) then -- First sample marks
v.sop_dly(0) := '1'; -- the start of a packet
@@ -257,9 +257,9 @@ begin
v.state := s_run;
end if;
- when others =>
- v.state := s_idle;
- end case;
+ when others =>
+ v.state := s_idle;
+ end case;
if(rst = '1') then
v.out_sosi_arr := (others => c_dp_sosi_rst);
diff --git a/libraries/dsp/si/tb/vhdl/tb_si.vhd b/libraries/dsp/si/tb/vhdl/tb_si.vhd
index 98cc1d9762ef1c18df3e60e9f1f8702a32392934..a55ad221f1b65ead9b630e83c71fdd157a8b323c 100755
--- a/libraries/dsp/si/tb/vhdl/tb_si.vhd
+++ b/libraries/dsp/si/tb/vhdl/tb_si.vhd
@@ -229,7 +229,7 @@ begin
if not (v_clip_even = '1') then
if not (v_clip_odd = '1') then
report "Wrong negate value at valid (v_even = " & int_to_str(v_even) & " v_odd = " & int_to_str(v_odd) severity ERROR;
- end if;
+ end if;
end if;
end if;
end if;
diff --git a/libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd b/libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd
index 94a2a2e126883661dbde81fa438d4d57aef755ff..5c274001c1e8a881ca99be1ac6db46f3d619e1b6 100644
--- a/libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd
+++ b/libraries/dsp/wpfb/quartus_iwave/alma/iwave_synthesis_wpfb_alma.vhd
@@ -23,11 +23,11 @@
-- Design name:
-- . iwave_synthesis_wpfb_alma
-- Purpose:
--- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband
+-- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband
-- statistics and streaming interfaces) synthesis design for iwave Agilex 7
-- (c_tech_agi027_1e1v).
--- . Implements the functionality of the subband filterbank (Fsub) using the
--- ALMA design parameters.
+-- . Implements the functionality of the subband filterbank (Fsub) using the
+-- ALMA design parameters.
-- Description:
-- . The subband filterbank seperates the incoming timestamped ADC samples into
-- ?? (TBD) frequency bands called subbands.
@@ -37,7 +37,7 @@
-- . The number of points of the FFT is ?? (TBD).
-- Description:
-- . The quantized subbands are output (and used for the SST) because it uses more logic.
--- ____
+-- ____
-- | |
-- | |--raw----> X (not included in synthesis)
-- |WPFB|
diff --git a/libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd b/libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd
index a544fcc36137d35bfe532ca703fe7327b4d64e28..a21feab0f6edf3d3fcb9cdfe4d5ff382f6aab701 100644
--- a/libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd
+++ b/libraries/dsp/wpfb/quartus_iwave/lofar2/iwave_synthesis_wpfb_lofar2.vhd
@@ -23,11 +23,11 @@
-- Design name:
-- . iwave_synthesis_wpfb_lofar2
-- Purpose:
--- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband
+-- . Wrapper for wpfb (wideband polyphase filterbank with ports for subband
-- statistics and streaming interfaces) synthesis design for iwave Agilex 7
-- (c_tech_agi027_1e1v).
--- . Implements the functionality of the subband filterbank (Fsub) using the
--- LOFAR2 design parameters.
+-- . Implements the functionality of the subband filterbank (Fsub) using the
+-- LOFAR2 design parameters.
-- Description:
-- . The subband filterbank seperates the incoming timestamped ADC samples into
-- 512 frequency bands called subbands.
@@ -37,7 +37,7 @@
-- . The number of points of the FFT is 1024.
-- Description:
-- . The quantized subbands are output (and used for the SST) because it uses more logic.
--- ____
+-- ____
-- | |
-- | |--raw----> X (not included in synthesis)
-- |WPFB|
diff --git a/libraries/io/ddr/src/vhdl/io_ddr.vhd b/libraries/io/ddr/src/vhdl/io_ddr.vhd
index 9790af79c68b0bf4872809f6b810d5be011dd273..b657a74bb8e3d7b884274c140ea9af064956a173 100644
--- a/libraries/io/ddr/src/vhdl/io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/io_ddr.vhd
@@ -226,7 +226,7 @@ entity io_ddr is
phy4_ou : out t_tech_ddr4_phy_ou;
-- DDR Calibration result
- ddr_cal_ok : out std_logic := '0'
+ ddr_cal_ok : out std_logic := '0'
);
end io_ddr;
diff --git a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
index d8c4ad415829f14fd17d90e6ef9239e365dee73f..d1e8ea65c0915df89726a25673f5351fa86efabe 100644
--- a/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
+++ b/libraries/io/ddr/src/vhdl/mms_io_ddr.vhd
@@ -93,7 +93,7 @@ entity mms_io_ddr is
phy4_ou : out t_tech_ddr4_phy_ou;
-- DDR Calibration result
- ddr_cal_ok : out std_logic := '0'
+ ddr_cal_ok : out std_logic := '0'
);
end mms_io_ddr;
diff --git a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
index 9805ce05f447b20129cfd0ea6e91afebd082efab..183bf84ac08b85d99a027e28330dfa2d9b5e737a 100644
--- a/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
+++ b/libraries/io/ddr3/src/vhdl/ddr3_pkg.vhd
@@ -224,51 +224,51 @@ package ddr3_pkg is
end component;
component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en is
- generic (
- MEM_IF_ADDR_WIDTH : integer := 0;
- MEM_IF_ROW_ADDR_WIDTH : integer := 0;
- MEM_IF_COL_ADDR_WIDTH : integer := 0;
- MEM_IF_CS_PER_RANK : integer := 0;
- MEM_IF_CONTROL_WIDTH : integer := 0;
- MEM_IF_DQS_WIDTH : integer := 0;
- MEM_IF_CS_WIDTH : integer := 0;
- MEM_IF_BANKADDR_WIDTH : integer := 0;
- MEM_IF_DQ_WIDTH : integer := 0;
- MEM_IF_CK_WIDTH : integer := 0;
- MEM_IF_CLK_EN_WIDTH : integer := 0;
- DEVICE_WIDTH : integer := 1;
- MEM_TRCD : integer := 0;
- MEM_TRTP : integer := 0;
- MEM_DQS_TO_CLK_CAPTURE_DELAY : integer := 0;
- MEM_CLK_TO_DQS_CAPTURE_DELAY : integer := 0;
- MEM_IF_ODT_WIDTH : integer := 0;
- MEM_MIRROR_ADDRESSING_DEC : integer := 0;
- MEM_REGDIMM_ENABLED : boolean := false;
- DEVICE_DEPTH : integer := 1;
- MEM_GUARANTEED_WRITE_INIT : boolean := false;
- MEM_VERBOSE : boolean := true;
- MEM_INIT_EN : boolean := false;
- MEM_INIT_FILE : string := "";
- DAT_DATA_WIDTH : integer := 32
- );
- port (
- mem_a : in std_logic_vector(14 downto 0) := (others => 'X'); -- mem_a
- mem_ba : in std_logic_vector(2 downto 0) := (others => 'X'); -- mem_ba
- mem_ck : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ck
- mem_ck_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ck_n
- mem_cke : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_cke
- mem_cs_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_cs_n
- mem_dm : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dm
- mem_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ras_n
- mem_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_cas_n
- mem_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_we_n
- mem_reset_n : in std_logic := 'X'; -- mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_odt : in std_logic_vector(1 downto 0) := (others => 'X') -- mem_odt
- );
- end component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en;
+ generic (
+ MEM_IF_ADDR_WIDTH : integer := 0;
+ MEM_IF_ROW_ADDR_WIDTH : integer := 0;
+ MEM_IF_COL_ADDR_WIDTH : integer := 0;
+ MEM_IF_CS_PER_RANK : integer := 0;
+ MEM_IF_CONTROL_WIDTH : integer := 0;
+ MEM_IF_DQS_WIDTH : integer := 0;
+ MEM_IF_CS_WIDTH : integer := 0;
+ MEM_IF_BANKADDR_WIDTH : integer := 0;
+ MEM_IF_DQ_WIDTH : integer := 0;
+ MEM_IF_CK_WIDTH : integer := 0;
+ MEM_IF_CLK_EN_WIDTH : integer := 0;
+ DEVICE_WIDTH : integer := 1;
+ MEM_TRCD : integer := 0;
+ MEM_TRTP : integer := 0;
+ MEM_DQS_TO_CLK_CAPTURE_DELAY : integer := 0;
+ MEM_CLK_TO_DQS_CAPTURE_DELAY : integer := 0;
+ MEM_IF_ODT_WIDTH : integer := 0;
+ MEM_MIRROR_ADDRESSING_DEC : integer := 0;
+ MEM_REGDIMM_ENABLED : boolean := false;
+ DEVICE_DEPTH : integer := 1;
+ MEM_GUARANTEED_WRITE_INIT : boolean := false;
+ MEM_VERBOSE : boolean := true;
+ MEM_INIT_EN : boolean := false;
+ MEM_INIT_FILE : string := "";
+ DAT_DATA_WIDTH : integer := 32
+ );
+ port (
+ mem_a : in std_logic_vector(14 downto 0) := (others => 'X'); -- mem_a
+ mem_ba : in std_logic_vector(2 downto 0) := (others => 'X'); -- mem_ba
+ mem_ck : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ck
+ mem_ck_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_ck_n
+ mem_cke : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_cke
+ mem_cs_n : in std_logic_vector(1 downto 0) := (others => 'X'); -- mem_cs_n
+ mem_dm : in std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dm
+ mem_ras_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_ras_n
+ mem_cas_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_cas_n
+ mem_we_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_we_n
+ mem_reset_n : in std_logic := 'X'; -- mem_reset_n
+ mem_dq : inout std_logic_vector(63 downto 0) := (others => 'X'); -- mem_dq
+ mem_dqs : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(7 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_odt : in std_logic_vector(1 downto 0) := (others => 'X') -- mem_odt
+ );
+ end component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en;
end ddr3_pkg;
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
index 4c6005a9a84132cd378bb8e1c011ca4bf8ffc0dc..e86d259cb1118eb2e4d5901137f7c6c0d54cf14a 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3.vhd
@@ -187,55 +187,55 @@ begin
gen_uphy_4g_model : if c_phy > 0 generate
u_4gb_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
- generic map (
- MEM_IF_ADDR_WIDTH => 15,
- MEM_IF_ROW_ADDR_WIDTH => 15,
- MEM_IF_COL_ADDR_WIDTH => 10,
- MEM_IF_CS_PER_RANK => 1,
- MEM_IF_CONTROL_WIDTH => 1,
- MEM_IF_DQS_WIDTH => 8,
- MEM_IF_CS_WIDTH => 2,
- MEM_IF_BANKADDR_WIDTH => 3,
- MEM_IF_DQ_WIDTH => 64,
- MEM_IF_CK_WIDTH => 2,
- MEM_IF_CLK_EN_WIDTH => 2,
- DEVICE_WIDTH => 1,
- MEM_TRCD => 6,
- MEM_TRTP => 3,
- MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
- MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
- MEM_IF_ODT_WIDTH => 2,
- MEM_MIRROR_ADDRESSING_DEC => 0,
- MEM_REGDIMM_ENABLED => false,
- DEVICE_DEPTH => 1,
- MEM_GUARANTEED_WRITE_INIT => false,
- MEM_VERBOSE => true,
- MEM_INIT_EN => false,
- MEM_INIT_FILE => "",
- DAT_DATA_WIDTH => 32
- )
- port map (
- mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0), -- memory.mem_a
- mem_ba => phy_ou.ba, -- .mem_ba
- mem_ck => phy_ou.ck, -- .mem_ck
- mem_ck_n => phy_ou.ck_n, -- .mem_ck_n
- mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0), -- .mem_cke
- mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0), -- .mem_cs_n
- mem_dm => phy_ou.dm, -- .mem_dm
- mem_ras_n => ras_n, -- .mem_ras_n
- mem_cas_n => cas_n, -- .mem_cas_n
- mem_we_n => we_n, -- .mem_we_n
- mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
- mem_dq => phy_io.dq, -- .mem_dq
- mem_dqs => phy_io.dqs, -- .mem_dqs
- mem_dqs_n => phy_io.dqs_n, -- .mem_dqs_n
- mem_odt => phy_ou.odt -- .mem_odt
- );
-
- ras_n(0) <= phy_ou.ras_n;
- cas_n(0) <= phy_ou.cas_n;
- we_n(0) <= phy_ou.we_n;
- end generate;
+ generic map (
+ MEM_IF_ADDR_WIDTH => 15,
+ MEM_IF_ROW_ADDR_WIDTH => 15,
+ MEM_IF_COL_ADDR_WIDTH => 10,
+ MEM_IF_CS_PER_RANK => 1,
+ MEM_IF_CONTROL_WIDTH => 1,
+ MEM_IF_DQS_WIDTH => 8,
+ MEM_IF_CS_WIDTH => 2,
+ MEM_IF_BANKADDR_WIDTH => 3,
+ MEM_IF_DQ_WIDTH => 64,
+ MEM_IF_CK_WIDTH => 2,
+ MEM_IF_CLK_EN_WIDTH => 2,
+ DEVICE_WIDTH => 1,
+ MEM_TRCD => 6,
+ MEM_TRTP => 3,
+ MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+ MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+ MEM_IF_ODT_WIDTH => 2,
+ MEM_MIRROR_ADDRESSING_DEC => 0,
+ MEM_REGDIMM_ENABLED => false,
+ DEVICE_DEPTH => 1,
+ MEM_GUARANTEED_WRITE_INIT => false,
+ MEM_VERBOSE => true,
+ MEM_INIT_EN => false,
+ MEM_INIT_FILE => "",
+ DAT_DATA_WIDTH => 32
+ )
+ port map (
+ mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0), -- memory.mem_a
+ mem_ba => phy_ou.ba, -- .mem_ba
+ mem_ck => phy_ou.ck, -- .mem_ck
+ mem_ck_n => phy_ou.ck_n, -- .mem_ck_n
+ mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0), -- .mem_cke
+ mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0), -- .mem_cs_n
+ mem_dm => phy_ou.dm, -- .mem_dm
+ mem_ras_n => ras_n, -- .mem_ras_n
+ mem_cas_n => cas_n, -- .mem_cas_n
+ mem_we_n => we_n, -- .mem_we_n
+ mem_reset_n => phy_ou.reset_n, -- .mem_reset_n
+ mem_dq => phy_io.dq, -- .mem_dq
+ mem_dqs => phy_io.dqs, -- .mem_dqs
+ mem_dqs_n => phy_io.dqs_n, -- .mem_dqs_n
+ mem_odt => phy_ou.odt -- .mem_odt
+ );
+
+ ras_n(0) <= phy_ou.ras_n;
+ cas_n(0) <= phy_ou.cas_n;
+ we_n(0) <= phy_ou.we_n;
+ end generate;
u_ddr3_module: entity work.ddr3
generic map(
diff --git a/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
index a9e1cb53c3872c3e5cddc1c6e95ae51db0e4dfe1..b44a81f3899dbaf5c4ef30e0ffb6fc62b17eecc4 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_ddr3_transpose.vhd
@@ -296,54 +296,54 @@ begin
);
u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
- generic map (
- MEM_IF_ADDR_WIDTH => 15,
- MEM_IF_ROW_ADDR_WIDTH => 15,
- MEM_IF_COL_ADDR_WIDTH => 10,
- MEM_IF_CS_PER_RANK => 1,
- MEM_IF_CONTROL_WIDTH => 1,
- MEM_IF_DQS_WIDTH => 8,
- MEM_IF_CS_WIDTH => 2,
- MEM_IF_BANKADDR_WIDTH => 3,
- MEM_IF_DQ_WIDTH => 64,
- MEM_IF_CK_WIDTH => 2,
- MEM_IF_CLK_EN_WIDTH => 2,
- DEVICE_WIDTH => 1,
- MEM_TRCD => 6,
- MEM_TRTP => 3,
- MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
- MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
- MEM_IF_ODT_WIDTH => 2,
- MEM_MIRROR_ADDRESSING_DEC => 0,
- MEM_REGDIMM_ENABLED => false,
- DEVICE_DEPTH => 1,
- MEM_GUARANTEED_WRITE_INIT => false,
- MEM_VERBOSE => true,
- MEM_INIT_EN => false,
- MEM_INIT_FILE => "",
- DAT_DATA_WIDTH => 32
- )
- port map (
- mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0),
- mem_ba => phy_ou.ba,
- mem_ck => phy_ou.ck,
- mem_ck_n => phy_ou.ck_n,
- mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0),
- mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0),
- mem_dm => phy_ou.dm,
- mem_ras_n => ras_n,
- mem_cas_n => cas_n,
- mem_we_n => we_n,
- mem_reset_n => phy_ou.reset_n,
- mem_dq => phy_io.dq,
- mem_dqs => phy_io.dqs,
- mem_dqs_n => phy_io.dqs_n,
- mem_odt => phy_ou.odt
- );
-
- ras_n(0) <= phy_ou.ras_n;
- cas_n(0) <= phy_ou.cas_n;
- we_n(0) <= phy_ou.we_n;
+ generic map (
+ MEM_IF_ADDR_WIDTH => 15,
+ MEM_IF_ROW_ADDR_WIDTH => 15,
+ MEM_IF_COL_ADDR_WIDTH => 10,
+ MEM_IF_CS_PER_RANK => 1,
+ MEM_IF_CONTROL_WIDTH => 1,
+ MEM_IF_DQS_WIDTH => 8,
+ MEM_IF_CS_WIDTH => 2,
+ MEM_IF_BANKADDR_WIDTH => 3,
+ MEM_IF_DQ_WIDTH => 64,
+ MEM_IF_CK_WIDTH => 2,
+ MEM_IF_CLK_EN_WIDTH => 2,
+ DEVICE_WIDTH => 1,
+ MEM_TRCD => 6,
+ MEM_TRTP => 3,
+ MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+ MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+ MEM_IF_ODT_WIDTH => 2,
+ MEM_MIRROR_ADDRESSING_DEC => 0,
+ MEM_REGDIMM_ENABLED => false,
+ DEVICE_DEPTH => 1,
+ MEM_GUARANTEED_WRITE_INIT => false,
+ MEM_VERBOSE => true,
+ MEM_INIT_EN => false,
+ MEM_INIT_FILE => "",
+ DAT_DATA_WIDTH => 32
+ )
+ port map (
+ mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0),
+ mem_ba => phy_ou.ba,
+ mem_ck => phy_ou.ck,
+ mem_ck_n => phy_ou.ck_n,
+ mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0),
+ mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0),
+ mem_dm => phy_ou.dm,
+ mem_ras_n => ras_n,
+ mem_cas_n => cas_n,
+ mem_we_n => we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq,
+ mem_dqs => phy_io.dqs,
+ mem_dqs_n => phy_io.dqs_n,
+ mem_odt => phy_ou.odt
+ );
+
+ ras_n(0) <= phy_ou.ras_n;
+ cas_n(0) <= phy_ou.cas_n;
+ we_n(0) <= phy_ou.we_n;
----------------------------------------------------------------------------
-- Sink: data buffer real
diff --git a/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
index 36e13b7c4385aabb52983a03d86ae9f6905b389e..a9a3c3afa35cafcd07d86a12bee6162c4c78f6c3 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_mms_ddr3.vhd
@@ -284,54 +284,54 @@ begin
gen_u_800_model : if c_phy > 0 generate
u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
- generic map (
- MEM_IF_ADDR_WIDTH => 15,
- MEM_IF_ROW_ADDR_WIDTH => 15,
- MEM_IF_COL_ADDR_WIDTH => 10,
- MEM_IF_CS_PER_RANK => 1,
- MEM_IF_CONTROL_WIDTH => 1,
- MEM_IF_DQS_WIDTH => 8,
- MEM_IF_CS_WIDTH => 2,
- MEM_IF_BANKADDR_WIDTH => 3,
- MEM_IF_DQ_WIDTH => 64,
- MEM_IF_CK_WIDTH => 2,
- MEM_IF_CLK_EN_WIDTH => 2,
- DEVICE_WIDTH => 1,
- MEM_TRCD => 6,
- MEM_TRTP => 3,
- MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
- MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
- MEM_IF_ODT_WIDTH => 2,
- MEM_MIRROR_ADDRESSING_DEC => 0,
- MEM_REGDIMM_ENABLED => false,
- DEVICE_DEPTH => 1,
- MEM_GUARANTEED_WRITE_INIT => false,
- MEM_VERBOSE => true,
- MEM_INIT_EN => false,
- MEM_INIT_FILE => "",
- DAT_DATA_WIDTH => 32
- )
- port map (
- mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0),
- mem_ba => phy_ou.ba,
- mem_ck => phy_ou.ck,
- mem_ck_n => phy_ou.ck_n,
- mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0),
- mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0),
- mem_dm => phy_ou.dm,
- mem_ras_n => ras_n,
- mem_cas_n => cas_n,
- mem_we_n => we_n,
- mem_reset_n => phy_ou.reset_n,
- mem_dq => phy_io.dq,
- mem_dqs => phy_io.dqs,
- mem_dqs_n => phy_io.dqs_n,
- mem_odt => phy_ou.odt
- );
-
- ras_n(0) <= phy_ou.ras_n;
- cas_n(0) <= phy_ou.cas_n;
- we_n(0) <= phy_ou.we_n;
+ generic map (
+ MEM_IF_ADDR_WIDTH => 15,
+ MEM_IF_ROW_ADDR_WIDTH => 15,
+ MEM_IF_COL_ADDR_WIDTH => 10,
+ MEM_IF_CS_PER_RANK => 1,
+ MEM_IF_CONTROL_WIDTH => 1,
+ MEM_IF_DQS_WIDTH => 8,
+ MEM_IF_CS_WIDTH => 2,
+ MEM_IF_BANKADDR_WIDTH => 3,
+ MEM_IF_DQ_WIDTH => 64,
+ MEM_IF_CK_WIDTH => 2,
+ MEM_IF_CLK_EN_WIDTH => 2,
+ DEVICE_WIDTH => 1,
+ MEM_TRCD => 6,
+ MEM_TRTP => 3,
+ MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+ MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+ MEM_IF_ODT_WIDTH => 2,
+ MEM_MIRROR_ADDRESSING_DEC => 0,
+ MEM_REGDIMM_ENABLED => false,
+ DEVICE_DEPTH => 1,
+ MEM_GUARANTEED_WRITE_INIT => false,
+ MEM_VERBOSE => true,
+ MEM_INIT_EN => false,
+ MEM_INIT_FILE => "",
+ DAT_DATA_WIDTH => 32
+ )
+ port map (
+ mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0),
+ mem_ba => phy_ou.ba,
+ mem_ck => phy_ou.ck,
+ mem_ck_n => phy_ou.ck_n,
+ mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0),
+ mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0),
+ mem_dm => phy_ou.dm,
+ mem_ras_n => ras_n,
+ mem_cas_n => cas_n,
+ mem_we_n => we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq,
+ mem_dqs => phy_io.dqs,
+ mem_dqs_n => phy_io.dqs_n,
+ mem_odt => phy_ou.odt
+ );
+
+ ras_n(0) <= phy_ou.ras_n;
+ cas_n(0) <= phy_ou.cas_n;
+ we_n(0) <= phy_ou.we_n;
end generate;
----------------------------------------------------------------------------
diff --git a/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
index fc800b38d513edd0b609061c21a99684ed293e9b..b24955d3a4dc34611e104eb9c9e91cea431b48bd 100644
--- a/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
+++ b/libraries/io/ddr3/tb/vhdl/tb_seq_ddr3.vhd
@@ -267,54 +267,54 @@ begin
gen_u_800_model : if c_phy > 0 generate
u_4gb_800_ddr3_model : component alt_mem_if_ddr3_mem_model_top_ddr3_mem_if_dm_pins_en_mem_if_dqsn_en
- generic map (
- MEM_IF_ADDR_WIDTH => 15,
- MEM_IF_ROW_ADDR_WIDTH => 15,
- MEM_IF_COL_ADDR_WIDTH => 10,
- MEM_IF_CS_PER_RANK => 1,
- MEM_IF_CONTROL_WIDTH => 1,
- MEM_IF_DQS_WIDTH => 8,
- MEM_IF_CS_WIDTH => 2,
- MEM_IF_BANKADDR_WIDTH => 3,
- MEM_IF_DQ_WIDTH => 64,
- MEM_IF_CK_WIDTH => 2,
- MEM_IF_CLK_EN_WIDTH => 2,
- DEVICE_WIDTH => 1,
- MEM_TRCD => 6,
- MEM_TRTP => 3,
- MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
- MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
- MEM_IF_ODT_WIDTH => 2,
- MEM_MIRROR_ADDRESSING_DEC => 0,
- MEM_REGDIMM_ENABLED => false,
- DEVICE_DEPTH => 1,
- MEM_GUARANTEED_WRITE_INIT => false,
- MEM_VERBOSE => true,
- MEM_INIT_EN => false,
- MEM_INIT_FILE => "",
- DAT_DATA_WIDTH => 32
- )
- port map (
- mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0),
- mem_ba => phy_ou.ba,
- mem_ck => phy_ou.ck,
- mem_ck_n => phy_ou.ck_n,
- mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0),
- mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0),
- mem_dm => phy_ou.dm,
- mem_ras_n => ras_n,
- mem_cas_n => cas_n,
- mem_we_n => we_n,
- mem_reset_n => phy_ou.reset_n,
- mem_dq => phy_io.dq,
- mem_dqs => phy_io.dqs,
- mem_dqs_n => phy_io.dqs_n,
- mem_odt => phy_ou.odt
- );
-
- ras_n(0) <= phy_ou.ras_n;
- cas_n(0) <= phy_ou.cas_n;
- we_n(0) <= phy_ou.we_n;
+ generic map (
+ MEM_IF_ADDR_WIDTH => 15,
+ MEM_IF_ROW_ADDR_WIDTH => 15,
+ MEM_IF_COL_ADDR_WIDTH => 10,
+ MEM_IF_CS_PER_RANK => 1,
+ MEM_IF_CONTROL_WIDTH => 1,
+ MEM_IF_DQS_WIDTH => 8,
+ MEM_IF_CS_WIDTH => 2,
+ MEM_IF_BANKADDR_WIDTH => 3,
+ MEM_IF_DQ_WIDTH => 64,
+ MEM_IF_CK_WIDTH => 2,
+ MEM_IF_CLK_EN_WIDTH => 2,
+ DEVICE_WIDTH => 1,
+ MEM_TRCD => 6,
+ MEM_TRTP => 3,
+ MEM_DQS_TO_CLK_CAPTURE_DELAY => 100,
+ MEM_CLK_TO_DQS_CAPTURE_DELAY => 100000,
+ MEM_IF_ODT_WIDTH => 2,
+ MEM_MIRROR_ADDRESSING_DEC => 0,
+ MEM_REGDIMM_ENABLED => false,
+ DEVICE_DEPTH => 1,
+ MEM_GUARANTEED_WRITE_INIT => false,
+ MEM_VERBOSE => true,
+ MEM_INIT_EN => false,
+ MEM_INIT_FILE => "",
+ DAT_DATA_WIDTH => 32
+ )
+ port map (
+ mem_a => phy_ou.a(c_ddr.a_w - 1 downto 0),
+ mem_ba => phy_ou.ba,
+ mem_ck => phy_ou.ck,
+ mem_ck_n => phy_ou.ck_n,
+ mem_cke => phy_ou.cke(c_ddr.cs_w - 1 downto 0),
+ mem_cs_n => phy_ou.cs_n(c_ddr.cs_w - 1 downto 0),
+ mem_dm => phy_ou.dm,
+ mem_ras_n => ras_n,
+ mem_cas_n => cas_n,
+ mem_we_n => we_n,
+ mem_reset_n => phy_ou.reset_n,
+ mem_dq => phy_io.dq,
+ mem_dqs => phy_io.dqs,
+ mem_dqs_n => phy_io.dqs_n,
+ mem_odt => phy_ou.odt
+ );
+
+ ras_n(0) <= phy_ou.ras_n;
+ cas_n(0) <= phy_ou.cas_n;
+ we_n(0) <= phy_ou.we_n;
end generate;
----------------------------------------------------------------------------
diff --git a/libraries/io/epcs/src/vhdl/mms_epcs.vhd b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
index d7c837f85891751e521a4e7b9a3743d6d1db465f..8857f04d280aaa1872463ce4909ba0f39a8946f8 100644
--- a/libraries/io/epcs/src/vhdl/mms_epcs.vhd
+++ b/libraries/io/epcs/src/vhdl/mms_epcs.vhd
@@ -233,20 +233,20 @@ begin
g_sim_flash_model => g_sim_flash_model
)
port map (
- addr => epcs_in_addr,
- clkin => epcs_clk,
- datain => epcs_in_datain,
- rden => epcs_in_rden,
- read => epcs_in_read,
- shift_bytes => epcs_in_shift_bytes,
- wren => epcs_in_wren,
- write => epcs_in_write,
+ addr => epcs_in_addr,
+ clkin => epcs_clk,
+ datain => epcs_in_datain,
+ rden => epcs_in_rden,
+ read => epcs_in_read,
+ shift_bytes => epcs_in_shift_bytes,
+ wren => epcs_in_wren,
+ write => epcs_in_write,
sector_erase => epcs_in_sector_erase,
- busy => epcs_out_busy,
- data_valid => nxt_epcs_out_data_valid,
- dataout => nxt_epcs_out_dataout,
- illegal_write => OPEN,
+ busy => epcs_out_busy,
+ data_valid => nxt_epcs_out_data_valid,
+ dataout => nxt_epcs_out_dataout,
+ illegal_write => OPEN,
illegal_erase => open
);
diff --git a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
index a607d66323baea9c444ddb34f40d2d2ac0fc8256..13ea9c3fd54eedf0bbb0fe7cdcd05866fefd909f 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/src/vhdl/unb1_eth_10g.vhd
@@ -626,7 +626,7 @@ begin
-----------------------------------------------------------------------------
u_header_check : entity dp_lib.dp_offload_rx_filter_mm
generic map(
- g_bypass => c_bypass_rx_filter,
+ g_bypass => c_bypass_rx_filter,
g_nof_streams => c_nof_streams, -- : POSITIVE;
g_data_w => c_data_w, -- : NATURAL;
g_hdr_field_arr => c_hdr_field_arr -- : t_common_field_arr
diff --git a/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd b/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd
index c5c71f81fa43ba7a20ca0d14a1c3fa3a97b55141..4ea3670f96cad7049b7641eb36a9b36a47dbbb98 100644
--- a/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd
+++ b/libraries/io/eth/designs/unb1_eth_10g/tb/vhdl/tb_unb1_eth_10g.vhd
@@ -79,8 +79,8 @@ architecture tb of tb_unb1_eth_10g is
signal si_fn_3_lcu_rx : std_logic_vector(c_unb1_board_ci.tr.bus_w - 1 downto 0);
signal VERSION : std_logic_vector(c_unb1_board_aux.version_w - 1 downto 0) := c_version;
- signal ID_lcu : std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0) := c_id_lcu;
- signal ID_dut : std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0) := c_id_dut;
+ signal ID_lcu : std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0) := c_id_lcu;
+ signal ID_dut : std_logic_vector(c_unb1_board_aux.id_w - 1 downto 0) := c_id_dut;
begin
----------------------------------------------------------------------------
-- Externally generated clocks
diff --git a/libraries/io/eth/src/vhdl/eth_ip_offload_tx.vhd b/libraries/io/eth/src/vhdl/eth_ip_offload_tx.vhd
index f4e4c935f61481f4a2e827155375f20ff7647093..1e9df7d5dbbef043478a4d03bd5fb3b71486fb3b 100644
--- a/libraries/io/eth/src/vhdl/eth_ip_offload_tx.vhd
+++ b/libraries/io/eth/src/vhdl/eth_ip_offload_tx.vhd
@@ -19,11 +19,11 @@
-------------------------------------------------------------------------------
-- Author: R. van der Walle
-- Purpose:
--- . concatenate header from hdr_fields_in_arr to incoming sosi stream and
+-- . concatenate header from hdr_fields_in_arr to incoming sosi stream and
-- calculate + insert ip header checksum (crc).
-- Description:
-- . dp_offload_tx_v3 is used to concatenate the header to the dp sosi stream.
--- . eth_ip_header_checksum is used to calculate and insert the ip header
+-- . eth_ip_header_checksum is used to calculate and insert the ip header
-- checksum.
library IEEE, common_lib, dp_lib;
use IEEE.std_logic_1164.all;
@@ -65,8 +65,8 @@ end eth_ip_offload_tx;
architecture str of eth_ip_offload_tx is
- signal dp_offload_tx_src_out_arr : t_dp_sosi_arr(g_nof_streams-1 downto 0) := (others => c_dp_sosi_rst);
- signal dp_offload_tx_src_in_arr : t_dp_siso_arr(g_nof_streams-1 downto 0) := (others => c_dp_siso_rdy);
+ signal dp_offload_tx_src_out_arr : t_dp_sosi_arr(g_nof_streams - 1 downto 0) := (others => c_dp_sosi_rst);
+ signal dp_offload_tx_src_in_arr : t_dp_siso_arr(g_nof_streams - 1 downto 0) := (others => c_dp_siso_rdy);
signal dp_offload_tx_hdr_fields_out_arr : t_slv_1024_arr(g_nof_streams - 1 downto 0);
begin
diff --git a/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd b/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
index 389c96fb2fa8618a86ac1229b8741c4a48083abb..161690a8c80cf2bc2b2b1606f16a7a4d51825a5a 100644
--- a/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
+++ b/libraries/io/i2c/src/vhdl/avs_i2c_master.vhd
@@ -159,6 +159,6 @@ begin
-- I2C interface
---------------------------------------------------------------------------
scl => coe_i2c_scl_export,
- sda => coe_i2c_sda_export
+ sda => coe_i2c_sda_export
);
end wrap;
diff --git a/libraries/io/i2c/src/vhdl/i2c_master.vhd b/libraries/io/i2c/src/vhdl/i2c_master.vhd
index 668aea77ac905d5fbf22335b22622944e047bd63..161766315cab44b5f0dd6d1ff538d81b093c9539 100644
--- a/libraries/io/i2c/src/vhdl/i2c_master.vhd
+++ b/libraries/io/i2c/src/vhdl/i2c_master.vhd
@@ -68,7 +68,7 @@ entity i2c_master is
-- I2C interface
---------------------------------------------------------------------------
scl : inout std_logic; -- I2C Serial Clock Line
- sda : inout std_logic -- I2C Serial Data Line
+ sda : inout std_logic -- I2C Serial Data Line
);
end i2c_master;
diff --git a/libraries/io/i2c/src/vhdl/i2cslave.vhd b/libraries/io/i2c/src/vhdl/i2cslave.vhd
index 47e65a0c3ec93cb3272c7a7eed7685bbc2065eaf..17f2ffc61d05f31c794032a85f6d5161080f8088 100644
--- a/libraries/io/i2c/src/vhdl/i2cslave.vhd
+++ b/libraries/io/i2c/src/vhdl/i2cslave.vhd
@@ -36,7 +36,7 @@ entity i2cslave is
);
port(
clk : in std_logic; -- system clock (clk freq >> SCL freq)
- SDA : inout std_logic; -- I2C Serial Data Line
+ SDA : inout std_logic; -- I2C Serial Data Line
SCL : in std_logic; -- I2C Serial Clock Line
RST : in std_logic; -- optional reset bit
CTRL_REG : out std_logic_vector(8 * g_nof_ctrl_bytes - 1 downto 0) -- ctrl for RCU control
diff --git a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
index 1b7e84b0e8f82a03c95af3a162dea3c0205b92c6..8164e1904075ccf4b1000a7e98026b5186f75cff 100644
--- a/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_max1618.vhd
@@ -56,7 +56,7 @@ begin
g_address => g_address
)
port map (
- scl => scl,
+ scl => scl,
sda => sda,
en => enable,
p => stop,
diff --git a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
index 65a3f2c7bcfd3786a0b46597a5911e9d03c716a1..aff2b064be12a3b3f7156ab08baaf4de5d2f18a9 100644
--- a/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
+++ b/libraries/io/i2c/tb/vhdl/dev_pmbus.vhd
@@ -61,7 +61,7 @@ begin
g_address => g_address
)
port map (
- scl => scl,
+ scl => scl,
sda => sda,
en => enable,
p => stop,
diff --git a/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd b/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
index 10a8d997b3d72b622df0b38e5b167af4011a3dc9..e9abd230aeea0c0f0eb27663e407218abc9420eb 100644
--- a/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
+++ b/libraries/io/i2c/tb/vhdl/tb_avs_i2c_master.vhd
@@ -27,39 +27,39 @@ entity tb_avs_i2c_master is
end tb_avs_i2c_master;
architecture tb of tb_avs_i2c_master is
- component avs_i2c_master is
- generic (
- g_control_adr_w : natural := 1;
- g_protocol_adr_w : natural := 10;
- g_result_adr_w : natural := 10;
- g_clk_cnt : natural := 399;
- g_comma_w : natural := 0
- );
- port (
- coe_gs_sim_export : in std_logic := 'X'; -- gs_sim.export
- coe_sync_export : in std_logic := 'X'; -- sync.export
- coe_i2c_scl_export : inout std_logic := 'X'; -- i2c_scl.export
- coe_i2c_sda_export : inout std_logic := 'X'; -- i2c_sda.export
- csi_system_reset : in std_logic := 'X'; -- system.reset
- csi_system_clk : in std_logic := 'X'; -- .clk
- avs_control_address : in std_logic := 'X'; -- control.address
- avs_control_write : in std_logic := 'X'; -- .write
- avs_control_read : in std_logic := 'X'; -- .read
- avs_control_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- .writedata
- avs_control_readdata : out std_logic_vector(31 downto 0); -- .readdata
- avs_protocol_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- protocol.address
- avs_protocol_write : in std_logic := 'X'; -- .write
- avs_protocol_read : in std_logic := 'X'; -- .read
- avs_protocol_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- .writedata
- avs_protocol_readdata : out std_logic_vector(7 downto 0); -- .readdata
- avs_result_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- result.address
- avs_result_write : in std_logic := 'X'; -- .write
- avs_result_read : in std_logic := 'X'; -- .read
- avs_result_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- .writedata
- avs_result_readdata : out std_logic_vector(7 downto 0); -- .readdata
- ins_interrupt_irq : out std_logic -- interrupt.irq
- );
- end component avs_i2c_master;
+ component avs_i2c_master is
+ generic (
+ g_control_adr_w : natural := 1;
+ g_protocol_adr_w : natural := 10;
+ g_result_adr_w : natural := 10;
+ g_clk_cnt : natural := 399;
+ g_comma_w : natural := 0
+ );
+ port (
+ coe_gs_sim_export : in std_logic := 'X'; -- gs_sim.export
+ coe_sync_export : in std_logic := 'X'; -- sync.export
+ coe_i2c_scl_export : inout std_logic := 'X'; -- i2c_scl.export
+ coe_i2c_sda_export : inout std_logic := 'X'; -- i2c_sda.export
+ csi_system_reset : in std_logic := 'X'; -- system.reset
+ csi_system_clk : in std_logic := 'X'; -- .clk
+ avs_control_address : in std_logic := 'X'; -- control.address
+ avs_control_write : in std_logic := 'X'; -- .write
+ avs_control_read : in std_logic := 'X'; -- .read
+ avs_control_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- .writedata
+ avs_control_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ avs_protocol_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- protocol.address
+ avs_protocol_write : in std_logic := 'X'; -- .write
+ avs_protocol_read : in std_logic := 'X'; -- .read
+ avs_protocol_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- .writedata
+ avs_protocol_readdata : out std_logic_vector(7 downto 0); -- .readdata
+ avs_result_address : in std_logic_vector(9 downto 0) := (others => 'X'); -- result.address
+ avs_result_write : in std_logic := 'X'; -- .write
+ avs_result_read : in std_logic := 'X'; -- .read
+ avs_result_writedata : in std_logic_vector(7 downto 0) := (others => 'X'); -- .writedata
+ avs_result_readdata : out std_logic_vector(7 downto 0); -- .readdata
+ ins_interrupt_irq : out std_logic -- interrupt.irq
+ );
+ end component avs_i2c_master;
constant c_clk_period : time := 5 ns;
diff --git a/libraries/io/mdio/src/vhdl/mdio_mm.vhd b/libraries/io/mdio/src/vhdl/mdio_mm.vhd
index 676c286d001db22c91d0610c8ec06fa56e4e74ca..ab88cab7d7fac105be5bec630bb3c5e5f609796b 100644
--- a/libraries/io/mdio/src/vhdl/mdio_mm.vhd
+++ b/libraries/io/mdio/src/vhdl/mdio_mm.vhd
@@ -112,16 +112,16 @@ begin
g_reg => c_reg_mdio
)
port map (
- rst => rst,
- clk => clk,
+ rst => rst,
+ clk => clk,
-- control side
- wr_en => mms_header_write,
- wr_adr => mms_header_address,
- wr_dat => mms_header_writedata,
- rd_en => mms_header_read,
- rd_adr => mms_header_address,
- rd_dat => mms_header_readdata,
- rd_val => OPEN,
+ wr_en => mms_header_write,
+ wr_adr => mms_header_address,
+ wr_dat => mms_header_writedata,
+ rd_en => mms_header_read,
+ rd_adr => mms_header_address,
+ rd_dat => mms_header_readdata,
+ rd_val => OPEN,
-- data side
out_reg => reg_header,
in_reg => reg_header
@@ -132,16 +132,16 @@ begin
g_reg => c_reg_mdio
)
port map (
- rst => rst,
- clk => clk,
+ rst => rst,
+ clk => clk,
-- control side
- wr_en => mms_data_write,
- wr_adr => mms_data_address,
- wr_dat => mms_data_writedata,
- rd_en => mms_data_read,
- rd_adr => mms_data_address,
- rd_dat => mms_data_readdata,
- rd_val => OPEN,
+ wr_en => mms_data_write,
+ wr_adr => mms_data_address,
+ wr_dat => mms_data_writedata,
+ rd_en => mms_data_read,
+ rd_adr => mms_data_address,
+ rd_dat => mms_data_readdata,
+ rd_val => OPEN,
-- data side
out_reg => reg_data,
in_reg => reg_data_rd
diff --git a/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd b/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
index 8ac3fed9ca7866758fa272180339a59b80b0e779..68ae9d4465de635402da33deb05b02f002911906 100644
--- a/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
+++ b/libraries/io/nw_10GbE/src/vhdl/nw_ping_response.vhd
@@ -136,12 +136,12 @@ begin
v.ip_sum := r.ip_sum
+ unsigned(r.hdr_response(1)(c_halfword_w - 1 downto 0)) -- ip_version, ip_header_length, ip_services
+ unsigned(r.hdr_response(2)(c_halfword_w * 4 - 1 downto c_halfword_w * 3)) -- ip_total_length
- + unsigned(r.hdr_response(2)(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_identification
- + unsigned(r.hdr_response(2)(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_flags, ip_fragment_offset
- + unsigned(r.hdr_response(2)(c_halfword_w - 1 downto 0)) -- ip_time_to_live, ip_protocol
+ + unsigned(r.hdr_response(2)(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_identification
+ + unsigned(r.hdr_response(2)(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_flags, ip_fragment_offset
+ + unsigned(r.hdr_response(2)(c_halfword_w - 1 downto 0)) -- ip_time_to_live, ip_protocol
+ unsigned(r.hdr_response(3)(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_src_addr(1/2)
- + unsigned(r.hdr_response(3)(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_src_addr(2/2)
- + unsigned(r.hdr_response(3)(c_halfword_w - 1 downto 0)) -- ip_dst_addr(1/2)
+ + unsigned(r.hdr_response(3)(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_src_addr(2/2)
+ + unsigned(r.hdr_response(3)(c_halfword_w - 1 downto 0)) -- ip_dst_addr(1/2)
+ unsigned(r.hdr_response(4)(c_halfword_w * 4 - 1 downto c_halfword_w * 3)); -- ip_dst_addr(2/2)
when s_output => -- Send out ICMP response
diff --git a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
index b2627f65513f6f29b508d2c955a5481241cb0755..8f3cb7ed8bbe5c4008b82ed178992f6ba7ba1d36 100644
--- a/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
+++ b/libraries/io/tr_10GbE/src/vhdl/tr_10GbE_ip_checksum.vhd
@@ -72,23 +72,23 @@ begin
sum <= (others => '0');
elsif cnt_en = '1' then
- case TO_UINT(count) is
- when 0 => -- 0 is the cycle after the sop due to the common_counter latency
- sum <= sum + unsigned(snk_in.data(c_halfword_w - 1 downto 0)); -- ip_version, ip_header_length, ip_services
- when 1 =>
- sum <= sum + unsigned(snk_in.data(c_halfword_w * 4 - 1 downto c_halfword_w * 3)) -- ip_total_length
- + unsigned(snk_in.data(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_identification
- + unsigned(snk_in.data(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_flags, ip_fragment_offset
- + unsigned(snk_in.data(c_halfword_w - 1 downto 0)); -- ip_time_to_live, ip_protocol
- when 2 => -- skip ip_header_checksum
- sum <= sum + unsigned(snk_in.data(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_src_addr(1/2)
- + unsigned(snk_in.data(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_src_addr(2/2)
- + unsigned(snk_in.data(c_halfword_w - 1 downto 0)); -- ip_dst_addr(1/2)
- when 3 =>
- sum <= sum + unsigned(snk_in.data(c_halfword_w * 4 - 1 downto c_halfword_w * 3)); -- ip_dst_addr(2/2)
+ case TO_UINT(count) is
+ when 0 => -- 0 is the cycle after the sop due to the common_counter latency
+ sum <= sum + unsigned(snk_in.data(c_halfword_w - 1 downto 0)); -- ip_version, ip_header_length, ip_services
+ when 1 =>
+ sum <= sum + unsigned(snk_in.data(c_halfword_w * 4 - 1 downto c_halfword_w * 3)) -- ip_total_length
+ + unsigned(snk_in.data(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_identification
+ + unsigned(snk_in.data(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_flags, ip_fragment_offset
+ + unsigned(snk_in.data(c_halfword_w - 1 downto 0)); -- ip_time_to_live, ip_protocol
+ when 2 => -- skip ip_header_checksum
+ sum <= sum + unsigned(snk_in.data(c_halfword_w * 3 - 1 downto c_halfword_w * 2)) -- ip_src_addr(1/2)
+ + unsigned(snk_in.data(c_halfword_w * 2 - 1 downto c_halfword_w)) -- ip_src_addr(2/2)
+ + unsigned(snk_in.data(c_halfword_w - 1 downto 0)); -- ip_dst_addr(1/2)
+ when 3 =>
+ sum <= sum + unsigned(snk_in.data(c_halfword_w * 4 - 1 downto c_halfword_w * 3)); -- ip_dst_addr(2/2)
- when others =>
- end case;
+ when others =>
+ end case;
end if;
end if;
end process;
diff --git a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
index a8c8d20b50041cc02ac6832370421b749e0361bb..1f561f3d1e9c5ee8c0271e6239210f5167d354b9 100644
--- a/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
+++ b/libraries/technology/10gbase_r/tech_10gbase_r_component_pkg.vhd
@@ -799,48 +799,48 @@ package tech_10gbase_r_component_pkg is
component ip_arria10_e1sg_phy_10gbase_r is
port (
- rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
- rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
- rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
- rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
- rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
- rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
- rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
- rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
- rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
- rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
- rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
- rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
- rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
- rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
- rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
- rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
- rx_prbs_done : out std_logic_vector(0 downto 0); -- rx_prbs_done.rx_prbs_done
- rx_prbs_err : out std_logic_vector(0 downto 0); -- rx_prbs_err.rx_prbs_err
- rx_prbs_err_clr : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
- rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
- rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
- tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
- tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
- tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
- tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
- tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
- tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
- tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
- tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
- tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
- tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
- tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
- tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
- tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
- tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
- tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
- unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
- unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
- unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
- unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
- );
+ rx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_analogreset.rx_analogreset
+ rx_cal_busy : out std_logic_vector(0 downto 0); -- rx_cal_busy.rx_cal_busy
+ rx_cdr_refclk0 : in std_logic := '0'; -- rx_cdr_refclk0.clk
+ rx_clkout : out std_logic_vector(0 downto 0); -- rx_clkout.clk
+ rx_control : out std_logic_vector(7 downto 0); -- rx_control.rx_control
+ rx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_coreclkin.clk
+ rx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_digitalreset.rx_digitalreset
+ rx_enh_blk_lock : out std_logic_vector(0 downto 0); -- rx_enh_blk_lock.rx_enh_blk_lock
+ rx_enh_data_valid : out std_logic_vector(0 downto 0); -- rx_enh_data_valid.rx_enh_data_valid
+ rx_enh_fifo_del : out std_logic_vector(0 downto 0); -- rx_enh_fifo_del.rx_enh_fifo_del
+ rx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- rx_enh_fifo_empty.rx_enh_fifo_empty
+ rx_enh_fifo_full : out std_logic_vector(0 downto 0); -- rx_enh_fifo_full.rx_enh_fifo_full
+ rx_enh_fifo_insert : out std_logic_vector(0 downto 0); -- rx_enh_fifo_insert.rx_enh_fifo_insert
+ rx_enh_highber : out std_logic_vector(0 downto 0); -- rx_enh_highber.rx_enh_highber
+ rx_is_lockedtodata : out std_logic_vector(0 downto 0); -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_is_lockedtoref : out std_logic_vector(0 downto 0); -- rx_is_lockedtoref.rx_is_lockedtoref
+ rx_parallel_data : out std_logic_vector(63 downto 0); -- rx_parallel_data.rx_parallel_data
+ rx_prbs_done : out std_logic_vector(0 downto 0); -- rx_prbs_done.rx_prbs_done
+ rx_prbs_err : out std_logic_vector(0 downto 0); -- rx_prbs_err.rx_prbs_err
+ rx_prbs_err_clr : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_prbs_err_clr.rx_prbs_err_clr
+ rx_serial_data : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_serial_data.rx_serial_data
+ rx_seriallpbken : in std_logic_vector(0 downto 0) := (others => '0'); -- rx_seriallpbken.rx_seriallpbken
+ tx_analogreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_analogreset.tx_analogreset
+ tx_cal_busy : out std_logic_vector(0 downto 0); -- tx_cal_busy.tx_cal_busy
+ tx_clkout : out std_logic_vector(0 downto 0); -- tx_clkout.clk
+ tx_control : in std_logic_vector(7 downto 0) := (others => '0'); -- tx_control.tx_control
+ tx_coreclkin : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_coreclkin.clk
+ tx_digitalreset : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_digitalreset.tx_digitalreset
+ tx_enh_data_valid : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_enh_data_valid.tx_enh_data_valid
+ tx_enh_fifo_empty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_empty.tx_enh_fifo_empty
+ tx_enh_fifo_full : out std_logic_vector(0 downto 0); -- tx_enh_fifo_full.tx_enh_fifo_full
+ tx_enh_fifo_pempty : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pempty.tx_enh_fifo_pempty
+ tx_enh_fifo_pfull : out std_logic_vector(0 downto 0); -- tx_enh_fifo_pfull.tx_enh_fifo_pfull
+ tx_err_ins : in std_logic := '0'; -- tx_err_ins.tx_err_ins
+ tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0'); -- tx_parallel_data.tx_parallel_data
+ tx_serial_clk0 : in std_logic_vector(0 downto 0) := (others => '0'); -- tx_serial_clk0.clk
+ tx_serial_data : out std_logic_vector(0 downto 0); -- tx_serial_data.tx_serial_data
+ unused_rx_control : out std_logic_vector(11 downto 0); -- unused_rx_control.unused_rx_control
+ unused_rx_parallel_data : out std_logic_vector(63 downto 0); -- unused_rx_parallel_data.unused_rx_parallel_data
+ unused_tx_control : in std_logic_vector(8 downto 0) := (others => '0'); -- unused_tx_control.unused_tx_control
+ unused_tx_parallel_data : in std_logic_vector(63 downto 0) := (others => '0') -- unused_tx_parallel_data.unused_tx_parallel_data
+ );
end component;
component ip_arria10_e1sg_phy_10gbase_r_3 is
diff --git a/libraries/technology/ddr/tech_ddr_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
index fb1f0bf99002831f2659b41cd0d0a6d60291c365..7679e60118739a6d1c9e42dcd86015e36b7e713a 100644
--- a/libraries/technology/ddr/tech_ddr_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_component_pkg.vhd
@@ -136,52 +136,52 @@ package tech_ddr_component_pkg is
-- Manually derived VHDL entity from Verilog module $HDL_BUILD_DIR/ip_stratixiv_ddr3_uphy_4g_single_rank_800_master.v
component ip_stratixiv_ddr3_uphy_4g_single_rank_800_master is
port (
- pll_ref_clk : in std_logic; -- pll_ref_clk.clk
- global_reset_n : in std_logic; -- global_reset.reset_n
- soft_reset_n : in std_logic; -- soft_reset.reset_n
- afi_clk : out std_logic; -- afi_clk.clk
- afi_half_clk : out std_logic; -- afi_half_clk.clk
- afi_reset_n : out std_logic; -- afi_reset.reset_n
- mem_a : out std_logic_vector(15 downto 0); -- memory.mem_a
- mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
- mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_cke : out std_logic; -- .mem_cke
- mem_cs_n : out std_logic; -- .mem_cs_n
- mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
- mem_ras_n : out std_logic; -- .mem_ras_n
- mem_cas_n : out std_logic; -- .mem_cas_n
- mem_we_n : out std_logic; -- .mem_we_n
- mem_reset_n : out std_logic; -- .mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
- mem_odt : out std_logic; -- .mem_odt
- avl_ready : out std_logic; -- avl.waitrequest_n
- avl_burstbegin : in std_logic; -- .beginbursttransfer
- avl_addr : in std_logic_vector(26 downto 0); -- .address
- avl_rdata_valid : out std_logic; -- .readdatavalid
- avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
- avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
- avl_be : in std_logic_vector(31 downto 0); -- .byteenable
- avl_read_req : in std_logic; -- .read
- avl_write_req : in std_logic; -- .write
- avl_size : in std_logic_vector(6 downto 0); -- .burstcount
- local_init_done : out std_logic; -- status.local_init_done
- local_cal_success : out std_logic; -- .local_cal_success
- local_cal_fail : out std_logic; -- .local_cal_fail
- oct_rdn : in std_logic; -- oct.rdn
- oct_rup : in std_logic; -- .rup
- seriesterminationcontrol : out std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol : out std_logic_vector(13 downto 0); -- .parallelterminationcontrol
- pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
- pll_write_clk : out std_logic; -- .pll_write_clk
- pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
- pll_locked : out std_logic; -- .pll_locked
- pll_avl_clk : out std_logic; -- .pll_avl_clk
- pll_config_clk : out std_logic; -- .pll_config_clk
- dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
+ pll_ref_clk : in std_logic; -- pll_ref_clk.clk
+ global_reset_n : in std_logic; -- global_reset.reset_n
+ soft_reset_n : in std_logic; -- soft_reset.reset_n
+ afi_clk : out std_logic; -- afi_clk.clk
+ afi_half_clk : out std_logic; -- afi_half_clk.clk
+ afi_reset_n : out std_logic; -- afi_reset.reset_n
+ mem_a : out std_logic_vector(15 downto 0); -- memory.mem_a
+ mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
+ mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
+ mem_cke : out std_logic; -- .mem_cke
+ mem_cs_n : out std_logic; -- .mem_cs_n
+ mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
+ mem_ras_n : out std_logic; -- .mem_ras_n
+ mem_cas_n : out std_logic; -- .mem_cas_n
+ mem_we_n : out std_logic; -- .mem_we_n
+ mem_reset_n : out std_logic; -- .mem_reset_n
+ mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
+ mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
+ mem_odt : out std_logic; -- .mem_odt
+ avl_ready : out std_logic; -- avl.waitrequest_n
+ avl_burstbegin : in std_logic; -- .beginbursttransfer
+ avl_addr : in std_logic_vector(26 downto 0); -- .address
+ avl_rdata_valid : out std_logic; -- .readdatavalid
+ avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
+ avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
+ avl_be : in std_logic_vector(31 downto 0); -- .byteenable
+ avl_read_req : in std_logic; -- .read
+ avl_write_req : in std_logic; -- .write
+ avl_size : in std_logic_vector(6 downto 0); -- .burstcount
+ local_init_done : out std_logic; -- status.local_init_done
+ local_cal_success : out std_logic; -- .local_cal_success
+ local_cal_fail : out std_logic; -- .local_cal_fail
+ oct_rdn : in std_logic; -- oct.rdn
+ oct_rup : in std_logic; -- .rup
+ seriesterminationcontrol : out std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol : out std_logic_vector(13 downto 0); -- .parallelterminationcontrol
+ pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
+ pll_write_clk : out std_logic; -- .pll_write_clk
+ pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
+ pll_locked : out std_logic; -- .pll_locked
+ pll_avl_clk : out std_logic; -- .pll_avl_clk
+ pll_config_clk : out std_logic; -- .pll_config_clk
+ dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
);
end component;
@@ -189,50 +189,50 @@ package tech_ddr_component_pkg is
-- . diff with master is that only master has oct_* inputs and that the *terminationcontrol are inputs for the slave
component ip_stratixiv_ddr3_uphy_4g_single_rank_800_slave is
port (
- pll_ref_clk : in std_logic; -- pll_ref_clk.clk
- global_reset_n : in std_logic; -- global_reset.reset_n
- soft_reset_n : in std_logic; -- soft_reset.reset_n
- afi_clk : out std_logic; -- afi_clk_in.clk
- afi_half_clk : out std_logic; -- afi_half_clk_in.clk
- afi_reset_n : out std_logic; -- afi_reset_in.reset_n
- mem_a : out std_logic_vector(15 downto 0); -- memory.mem_a
- mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
- mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
- mem_cke : out std_logic; -- .mem_cke
- mem_cs_n : out std_logic; -- .mem_cs_n
- mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
- mem_ras_n : out std_logic; -- .mem_ras_n
- mem_cas_n : out std_logic; -- .mem_cas_n
- mem_we_n : out std_logic; -- .mem_we_n
- mem_reset_n : out std_logic; -- .mem_reset_n
- mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
- mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
- mem_odt : out std_logic; -- .mem_odt
- avl_ready : out std_logic; -- avl.waitrequest_n
- avl_burstbegin : in std_logic; -- .beginbursttransfer
- avl_addr : in std_logic_vector(26 downto 0); -- .address
- avl_rdata_valid : out std_logic; -- .readdatavalid
- avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
- avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
- avl_be : in std_logic_vector(31 downto 0); -- .byteenable
- avl_read_req : in std_logic; -- .read
- avl_write_req : in std_logic; -- .write
- avl_size : in std_logic_vector(6 downto 0); -- .burstcount
- local_init_done : out std_logic; -- status.local_init_done
- local_cal_success : out std_logic; -- .local_cal_success
- local_cal_fail : out std_logic; -- .local_cal_fail
- seriesterminationcontrol : in std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
- parallelterminationcontrol : in std_logic_vector(13 downto 0); -- .parallelterminationcontrol
- pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
- pll_write_clk : out std_logic; -- .pll_write_clk
- pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
- pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
- pll_locked : out std_logic; -- .pll_locked
- pll_avl_clk : out std_logic; -- .pll_avl_clk
- pll_config_clk : out std_logic; -- .pll_config_clk
- dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
+ pll_ref_clk : in std_logic; -- pll_ref_clk.clk
+ global_reset_n : in std_logic; -- global_reset.reset_n
+ soft_reset_n : in std_logic; -- soft_reset.reset_n
+ afi_clk : out std_logic; -- afi_clk_in.clk
+ afi_half_clk : out std_logic; -- afi_half_clk_in.clk
+ afi_reset_n : out std_logic; -- afi_reset_in.reset_n
+ mem_a : out std_logic_vector(15 downto 0); -- memory.mem_a
+ mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba
+ mem_ck : out std_logic_vector(1 downto 0); -- .mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- .mem_ck_n
+ mem_cke : out std_logic; -- .mem_cke
+ mem_cs_n : out std_logic; -- .mem_cs_n
+ mem_dm : out std_logic_vector(7 downto 0); -- .mem_dm
+ mem_ras_n : out std_logic; -- .mem_ras_n
+ mem_cas_n : out std_logic; -- .mem_cas_n
+ mem_we_n : out std_logic; -- .mem_we_n
+ mem_reset_n : out std_logic; -- .mem_reset_n
+ mem_dq : inout std_logic_vector(63 downto 0); -- .mem_dq
+ mem_dqs : inout std_logic_vector(7 downto 0); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(7 downto 0); -- .mem_dqs_n
+ mem_odt : out std_logic; -- .mem_odt
+ avl_ready : out std_logic; -- avl.waitrequest_n
+ avl_burstbegin : in std_logic; -- .beginbursttransfer
+ avl_addr : in std_logic_vector(26 downto 0); -- .address
+ avl_rdata_valid : out std_logic; -- .readdatavalid
+ avl_rdata : out std_logic_vector(255 downto 0); -- .readdata
+ avl_wdata : in std_logic_vector(255 downto 0); -- .writedata
+ avl_be : in std_logic_vector(31 downto 0); -- .byteenable
+ avl_read_req : in std_logic; -- .read
+ avl_write_req : in std_logic; -- .write
+ avl_size : in std_logic_vector(6 downto 0); -- .burstcount
+ local_init_done : out std_logic; -- status.local_init_done
+ local_cal_success : out std_logic; -- .local_cal_success
+ local_cal_fail : out std_logic; -- .local_cal_fail
+ seriesterminationcontrol : in std_logic_vector(13 downto 0); -- oct_sharing.seriesterminationcontrol
+ parallelterminationcontrol : in std_logic_vector(13 downto 0); -- .parallelterminationcontrol
+ pll_mem_clk : out std_logic; -- pll_sharing.pll_mem_clk
+ pll_write_clk : out std_logic; -- .pll_write_clk
+ pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk
+ pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk
+ pll_locked : out std_logic; -- .pll_locked
+ pll_avl_clk : out std_logic; -- .pll_avl_clk
+ pll_config_clk : out std_logic; -- .pll_config_clk
+ dll_delayctrl : out std_logic_vector(5 downto 0) -- dll_sharing.dll_delayctrl
);
end component;
diff --git a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
index 65a8e2493f0a0351fde3803f1cfe973e43c56c9b..1b8b5d4acd9ebdf55904d81982342dfd33174d32 100644
--- a/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
+++ b/libraries/technology/ddr/tech_ddr_mem_model_component_pkg.vhd
@@ -87,24 +87,24 @@ package tech_ddr_mem_model_component_pkg is
-- Manually derived VHDL entity from ed_sim_altera_emif_mem_model_141_z3tvrmq.vhd in:
-- $HDL_WORK/libraries/technology/ip_arria10/ddr4_4g_1600/emif_0_example_design/sim/altera_emif_mem_model_141/sim
component ed_sim_altera_emif_mem_model_141_z3tvrmq is
- port (
- mem_ck : in std_logic_vector(0 downto 0) := (others => '0'); -- mem_conduit_end.mem_ck
- mem_ck_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_ck_n
- mem_a : in std_logic_vector(16 downto 0) := (others => '0'); -- .mem_a
- mem_act_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_act_n
- mem_ba : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_ba
- mem_bg : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_bg
- mem_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cke
- mem_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cs_n
- mem_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_odt
- mem_reset_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_reset_n
- mem_par : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_par
- mem_alert_n : out std_logic_vector(0 downto 0); -- .mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0') -- .mem_dbi_n
- );
+ port (
+ mem_ck : in std_logic_vector(0 downto 0) := (others => '0'); -- mem_conduit_end.mem_ck
+ mem_ck_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_ck_n
+ mem_a : in std_logic_vector(16 downto 0) := (others => '0'); -- .mem_a
+ mem_act_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_act_n
+ mem_ba : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_ba
+ mem_bg : in std_logic_vector(1 downto 0) := (others => '0'); -- .mem_bg
+ mem_cke : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cke
+ mem_cs_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_cs_n
+ mem_odt : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_odt
+ mem_reset_n : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_reset_n
+ mem_par : in std_logic_vector(0 downto 0) := (others => '0'); -- .mem_par
+ mem_alert_n : out std_logic_vector(0 downto 0); -- .mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => '0'); -- .mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => '0'); -- .mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => '0') -- .mem_dbi_n
+ );
end component ed_sim_altera_emif_mem_model_141_z3tvrmq;
end tech_ddr_mem_model_component_pkg;
diff --git a/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
index 39d77831af1a00069b3c41ab43095fbe2941f305..3e9550f64fb6e0015a73742cc488dcd457f70ced 100644
--- a/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
+++ b/libraries/technology/eth_10g/tech_eth_10g_stratixiv.vhd
@@ -143,37 +143,37 @@ begin
port map(
-- Transceiver PLL reference clock
tr_ref_clk_156 => tr_ref_clk_156,
- tr_ref_rst_156 => tr_ref_rst_156,
+ tr_ref_rst_156 => tr_ref_rst_156,
- -- Calibration & reconfig clock
- cal_rec_clk => cal_rec_clk,
+ -- Calibration & reconfig clock
+ cal_rec_clk => cal_rec_clk,
- -- Data clocks
- tx_clk_arr_in => tx_clk_arr_in,
- tx_rst_arr_out => tx_rst_arr_out,
- rx_clk_arr_out => rx_clk_arr_out,
- rx_clk_arr_in => rx_clk_arr_in,
- rx_rst_arr_out => rx_rst_arr_out,
+ -- Data clocks
+ tx_clk_arr_in => tx_clk_arr_in,
+ tx_rst_arr_out => tx_rst_arr_out,
+ rx_clk_arr_out => rx_clk_arr_out,
+ rx_clk_arr_in => rx_clk_arr_in,
+ rx_rst_arr_out => rx_rst_arr_out,
- -- MM
- mm_clk => mm_clk,
- mm_rst => mm_rst,
+ -- MM
+ mm_clk => mm_clk,
+ mm_rst => mm_rst,
- mac_mosi => mac_mosi,
- mac_miso => mac_miso,
+ mac_mosi => mac_mosi,
+ mac_miso => mac_miso,
- xaui_mosi => xaui_mosi,
- xaui_miso => xaui_miso,
+ xaui_mosi => xaui_mosi,
+ xaui_miso => xaui_miso,
- -- ST
- tx_snk_in_arr => tx_snk_in_arr,
- tx_snk_out_arr => tx_snk_out_arr,
+ -- ST
+ tx_snk_in_arr => tx_snk_in_arr,
+ tx_snk_out_arr => tx_snk_out_arr,
- rx_src_out_arr => rx_src_out_arr,
- rx_src_in_arr => rx_src_in_arr,
+ rx_src_out_arr => rx_src_out_arr,
+ rx_src_in_arr => rx_src_in_arr,
- -- XAUI serial IO
- xaui_tx_arr => xaui_tx_arr,
- xaui_rx_arr => xaui_rx_arr
+ -- XAUI serial IO
+ xaui_tx_arr => xaui_tx_arr,
+ xaui_rx_arr => xaui_rx_arr
);
end str;
diff --git a/libraries/technology/fifo/tech_fifo_component_pkg.vhd b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
index b8b1970875b38fab24bec396d6d2e32a271890ef..f51dcd474a13cb71d838d9eaa9fe8646b85817c4 100644
--- a/libraries/technology/fifo/tech_fifo_component_pkg.vhd
+++ b/libraries/technology/fifo/tech_fifo_component_pkg.vhd
@@ -20,7 +20,7 @@
--
-- Author : -
-- Changed by : D.F. Brouwer
--- Purpose:
+-- Purpose:
-- IP components declarations for various devices that get wrapped by the tech components
library IEEE, technology_lib;
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
index c1a0615bb10603daafbcbbfceecb5cd6c38bed4d..e74880e3f006feba5d1749241d132a1c3e74a4ff 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens.vhd
@@ -36,44 +36,44 @@ entity tech_fpga_temp_sens is
generic (
g_technology : natural := c_tech_select_default
);
- port (
- corectl : in std_logic := '0'; -- corectl.corectl
- eoc : out std_logic; -- eoc.eoc
- reset : in std_logic := '0'; -- reset.reset
- tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
- );
+ port (
+ corectl : in std_logic := '0'; -- corectl.corectl
+ eoc : out std_logic; -- eoc.eoc
+ reset : in std_logic := '0'; -- reset.reset
+ tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
+ );
end tech_fpga_temp_sens;
architecture str of tech_fpga_temp_sens is
begin
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
- u0 : ip_arria10_temp_sense
- port map (
- corectl => corectl, -- corectl.corectl
- reset => reset, -- reset.reset
- tempout => tempout, -- tempout.tempout
- eoc => eoc -- eoc.eoc
- );
+ u0 : ip_arria10_temp_sense
+ port map (
+ corectl => corectl, -- corectl.corectl
+ reset => reset, -- reset.reset
+ tempout => tempout, -- tempout.tempout
+ eoc => eoc -- eoc.eoc
+ );
end generate;
gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 generate
- u0 : ip_arria10_e3sge3_temp_sense
- port map (
- corectl => corectl, -- corectl.corectl
- reset => reset, -- reset.reset
- tempout => tempout, -- tempout.tempout
- eoc => eoc -- eoc.eoc
- );
+ u0 : ip_arria10_e3sge3_temp_sense
+ port map (
+ corectl => corectl, -- corectl.corectl
+ reset => reset, -- reset.reset
+ tempout => tempout, -- tempout.tempout
+ eoc => eoc -- eoc.eoc
+ );
end generate;
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
- u0 : ip_arria10_e1sg_temp_sense
- port map (
- corectl => corectl, -- corectl.corectl
- reset => reset, -- reset.reset
- tempout => tempout, -- tempout.tempout
- eoc => eoc -- eoc.eoc
- );
+ u0 : ip_arria10_e1sg_temp_sense
+ port map (
+ corectl => corectl, -- corectl.corectl
+ reset => reset, -- reset.reset
+ tempout => tempout, -- tempout.tempout
+ eoc => eoc -- eoc.eoc
+ );
end generate;
gen_ip_arria10_e2sg : if g_technology = c_tech_arria10_e2sg generate
diff --git a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
index 8cf7fbc8d139f4031a7e20e0bf621e8509bb59a5..a0e8f9dc4bf4ea9e066b7cfcc3537fbd8ecae78e 100644
--- a/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_temp_sens/tech_fpga_temp_sens_component_pkg.vhd
@@ -26,30 +26,30 @@ use IEEE.std_logic_1164.all;
package tech_fpga_temp_sens_component_pkg is
component ip_arria10_temp_sense is
- port (
- corectl : in std_logic := '0'; -- corectl.corectl
- eoc : out std_logic; -- eoc.eoc
- reset : in std_logic := '0'; -- reset.reset
- tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
- );
+ port (
+ corectl : in std_logic := '0'; -- corectl.corectl
+ eoc : out std_logic; -- eoc.eoc
+ reset : in std_logic := '0'; -- reset.reset
+ tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
+ );
end component;
component ip_arria10_e3sge3_temp_sense is
- port (
- corectl : in std_logic := '0'; -- corectl.corectl
- eoc : out std_logic; -- eoc.eoc
- reset : in std_logic := '0'; -- reset.reset
- tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
- );
+ port (
+ corectl : in std_logic := '0'; -- corectl.corectl
+ eoc : out std_logic; -- eoc.eoc
+ reset : in std_logic := '0'; -- reset.reset
+ tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
+ );
end component;
component ip_arria10_e1sg_temp_sense is
- port (
- corectl : in std_logic := '0'; -- corectl.corectl
- eoc : out std_logic; -- eoc.eoc
- reset : in std_logic := '0'; -- reset.reset
- tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
- );
+ port (
+ corectl : in std_logic := '0'; -- corectl.corectl
+ eoc : out std_logic; -- eoc.eoc
+ reset : in std_logic := '0'; -- reset.reset
+ tempout : out std_logic_vector(9 downto 0) -- tempout.tempout
+ );
end component;
component ip_arria10_e2sg_temp_sense is
diff --git a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
index 89cee1b2e3083c976ceca56174b523e8db084bf9..4ee6ff807f152ddeadc6e945a6ae318edbbe7097 100644
--- a/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
+++ b/libraries/technology/fpga_voltage_sens/tech_fpga_voltage_sens_component_pkg.vhd
@@ -26,57 +26,57 @@ use IEEE.std_logic_1164.all;
package tech_fpga_voltage_sens_component_pkg is
component ip_arria10_voltage_sense is
- port (
- clock_clk : in std_logic := '0';
- reset_sink_reset : in std_logic;
- controller_csr_address : in std_logic := '0';
- controller_csr_read : in std_logic := '0';
- controller_csr_write : in std_logic := '0';
- controller_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
- controller_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
- sample_store_csr_address : in std_logic_vector(3 downto 0) := "0000";
- sample_store_csr_read : in std_logic := '0';
- sample_store_csr_write : in std_logic := '0';
- sample_store_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
- sample_store_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
- sample_store_irq_irq : out std_logic
- );
+ port (
+ clock_clk : in std_logic := '0';
+ reset_sink_reset : in std_logic;
+ controller_csr_address : in std_logic := '0';
+ controller_csr_read : in std_logic := '0';
+ controller_csr_write : in std_logic := '0';
+ controller_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ controller_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
+ sample_store_csr_address : in std_logic_vector(3 downto 0) := "0000";
+ sample_store_csr_read : in std_logic := '0';
+ sample_store_csr_write : in std_logic := '0';
+ sample_store_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ sample_store_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
+ sample_store_irq_irq : out std_logic
+ );
end component;
component ip_arria10_e3sge3_voltage_sense is
- port (
- clock_clk : in std_logic := '0';
- reset_sink_reset : in std_logic;
- controller_csr_address : in std_logic := '0';
- controller_csr_read : in std_logic := '0';
- controller_csr_write : in std_logic := '0';
- controller_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
- controller_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
- sample_store_csr_address : in std_logic_vector(3 downto 0) := "0000";
- sample_store_csr_read : in std_logic := '0';
- sample_store_csr_write : in std_logic := '0';
- sample_store_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
- sample_store_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
- sample_store_irq_irq : out std_logic
- );
+ port (
+ clock_clk : in std_logic := '0';
+ reset_sink_reset : in std_logic;
+ controller_csr_address : in std_logic := '0';
+ controller_csr_read : in std_logic := '0';
+ controller_csr_write : in std_logic := '0';
+ controller_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ controller_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
+ sample_store_csr_address : in std_logic_vector(3 downto 0) := "0000";
+ sample_store_csr_read : in std_logic := '0';
+ sample_store_csr_write : in std_logic := '0';
+ sample_store_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ sample_store_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
+ sample_store_irq_irq : out std_logic
+ );
end component;
component ip_arria10_e1sg_voltage_sense is
- port (
- clock_clk : in std_logic := '0';
- reset_sink_reset : in std_logic;
- controller_csr_address : in std_logic := '0';
- controller_csr_read : in std_logic := '0';
- controller_csr_write : in std_logic := '0';
- controller_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
- controller_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
- sample_store_csr_address : in std_logic_vector(3 downto 0) := "0000";
- sample_store_csr_read : in std_logic := '0';
- sample_store_csr_write : in std_logic := '0';
- sample_store_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
- sample_store_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
- sample_store_irq_irq : out std_logic
- );
+ port (
+ clock_clk : in std_logic := '0';
+ reset_sink_reset : in std_logic;
+ controller_csr_address : in std_logic := '0';
+ controller_csr_read : in std_logic := '0';
+ controller_csr_write : in std_logic := '0';
+ controller_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ controller_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
+ sample_store_csr_address : in std_logic_vector(3 downto 0) := "0000";
+ sample_store_csr_read : in std_logic := '0';
+ sample_store_csr_write : in std_logic := '0';
+ sample_store_csr_writedata : in std_logic_vector(31 downto 0) := (others => '0');
+ sample_store_csr_readdata : out std_logic_vector(31 downto 0) := (others => '0');
+ sample_store_irq_irq : out std_logic
+ );
end component;
component ip_arria10_e2sg_voltage_sense is
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
index 8b567885cdfd462038e41c4239fe8803077fec6a..6e10478041a1781e75b4c2f1fd6213ed7fe67424 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk125.vhd
@@ -51,42 +51,42 @@ begin
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_fractional_pll_clk125
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- outclk3 => c3, -- outclk3.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ outclk3 => c3, -- outclk3.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
);
end generate;
gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 generate
u0 : ip_arria10_e3sge3_fractional_pll_clk125
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- outclk3 => c3, -- outclk3.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ outclk3 => c3, -- outclk3.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
);
end generate;
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
u0 : ip_arria10_e1sg_fractional_pll_clk125
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- outclk3 => c3, -- outclk3.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ outclk3 => c3, -- outclk3.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
);
end generate;
diff --git a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
index dde0319d8e1db86fb08217328ba7b05a5af32528..b19d46e4140ebde17e20c684a41716c5cad80948 100644
--- a/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
+++ b/libraries/technology/fractional_pll/tech_fractional_pll_clk200.vhd
@@ -50,39 +50,39 @@ begin
gen_ip_arria10 : if g_technology = c_tech_arria10_proto generate
u0 : ip_arria10_fractional_pll_clk200
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
);
end generate;
gen_ip_arria10_e3sge3 : if g_technology = c_tech_arria10_e3sge3 generate
u0 : ip_arria10_e3sge3_fractional_pll_clk200
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
);
end generate;
gen_ip_arria10_e1sg : if g_technology = c_tech_arria10_e1sg generate
u0 : ip_arria10_e1sg_fractional_pll_clk200
port map (
- outclk0 => c0, -- outclk0.clk
- outclk1 => c1, -- outclk1.clk
- outclk2 => c2, -- outclk2.clk
- pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
- pll_locked => locked, -- pll_locked.pll_locked
- pll_powerdown => areset, -- pll_powerdown.pll_powerdown
- pll_refclk0 => inclk0 -- pll_refclk0.clk
+ outclk0 => c0, -- outclk0.clk
+ outclk1 => c1, -- outclk1.clk
+ outclk2 => c2, -- outclk2.clk
+ pll_cal_busy => OPEN, -- pll_cal_busy.pll_cal_busy
+ pll_locked => locked, -- pll_locked.pll_locked
+ pll_powerdown => areset, -- pll_powerdown.pll_powerdown
+ pll_refclk0 => inclk0 -- pll_refclk0.clk
);
end generate;
diff --git a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
index e25ac036c6ef3a2269c9756056ed5a4d723817d6..f27b9fa33506139d398babc99cef3b9ce0076813 100644
--- a/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
+++ b/libraries/technology/iobuf/tech_iobuf_component_pkg.vhd
@@ -20,7 +20,7 @@
--
-- Author : -
-- Changed by : D.F. Brouwer
--- Purpose:
+-- Purpose:
-- IP components declarations for various devices that get wrapped by the tech components
library IEEE;
diff --git a/libraries/technology/ip_agi027_1e1v/complex_mult_rtl/ip_agi027_1e1v_complex_mult_rtl.vhd b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl/ip_agi027_1e1v_complex_mult_rtl.vhd
index e59abe7833458060aa91d6119409b7e65df6b7d8..5c0c85f418a9998a7a56da5dcdd040a26be183a2 100644
--- a/libraries/technology/ip_agi027_1e1v/complex_mult_rtl/ip_agi027_1e1v_complex_mult_rtl.vhd
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl/ip_agi027_1e1v_complex_mult_rtl.vhd
@@ -19,7 +19,7 @@
-- -------------------------------------------------------------------------
--
-- Author : D.F. Brouwer
--- Reference:
+-- Reference:
-- Copied from */technology/ip_arria10/complex_mult_rtl/ip_arria10_complex_mult_rtl.vhd.
library IEEE;
diff --git a/libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/ip_agi027_1e1v_complex_mult_rtl_canonical.vhd b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/ip_agi027_1e1v_complex_mult_rtl_canonical.vhd
index 65e5a96d9fbfcc2d3344c5edd6878e476164cd77..fa1d969f617f44edbd84bb1723889c8ac6bd4188 100644
--- a/libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/ip_agi027_1e1v_complex_mult_rtl_canonical.vhd
+++ b/libraries/technology/ip_agi027_1e1v/complex_mult_rtl_canonical/ip_agi027_1e1v_complex_mult_rtl_canonical.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author :
+-- Author :
-- . D.F. Brouwer
-- Purpose:
-- . RTL complex multiplier, canonical version (3 simple multipliers).
diff --git a/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in.vhd b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in.vhd
index 0f9550274a3b67a764627652241b34b869d73ca4..c4015c6c14c35aa9a8b6435615b5eacbf8ea88cb 100644
--- a/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_in.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Purpose:
-- RadioHDL wrapper for ip_agi027_1e1v_ddio_in_1 to support g_width >= 1
diff --git a/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out.vhd b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out.vhd
index 4e79aa414e8e5b9f603d8171bfea6f89d939848a..4ed587d7715758536cf3567a5770428b542b7582 100644
--- a/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/ip_agi027_1e1v_ddio_out.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Purpose:
-- RadioHDL wrapper for ip_agi027_1e1v_ddio_out_1 to support g_width >= 1
diff --git a/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_in_1.vhd b/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_in_1.vhd
index fd3a418565dedf7239d48788613230640144e710..365fd0116b5d2f5df1c4808ea15c4711a30e1495 100644
--- a/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_in_1.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_in_1.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Purpose:
-- Simulation model for DDIO in
@@ -36,19 +36,19 @@
-- dataout_h 1 3 5
-- dataout_l 0 2 4
-- Reference:
--- Copied from ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd
+-- Copied from ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity ip_agi027_1e1v_ddio_in_1 is
- port (
- datain : in std_logic_vector(0 downto 0) := (others => '0');
- ck : in std_logic := '0';
- aclr : in std_logic := '0';
- dataout_h : out std_logic_vector(0 downto 0);
- dataout_l : out std_logic_vector(0 downto 0)
- );
+ port (
+ datain : in std_logic_vector(0 downto 0) := (others => '0');
+ ck : in std_logic := '0';
+ aclr : in std_logic := '0';
+ dataout_h : out std_logic_vector(0 downto 0);
+ dataout_l : out std_logic_vector(0 downto 0)
+ );
end ip_agi027_1e1v_ddio_in_1;
architecture beh of ip_agi027_1e1v_ddio_in_1 is
diff --git a/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_out_1.vhd b/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_out_1.vhd
index fa74c78052bbeeb214ec1691a15347d7d83cb7a3..52d764203772293624f4b68dce77d159b51570c6 100644
--- a/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_out_1.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/sim/ip_agi027_1e1v_ddio_out_1.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Purpose:
-- Simulation model for DDIO out
@@ -33,20 +33,20 @@
-- dataout @ f 0 2 4
-- dataout 0 1 2 3 4 5 6 7
-- Reference:
--- Copied from ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd
+-- Copied from ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd
library IEEE;
use IEEE.std_logic_1164.all;
entity ip_agi027_1e1v_ddio_out_1 is
- port (
- dataout : out std_logic_vector(0 downto 0);
- outclock : in std_logic := '0';
- aclr : in std_logic := '0';
- datain_h : in std_logic_vector(0 downto 0) := (others => '0');
- datain_l : in std_logic_vector(0 downto 0) := (others => '0')
- );
+ port (
+ dataout : out std_logic_vector(0 downto 0);
+ outclock : in std_logic := '0';
+ aclr : in std_logic := '0';
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0');
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0')
+ );
end ip_agi027_1e1v_ddio_out_1;
architecture beh of ip_agi027_1e1v_ddio_out_1 is
diff --git a/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd b/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd
index 5ec4d1b24b4388e3a888855871ae8726fad66e21..e911163a9e384defe00d7fc706560e8e012df5a0 100644
--- a/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ddio/sim/tb_ip_agi027_1e1v_ddio_1.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Purpose:
-- Test bench for the DDIO in and out simulation models
@@ -38,7 +38,7 @@
-- > as 3
-- > run -a
-- Reference:
--- Copied from ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
+-- Copied from ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
library IEEE;
use IEEE.std_logic_1164.all;
@@ -95,32 +95,32 @@ begin
in_data(0) <= in_dat;
u_ddio_in : entity work.ip_agi027_1e1v_ddio_in_1
- port map (
- datain => in_data,
- ck => clk,
- dataout_h => data_h,
- dataout_l => data_l
- );
+ port map (
+ datain => in_data,
+ ck => clk,
+ dataout_h => data_h,
+ dataout_l => data_l
+ );
u_ddio_out : entity work.ip_agi027_1e1v_ddio_out_1
- port map (
- dataout => out_data,
- outclock => clk,
- datain_h => data_h,
- datain_l => data_l
- );
+ port map (
+ dataout => out_data,
+ outclock => clk,
+ datain_h => data_h,
+ datain_l => data_l
+ );
- out_dat <= out_data(0);
+ out_dat <= out_data(0);
- out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
+ out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
- p_verify : process(clk)
- begin
- if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at falling edge";
- end if;
- if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at rising edge";
- end if;
- end process;
+ p_verify : process(clk)
+ begin
+ if falling_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at falling edge";
+ end if;
+ if rising_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_agi027_1e1v_ddio_1: Error, unexpeced data at rising edge";
+ end if;
+ end process;
end tb;
diff --git a/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.vhd b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.vhd
index 6db47019ee3a43fb4f392387f499d7fc56d5ccda..e6da71ebd4acb86890d4e45866ae6d3f927eb4f0 100644
--- a/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.vhd
+++ b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc.vhd
@@ -19,7 +19,7 @@
-- -----------------------------------------------------------------------------
--
-- Author: D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper / Instantiate FIFO IP with generics
-- Description:
-- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_1e1v_fifo_dc_fifo_1921_kss5lzq.vhd
diff --git a/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.vhd b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.vhd
index 92502ae0f1f0e973f174a7c8f19f1ee5c684b5a4..d14b9c6a4bc74ab750a592552c51a8888d77a8a6 100644
--- a/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.vhd
+++ b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_dc_mixed_widths.vhd
@@ -19,7 +19,7 @@
-- -----------------------------------------------------------------------------
--
-- Author: D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper / Instantiate FIFO IP with generics
-- Description:
-- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_1e1v_fifo_dc_mixed_widths_fifo_1921_qaaak5a.vhd
@@ -39,7 +39,7 @@ entity ip_agi027_1e1v_fifo_dc_mixed_widths is
generic (
g_nof_words : natural := 1024; -- FIFO size in nof wr_dat words;
g_wrdat_w : natural := 20;
- g_rddat_w : natural := 10
+ g_rddat_w : natural := 10
);
port (
aclr : in std_logic := '0';
diff --git a/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.vhd b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.vhd
index 7633a79ccf9a0feac575f8c4571e00b9a99b80c3..340a8654cde9650b0aeb0b439eb4c58a6fcf3bf6 100644
--- a/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.vhd
+++ b/libraries/technology/ip_agi027_1e1v/fifo/ip_agi027_1e1v_fifo_sc.vhd
@@ -19,7 +19,7 @@
-- -----------------------------------------------------------------------------
--
-- Author: D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper / Instantiate FIFO IP with generics
-- Description:
-- Copied component declaration and instance example from generated/fifo_1921/sim/ip_agi027_1e1v_fifo_sc_fifo_1921_7egef6q.vhd
diff --git a/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult.vhd b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult.vhd
index 10f523830f2a4c89aac94bbb4acdf0bdabf3122d..1a5687f71221a488b7c0c95db11d8a36b1b436c3 100644
--- a/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult.vhd
+++ b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult.vhd
@@ -19,9 +19,9 @@
-- -------------------------------------------------------------------------
--
-- Author : D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper / Instantiate MULTiplier IP with generics
--- Reference:
+-- Reference:
-- Copied from */technology/ip_arria10/mult/ip_arria10_mult.vhd and add component declaration lpm_mult from
-- generated/lpm_mult_1920/sim/ip_agi027_1e1v_lpm_mult_lpm_mult_1920_sphm57q.vhd
-- Remark:
diff --git a/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult_rtl.vhd b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult_rtl.vhd
index bea7c84566105d1ea879e9958675d12119224c4b..46dcc5225747011176f8be58cfe8b48b6b8e8c88 100644
--- a/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult_rtl.vhd
+++ b/libraries/technology/ip_agi027_1e1v/mult/ip_agi027_1e1v_mult_rtl.vhd
@@ -19,9 +19,9 @@
-- -----------------------------------------------------------------------------
--
-- Author : D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper
--- Reference:
+-- Reference:
-- Copied from */technology/ip_arria10/mult/ip_arria10_mult_rtl.vhd
library IEEE;
diff --git a/libraries/technology/ip_agi027_1e1v/mult_add2/ip_agi027_1e1v_mult_add2_rtl.vhd b/libraries/technology/ip_agi027_1e1v/mult_add2/ip_agi027_1e1v_mult_add2_rtl.vhd
index d96a9b44ac184f049cc505251ab7e663f973d3ed..8c5b5d698efb050db9b0ff828c3b0a14db165c52 100644
--- a/libraries/technology/ip_agi027_1e1v/mult_add2/ip_agi027_1e1v_mult_add2_rtl.vhd
+++ b/libraries/technology/ip_agi027_1e1v/mult_add2/ip_agi027_1e1v_mult_add2_rtl.vhd
@@ -19,9 +19,9 @@
-- -----------------------------------------------------------------------------
--
-- Author : D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper
--- Reference:
+-- Reference:
-- Copied from */technology/ip_arria10_e2sg/mult_add2/ip_arria10_e2sg_mult_add2.vhd,
-- that is based on ip_stratixiv_mult_add2_rtl
diff --git a/libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4_rtl.vhd b/libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4_rtl.vhd
index 97df4ea8f4f20e0670049d6b64384e67ff9c8092..00d127bd203e4b212e2e5cc1755966050a206cc0 100644
--- a/libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4_rtl.vhd
+++ b/libraries/technology/ip_agi027_1e1v/mult_add4/ip_agi027_1e1v_mult_add4_rtl.vhd
@@ -19,9 +19,9 @@
-- -----------------------------------------------------------------------------
--
-- Author : D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper
--- Reference:
+-- Reference:
-- Copied from */technology/ip_arria10_e2sg/mult_add4/ip_arria10_e2sg_mult_add2.vhd
library IEEE, common_lib;
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
index a4c4ca03da38bf25001b5957644909e4b1292987..b4abedfa5274fa911470e669661bb39219261809 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_cr_cw.vhd
@@ -19,7 +19,7 @@
-- -----------------------------------------------------------------------------
--
-- Author: D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_cr_cw_ram_2port_2040_cmcw2dy.vhd
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
index 83b0334f4149c88305a4c85455e03a0a5a44591b..26b844c14b6072c68520858aa80a928dd1e2ba19 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_crk_cw.vhd
@@ -19,18 +19,18 @@
-- -----------------------------------------------------------------------------
--
-- Author: D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
-- Simple dual port ram with dual clock domain and with ratio data widths
-- Port a is only used for write in write clock domain
-- Port b is only used for read in read clock domain
-- Reference:
--- Copied component declaration and instance example from
+-- Copied component declaration and instance example from
-- generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_crk_cw_ram_2port_2040_aadk55y.vhd
-- Remark:
-- Created this IP for the Agilex 7 (agi027_1e1v) due to incompatibility with
--- the standard crwk_crw IP variant, to facilitate its integration into
+-- the standard crwk_crw IP variant, to facilitate its integration into
-- common_ram_cr_cw_ratio.
library ieee, technology_lib;
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
index a2a2882d2503ede1ab53fed12830f28be5bf36d7..7bc85bf4a18bdf9305a2cd3412c189d14573a93e 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_r_w.vhd
@@ -19,7 +19,7 @@
-- -----------------------------------------------------------------------------
--
-- Author: D. F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
-- Copied component declaration and instance example from generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_r_w_ram_2port_2040_gbkw2ny.vhd
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
index 85bbd7b68c5ae662fb503ee81169381960fcc80f..bcbe6a9e1b5cba80c4399731d4bfb872245f4f3a 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_ram_rw_rw.vhd
@@ -19,14 +19,14 @@
-- -----------------------------------------------------------------------------
--
-- Author: D.F. Brouwer
--- Purpose:
+-- Purpose:
-- RadioHDL wrapper / Instantiate RAM IP with generics
-- Description:
--- Copied component declaration and instance example from
+-- Copied component declaration and instance example from
-- generated/ram_2port_2040/sim/ip_agi027_1e1v_ram_rw_rw_ram_2port_2040_uxwhvmq.vhd
-- Remark:
--- The outcome of the synthesis is that the parameter
--- read_during_write_mode_mixed_ports cannot be set to the
+-- The outcome of the synthesis is that the parameter
+-- read_during_write_mode_mixed_ports cannot be set to the
-- value OLD_DATA for the Agilex 7, otherwise an error occurs.
library ieee, technology_lib;
@@ -38,7 +38,7 @@ library altera_lnsim;
use altera_lnsim.altera_lnsim_components.all;
entity ip_agi027_1e1v_ram_rw_rw is
- generic (
+ generic (
g_inferred : boolean := false;
g_adr_w : natural := 5;
g_dat_w : natural := 8;
@@ -61,7 +61,7 @@ end ip_agi027_1e1v_ram_rw_rw;
architecture SYN of ip_agi027_1e1v_ram_rw_rw is
constant c_outdata_reg : string := tech_sel_a_b(g_rd_latency = 1, "UNREGISTERED", "CLOCK0");
-
+
component altera_syncram
generic (
address_reg_b : string;
@@ -106,9 +106,9 @@ architecture SYN of ip_agi027_1e1v_ram_rw_rw is
q_b : out std_logic_vector(g_dat_w - 1 downto 0)
);
end component;
-
+
-- Is used for gen_inferred:
- signal addr_a : natural range 0 to g_nof_words - 1;
+ signal addr_a : natural range 0 to g_nof_words - 1;
signal addr_b : natural range 0 to g_nof_words - 1;
signal out_a : std_logic_vector(g_dat_w - 1 downto 0);
@@ -118,7 +118,7 @@ architecture SYN of ip_agi027_1e1v_ram_rw_rw is
signal reg_b : std_logic_vector(g_dat_w - 1 downto 0);
begin
assert g_rd_latency = 1 or g_rd_latency = 2 report "ip_agi027_1e1v_ram_rw_rw : read latency must be 1 (default) or 2" severity FAILURE;
-
+
gen_ip : if g_inferred = false generate
u_altera_syncram : altera_syncram
generic map (
@@ -163,9 +163,9 @@ begin
q_a => q_a,
q_b => q_b
);
-
+
end generate;
-
+
gen_inferred : if g_inferred = true generate
addr_a <= to_integer(unsigned(address_a));
addr_b <= to_integer(unsigned(address_b));
@@ -193,5 +193,5 @@ begin
q_a <= out_a when g_rd_latency = 1 else reg_a;
q_b <= out_b when g_rd_latency = 1 else reg_b;
end generate;
-
+
end SYN;
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd
index 18b7ad2a89d9bfff642be56a3fe3661fda411ca9..5d05a15d508a3817cc0ff93603c3946cb7a15659 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_dual_clock.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Purpose:
-- RadioHDL wrapper
@@ -29,7 +29,7 @@
-- Reference:
-- Copied from ip_arria10_e2sg/ip_arria10_e2sg_simple_dual_port_ram_dual_clock.vhd
-- and the inferred Altera code was obtained using template insert with
--- Quartus 14.0a10.
+-- Quartus 14.0a10.
library ieee;
use ieee.std_logic_1164.all;
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
index 1db71ba51a45739a6ca0ae69e4f9a35e7e42d581..b39f324843e4c35be2e44d61f92ddd729485596f 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_simple_dual_port_ram_single_clock.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Purpose:
-- RadioHDL wrapper
@@ -29,7 +29,7 @@
-- Reference:
-- Copied from ip_arria10_e2sg/ip_arria10_e2sg_simple_dual_port_ram_simple_clock.vhd
-- and the inferred Altera code was obtained using template insert with
--- Quartus 14.0a10.
+-- Quartus 14.0a10.
library ieee;
use ieee.std_logic_1164.all;
diff --git a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
index 1c4e5887939008a688f145729f856d21df79694f..495fb1624c07ebdbb8d992350a81b8542661e322 100644
--- a/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
+++ b/libraries/technology/ip_agi027_1e1v/ram/ip_agi027_1e1v_true_dual_port_ram_single_clock.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Purpose:
-- RadioHDL wrapper
@@ -30,7 +30,7 @@
-- Reference:
-- Copied from ip_arria10_e2sg/ip_arria10_e2sg_true_dual_port_ram_dual_clock.vhd
-- and the inferred Altera code was obtained using template insert with
--- Quartus 14.0a10.
+-- Quartus 14.0a10.
-- Remark:
-- The orignal file is for True Dual-Port RAM with dual clock. However, that is
-- not supported by the Agilex 7 in the way it is used before Agilex 7.
diff --git a/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_component_pkg.vhd b/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_component_pkg.vhd
index 2607c428e0b2bf817959fdb4cdb80469b12e165d..3e33a817c1405b34d4f359f75abf433fda02eced 100644
--- a/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_component_pkg.vhd
+++ b/libraries/technology/ip_agi027_1e1v/reset_release/ip_agi027_1e1v_reset_release_component_pkg.vhd
@@ -27,7 +27,7 @@
-- Description:
-- . Wrapper for reset release IPs, specific for technology c_tech_agi027_1e1v
-- that is used by the iwave FPGA platform.
--- . The Reset Release IP is necessary to use for Agilex7 devices.
+-- . The Reset Release IP is necessary to use for Agilex7 devices.
-- See README.txt for more information about this.
--
-------------------------------------------------------------------------------
diff --git a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd
index ec1bc006bcf15dd0a3b8352b76460be6ce88febb..8ffae3429adc9b75650025a2b3779dfa63336de6 100644
--- a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd
+++ b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_in_1.vhd
@@ -39,13 +39,13 @@ library IEEE;
use IEEE.std_logic_1164.all;
entity ip_arria10_ddio_in_1 is
- port (
- datain : in std_logic_vector(0 downto 0) := (others => '0');
- inclock : in std_logic := '0';
- aclr : in std_logic := '0';
- dataout_h : out std_logic_vector(0 downto 0);
- dataout_l : out std_logic_vector(0 downto 0)
- );
+ port (
+ datain : in std_logic_vector(0 downto 0) := (others => '0');
+ inclock : in std_logic := '0';
+ aclr : in std_logic := '0';
+ dataout_h : out std_logic_vector(0 downto 0);
+ dataout_l : out std_logic_vector(0 downto 0)
+ );
end ip_arria10_ddio_in_1;
architecture beh of ip_arria10_ddio_in_1 is
diff --git a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd
index 99ad1519d6ec0abe1d1920c480b0c0a88e1880cc..b8a5cb6f5c94924105cab97b188da2ed05e92845 100644
--- a/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd
+++ b/libraries/technology/ip_arria10/ddio/sim/ip_arria10_ddio_out_1.vhd
@@ -36,13 +36,13 @@ library IEEE;
use IEEE.std_logic_1164.all;
entity ip_arria10_ddio_out_1 is
- port (
- dataout : out std_logic_vector(0 downto 0);
- outclock : in std_logic := '0';
- aclr : in std_logic := '0';
- datain_h : in std_logic_vector(0 downto 0) := (others => '0');
- datain_l : in std_logic_vector(0 downto 0) := (others => '0')
- );
+ port (
+ dataout : out std_logic_vector(0 downto 0);
+ outclock : in std_logic := '0';
+ aclr : in std_logic := '0';
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0');
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0')
+ );
end ip_arria10_ddio_out_1;
architecture beh of ip_arria10_ddio_out_1 is
diff --git a/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd b/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
index 0c619c5edbcfd63986e20d6fa9c37c32c066c7fe..322a320bac5e5f2aeac5f4b1feeaf34408b31087 100644
--- a/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
+++ b/libraries/technology/ip_arria10/ddio/sim/tb_ip_arria10_ddio_1.vhd
@@ -90,32 +90,32 @@ begin
in_data(0) <= in_dat;
u_ddio_in : entity work.ip_arria10_ddio_in_1
- port map (
- datain => in_data,
- inclock => clk,
- dataout_h => data_h,
- dataout_l => data_l
- );
+ port map (
+ datain => in_data,
+ inclock => clk,
+ dataout_h => data_h,
+ dataout_l => data_l
+ );
u_ddio_out : entity work.ip_arria10_ddio_out_1
- port map (
- dataout => out_data,
- outclock => clk,
- datain_h => data_h,
- datain_l => data_l
- );
+ port map (
+ dataout => out_data,
+ outclock => clk,
+ datain_h => data_h,
+ datain_l => data_l
+ );
- out_dat <= out_data(0);
+ out_dat <= out_data(0);
- out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
+ out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
- p_verify : process(clk)
- begin
- if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_ddio_1: Error, unexpeced data at falling edge";
- end if;
- if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_ddio_1: Error, unexpeced data at rising edge";
- end if;
- end process;
+ p_verify : process(clk)
+ begin
+ if falling_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_arria10_ddio_1: Error, unexpeced data at falling edge";
+ end if;
+ if rising_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_arria10_ddio_1: Error, unexpeced data at rising edge";
+ end if;
+ end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
index 1fa58c09df658fe769799e9d15fe9a03b353fbbe..a89b791b4089f034214a7af1fef6b4401e205de7 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_in_1.vhd
@@ -39,13 +39,13 @@ library IEEE;
use IEEE.std_logic_1164.all;
entity ip_arria10_e1sg_ddio_in_1 is
- port (
- datain : in std_logic_vector(0 downto 0) := (others => '0');
- inclock : in std_logic := '0';
- aclr : in std_logic := '0';
- dataout_h : out std_logic_vector(0 downto 0);
- dataout_l : out std_logic_vector(0 downto 0)
- );
+ port (
+ datain : in std_logic_vector(0 downto 0) := (others => '0');
+ inclock : in std_logic := '0';
+ aclr : in std_logic := '0';
+ dataout_h : out std_logic_vector(0 downto 0);
+ dataout_l : out std_logic_vector(0 downto 0)
+ );
end ip_arria10_e1sg_ddio_in_1;
architecture beh of ip_arria10_e1sg_ddio_in_1 is
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
index fc28a379d95e90944401bb65cc1a92a91cb00a23..efbccf606873d64ffcbd949bad1f7b6f5f8608fe 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/ip_arria10_e1sg_ddio_out_1.vhd
@@ -36,13 +36,13 @@ library IEEE;
use IEEE.std_logic_1164.all;
entity ip_arria10_e1sg_ddio_out_1 is
- port (
- dataout : out std_logic_vector(0 downto 0);
- outclock : in std_logic := '0';
- aclr : in std_logic := '0';
- datain_h : in std_logic_vector(0 downto 0) := (others => '0');
- datain_l : in std_logic_vector(0 downto 0) := (others => '0')
- );
+ port (
+ dataout : out std_logic_vector(0 downto 0);
+ outclock : in std_logic := '0';
+ aclr : in std_logic := '0';
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0');
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0')
+ );
end ip_arria10_e1sg_ddio_out_1;
architecture beh of ip_arria10_e1sg_ddio_out_1 is
diff --git a/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd b/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
index 7521516fe76bbbe872297649543d9b6dd6cec6d0..fc77aadfc88883c1ed9f64fee6044e121a17dc31 100644
--- a/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddio/sim/tb_ip_arria10_e1sg_ddio_1.vhd
@@ -90,32 +90,32 @@ begin
in_data(0) <= in_dat;
u_ddio_in : entity work.ip_arria10_e1sg_ddio_in_1
- port map (
- datain => in_data,
- inclock => clk,
- dataout_h => data_h,
- dataout_l => data_l
- );
+ port map (
+ datain => in_data,
+ inclock => clk,
+ dataout_h => data_h,
+ dataout_l => data_l
+ );
u_ddio_out : entity work.ip_arria10_e1sg_ddio_out_1
- port map (
- dataout => out_data,
- outclock => clk,
- datain_h => data_h,
- datain_l => data_l
- );
+ port map (
+ dataout => out_data,
+ outclock => clk,
+ datain_h => data_h,
+ datain_l => data_l
+ );
- out_dat <= out_data(0);
+ out_dat <= out_data(0);
- out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
+ out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
- p_verify : process(clk)
- begin
- if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at falling edge";
- end if;
- if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at rising edge";
- end if;
- end process;
+ p_verify : process(clk)
+ begin
+ if falling_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at falling edge";
+ end if;
+ if rising_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_arria10_e1sg_ddio_1: Error, unexpeced data at rising edge";
+ end if;
+ end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
index cc07d963c90b7fffc61cfd21e35ddc6887ae124b..3481020aa847daa94f421e44b39496ec33912fff 100644
--- a/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400/ip_arria10_e1sg_ddr4_8g_2400_inst.vhd
@@ -1,72 +1,72 @@
- component ip_arria10_e1sg_ddr4_8g_2400 is
- port (
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- emif_usr_clk : out std_logic; -- clk
- emif_usr_reset_n : out std_logic; -- reset_n
- global_reset_n : in std_logic := 'X'; -- reset_n
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- pll_ref_clk : in std_logic := 'X'; -- clk
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic -- local_cal_fail
- );
- end component ip_arria10_e1sg_ddr4_8g_2400;
+ component ip_arria10_e1sg_ddr4_8g_2400 is
+ port (
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic; -- readdatavalid
+ emif_usr_clk : out std_logic; -- clk
+ emif_usr_reset_n : out std_logic; -- reset_n
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic -- local_cal_fail
+ );
+ end component ip_arria10_e1sg_ddr4_8g_2400;
- u0 : component ip_arria10_e1sg_ddr4_8g_2400
- port map (
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk_clock_source.clk
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_reset_source.reset_n
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_reset_sink.reset_n
- mem_ck => CONNECTED_TO_mem_ck, -- mem_conduit_end.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct_conduit_end.oct_rzqin
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk_clock_sink.clk
- local_cal_success => CONNECTED_TO_local_cal_success, -- status_conduit_end.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
- );
+ u0 : component ip_arria10_e1sg_ddr4_8g_2400
+ port map (
+ amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_avalon_slave_0.waitrequest_n
+ amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
+ amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
+ amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk_clock_source.clk
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_reset_source.reset_n
+ global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_reset_sink.reset_n
+ mem_ck => CONNECTED_TO_mem_ck, -- mem_conduit_end.mem_ck
+ mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
+ mem_a => CONNECTED_TO_mem_a, -- .mem_a
+ mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
+ mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
+ mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
+ mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
+ mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
+ mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
+ mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
+ mem_par => CONNECTED_TO_mem_par, -- .mem_par
+ mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
+ mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
+ mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
+ oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct_conduit_end.oct_rzqin
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk_clock_sink.clk
+ local_cal_success => CONNECTED_TO_local_cal_success, -- status_conduit_end.local_cal_success
+ local_cal_fail => CONNECTED_TO_local_cal_fail -- .local_cal_fail
+ );
diff --git a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
index d6f8e5d7c4e426f455ee85725d61eb4b9ceeebe8..9ed043eb1ad7c959601c6808f37fc1221e43e817 100644
--- a/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/ram/ip_arria10_e1sg_ram_crwk_crw/ip_arria10_e1sg_ram_crwk_crw_inst.vhd
@@ -1,32 +1,32 @@
- component ip_arria10_e1sg_ram_crwk_crw is
- port (
- data_a : in std_logic_vector(31 downto 0) := (others => 'X'); -- datain_a
- data_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_b
- address_a : in std_logic_vector(7 downto 0) := (others => 'X'); -- address_a
- address_b : in std_logic_vector(9 downto 0) := (others => 'X'); -- address_b
- wren_a : in std_logic := 'X'; -- wren_a
- wren_b : in std_logic := 'X'; -- wren_b
- clock_a : in std_logic := 'X'; -- clock_a
- clock_b : in std_logic := 'X'; -- clock_b
- rden_a : in std_logic := 'X'; -- rden_a
- rden_b : in std_logic := 'X'; -- rden_b
- q_a : out std_logic_vector(31 downto 0); -- dataout_a
- q_b : out std_logic_vector(7 downto 0) -- dataout_b
- );
- end component ip_arria10_e1sg_ram_crwk_crw;
+ component ip_arria10_e1sg_ram_crwk_crw is
+ port (
+ data_a : in std_logic_vector(31 downto 0) := (others => 'X'); -- datain_a
+ data_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_b
+ address_a : in std_logic_vector(7 downto 0) := (others => 'X'); -- address_a
+ address_b : in std_logic_vector(9 downto 0) := (others => 'X'); -- address_b
+ wren_a : in std_logic := 'X'; -- wren_a
+ wren_b : in std_logic := 'X'; -- wren_b
+ clock_a : in std_logic := 'X'; -- clock_a
+ clock_b : in std_logic := 'X'; -- clock_b
+ rden_a : in std_logic := 'X'; -- rden_a
+ rden_b : in std_logic := 'X'; -- rden_b
+ q_a : out std_logic_vector(31 downto 0); -- dataout_a
+ q_b : out std_logic_vector(7 downto 0) -- dataout_b
+ );
+ end component ip_arria10_e1sg_ram_crwk_crw;
- u0 : component ip_arria10_e1sg_ram_crwk_crw
- port map (
- data_a => CONNECTED_TO_data_a, -- ram_input.datain_a
- data_b => CONNECTED_TO_data_b, -- .datain_b
- address_a => CONNECTED_TO_address_a, -- .address_a
- address_b => CONNECTED_TO_address_b, -- .address_b
- wren_a => CONNECTED_TO_wren_a, -- .wren_a
- wren_b => CONNECTED_TO_wren_b, -- .wren_b
- clock_a => CONNECTED_TO_clock_a, -- .clock_a
- clock_b => CONNECTED_TO_clock_b, -- .clock_b
- rden_a => CONNECTED_TO_rden_a, -- .rden_a
- rden_b => CONNECTED_TO_rden_b, -- .rden_b
- q_a => CONNECTED_TO_q_a, -- ram_output.dataout_a
- q_b => CONNECTED_TO_q_b -- .dataout_b
- );
+ u0 : component ip_arria10_e1sg_ram_crwk_crw
+ port map (
+ data_a => CONNECTED_TO_data_a, -- ram_input.datain_a
+ data_b => CONNECTED_TO_data_b, -- .datain_b
+ address_a => CONNECTED_TO_address_a, -- .address_a
+ address_b => CONNECTED_TO_address_b, -- .address_b
+ wren_a => CONNECTED_TO_wren_a, -- .wren_a
+ wren_b => CONNECTED_TO_wren_b, -- .wren_b
+ clock_a => CONNECTED_TO_clock_a, -- .clock_a
+ clock_b => CONNECTED_TO_clock_b, -- .clock_b
+ rden_a => CONNECTED_TO_rden_a, -- .rden_a
+ rden_b => CONNECTED_TO_rden_b, -- .rden_b
+ q_a => CONNECTED_TO_q_a, -- ram_output.dataout_a
+ q_b => CONNECTED_TO_q_b -- .dataout_b
+ );
diff --git a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
index 340470c1754886571c8d2ec237c9c2b81c18873f..f4e5e0239f626418a32ca1772ed0203ed7833a19 100644
--- a/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
+++ b/libraries/technology/ip_arria10_e1sg/transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3/ip_arria10_e1sg_transceiver_reset_controller_3_inst.vhd
@@ -1,36 +1,36 @@
- component ip_arria10_e1sg_transceiver_reset_controller_3 is
- port (
- clock : in std_logic := 'X'; -- clk
- pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
- pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
- pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
- reset : in std_logic := 'X'; -- reset
- rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
- rx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_cal_busy
- rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
- rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_is_lockedtodata
- rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
- tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
- tx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_cal_busy
- tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
- tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
- );
- end component ip_arria10_e1sg_transceiver_reset_controller_3;
+ component ip_arria10_e1sg_transceiver_reset_controller_3 is
+ port (
+ clock : in std_logic := 'X'; -- clk
+ pll_locked : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_locked
+ pll_powerdown : out std_logic_vector(0 downto 0); -- pll_powerdown
+ pll_select : in std_logic_vector(0 downto 0) := (others => 'X'); -- pll_select
+ reset : in std_logic := 'X'; -- reset
+ rx_analogreset : out std_logic_vector(2 downto 0); -- rx_analogreset
+ rx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_cal_busy
+ rx_digitalreset : out std_logic_vector(2 downto 0); -- rx_digitalreset
+ rx_is_lockedtodata : in std_logic_vector(2 downto 0) := (others => 'X'); -- rx_is_lockedtodata
+ rx_ready : out std_logic_vector(2 downto 0); -- rx_ready
+ tx_analogreset : out std_logic_vector(2 downto 0); -- tx_analogreset
+ tx_cal_busy : in std_logic_vector(2 downto 0) := (others => 'X'); -- tx_cal_busy
+ tx_digitalreset : out std_logic_vector(2 downto 0); -- tx_digitalreset
+ tx_ready : out std_logic_vector(2 downto 0) -- tx_ready
+ );
+ end component ip_arria10_e1sg_transceiver_reset_controller_3;
- u0 : component ip_arria10_e1sg_transceiver_reset_controller_3
- port map (
- clock => CONNECTED_TO_clock, -- clock.clk
- pll_locked => CONNECTED_TO_pll_locked, -- pll_locked.pll_locked
- pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
- pll_select => CONNECTED_TO_pll_select, -- pll_select.pll_select
- reset => CONNECTED_TO_reset, -- reset.reset
- rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
- rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
- rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
- rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
- rx_ready => CONNECTED_TO_rx_ready, -- rx_ready.rx_ready
- tx_analogreset => CONNECTED_TO_tx_analogreset, -- tx_analogreset.tx_analogreset
- tx_cal_busy => CONNECTED_TO_tx_cal_busy, -- tx_cal_busy.tx_cal_busy
- tx_digitalreset => CONNECTED_TO_tx_digitalreset, -- tx_digitalreset.tx_digitalreset
- tx_ready => CONNECTED_TO_tx_ready -- tx_ready.tx_ready
- );
+ u0 : component ip_arria10_e1sg_transceiver_reset_controller_3
+ port map (
+ clock => CONNECTED_TO_clock, -- clock.clk
+ pll_locked => CONNECTED_TO_pll_locked, -- pll_locked.pll_locked
+ pll_powerdown => CONNECTED_TO_pll_powerdown, -- pll_powerdown.pll_powerdown
+ pll_select => CONNECTED_TO_pll_select, -- pll_select.pll_select
+ reset => CONNECTED_TO_reset, -- reset.reset
+ rx_analogreset => CONNECTED_TO_rx_analogreset, -- rx_analogreset.rx_analogreset
+ rx_cal_busy => CONNECTED_TO_rx_cal_busy, -- rx_cal_busy.rx_cal_busy
+ rx_digitalreset => CONNECTED_TO_rx_digitalreset, -- rx_digitalreset.rx_digitalreset
+ rx_is_lockedtodata => CONNECTED_TO_rx_is_lockedtodata, -- rx_is_lockedtodata.rx_is_lockedtodata
+ rx_ready => CONNECTED_TO_rx_ready, -- rx_ready.rx_ready
+ tx_analogreset => CONNECTED_TO_tx_analogreset, -- tx_analogreset.tx_analogreset
+ tx_cal_busy => CONNECTED_TO_tx_cal_busy, -- tx_cal_busy.tx_cal_busy
+ tx_digitalreset => CONNECTED_TO_tx_digitalreset, -- tx_digitalreset.tx_digitalreset
+ tx_ready => CONNECTED_TO_tx_ready -- tx_ready.tx_ready
+ );
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd
index 6422bbee2dcf6b681ebe79cb5815e383b5834c7b..afb6c94cf523a50159a8b4b9b88c27bedbdd468f 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_in_1.vhd
@@ -39,13 +39,13 @@ library IEEE;
use IEEE.std_logic_1164.all;
entity ip_arria10_e2sg_ddio_in_1 is
- port (
- datain : in std_logic_vector(0 downto 0) := (others => '0');
- ck : in std_logic := '0';
- aclr : in std_logic := '0';
- dataout_h : out std_logic_vector(0 downto 0);
- dataout_l : out std_logic_vector(0 downto 0)
- );
+ port (
+ datain : in std_logic_vector(0 downto 0) := (others => '0');
+ ck : in std_logic := '0';
+ aclr : in std_logic := '0';
+ dataout_h : out std_logic_vector(0 downto 0);
+ dataout_l : out std_logic_vector(0 downto 0)
+ );
end ip_arria10_e2sg_ddio_in_1;
architecture beh of ip_arria10_e2sg_ddio_in_1 is
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd
index b27ef2ac7fc403b6862f8a9cc25ece49c39dfd12..4b819029dabcfbe502fb37b616e9cf69f94edf5f 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/ip_arria10_e2sg_ddio_out_1.vhd
@@ -36,13 +36,13 @@ library IEEE;
use IEEE.std_logic_1164.all;
entity ip_arria10_e2sg_ddio_out_1 is
- port (
- dataout : out std_logic_vector(0 downto 0);
- outclock : in std_logic := '0';
- aclr : in std_logic := '0';
- datain_h : in std_logic_vector(0 downto 0) := (others => '0');
- datain_l : in std_logic_vector(0 downto 0) := (others => '0')
- );
+ port (
+ dataout : out std_logic_vector(0 downto 0);
+ outclock : in std_logic := '0';
+ aclr : in std_logic := '0';
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0');
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0')
+ );
end ip_arria10_e2sg_ddio_out_1;
architecture beh of ip_arria10_e2sg_ddio_out_1 is
diff --git a/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd b/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
index 4f443703ccb3ece5a38e50d11c63fef1dfd1f819..11481111e86f1a77bb18ebd98e9dd92b5b8d0dcf 100644
--- a/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddio/sim/tb_ip_arria10_e2sg_ddio_1.vhd
@@ -90,32 +90,32 @@ begin
in_data(0) <= in_dat;
u_ddio_in : entity work.ip_arria10_e2sg_ddio_in_1
- port map (
- datain => in_data,
- ck => clk,
- dataout_h => data_h,
- dataout_l => data_l
- );
+ port map (
+ datain => in_data,
+ ck => clk,
+ dataout_h => data_h,
+ dataout_l => data_l
+ );
u_ddio_out : entity work.ip_arria10_e2sg_ddio_out_1
- port map (
- dataout => out_data,
- outclock => clk,
- datain_h => data_h,
- datain_l => data_l
- );
+ port map (
+ dataout => out_data,
+ outclock => clk,
+ datain_h => data_h,
+ datain_l => data_l
+ );
- out_dat <= out_data(0);
+ out_dat <= out_data(0);
- out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
+ out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
- p_verify : process(clk)
- begin
- if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at falling edge";
- end if;
- if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at rising edge";
- end if;
- end process;
+ p_verify : process(clk)
+ begin
+ if falling_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at falling edge";
+ end if;
+ if rising_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_arria10_e2sg_ddio_1: Error, unexpeced data at rising edge";
+ end if;
+ end process;
end tb;
diff --git a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
index 03062d9b02f9e011238dfc6b4cd39b0bc78ac2bc..fd1386a58d73137c8be2b4f16798e3163f760c6c 100644
--- a/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600/ip_arria10_e2sg_ddr4_8g_1600_inst.vhd
@@ -1,90 +1,90 @@
- component ip_arria10_e2sg_ddr4_8g_1600 is
- port (
- global_reset_n : in std_logic := 'X'; -- reset_n
- pll_ref_clk : in std_logic := 'X'; -- clk
- oct_rzqin : in std_logic := 'X'; -- oct_rzqin
- mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
- mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
- mem_a : out std_logic_vector(16 downto 0); -- mem_a
- mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
- mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
- mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
- mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
- mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
- mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
- mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
- mem_par : out std_logic_vector(0 downto 0); -- mem_par
- mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
- mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
- mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
- mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
- mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
- local_cal_success : out std_logic; -- local_cal_success
- local_cal_fail : out std_logic; -- local_cal_fail
- emif_usr_reset_n : out std_logic; -- reset_n
- emif_usr_clk : out std_logic; -- clk
- amm_ready_0 : out std_logic; -- waitrequest_n
- amm_read_0 : in std_logic := 'X'; -- read
- amm_write_0 : in std_logic := 'X'; -- write
- amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
- amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
- amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
- amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
- amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
- amm_readdatavalid_0 : out std_logic; -- readdatavalid
- mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
- mmr_slave_read_0 : in std_logic := 'X'; -- read
- mmr_slave_write_0 : in std_logic := 'X'; -- write
- mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
- mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
- mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
- mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
- mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
- mmr_slave_readdatavalid_0 : out std_logic -- readdatavalid
- );
- end component ip_arria10_e2sg_ddr4_8g_1600;
+ component ip_arria10_e2sg_ddr4_8g_1600 is
+ port (
+ global_reset_n : in std_logic := 'X'; -- reset_n
+ pll_ref_clk : in std_logic := 'X'; -- clk
+ oct_rzqin : in std_logic := 'X'; -- oct_rzqin
+ mem_ck : out std_logic_vector(1 downto 0); -- mem_ck
+ mem_ck_n : out std_logic_vector(1 downto 0); -- mem_ck_n
+ mem_a : out std_logic_vector(16 downto 0); -- mem_a
+ mem_act_n : out std_logic_vector(0 downto 0); -- mem_act_n
+ mem_ba : out std_logic_vector(1 downto 0); -- mem_ba
+ mem_bg : out std_logic_vector(1 downto 0); -- mem_bg
+ mem_cke : out std_logic_vector(1 downto 0); -- mem_cke
+ mem_cs_n : out std_logic_vector(1 downto 0); -- mem_cs_n
+ mem_odt : out std_logic_vector(1 downto 0); -- mem_odt
+ mem_reset_n : out std_logic_vector(0 downto 0); -- mem_reset_n
+ mem_par : out std_logic_vector(0 downto 0); -- mem_par
+ mem_alert_n : in std_logic_vector(0 downto 0) := (others => 'X'); -- mem_alert_n
+ mem_dqs : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs
+ mem_dqs_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dqs_n
+ mem_dq : inout std_logic_vector(71 downto 0) := (others => 'X'); -- mem_dq
+ mem_dbi_n : inout std_logic_vector(8 downto 0) := (others => 'X'); -- mem_dbi_n
+ local_cal_success : out std_logic; -- local_cal_success
+ local_cal_fail : out std_logic; -- local_cal_fail
+ emif_usr_reset_n : out std_logic; -- reset_n
+ emif_usr_clk : out std_logic; -- clk
+ amm_ready_0 : out std_logic; -- waitrequest_n
+ amm_read_0 : in std_logic := 'X'; -- read
+ amm_write_0 : in std_logic := 'X'; -- write
+ amm_address_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address
+ amm_readdata_0 : out std_logic_vector(575 downto 0); -- readdata
+ amm_writedata_0 : in std_logic_vector(575 downto 0) := (others => 'X'); -- writedata
+ amm_burstcount_0 : in std_logic_vector(6 downto 0) := (others => 'X'); -- burstcount
+ amm_byteenable_0 : in std_logic_vector(71 downto 0) := (others => 'X'); -- byteenable
+ amm_readdatavalid_0 : out std_logic; -- readdatavalid
+ mmr_slave_waitrequest_0 : out std_logic; -- waitrequest
+ mmr_slave_read_0 : in std_logic := 'X'; -- read
+ mmr_slave_write_0 : in std_logic := 'X'; -- write
+ mmr_slave_address_0 : in std_logic_vector(9 downto 0) := (others => 'X'); -- address
+ mmr_slave_readdata_0 : out std_logic_vector(31 downto 0); -- readdata
+ mmr_slave_writedata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
+ mmr_slave_burstcount_0 : in std_logic_vector(1 downto 0) := (others => 'X'); -- burstcount
+ mmr_slave_beginbursttransfer_0 : in std_logic := 'X'; -- beginbursttransfer
+ mmr_slave_readdatavalid_0 : out std_logic -- readdatavalid
+ );
+ end component ip_arria10_e2sg_ddr4_8g_1600;
- u0 : component ip_arria10_e2sg_ddr4_8g_1600
- port map (
- global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
- pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
- oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
- mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
- mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
- mem_a => CONNECTED_TO_mem_a, -- .mem_a
- mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
- mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
- mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
- mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
- mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
- mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
- mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
- mem_par => CONNECTED_TO_mem_par, -- .mem_par
- mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
- mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
- mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
- mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
- mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
- local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
- local_cal_fail => CONNECTED_TO_local_cal_fail, -- .local_cal_fail
- emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
- emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
- amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
- amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
- amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
- amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
- amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
- amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
- amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
- amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
- amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
- mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
- mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
- mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
- mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
- mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
- mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
- mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
- mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
- mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0 -- .readdatavalid
- );
+ u0 : component ip_arria10_e2sg_ddr4_8g_1600
+ port map (
+ global_reset_n => CONNECTED_TO_global_reset_n, -- global_reset_n.reset_n
+ pll_ref_clk => CONNECTED_TO_pll_ref_clk, -- pll_ref_clk.clk
+ oct_rzqin => CONNECTED_TO_oct_rzqin, -- oct.oct_rzqin
+ mem_ck => CONNECTED_TO_mem_ck, -- mem.mem_ck
+ mem_ck_n => CONNECTED_TO_mem_ck_n, -- .mem_ck_n
+ mem_a => CONNECTED_TO_mem_a, -- .mem_a
+ mem_act_n => CONNECTED_TO_mem_act_n, -- .mem_act_n
+ mem_ba => CONNECTED_TO_mem_ba, -- .mem_ba
+ mem_bg => CONNECTED_TO_mem_bg, -- .mem_bg
+ mem_cke => CONNECTED_TO_mem_cke, -- .mem_cke
+ mem_cs_n => CONNECTED_TO_mem_cs_n, -- .mem_cs_n
+ mem_odt => CONNECTED_TO_mem_odt, -- .mem_odt
+ mem_reset_n => CONNECTED_TO_mem_reset_n, -- .mem_reset_n
+ mem_par => CONNECTED_TO_mem_par, -- .mem_par
+ mem_alert_n => CONNECTED_TO_mem_alert_n, -- .mem_alert_n
+ mem_dqs => CONNECTED_TO_mem_dqs, -- .mem_dqs
+ mem_dqs_n => CONNECTED_TO_mem_dqs_n, -- .mem_dqs_n
+ mem_dq => CONNECTED_TO_mem_dq, -- .mem_dq
+ mem_dbi_n => CONNECTED_TO_mem_dbi_n, -- .mem_dbi_n
+ local_cal_success => CONNECTED_TO_local_cal_success, -- status.local_cal_success
+ local_cal_fail => CONNECTED_TO_local_cal_fail, -- .local_cal_fail
+ emif_usr_reset_n => CONNECTED_TO_emif_usr_reset_n, -- emif_usr_reset_n.reset_n
+ emif_usr_clk => CONNECTED_TO_emif_usr_clk, -- emif_usr_clk.clk
+ amm_ready_0 => CONNECTED_TO_amm_ready_0, -- ctrl_amm_0.waitrequest_n
+ amm_read_0 => CONNECTED_TO_amm_read_0, -- .read
+ amm_write_0 => CONNECTED_TO_amm_write_0, -- .write
+ amm_address_0 => CONNECTED_TO_amm_address_0, -- .address
+ amm_readdata_0 => CONNECTED_TO_amm_readdata_0, -- .readdata
+ amm_writedata_0 => CONNECTED_TO_amm_writedata_0, -- .writedata
+ amm_burstcount_0 => CONNECTED_TO_amm_burstcount_0, -- .burstcount
+ amm_byteenable_0 => CONNECTED_TO_amm_byteenable_0, -- .byteenable
+ amm_readdatavalid_0 => CONNECTED_TO_amm_readdatavalid_0, -- .readdatavalid
+ mmr_slave_waitrequest_0 => CONNECTED_TO_mmr_slave_waitrequest_0, -- ctrl_mmr_slave_0.waitrequest
+ mmr_slave_read_0 => CONNECTED_TO_mmr_slave_read_0, -- .read
+ mmr_slave_write_0 => CONNECTED_TO_mmr_slave_write_0, -- .write
+ mmr_slave_address_0 => CONNECTED_TO_mmr_slave_address_0, -- .address
+ mmr_slave_readdata_0 => CONNECTED_TO_mmr_slave_readdata_0, -- .readdata
+ mmr_slave_writedata_0 => CONNECTED_TO_mmr_slave_writedata_0, -- .writedata
+ mmr_slave_burstcount_0 => CONNECTED_TO_mmr_slave_burstcount_0, -- .burstcount
+ mmr_slave_beginbursttransfer_0 => CONNECTED_TO_mmr_slave_beginbursttransfer_0, -- .beginbursttransfer
+ mmr_slave_readdatavalid_0 => CONNECTED_TO_mmr_slave_readdatavalid_0 -- .readdatavalid
+ );
diff --git a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
index 9c6b139903684980cc8b5d8d919c29f563d62219..2555d7e33db261a589dede765e698d0453359287 100644
--- a/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
+++ b/libraries/technology/ip_arria10_e2sg/ram/ip_arria10_e2sg_ram_crw_crw/ip_arria10_e2sg_ram_crw_crw_inst.vhd
@@ -1,28 +1,28 @@
- component ip_arria10_e2sg_ram_crw_crw is
- port (
- data_a : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_a
- q_a : out std_logic_vector(7 downto 0); -- dataout_a
- data_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_b
- q_b : out std_logic_vector(7 downto 0); -- dataout_b
- address_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_a
- address_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_b
- wren_a : in std_logic := 'X'; -- wren_a
- wren_b : in std_logic := 'X'; -- wren_b
- clock_a : in std_logic := 'X'; -- clk
- clock_b : in std_logic := 'X' -- clk
- );
- end component ip_arria10_e2sg_ram_crw_crw;
+ component ip_arria10_e2sg_ram_crw_crw is
+ port (
+ data_a : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_a
+ q_a : out std_logic_vector(7 downto 0); -- dataout_a
+ data_b : in std_logic_vector(7 downto 0) := (others => 'X'); -- datain_b
+ q_b : out std_logic_vector(7 downto 0); -- dataout_b
+ address_a : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_a
+ address_b : in std_logic_vector(4 downto 0) := (others => 'X'); -- address_b
+ wren_a : in std_logic := 'X'; -- wren_a
+ wren_b : in std_logic := 'X'; -- wren_b
+ clock_a : in std_logic := 'X'; -- clk
+ clock_b : in std_logic := 'X' -- clk
+ );
+ end component ip_arria10_e2sg_ram_crw_crw;
- u0 : component ip_arria10_e2sg_ram_crw_crw
- port map (
- data_a => CONNECTED_TO_data_a, -- data_a.datain_a
- q_a => CONNECTED_TO_q_a, -- q_a.dataout_a
- data_b => CONNECTED_TO_data_b, -- data_b.datain_b
- q_b => CONNECTED_TO_q_b, -- q_b.dataout_b
- address_a => CONNECTED_TO_address_a, -- address_a.address_a
- address_b => CONNECTED_TO_address_b, -- address_b.address_b
- wren_a => CONNECTED_TO_wren_a, -- wren_a.wren_a
- wren_b => CONNECTED_TO_wren_b, -- wren_b.wren_b
- clock_a => CONNECTED_TO_clock_a, -- clock_a.clk
- clock_b => CONNECTED_TO_clock_b -- clock_b.clk
- );
+ u0 : component ip_arria10_e2sg_ram_crw_crw
+ port map (
+ data_a => CONNECTED_TO_data_a, -- data_a.datain_a
+ q_a => CONNECTED_TO_q_a, -- q_a.dataout_a
+ data_b => CONNECTED_TO_data_b, -- data_b.datain_b
+ q_b => CONNECTED_TO_q_b, -- q_b.dataout_b
+ address_a => CONNECTED_TO_address_a, -- address_a.address_a
+ address_b => CONNECTED_TO_address_b, -- address_b.address_b
+ wren_a => CONNECTED_TO_wren_a, -- wren_a.wren_a
+ wren_b => CONNECTED_TO_wren_b, -- wren_b.wren_b
+ clock_a => CONNECTED_TO_clock_a, -- clock_a.clk
+ clock_b => CONNECTED_TO_clock_b -- clock_b.clk
+ );
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd b/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd
index 757284ef4804d4cc036d4f22098de65c6ad987da..e4e2cc945ddff6e79d0a58ec98dd7581f53bc2b2 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_in_1.vhd
@@ -39,13 +39,13 @@ library IEEE;
use IEEE.std_logic_1164.all;
entity ip_arria10_e3sge3_ddio_in_1 is
- port (
- datain : in std_logic_vector(0 downto 0) := (others => '0');
- inclock : in std_logic := '0';
- aclr : in std_logic := '0';
- dataout_h : out std_logic_vector(0 downto 0);
- dataout_l : out std_logic_vector(0 downto 0)
- );
+ port (
+ datain : in std_logic_vector(0 downto 0) := (others => '0');
+ inclock : in std_logic := '0';
+ aclr : in std_logic := '0';
+ dataout_h : out std_logic_vector(0 downto 0);
+ dataout_l : out std_logic_vector(0 downto 0)
+ );
end ip_arria10_e3sge3_ddio_in_1;
architecture beh of ip_arria10_e3sge3_ddio_in_1 is
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd b/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd
index d18787b4fba26a3765f03a99b6f605c442b2f7db..e6f93895324d5a5738f6960f36cd847f6ba7fb95 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/sim/ip_arria10_e3sge3_ddio_out_1.vhd
@@ -36,13 +36,13 @@ library IEEE;
use IEEE.std_logic_1164.all;
entity ip_arria10_e3sge3_ddio_out_1 is
- port (
- dataout : out std_logic_vector(0 downto 0);
- outclock : in std_logic := '0';
- aclr : in std_logic := '0';
- datain_h : in std_logic_vector(0 downto 0) := (others => '0');
- datain_l : in std_logic_vector(0 downto 0) := (others => '0')
- );
+ port (
+ dataout : out std_logic_vector(0 downto 0);
+ outclock : in std_logic := '0';
+ aclr : in std_logic := '0';
+ datain_h : in std_logic_vector(0 downto 0) := (others => '0');
+ datain_l : in std_logic_vector(0 downto 0) := (others => '0')
+ );
end ip_arria10_e3sge3_ddio_out_1;
architecture beh of ip_arria10_e3sge3_ddio_out_1 is
diff --git a/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd b/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd
index c90e97ad924996ffee42ab1717ee503d844c9533..b03e85e4744aaebad8e2d1ac0fa9b665d5c468f1 100644
--- a/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd
+++ b/libraries/technology/ip_arria10_e3sge3/ddio/sim/tb_ip_arria10_e3sge3_ddio_1.vhd
@@ -90,32 +90,32 @@ begin
in_data(0) <= in_dat;
u_ddio_in : entity work.ip_arria10_e3sge3_ddio_in_1
- port map (
- datain => in_data,
- inclock => clk,
- dataout_h => data_h,
- dataout_l => data_l
- );
+ port map (
+ datain => in_data,
+ inclock => clk,
+ dataout_h => data_h,
+ dataout_l => data_l
+ );
u_ddio_out : entity work.ip_arria10_e3sge3_ddio_out_1
- port map (
- dataout => out_data,
- outclock => clk,
- datain_h => data_h,
- datain_l => data_l
- );
+ port map (
+ dataout => out_data,
+ outclock => clk,
+ datain_h => data_h,
+ datain_l => data_l
+ );
- out_dat <= out_data(0);
+ out_dat <= out_data(0);
- out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
+ out_dat_exp <= transport in_dat after c_clk_period * 1.5 + 1 ps;
- p_verify : process(clk)
- begin
- if falling_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e3sge3_ddio_1: Error, unexpeced data at falling edge";
- end if;
- if rising_edge(clk) then
- assert out_dat = out_dat_exp report "tb_ip_arria10_e3sge3_ddio_1: Error, unexpeced data at rising edge";
- end if;
- end process;
+ p_verify : process(clk)
+ begin
+ if falling_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_arria10_e3sge3_ddio_1: Error, unexpeced data at falling edge";
+ end if;
+ if rising_edge(clk) then
+ assert out_dat = out_dat_exp report "tb_ip_arria10_e3sge3_ddio_1: Error, unexpeced data at rising edge";
+ end if;
+ end process;
end tb;
diff --git a/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_out.vhd b/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_out.vhd
index 13c171d62c6cd0706d8998b29034a9400a6a6855..dc8d83fddaa986c507dba877299df94ac84b95fd 100644
--- a/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_out.vhd
+++ b/libraries/technology/ip_stratixiv/ddio/ip_stratixiv_ddio_out.vhd
@@ -76,23 +76,23 @@ end ip_stratixiv_ddio_out;
architecture str of ip_stratixiv_ddio_out is
begin
- ddio : ALTDDIO_OUT
- generic map (
- extend_oe_disable => "OFF",
- intended_device_family => g_device_family,
- invert_output => "OFF",
- lpm_hint => "UNUSED",
- lpm_type => "altddio_out",
- oe_reg => "UNREGISTERED",
- power_up_high => "OFF",
- width => g_width
- )
- port map (
- aclr => rst,
- datain_h => in_dat_hi,
- datain_l => in_dat_lo,
- outclock => in_clk,
- outclocken => in_clk_en,
- dataout => out_dat
- );
+ ddio : ALTDDIO_OUT
+ generic map (
+ extend_oe_disable => "OFF",
+ intended_device_family => g_device_family,
+ invert_output => "OFF",
+ lpm_hint => "UNUSED",
+ lpm_type => "altddio_out",
+ oe_reg => "UNREGISTERED",
+ power_up_high => "OFF",
+ width => g_width
+ )
+ port map (
+ aclr => rst,
+ datain_h => in_dat_hi,
+ datain_l => in_dat_lo,
+ outclock => in_clk,
+ outclocken => in_clk_en,
+ dataout => out_dat
+ );
end str;
diff --git a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
index 017f5c0a0319f09a43a40a62c4b5b491ab9ad038..947d81825c2e443f6db42f3f027dce36e0f98052 100644
--- a/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
+++ b/libraries/technology/ip_stratixiv/phy_xaui/tb_ip_stratixiv_phy_xaui.vhd
@@ -186,23 +186,23 @@ begin
-- DUT:
u_ip_phy_xaui : entity work.ip_stratixiv_phy_xaui_0
port map (
- pll_ref_clk => tr_clk,
- xgmii_tx_clk => tx_clk, -- rx_clk
- xgmii_rx_clk => rx_clk,
- xgmii_rx_dc => xgmii_rx_dc,
- xgmii_tx_dc => xgmii_tx_dc,
- xaui_rx_serial_data => xaui_rx_serial,
- xaui_tx_serial_data => xaui_tx_serial,
- rx_ready => OPEN,
- tx_ready => OPEN,
- phy_mgmt_clk => mm_clk,
- phy_mgmt_clk_reset => mm_rst,
- phy_mgmt_address => (others => '0'),
- phy_mgmt_read => '0',
- phy_mgmt_readdata => OPEN,
- phy_mgmt_write => '0',
- phy_mgmt_writedata => (others => '0'),
- phy_mgmt_waitrequest => OPEN,
+ pll_ref_clk => tr_clk,
+ xgmii_tx_clk => tx_clk, -- rx_clk
+ xgmii_rx_clk => rx_clk,
+ xgmii_rx_dc => xgmii_rx_dc,
+ xgmii_tx_dc => xgmii_tx_dc,
+ xaui_rx_serial_data => xaui_rx_serial,
+ xaui_tx_serial_data => xaui_tx_serial,
+ rx_ready => OPEN,
+ tx_ready => OPEN,
+ phy_mgmt_clk => mm_clk,
+ phy_mgmt_clk_reset => mm_rst,
+ phy_mgmt_address => (others => '0'),
+ phy_mgmt_read => '0',
+ phy_mgmt_readdata => OPEN,
+ phy_mgmt_write => '0',
+ phy_mgmt_writedata => (others => '0'),
+ phy_mgmt_waitrequest => OPEN,
rx_channelaligned => rx_channelaligned
);
diff --git a/libraries/technology/memory/tech_memory_component_pkg.vhd b/libraries/technology/memory/tech_memory_component_pkg.vhd
index 5a40065c129470e74d175d674cfffc4cf975cd34..a27bee7d75e6a9223717498124dd2061e05edf56 100644
--- a/libraries/technology/memory/tech_memory_component_pkg.vhd
+++ b/libraries/technology/memory/tech_memory_component_pkg.vhd
@@ -20,7 +20,7 @@
--
-- Author : -
-- Changed by : D.F. Brouwer
--- Purpose:
+-- Purpose:
-- IP components declarations for various devices that get wrapped by the tech components
library IEEE;
@@ -568,7 +568,7 @@ package tech_memory_component_pkg is
-- ip_agi027_1e1v
-----------------------------------------------------------------------------
- -- components ip_agi027_1e1v_ram_crwk_crw and ip_agi027_1e1v_ram_crw_crw are
+ -- components ip_agi027_1e1v_ram_crwk_crw and ip_agi027_1e1v_ram_crw_crw are
-- not available for the Agilex 7. For more details please refer the
-- README.txt in the technology/ip_agi027_1e1v/ram/ folder.
@@ -608,7 +608,7 @@ package tech_memory_component_pkg is
(
data : in std_logic_vector(g_wr_dat_w - 1 downto 0);
wraddress : in std_logic_vector(g_wr_adr_w - 1 downto 0);
- wrclk : in std_logic := '1';
+ wrclk : in std_logic := '1';
wren : in std_logic := '0';
rdaddress : in std_logic_vector(g_rd_adr_w - 1 downto 0);
rdclk : in std_logic;
diff --git a/libraries/technology/memory/tech_memory_ram_crk_cw.vhd b/libraries/technology/memory/tech_memory_ram_crk_cw.vhd
index 7ad3f7c465bdff476d4f67b0673ddb915d249ebd..619b49a2f75898ef240426c052703a74f6f41e58 100644
--- a/libraries/technology/memory/tech_memory_ram_crk_cw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crk_cw.vhd
@@ -18,7 +18,7 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Remark:
-- Due to the lack of support by the Agilex 7 (agi027_1e1v) for the crwk_crw
@@ -28,8 +28,8 @@
-- details please refer the README.txt in the ip_agi027_1e1v/ram/ folder.
-- Reference:
-- Based on tech_memory_ram_crwk_crw.vhd and tech_memory_ram_cr_cw.vhd.
--- Changed the generics and ports to common_ram_cr_cw_ratio.vhd and
--- ip_agi027_ram_crk_cw.vhd. These changes have been incorporated into the
+-- Changed the generics and ports to common_ram_cr_cw_ratio.vhd and
+-- ip_agi027_ram_crk_cw.vhd. These changes have been incorporated into the
-- existing generate-blocks and the generate-block for agi_1e1v is added.
library ieee, technology_lib;
@@ -70,7 +70,7 @@ entity tech_memory_ram_crk_cw is -- support different port data widths and corr
rden_a : in std_logic := '1';
rden_b : in std_logic := '1';
wren : in std_logic := '0';
- q : out std_logic_vector(g_rd_dat_w - 1 downto 0)
+ q : out std_logic_vector(g_rd_dat_w - 1 downto 0)
);
end tech_memory_ram_crk_cw;
diff --git a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
index 9f47323b74dd643e5155a22901eb501edf600d1c..a9dcdd53ce00180de5cccb6c9e59482a5ef44096 100644
--- a/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_crw_crw.vhd
@@ -21,9 +21,9 @@
-- Author : -
-- Changed by : D.F. Brouwer
-- Remark:
--- . The Agilex 7 (agi027_1e1v) doesn't support this IP as used for previous
+-- . The Agilex 7 (agi027_1e1v) doesn't support this IP as used for previous
-- FPGA technology identifiers (device types). Instead, the rw_rw IP should
--- be used. For previous technology identifiers, it is constructed using
+-- be used. For previous technology identifiers, it is constructed using
-- this crw_crw IP by providing the same clock twice. For more details
-- please refer the README.txt in the ip_agi027_1e1v/ram/ folder.
-- . For Agilex 7 (agi027_1e1v) is also the ip_agi027_1e1v_ram_rw_rw added
diff --git a/libraries/technology/memory/tech_memory_ram_rw_rw.vhd b/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
index c7b6f66b2a27871546d4cbf0483e363b1a12ce22..9302e2122108ea50258d8b4b4994cc4b27de8bfd 100644
--- a/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
+++ b/libraries/technology/memory/tech_memory_ram_rw_rw.vhd
@@ -18,12 +18,12 @@
--
-- -----------------------------------------------------------------------------
--
--- Author:
+-- Author:
-- D.F. Brouwer
-- Remark:
-- Because the crw_crw IP isn't supported as used for previous FPGA
-- technology identifiers (device types) by the Agilex 7 (agi027_1e1v), the
--- rw_rw IP should be used. For the previous technology identifiers, it is
+-- rw_rw IP should be used. For the previous technology identifiers, it is
-- constructed using the crw_crw IPs by providing the same clock twice. For
-- more details please refer the README.txt in the ip_agi027_1e1v/ram/ folder.
-- Reference:
diff --git a/libraries/technology/mult/tech_mult_component_pkg.vhd b/libraries/technology/mult/tech_mult_component_pkg.vhd
index 6de7faa2ab310466cb3eff02514e699093d645a7..954b1819489cb384b92255dc224b91173db372eb 100644
--- a/libraries/technology/mult/tech_mult_component_pkg.vhd
+++ b/libraries/technology/mult/tech_mult_component_pkg.vhd
@@ -20,7 +20,7 @@
--
-- Author : -
-- Changed by : D.F. Brouwer
--- Purpose:
+-- Purpose:
-- IP components declarations for various devices that get wrapped by the tech components
library IEEE;
diff --git a/libraries/technology/technology_select_pkg_iwave.vhd b/libraries/technology/technology_select_pkg_iwave.vhd
index a8b2e35628d5fdaf42fdd3d5f04a0a4ca1b3978a..c302ccd8419a883476c8dfbf73cd7d187dc59e4d 100644
--- a/libraries/technology/technology_select_pkg_iwave.vhd
+++ b/libraries/technology/technology_select_pkg_iwave.vhd
@@ -18,7 +18,7 @@
--
-------------------------------------------------------------------------------
-- Author: D.F. Brouwer
--- Purpose:
+-- Purpose:
-- Define default technology selection value for g_technology
-- Description:
-- In case g_technology is not overruled by the application design then the
diff --git a/libraries/technology/xaui/tech_xaui_component_pkg.vhd b/libraries/technology/xaui/tech_xaui_component_pkg.vhd
index 68693bdce1f930b66f3d4cbfdfa5410ef715e35b..c41813e96435768af4f5d8b99956222224ad4ef4 100644
--- a/libraries/technology/xaui/tech_xaui_component_pkg.vhd
+++ b/libraries/technology/xaui/tech_xaui_component_pkg.vhd
@@ -33,190 +33,190 @@ package tech_xaui_component_pkg is
------------------------------------------------------------------------------
component ip_stratixiv_phy_xaui_0 is
- port (
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
- xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
- xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
- xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
- xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
- xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
- xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
- rx_ready : out std_logic; -- rx_ready.export
- tx_ready : out std_logic; -- tx_ready.export
- phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
- phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
- phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
- phy_mgmt_read : in std_logic := '0'; -- .read
- phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
- phy_mgmt_write : in std_logic := '0'; -- .write
- phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- phy_mgmt_waitrequest : out std_logic; -- .waitrequest
- rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
- tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
- rx_channelaligned : out std_logic; -- rx_channelaligned.data
- rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
- rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
- rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
- rx_analogreset : in std_logic := '0'; -- rx_analogreset.data
- rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data
- rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data
- rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data
- rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data
- tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data
- rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data
- rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data
- rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data
- rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data
- rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data
- rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data
- tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data
- rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data
- rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data
- rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data
- rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data
- cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
- gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
- pll_locked : out std_logic; -- pll_locked.data
- reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data
- reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
- );
+ port (
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
+ xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
+ xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
+ xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
+ xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
+ xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
+ xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
+ rx_ready : out std_logic; -- rx_ready.export
+ tx_ready : out std_logic; -- tx_ready.export
+ phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
+ phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
+ phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
+ phy_mgmt_read : in std_logic := '0'; -- .read
+ phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ phy_mgmt_write : in std_logic := '0'; -- .write
+ phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ phy_mgmt_waitrequest : out std_logic; -- .waitrequest
+ rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
+ tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
+ rx_channelaligned : out std_logic; -- rx_channelaligned.data
+ rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
+ rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
+ rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
+ rx_analogreset : in std_logic := '0'; -- rx_analogreset.data
+ rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data
+ rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data
+ rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data
+ tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data
+ rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data
+ rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data
+ rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data
+ rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data
+ tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data
+ rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data
+ rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data
+ rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data
+ rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data
+ cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
+ gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
+ pll_locked : out std_logic; -- pll_locked.data
+ reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data
+ reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
+ );
end component;
component ip_stratixiv_phy_xaui_1 is
- port (
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
- xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
- xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
- xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
- xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
- xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
- xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
- rx_ready : out std_logic; -- rx_ready.export
- tx_ready : out std_logic; -- tx_ready.export
- phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
- phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
- phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
- phy_mgmt_read : in std_logic := '0'; -- .read
- phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
- phy_mgmt_write : in std_logic := '0'; -- .write
- phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- phy_mgmt_waitrequest : out std_logic; -- .waitrequest
- rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
- tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
- rx_channelaligned : out std_logic; -- rx_channelaligned.data
- rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
- rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
- rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
- rx_analogreset : in std_logic := '0'; -- rx_analogreset.data
- rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data
- rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data
- rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data
- rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data
- tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data
- rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data
- rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data
- rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data
- rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data
- rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data
- rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data
- tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data
- rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data
- rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data
- rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data
- rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data
- cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
- gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
- pll_locked : out std_logic; -- pll_locked.data
- reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data
- reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
- );
+ port (
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
+ xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
+ xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
+ xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
+ xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
+ xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
+ xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
+ rx_ready : out std_logic; -- rx_ready.export
+ tx_ready : out std_logic; -- tx_ready.export
+ phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
+ phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
+ phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
+ phy_mgmt_read : in std_logic := '0'; -- .read
+ phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ phy_mgmt_write : in std_logic := '0'; -- .write
+ phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ phy_mgmt_waitrequest : out std_logic; -- .waitrequest
+ rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
+ tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
+ rx_channelaligned : out std_logic; -- rx_channelaligned.data
+ rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
+ rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
+ rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
+ rx_analogreset : in std_logic := '0'; -- rx_analogreset.data
+ rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data
+ rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data
+ rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data
+ tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data
+ rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data
+ rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data
+ rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data
+ rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data
+ tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data
+ rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data
+ rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data
+ rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data
+ rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data
+ cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
+ gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
+ pll_locked : out std_logic; -- pll_locked.data
+ reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data
+ reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
+ );
end component;
component ip_stratixiv_phy_xaui_2 is
- port (
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
- xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
- xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
- xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
- xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
- xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
- xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
- rx_ready : out std_logic; -- rx_ready.export
- tx_ready : out std_logic; -- tx_ready.export
- phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
- phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
- phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
- phy_mgmt_read : in std_logic := '0'; -- .read
- phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
- phy_mgmt_write : in std_logic := '0'; -- .write
- phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- phy_mgmt_waitrequest : out std_logic; -- .waitrequest
- rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
- tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
- rx_channelaligned : out std_logic; -- rx_channelaligned.data
- rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
- rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
- rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
- rx_analogreset : in std_logic := '0'; -- rx_analogreset.data
- rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data
- rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data
- rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data
- rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data
- tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data
- rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data
- rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data
- rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data
- rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data
- rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data
- rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data
- tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data
- rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data
- rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data
- rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data
- rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data
- cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
- gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
- pll_locked : out std_logic; -- pll_locked.data
- reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data
- reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
- );
+ port (
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
+ xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
+ xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
+ xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
+ xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
+ xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
+ xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
+ rx_ready : out std_logic; -- rx_ready.export
+ tx_ready : out std_logic; -- tx_ready.export
+ phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
+ phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
+ phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
+ phy_mgmt_read : in std_logic := '0'; -- .read
+ phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ phy_mgmt_write : in std_logic := '0'; -- .write
+ phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ phy_mgmt_waitrequest : out std_logic; -- .waitrequest
+ rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
+ tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
+ rx_channelaligned : out std_logic; -- rx_channelaligned.data
+ rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
+ rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
+ rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
+ rx_analogreset : in std_logic := '0'; -- rx_analogreset.data
+ rx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_invpolarity.data
+ rx_set_locktodata : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktodata.data
+ rx_set_locktoref : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_set_locktoref.data
+ rx_seriallpbken : in std_logic_vector(3 downto 0) := (others => '0'); -- rx_seriallpbken.data
+ tx_invpolarity : in std_logic_vector(3 downto 0) := (others => '0'); -- tx_invpolarity.data
+ rx_is_lockedtodata : out std_logic_vector(3 downto 0); -- rx_is_lockedtodata.data
+ rx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- rx_phase_comp_fifo_error.data
+ rx_is_lockedtoref : out std_logic_vector(3 downto 0); -- rx_is_lockedtoref.data
+ rx_rlv : out std_logic_vector(3 downto 0); -- rx_rlv.data
+ rx_rmfifoempty : out std_logic_vector(3 downto 0); -- rx_rmfifoempty.data
+ rx_rmfifofull : out std_logic_vector(3 downto 0); -- rx_rmfifofull.data
+ tx_phase_comp_fifo_error : out std_logic_vector(3 downto 0); -- tx_phase_comp_fifo_error.data
+ rx_patterndetect : out std_logic_vector(7 downto 0); -- rx_patterndetect.data
+ rx_rmfifodatadeleted : out std_logic_vector(7 downto 0); -- rx_rmfifodatadeleted.data
+ rx_rmfifodatainserted : out std_logic_vector(7 downto 0); -- rx_rmfifodatainserted.data
+ rx_runningdisp : out std_logic_vector(7 downto 0); -- rx_runningdisp.data
+ cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
+ gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
+ pll_locked : out std_logic; -- pll_locked.data
+ reconfig_from_xcvr : out std_logic_vector(16 downto 0); -- reconfig_from_xcvr.data
+ reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
+ );
end component;
component ip_stratixiv_phy_xaui_soft is
- port (
- pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
- xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
- xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
- xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
- xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
- xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
- xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
- rx_ready : out std_logic; -- rx_ready.export
- tx_ready : out std_logic; -- tx_ready.export
- phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
- phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
- phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
- phy_mgmt_read : in std_logic := '0'; -- .read
- phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
- phy_mgmt_write : in std_logic := '0'; -- .write
- phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
- phy_mgmt_waitrequest : out std_logic; -- .waitrequest
- rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
- tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
- rx_channelaligned : out std_logic; -- rx_channelaligned.data
- rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
- rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
- rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
- cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
- pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
- gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
- pll_locked : out std_logic; -- pll_locked.data
- reconfig_from_xcvr : out std_logic_vector(67 downto 0); -- reconfig_from_xcvr.data
- reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
- );
+ port (
+ pll_ref_clk : in std_logic := '0'; -- pll_ref_clk.clk
+ xgmii_tx_clk : in std_logic := '0'; -- xgmii_tx_clk.clk
+ xgmii_rx_clk : out std_logic; -- xgmii_rx_clk.clk
+ xgmii_rx_dc : out std_logic_vector(71 downto 0); -- xgmii_rx_dc.data
+ xgmii_tx_dc : in std_logic_vector(71 downto 0) := (others => '0'); -- xgmii_tx_dc.data
+ xaui_rx_serial_data : in std_logic_vector(3 downto 0) := (others => '0'); -- xaui_rx_serial_data.export
+ xaui_tx_serial_data : out std_logic_vector(3 downto 0); -- xaui_tx_serial_data.export
+ rx_ready : out std_logic; -- rx_ready.export
+ tx_ready : out std_logic; -- tx_ready.export
+ phy_mgmt_clk : in std_logic := '0'; -- phy_mgmt_clk.clk
+ phy_mgmt_clk_reset : in std_logic := '0'; -- phy_mgmt_clk_reset.reset
+ phy_mgmt_address : in std_logic_vector(8 downto 0) := (others => '0'); -- phy_mgmt.address
+ phy_mgmt_read : in std_logic := '0'; -- .read
+ phy_mgmt_readdata : out std_logic_vector(31 downto 0); -- .readdata
+ phy_mgmt_write : in std_logic := '0'; -- .write
+ phy_mgmt_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata
+ phy_mgmt_waitrequest : out std_logic; -- .waitrequest
+ rx_digitalreset : in std_logic := '0'; -- rx_digitalreset.data
+ tx_digitalreset : in std_logic := '0'; -- tx_digitalreset.data
+ rx_channelaligned : out std_logic; -- rx_channelaligned.data
+ rx_syncstatus : out std_logic_vector(7 downto 0); -- rx_syncstatus.data
+ rx_disperr : out std_logic_vector(7 downto 0); -- rx_disperr.data
+ rx_errdetect : out std_logic_vector(7 downto 0); -- rx_errdetect.data
+ cal_blk_powerdown : in std_logic := '0'; -- cal_blk_powerdown.data
+ pll_powerdown : in std_logic := '0'; -- pll_powerdown.data
+ gxb_powerdown : in std_logic := '0'; -- gxb_powerdown.data
+ pll_locked : out std_logic; -- pll_locked.data
+ reconfig_from_xcvr : out std_logic_vector(67 downto 0); -- reconfig_from_xcvr.data
+ reconfig_to_xcvr : in std_logic_vector(3 downto 0) := (others => '0') -- reconfig_to_xcvr.data
+ );
end component;
component ip_stratixiv_gxb_reconfig_v111 is
diff --git a/libraries/technology/xaui/tech_xaui_stratixiv.vhd b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
index 9b6a4bb8ae00d0cba0a9ae433c607106b67900e0..b8311c7dc9224258a16388f06dadc057b717d169 100644
--- a/libraries/technology/xaui/tech_xaui_stratixiv.vhd
+++ b/libraries/technology/xaui/tech_xaui_stratixiv.vhd
@@ -149,23 +149,23 @@ begin
gen_hard_xaui_0: if i = 0 generate
u_ip_phy_xaui : ip_stratixiv_phy_xaui_0
port map (
- pll_ref_clk => tr_clk,
- xgmii_tx_clk => tx_clk_arr(i),
- xgmii_rx_clk => rx_clk_arr_out(i),
- xgmii_rx_dc => xgmii_rx_dc_arr(i),
- xgmii_tx_dc => xgmii_tx_dc_arr(i),
- xaui_rx_serial_data => xaui_rx_arr(i),
- xaui_tx_serial_data => xaui_tx_arr(i),
- rx_ready => a_rx_ready_arr(i),
- tx_ready => a_tx_ready_arr(i),
- phy_mgmt_clk => mm_clk,
- phy_mgmt_clk_reset => mm_rst,
- phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w - 1 downto 0),
- phy_mgmt_read => xaui_mosi_arr(i).rd,
- phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w - 1 downto 0),
- phy_mgmt_write => xaui_mosi_arr(i).wr,
- phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w - 1 downto 0),
- phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
+ pll_ref_clk => tr_clk,
+ xgmii_tx_clk => tx_clk_arr(i),
+ xgmii_rx_clk => rx_clk_arr_out(i),
+ xgmii_rx_dc => xgmii_rx_dc_arr(i),
+ xgmii_tx_dc => xgmii_tx_dc_arr(i),
+ xaui_rx_serial_data => xaui_rx_arr(i),
+ xaui_tx_serial_data => xaui_tx_arr(i),
+ rx_ready => a_rx_ready_arr(i),
+ tx_ready => a_tx_ready_arr(i),
+ phy_mgmt_clk => mm_clk,
+ phy_mgmt_clk_reset => mm_rst,
+ phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w - 1 downto 0),
+ phy_mgmt_read => xaui_mosi_arr(i).rd,
+ phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w - 1 downto 0),
+ phy_mgmt_write => xaui_mosi_arr(i).wr,
+ phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w - 1 downto 0),
+ phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
rx_channelaligned => a_rx_channelaligned_arr(i),
@@ -189,23 +189,23 @@ begin
gen_hard_xaui_1: if i = 1 generate
u_ip_phy_xaui : ip_stratixiv_phy_xaui_1
port map (
- pll_ref_clk => tr_clk,
- xgmii_tx_clk => tx_clk_arr(i),
- xgmii_rx_clk => rx_clk_arr_out(i),
- xgmii_rx_dc => xgmii_rx_dc_arr(i),
- xgmii_tx_dc => xgmii_tx_dc_arr(i),
- xaui_rx_serial_data => xaui_rx_arr(i),
- xaui_tx_serial_data => xaui_tx_arr(i),
- rx_ready => a_rx_ready_arr(i),
- tx_ready => a_tx_ready_arr(i),
- phy_mgmt_clk => mm_clk,
- phy_mgmt_clk_reset => mm_rst,
- phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w - 1 downto 0),
- phy_mgmt_read => xaui_mosi_arr(i).rd,
- phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w - 1 downto 0),
- phy_mgmt_write => xaui_mosi_arr(i).wr,
- phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w - 1 downto 0),
- phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
+ pll_ref_clk => tr_clk,
+ xgmii_tx_clk => tx_clk_arr(i),
+ xgmii_rx_clk => rx_clk_arr_out(i),
+ xgmii_rx_dc => xgmii_rx_dc_arr(i),
+ xgmii_tx_dc => xgmii_tx_dc_arr(i),
+ xaui_rx_serial_data => xaui_rx_arr(i),
+ xaui_tx_serial_data => xaui_tx_arr(i),
+ rx_ready => a_rx_ready_arr(i),
+ tx_ready => a_tx_ready_arr(i),
+ phy_mgmt_clk => mm_clk,
+ phy_mgmt_clk_reset => mm_rst,
+ phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w - 1 downto 0),
+ phy_mgmt_read => xaui_mosi_arr(i).rd,
+ phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w - 1 downto 0),
+ phy_mgmt_write => xaui_mosi_arr(i).wr,
+ phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w - 1 downto 0),
+ phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
rx_channelaligned => a_rx_channelaligned_arr(i),
@@ -229,23 +229,23 @@ begin
gen_hard_xaui_2: if i = 2 generate
u_ip_phy_xaui : ip_stratixiv_phy_xaui_2
port map (
- pll_ref_clk => tr_clk,
- xgmii_tx_clk => tx_clk_arr(i),
- xgmii_rx_clk => rx_clk_arr_out(i),
- xgmii_rx_dc => xgmii_rx_dc_arr(i),
- xgmii_tx_dc => xgmii_tx_dc_arr(i),
- xaui_rx_serial_data => xaui_rx_arr(i),
- xaui_tx_serial_data => xaui_tx_arr(i),
- rx_ready => a_rx_ready_arr(i),
- tx_ready => a_tx_ready_arr(i),
- phy_mgmt_clk => mm_clk,
- phy_mgmt_clk_reset => mm_rst,
- phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w - 1 downto 0),
- phy_mgmt_read => xaui_mosi_arr(i).rd,
- phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w - 1 downto 0),
- phy_mgmt_write => xaui_mosi_arr(i).wr,
- phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w - 1 downto 0),
- phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
+ pll_ref_clk => tr_clk,
+ xgmii_tx_clk => tx_clk_arr(i),
+ xgmii_rx_clk => rx_clk_arr_out(i),
+ xgmii_rx_dc => xgmii_rx_dc_arr(i),
+ xgmii_tx_dc => xgmii_tx_dc_arr(i),
+ xaui_rx_serial_data => xaui_rx_arr(i),
+ xaui_tx_serial_data => xaui_tx_arr(i),
+ rx_ready => a_rx_ready_arr(i),
+ tx_ready => a_tx_ready_arr(i),
+ phy_mgmt_clk => mm_clk,
+ phy_mgmt_clk_reset => mm_rst,
+ phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w - 1 downto 0),
+ phy_mgmt_read => xaui_mosi_arr(i).rd,
+ phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w - 1 downto 0),
+ phy_mgmt_write => xaui_mosi_arr(i).wr,
+ phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w - 1 downto 0),
+ phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
rx_channelaligned => a_rx_channelaligned_arr(i),
@@ -269,23 +269,23 @@ begin
gen_soft_xaui: if i = 3 generate -- NOTE: this 4th (soft) instance makes the Quartus fitter (11.1, no SP) fail, so is not supported.
u_ip_phy_xaui : ip_stratixiv_phy_xaui_soft
port map (
- pll_ref_clk => tr_clk,
- xgmii_tx_clk => tx_clk_arr(i),
- xgmii_rx_clk => rx_clk_arr_out(i),
- xgmii_rx_dc => xgmii_rx_dc_arr(i),
- xgmii_tx_dc => xgmii_tx_dc_arr(i),
- xaui_rx_serial_data => xaui_rx_arr(i),
- xaui_tx_serial_data => xaui_tx_arr(i),
- rx_ready => a_rx_ready_arr(i),
- tx_ready => a_tx_ready_arr(i),
- phy_mgmt_clk => mm_clk,
- phy_mgmt_clk_reset => mm_rst,
- phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w - 1 downto 0),
- phy_mgmt_read => xaui_mosi_arr(i).rd,
- phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w - 1 downto 0),
- phy_mgmt_write => xaui_mosi_arr(i).wr,
- phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w - 1 downto 0),
- phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
+ pll_ref_clk => tr_clk,
+ xgmii_tx_clk => tx_clk_arr(i),
+ xgmii_rx_clk => rx_clk_arr_out(i),
+ xgmii_rx_dc => xgmii_rx_dc_arr(i),
+ xgmii_tx_dc => xgmii_tx_dc_arr(i),
+ xaui_rx_serial_data => xaui_rx_arr(i),
+ xaui_tx_serial_data => xaui_tx_arr(i),
+ rx_ready => a_rx_ready_arr(i),
+ tx_ready => a_tx_ready_arr(i),
+ phy_mgmt_clk => mm_clk,
+ phy_mgmt_clk_reset => mm_rst,
+ phy_mgmt_address => xaui_mosi_arr(i).address(c_xaui_mosi_addr_w - 1 downto 0),
+ phy_mgmt_read => xaui_mosi_arr(i).rd,
+ phy_mgmt_readdata => xaui_miso_arr(i).rddata(c_word_w - 1 downto 0),
+ phy_mgmt_write => xaui_mosi_arr(i).wr,
+ phy_mgmt_writedata => xaui_mosi_arr(i).wrdata(c_word_w - 1 downto 0),
+ phy_mgmt_waitrequest => xaui_miso_arr(i).waitrequest,
rx_channelaligned => a_rx_channelaligned_arr(i),