Merge branch 'DISTURB-1' into 'master'

Resolve DISTURB-1

Closes DISTURB-1

See merge request desp/hdl!255

applications/disturb2/designs/disturb2_unb2b_station/disturb2_unb2b_station.fpga.yaml

+schema_name: args
+schema_version: 1.0
+schema_type: fpga
+
+hdl_library_name: disturb2_unb2b_station
+fpga_name: disturb2_unb2b_station
+fpga_description: "FPGA design disturb2_unb2b_station"
+parameters:
+  - { name: c_N_pol_bf,             value: 2 }  # NOTE: define c_N_pol_bf before c_N_pol, to avoid that c_N_pol_bf gets substituted by 2_bf
+  - { name: c_N_pol,                value: 2 }
+  - { name: c_N_beamsets,           value: 2 }
+  - { name: c_N_sub,                value: 512 }
+  - { name: c_N_fft,                value: 1024 }
+  - { name: c_N_pn_lb,              value: 16 }
+  - { name: c_S_pn,                 value: 12 }
+  - { name: c_Q_fft,                value: 2 }
+  - { name: c_P_sq,                 value: 1 + c_N_pn_lb // 2 }  # = 1 + 16 // 2 = 9, on revision xsub_one only first X_sq cell is used
+  - { name: c_X_sq,                 value: c_S_pn * c_S_pn }  # = 144
+  - { name: c_N_crosslets,          value: 7 }
+  - { name: c_N_taps,               value: 16 }
+  - { name: c_W_adc_jesd,           value: 16 }
+  - { name: c_W_adc,                value: 14 }
+  - { name: c_V_sample_delay,       value: 4096 }
+  - { name: c_V_si_db_large,        value: 131072 }
+  - { name: c_V_si_db,              value: 1024 }
+  - { name: c_V_si_histogram,       value: 512 }
+  - { name: c_W_fir_coef,           value: 16 }
+  - { name: c_W_subband,            value: 18 }
+  - { name: c_P_pfb,                value: c_S_pn / c_Q_fft }  # = 6
+  - { name: c_A_pn,                 value: c_S_pn / c_N_pol }  # = 6
+  - { name: c_S_sub_bf,             value: 488 }
+  - { name: c_f_adc_MHz,            value: 200 }
+  - { name: c_W_sub_weight,         value: 16 }
+  - { name: c_W_bf_weight,          value: 16 }
+  - { name: c_W_beamlet_scale,      value: 16 }
+  - { name: c_W_beamlet_resolution, value: 0 - 15 }  # EK: FIXME: support passing on negative values, workaround use 0 - positive
+  - { name: c_W_beamlet,            value: 8 }
+  - { name: c_stat_data_sz,         value: 2 }
+  - { name: c_nof_clk_per_pps,      value: c_f_adc_MHz * 10**6 }  # = 200000000
+  - { name: c_lane_nof_rx_monitors,      value: 16 } # per lane
+  - { name: c_lane_nof_tx_monitors,      value: 16 } # per lane
+  - { name: c_lane_nof_err_counts,       value: 8 }  # per lane
+  - { name: c_ring_nof_mac,              value: 3 } # 1 TX/RX for RING0 + 1 TX/RX for RING1 + 1 TX/RX for QSFP0
+
+peripherals:
+  #############################################################################
+  # Factory / minimal (see ctrl_unb2b_board.vhd)
+  #############################################################################
+  - peripheral_name: unb2b_board/system_info
+    lock_base_address: 0x10000
+    mm_port_names:
+      - ROM_SYSTEM_INFO
+      - PIO_SYSTEM_INFO
+
+  - peripheral_name: unb2b_board/wdi
+    mm_port_names:
+      - REG_WDI
+
+  - peripheral_name: unb2b_board/unb2_fpga_sens
+    mm_port_names:
+      - REG_FPGA_TEMP_SENS
+      - REG_FPGA_VOLTAGE_SENS
+    
+  - peripheral_name: unb2b_board/ram_scrap
+    mm_port_names:
+      - RAM_SCRAP
+      
+  - peripheral_name: eth/eth
+    mm_port_names:
+      - AVS_ETH_0_TSE
+      - AVS_ETH_0_REG
+      - AVS_ETH_0_RAM
+      
+  - peripheral_name: ppsh/ppsh
+    mm_port_names:
+      - PIO_PPS
+      
+  - peripheral_name: epcs/epcs
+    parameter_overrides:
+      - { name: "g_epcs_addr_w", value: 32 }
+    mm_port_names:
+      - REG_EPCS
+      
+  - peripheral_name: dp/dpmm
+    mm_port_names:
+      - REG_DPMM_CTRL
+      - REG_DPMM_DATA
+      
+  - peripheral_name: dp/mmdp
+    mm_port_names:
+      - REG_MMDP_CTRL
+      - REG_MMDP_DATA
+      
+  - peripheral_name: remu/remu
+    parameter_overrides:
+      - { name: g_data_w, value: 32 }
+    mm_port_names:
+      - REG_REMU
+ 
+  #############################################################################
+  # SDP Info
+  #############################################################################
+
+  - peripheral_name: sdp/sdp_info
+    mm_port_names:
+      - REG_SDP_INFO
+ 
+  #############################################################################
+  # Ring Info
+  #############################################################################
+
+  - peripheral_name: ring/ring_info
+    mm_port_names:
+      - REG_RING_INFO
+
+  #############################################################################
+  # AIT = ADC Input and Timing (see node_adc_input_and_timing.vhd)
+  #############################################################################
+  
+  - peripheral_name: tech_jesd204b/jesd_ctrl
+    mm_port_names:
+      - PIO_JESD_CTRL
+      
+  - peripheral_name: tech_jesd204b/jesd204b_arria10
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_S_pn }
+    mm_port_names:
+      - JESD204B
+  
+  - peripheral_name: dp/dp_shiftram
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_S_pn }
+      - { name: g_nof_words, value: c_V_sample_delay }
+      - { name: g_data_w, value: c_W_adc_jesd }
+    mm_port_names:
+      - REG_DP_SHIFTRAM
+
+  - peripheral_name: dp/dp_bsn_source_v2
+    parameter_overrides:
+      - { name: g_nof_clk_per_sync, value: c_nof_clk_per_pps }
+      - { name: g_block_size, value: c_N_fft }
+      - { name: g_bsn_time_offset_w, value: ceil_log2(c_N_fft) }
+    mm_port_names:
+      - REG_BSN_SOURCE_V2
+      
+  - peripheral_name: dp/dp_bsn_scheduler
+    mm_port_names:
+      - REG_BSN_SCHEDULER
+  
+  - peripheral_name: dp/dp_bsn_monitor
+    peripheral_group: input
+    mm_port_names:
+      - REG_BSN_MONITOR_INPUT
+  
+  - peripheral_name: diag/diag_wg_wideband
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_S_pn }
+    mm_port_names:
+      - REG_WG
+      - RAM_WG
+
+  - peripheral_name: st/st_histogram
+    parameter_overrides:
+      - { name: g_nof_instances, value: c_S_pn }
+      - { name: g_nof_bins, value: c_V_si_histogram }
+      - { name: g_nof_data_per_sync, value: c_nof_clk_per_pps}
+    mm_port_names:
+      - RAM_ST_HISTOGRAM   
+
+  - peripheral_name: aduh/aduh_mon_dc_power
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_S_pn }
+    mm_port_names:
+      - REG_ADUH_MONITOR
+
+  # Commented RAM_ADUH_MON, because use RAM_DIAG_DATA_BUF_BSN instead
+  #- peripheral_name: aduh/aduh_mon_data_buffer
+  #  parameter_overrides:
+  #    - { name: g_nof_streams, value: c_S_pn }
+  #    - { name: g_symbol_w, value: c_W_adc_jesd }
+  #    - { name: g_nof_symbols_per_data, value: 1 }
+  #    - { name: g_buffer_nof_symbols, value: 512 }
+  #    - { name: g_buffer_use_sync, value: True }
+  #  mm_port_names:
+  #    - RAM_ADUH_MON
+
+  - peripheral_name: diag/diag_data_buffer
+    peripheral_group: bsn
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_S_pn }
+      - { name: g_data_w, value: c_W_adc_jesd }
+      - { name: g_nof_data, value: c_V_si_db }
+    mm_port_names:
+      - REG_DIAG_DATA_BUFFER_BSN
+      - RAM_DIAG_DATA_BUFFER_BSN
+  
+  #############################################################################
+  # Fsub = Subband Filterbank (from node_sdp_filterbank.vhd)
+  #############################################################################
+  
+  - peripheral_name: si/si
+    mm_port_names:
+      - REG_SI
+      
+  - peripheral_name: filter/fil_ppf_w
+    parameter_overrides:
+      - { name: g_fil_ppf.wb_factor, value: 1 } # process at sample rate (so no parallel wideband factor)
+      - { name: g_fil_ppf.nof_chan, value: 0 } # process at sample rate (so no serial time multiplexing)
+      - { name: g_fil_ppf.nof_bands, value: c_N_fft }
+      - { name: g_fil_ppf.nof_taps, value: c_N_taps }
+      - { name: g_fil_ppf.nof_streams, value: 1 }
+      - { name: g_fil_ppf.coef_dat_w, value: c_W_fir_coef }
+    mm_port_names:
+      - RAM_FIL_COEFS
+      
+  - peripheral_name: sdp/sdp_subband_equalizer
+    mm_port_names:
+      - RAM_EQUALIZER_GAINS
+      
+  - peripheral_name: dp/dp_selector
+    mm_port_names:
+      - REG_DP_SELECTOR   # input_select = 0 for weighted subbands, input_select = 1 for raw subbands
+      
+  - peripheral_name: st/st_sst_for_sdp
+    mm_port_names:
+      - RAM_ST_SST
+      
+  - peripheral_name: common/common_variable_delay
+    peripheral_group: sst
+    mm_port_names:
+      - REG_STAT_ENABLE_SST
+
+  - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_sst
+    peripheral_group: sst
+    mm_port_names:
+      - REG_STAT_HDR_DAT_SST
+    
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: sst_udp
+    parameter_overrides:
+      - { name: g_nof_streams, value: 1 }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_SST_OFFLOAD
+
+  #############################################################################
+  # Xsub = Subband Correlator (from node_sdp_correlator.vhd)
+  #############################################################################
+
+  - peripheral_name: dp/dp_bsn_sync_scheduler
+    peripheral_group: xsub
+    mm_port_names:
+      - REG_BSN_SYNC_SCHEDULER_XSUB
+      
+  - peripheral_name: st/st_xst_for_sdp
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_P_sq }
+      - { name: g_nof_crosslets, value: c_N_crosslets }
+    mm_port_names:
+      - RAM_ST_XSQ
+      
+  - peripheral_name: sdp/sdp_crosslets_subband_select
+    mm_port_names:
+      - REG_CROSSLETS_INFO
+
+  - peripheral_name: sdp/sdp_nof_crosslets
+    mm_port_names:
+      - REG_NOF_CROSSLETS
+
+  - peripheral_name: common/common_variable_delay
+    peripheral_group: xst
+    mm_port_names:
+      - REG_STAT_ENABLE_XST
+
+  - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_xst
+    peripheral_group: xst
+    mm_port_names:
+      - REG_STAT_HDR_DAT_XST
+
+  - peripheral_name: dp/dp_bsn_align_v2
+    peripheral_group: xsub
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_P_sq }
+    mm_port_names:
+      - REG_BSN_ALIGN_V2_XSUB
+  
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: rx_align_xsub
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_P_sq }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_RX_ALIGN_XSUB
+  
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: aligned_xsub
+    parameter_overrides:
+      - { name: g_nof_streams, value: 1 }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_ALIGNED_XSUB
+  
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: xst_udp
+    parameter_overrides:
+      - { name: g_nof_streams, value: 1 }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_XST_OFFLOAD
+  
+  - peripheral_name: ring/ring_lane_info
+    peripheral_group: xsub
+    mm_port_names:
+      - REG_RING_LANE_INFO_XST
+   
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: ring_rx
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_lane_nof_rx_monitors }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_RING_RX_XST
+
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: ring_tx
+    parameter_overrides:
+      - { name: g_nof_streams, value: c_lane_nof_tx_monitors }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_RING_TX_XST
+
+  - peripheral_name: dp/dp_block_validate_err
+    parameter_overrides:
+      - { name: g_nof_err_counts, value: c_lane_nof_err_counts }
+    mm_port_names:
+      - REG_DP_BLOCK_VALIDATE_ERR_XST
+
+  - peripheral_name: dp/dp_block_validate_bsn_at_sync
+    mm_port_names:
+      - REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_XST
+  
+  - peripheral_name: tr_10GbE/tr_10GbE_unb2legacy # For ring interface
+    parameter_overrides:
+      - { name: g_nof_macs, value: c_ring_nof_mac }
+    mm_port_names:
+      - REG_TR_10GBE_MAC
+
+  - peripheral_name: tr_10GbE/tr_10GbE_eth10g # For ring interface
+    parameter_overrides:
+      - { name: g_nof_macs, value: c_ring_nof_mac }
+    mm_port_names:
+      - REG_TR_10GBE_ETH10G
+
+  #############################################################################
+  # BF = Beamformer (from node_sdp_beamformer.vhd)
+  #############################################################################
+  
+  - peripheral_name: reorder/reorder_col_wide
+    number_of_peripherals: c_N_beamsets
+    peripheral_span: ceil_pow2(c_P_pfb) * ceil_pow2(c_S_sub_bf * c_Q_fft) * MM_BUS_SIZE  # number_of_ports = c_P_pfb, mm_port_span = ceil_pow2(c_S_sub_bf * c_Q_fft) words
+    parameter_overrides:
+      - { name: g_wb_factor, value: c_P_pfb }
+      - { name: g_nof_ch_in, value: c_N_sub * c_Q_fft }
+      - { name: g_nof_ch_sel, value: c_S_sub_bf * c_Q_fft }
+    mm_port_names:
+      - RAM_SS_SS_WIDE
+
+  - peripheral_name: sdp/sdp_bf_weights
+    number_of_peripherals: c_N_beamsets
+    peripheral_span: ceil_pow2(c_N_pol_bf * c_P_pfb) * ceil_pow2(c_Q_fft * c_S_sub_bf) * MM_BUS_SIZE  # number_of_ports = c_N_pol_bf * c_P_pfb, mm_port_span = ceil_pow2(c_Q_fft * c_S_sub_bf) words
+    mm_port_names:
+      - RAM_BF_WEIGHTS
+
+  - peripheral_name: dp/dp_bsn_align_v2
+    peripheral_group: bf
+    number_of_peripherals: c_N_beamsets
+    parameter_overrides:
+      - { name: g_nof_streams, value: 2 }
+    mm_port_names:
+      - REG_BSN_ALIGN_V2_BF
+  
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: rx_align_bf
+    number_of_peripherals: c_N_beamsets
+    parameter_overrides:
+      - { name: g_nof_streams, value: 2 }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_RX_ALIGN_BF
+  
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: aligned_bf
+    number_of_peripherals: c_N_beamsets
+    parameter_overrides:
+      - { name: g_nof_streams, value: 1 }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_ALIGNED_BF
+  
+  - peripheral_name: ring/ring_lane_info
+    peripheral_group: bf
+    number_of_peripherals: c_N_beamsets
+    mm_port_names:
+      - REG_RING_LANE_INFO_BF
+   
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: ring_rx_bf
+    number_of_peripherals: c_N_beamsets
+    parameter_overrides:
+      - { name: g_nof_streams, value: 1 }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_RING_RX_BF
+
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: ring_tx_bf
+    number_of_peripherals: c_N_beamsets
+    parameter_overrides:
+      - { name: g_nof_streams, value: 1 }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_RING_TX_BF
+
+  - peripheral_name: dp/dp_block_validate_err
+    peripheral_group: bf
+    number_of_peripherals: c_N_beamsets
+    parameter_overrides:
+      - { name: g_nof_err_counts, value: c_lane_nof_err_counts }
+    mm_port_names:
+      - REG_DP_BLOCK_VALIDATE_ERR_BF
+
+  - peripheral_name: dp/dp_block_validate_bsn_at_sync
+    peripheral_group: bf
+    number_of_peripherals: c_N_beamsets
+    mm_port_names:
+      - REG_DP_BLOCK_VALIDATE_BSN_AT_SYNC_BF
+
+  - peripheral_name: sdp/sdp_bf_scale
+    number_of_peripherals: c_N_beamsets
+    peripheral_span: 2 * MM_BUS_SIZE  # number_of_ports = 1, mm_port_span = 2 words
+    parameter_overrides:
+      - { name: g_gain_w, value: c_W_beamlet_scale }
+      - { name: g_lsb_w, value: 0 - c_W_beamlet_resolution}
+    mm_port_names:
+      - REG_BF_SCALE
+
+  - peripheral_name: sdp/sdp_beamformer_output_hdr_dat
+    number_of_peripherals: c_N_beamsets
+    peripheral_span: 64 * MM_BUS_SIZE  # number_of_ports = 1, mm_port_span = 64 words
+    mm_port_names:
+      - REG_HDR_DAT
+
+  - peripheral_name: dp/dp_xonoff
+    number_of_peripherals: c_N_beamsets
+    peripheral_span: 2 * MM_BUS_SIZE  # number_of_ports = 1, mm_port_span = 2 words
+    parameter_overrides:
+      - { name: g_nof_streams, value: 1 }
+      - { name: g_combine_streams, value: False }
+    mm_port_names:
+      - REG_DP_XONOFF
+
+  - peripheral_name: st/st_bst_for_sdp
+    number_of_peripherals: c_N_beamsets
+    peripheral_span: ceil_pow2(c_stat_data_sz * c_S_sub_bf * c_N_pol_bf) * MM_BUS_SIZE  # number_of_ports = 1, mm_port_span = ceil_pow2(c_stat_data_sz * c_S_sub_bf * c_N_pol_bf) words
+    mm_port_names:
+      - RAM_ST_BST
+
+  - peripheral_name: common/common_variable_delay
+    peripheral_group: bst
+    number_of_peripherals: c_N_beamsets
+    peripheral_span: 2 * MM_BUS_SIZE  # number_of_ports = 1, mm_port_span = 2 words
+    mm_port_names:
+      - REG_STAT_ENABLE_BST
+
+  - peripheral_name: sdp/sdp_statistics_offload_hdr_dat_bst
+    peripheral_group: bst
+    number_of_peripherals: c_N_beamsets
+    peripheral_span: 64 * MM_BUS_SIZE  # number_of_ports = 1, mm_port_span = 64 words
+    mm_port_names:
+      - REG_STAT_HDR_DAT_BST
+
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: bst_udp
+    number_of_peripherals: c_N_beamsets
+    parameter_overrides:
+      - { name: g_nof_streams, value: 1 }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_BST_OFFLOAD
+
+  - peripheral_name: dp/dp_bsn_monitor_v2
+    peripheral_group: beamlet_output
+    number_of_peripherals: c_N_beamsets
+    parameter_overrides:
+      - { name: g_nof_streams, value: 1 }
+    mm_port_names:
+      - REG_BSN_MONITOR_V2_BEAMLET_OUTPUT
+
+  - peripheral_name: nw_10GbE/nw_10GbE_unb2legacy # For beamlet output
+    peripheral_group: beamlet_output
+    parameter_overrides:
+      - { name: g_nof_macs, value: 1 }
+    mm_port_names:
+      - REG_NW_10GBE_MAC
+
+  - peripheral_name: nw_10GbE/nw_10GbE_eth10g # For beamlet output
+    peripheral_group: beamlet_output
+    parameter_overrides:
+      - { name: g_nof_macs, value: 1 }
+    mm_port_names:
+      - REG_NW_10GBE_ETH10G

applications/disturb2/designs/disturb2_unb2b_station/hdllib.cfg

+hdl_lib_name = disturb2_unb2b_station
+hdl_library_clause_name = disturb2_unb2b_station_lib
+hdl_lib_uses_synth = common technology mm unb2b_board dp eth tech_tse tech_pll nw_10GbE diagnostics diag aduh wpfb tech_jesd204b disturb
+hdl_lib_uses_sim =  
+hdl_lib_technology = ip_arria10_e1sg
+hdl_lib_include_ip = 
+                     ip_arria10_e1sg_mac_10g
+                     ip_arria10_e1sg_pll_xgmii_mac_clocks
+                     ip_arria10_e1sg_transceiver_pll_10g
+                     ip_arria10_e1sg_phy_10gbase_r
+                     ip_arria10_e1sg_phy_10gbase_r_12
+                     ip_arria10_e1sg_transceiver_reset_controller_1
+                     ip_arria10_e1sg_transceiver_reset_controller_12
+
+synth_files =
+    src/vhdl/qsys_disturb2_unb2b_station_pkg.vhd
+    src/vhdl/disturb2_unb2b_station_pkg.vhd
+    src/vhdl/mmm_disturb2_unb2b_station.vhd
+    src/vhdl/disturb2_unb2b_station.vhd
+    
+test_bench_files = 
+    tb/vhdl/tb_disturb2_unb2b_station.vhd
+
+regression_test_vhdl =
+    tb/vhdl/tb_disturb2_unb2b_station.vhd
+
+[modelsim_project_file]
+modelsim_copy_files =
+    src/data data
+#### Overwrite hex files with sim data as hex file formatting is byte addressed in Modelsim instead of word addressed like in Quartus.
+    tb/data data    
+
+[quartus_project_file]
+quartus_copy_files =
+    quartus .
+

applications/disturb2/designs/disturb2_unb2b_station/quartus/disturb2_unb2b_station.sdc

+###############################################################################
+#
+# Copyright (C) 2018
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# JIVE (Joint Institute for VLBI in Europe) <http://www.jive.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+# Constrain the input I/O path
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_input_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+# Constrain the output I/O path
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -max 3 [all_inputs]
+#set_output_delay -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] -min 2 [all_inputs]
+
+
+# False path the PPS to DDIO:
+#set_input_delay  -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 3 [get_ports {PPS}]
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}; set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio~ddio_in_fr}
+
+
+#set_false_path -from [get_ports {PPS}] -to [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}]
+
+#set_input_delay -min -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 2 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+#set_input_delay -max -clock [get_clocks {u_ctrl|\gen_dp_clk_hardware:gen_pll:u_unb2b_board_clk200_pll|\gen_st_fractional_pll:u_st_fractional_pll|\gen_ip_arria10_e1sg:u0|xcvr_fpll_a10_0|outclk0}] 4 [get_ports {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|pps_ext_cap}]
+
+#set_false_path -from {PPS} -to {ctrl_unb2b_board:u_ctrl|mms_ppsh:u_mms_ppsh|ppsh:u_ppsh|common_ddio_in:u_in|tech_iobuf_ddio_in:u_ddio_in|ip_arria10_e1sg_ddio_in:\gen_ip_arria10_e1sg:u0|ip_arria10_e1sg_ddio_in_1:\gen_w:0:u_ip_arria10_e1sg_ddio_in_1|ip_arria10_e1sg_ddio_in_1_altera_gpio_151_ia6gnqq:ip_arria10_ddio_in_1|altera_gpio:core|altera_gpio_one_bit:gpio_one_bit.i_loop[0].altera_gpio_bit_i|input_path.in_path_fr.buffer_data_in_fr_ddio*}
+
+
+
+set_time_format -unit ns -decimal_places 3
+
+create_clock -period 125Mhz [get_ports {ETH_CLK}]
+create_clock -period 200Mhz [get_ports {CLK}]
+create_clock -period 100Mhz [get_ports {CLKUSR}]
+create_clock -period 644.53125Mhz [get_ports {SA_CLK}]
+create_clock -period 644.53125Mhz [get_ports {SB_CLK}]
+create_clock -period 200MHz -name {BCK_REF_CLK} { BCK_REF_CLK }
+
+# Create altera reserved tck to solve unconstrained clock warning.
+create_clock -period "100.000 ns" -name {altera_reserved_tck} {altera_reserved_tck}
+
+derive_pll_clocks
+derive_clock_uncertainty
+
+set_clock_groups -asynchronous -group {CLK}
+set_clock_groups -asynchronous -group {BCK_REF_CLK}
+set_clock_groups -asynchronous -group {CLK_USR}
+set_clock_groups -asynchronous -group {CLKUSR}
+set_clock_groups -asynchronous -group {SA_CLK}
+set_clock_groups -asynchronous -group {SB_CLK}
+# Do not put ETH_CLK in this list, otherwise the Triple Speed Ethernet does not work
+
+# Altera temp sense clock
+set_clock_groups -asynchronous -group [get_clocks altera_ts_clk]
+
+# ALtera JTAG clock
+set_clock_groups -asynchronous -group [get_clocks altera_reserved_tck]
+
+# IOPLL outputs (which have global names defined in the IP qsys settings)
+set_clock_groups -asynchronous -group [get_clocks pll_clk20]
+set_clock_groups -asynchronous -group [get_clocks pll_clk50]
+set_clock_groups -asynchronous -group [get_clocks pll_clk100]
+set_clock_groups -asynchronous -group [get_clocks pll_clk125]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200]
+set_clock_groups -asynchronous -group [get_clocks pll_clk200p]
+set_clock_groups -asynchronous -group [get_clocks pll_clk400]
+
+
+# FPLL outputs
+#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*mac_clock*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*dp_clk*xcvr_fpll_a10_0|outclk0}]
+#set_clock_groups -asynchronous -group [get_clocks {*xcvr_fpll_a10_0|outclk1}]
+set_clock_groups -asynchronous -group [get_clocks {*_board_clk125_pll|*xcvr_fpll_a10_0|outclk2}]
+set_clock_groups -asynchronous -group [get_clocks {*_board_clk125_pll|*xcvr_fpll_a10_0|outclk3}]
+
+set_clock_groups -asynchronous -group [get_clocks {*xcvr_native_a10_0|g_xcvr_native_insts[*]|rx_pma_clk}]
+
+#set_false_path -from {*u_rst200|u_async|din_meta[2]} -to {*FIFOram*}
+
+#set_clock_groups -asynchronous \
+#-group [get_clocks {inst2|xcvr_4ch_native_phy_inst|xcvr_native_a10_0|g_xcvr_native_insts[?]|rx_pma_clk}] \
+#-group [get_clocks {inst2|xcvr_pll_inst|xcvr_fpll_a10_0|tx_bonding_clocks[0]}]
+
+# false paths added for the jesd interface as these clocks are independent.
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|link_clk}]
+set_false_path -from [get_clocks {*iopll_0|link_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]
+set_false_path -from [get_clocks {*xcvr_fpll_a10_0|outclk2}] -to [get_clocks {*iopll_0|frame_clk}]
+set_false_path -from [get_clocks {*iopll_0|frame_clk}] -to [get_clocks {*xcvr_fpll_a10_0|outclk2}]

applications/disturb2/designs/disturb2_unb2b_station/quartus/disturb2_unb2b_station_beamlets_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2022
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+#
+### QSFP_1_0 For BF
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_TERM_SEL R_R1 -to                             QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP5 RADP_DFE_FXTAP5_0 -to          QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP4 RADP_DFE_FXTAP4_0 -to          QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP1 RADP_DFE_FXTAP1_0 -to          QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP7 RADP_DFE_FXTAP7_0 -to          QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP6 RADP_DFE_FXTAP6_0 -to          QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP3 RADP_DFE_FXTAP3_0 -to          QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_DFE_FXTAP2 RADP_DFE_FXTAP2_0 -to          QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ONE_STAGE_ENABLE NON_S1_MODE -to              QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_CTLE_ACGAIN_4S RADP_CTLE_ACGAIN_4S_8 -to  QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_EQ_DC_GAIN_TRIM NO_DC_GAIN -to                QSFP_1_RX[0]
+set_instance_assignment -name XCVR_A10_RX_ADP_VGA_SEL RADP_VGA_SEL_5 -to                QSFP_1_RX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_1_RX[0]
+
+set_instance_assignment -name IO_STANDARD "HSSI DIFFERENTIAL I/O" -to                   QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL 30 -to                  QSFP_1_TX[0]
+set_instance_assignment -name XCVR_VCCR_VCCT_VOLTAGE 1_0V -to                           QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_COMPENSATION_EN ENABLE -to                    QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 0 -to     QSFP_1_TX[0]
+set_instance_assignment -name XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP FIR_POST_1T_POS -to QSFP_1_TX[0]

applications/disturb2/designs/disturb2_unb2b_station/quartus/disturb2_unb2b_station_pins.tcl

+###############################################################################
+#
+# Copyright (C) 2014
+# ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+# P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+#
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+###############################################################################
+
+source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_minimal_pins.tcl
+# unb2b_jesd204_pins contains undesired QSFP pinning
+#source $::env(RADIOHDL_WORK)/boards/uniboard2b/libraries/unb2b_board/quartus/pinning/unb2b_jesd204b_pins.tcl
+#
+#=====================
+# QSFP pins
+# ====================
+
+set_location_assignment PIN_AL32 -to CLKUSR
+
+set_location_assignment PIN_Y36 -to SA_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to SA_CLK
+# internal termination should be enabled.
+set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SA_CLK
+
+set_location_assignment PIN_AH9 -to SB_CLK
+set_instance_assignment -name IO_STANDARD LVDS -to SB_CLK
+# internal termination should be enabled.
+set_instance_assignment -name XCVR_A10_REFCLK_TERM_TRISTATE TRISTATE_OFF -to SB_CLK
+
+
+set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
+
+
+set_location_assignment PIN_AT31 -to QSFP_RST
+
+set_location_assignment PIN_AY33 -to QSFP_SCL[0]
+set_location_assignment PIN_AY32 -to QSFP_SCL[1]
+set_location_assignment PIN_AY30 -to QSFP_SCL[2]
+set_location_assignment PIN_AN33 -to QSFP_SCL[3]
+set_location_assignment PIN_AN31 -to QSFP_SCL[4]
+set_location_assignment PIN_AJ33 -to QSFP_SCL[5]
+set_location_assignment PIN_BA32 -to QSFP_SDA[0]
+set_location_assignment PIN_BA31 -to QSFP_SDA[1]
+set_location_assignment PIN_AP33 -to QSFP_SDA[2]
+set_location_assignment PIN_AM33 -to QSFP_SDA[3]
+set_location_assignment PIN_AK33 -to QSFP_SDA[4]
+set_location_assignment PIN_AH32 -to QSFP_SDA[5]
+
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[5]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[0]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[1]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SDA[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[2]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[3]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_SCL[4]
+set_instance_assignment -name IO_STANDARD "1.8 V" -to QSFP_RST
+
+# QSFP_0_RX
+set_location_assignment PIN_AN38 -to QSFP_0_RX[0]
+set_location_assignment PIN_AM40 -to QSFP_0_RX[1]
+set_location_assignment PIN_AK40 -to QSFP_0_RX[2]
+set_location_assignment PIN_AJ38 -to QSFP_0_RX[3]
+
+# QSFP_0_TX
+set_location_assignment PIN_AN42 -to QSFP_0_TX[0]
+set_location_assignment PIN_AM44 -to QSFP_0_TX[1]
+set_location_assignment PIN_AK44 -to QSFP_0_TX[2]
+set_location_assignment PIN_AJ42 -to QSFP_0_TX[3]
+
+
+### QSFP_1_RX
+set_location_assignment PIN_AC38 -to QSFP_1_RX[0]
+set_location_assignment PIN_AD40 -to QSFP_1_RX[1]
+set_location_assignment PIN_AF40 -to QSFP_1_RX[2]
+set_location_assignment PIN_AG38 -to QSFP_1_RX[3]
+
+### QSFP_1_TX
+set_location_assignment PIN_AC42 -to QSFP_1_TX[0]
+set_location_assignment PIN_AD44 -to QSFP_1_TX[1]
+set_location_assignment PIN_AF44 -to QSFP_1_TX[2]
+set_location_assignment PIN_AG42 -to QSFP_1_TX[3]
+
+# RING pinning location
+set_location_assignment PIN_AP40 -to RING_0_RX[0]
+set_location_assignment PIN_AR38 -to RING_0_RX[1]
+set_location_assignment PIN_AT40 -to RING_0_RX[2]
+set_location_assignment PIN_AU38 -to RING_0_RX[3]
+set_location_assignment PIN_AP44 -to RING_0_TX[0]
+set_location_assignment PIN_AR42 -to RING_0_TX[1]
+set_location_assignment PIN_AT44 -to RING_0_TX[2]
+set_location_assignment PIN_AU42 -to RING_0_TX[3]
+set_location_assignment PIN_H40 -to RING_1_RX[0]
+set_location_assignment PIN_J38 -to RING_1_RX[1]
+set_location_assignment PIN_F40 -to RING_1_RX[2]
+set_location_assignment PIN_G38 -to RING_1_RX[3]
+set_location_assignment PIN_H44 -to RING_1_TX[0]
+set_location_assignment PIN_J42 -to RING_1_TX[1]
+set_location_assignment PIN_G42 -to RING_1_TX[2]
+set_location_assignment PIN_F44 -to RING_1_TX[3]
+
+
+