added TBs

applications/disturb2/designs/disturb2_unb2b_station/hdllib.cfg

@@ -22,6 +22,7 @@ test_bench_files =
     tb/vhdl/tb_disturb2_unb2b_station.vhd
 
 regression_test_vhdl =
+    tb/vhdl/tb_disturb2_unb2b_station.vhd
 
 [modelsim_project_file]
 modelsim_copy_files =

applications/disturb2/designs/disturb2_unb2b_station/revisions/disturb2_unb2b_station_full/hdllib.cfg

@@ -8,8 +8,10 @@ hdl_lib_technology = ip_arria10_e1sg
     disturb2_unb2b_station_full.vhd
 
 test_bench_files = 
+    tb_disturb2_unb2b_station_full.vhd
 
 regression_test_vhdl =
+    tb_disturb2_unb2b_station_full.vhd
 
 [modelsim_project_file]
 modelsim_copy_files =

applications/disturb2/designs/disturb2_unb2b_station/revisions/disturb2_unb2b_station_full/tb_disturb2_unb2b_station_full.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Reinier vd Walle
+-- Purpose: Tb to show that disturb2_unb2b_station_full can simulate
+-- Description:
+--   Must use c_sim = TRUE to speed up simulation
+--   This is a compile-only test bench
+-- Usage:
+--   Load sim    # check that design can load in vsim
+--   > as 10     # check that the hierarchy for g_design_name is complete
+--   > run -a    # check that design can simulate some us without error
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, disturb2_unb2b_station_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_disturb2_unb2b_station_full IS
+END tb_disturb2_unb2b_station_full;
+
+ARCHITECTURE tb OF tb_disturb2_unb2b_station_full IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period  : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_pps_period      : NATURAL := 1000;
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL JESD204B_SERIAL_DATA    : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL JESD204B_REFCLK         : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync_n     : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+BEGIN
+
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_adc : ENTITY disturb2_unb2b_station_lib.disturb2_unb2b_station
+  GENERIC MAP (
+    g_design_name => "disturb2_unb2b_station_full",
+    g_design_note => "Disturb2 full station design",
+    g_sim         => c_sim,
+    g_sim_unb_nr  => c_unb_nr,
+    g_sim_node_nr => c_node_nr
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- LEDs
+    QSFP_LED     => open,
+
+    -- back transceivers
+    JESD204B_SERIAL_DATA       => JESD204B_SERIAL_DATA,
+    JESD204B_REFCLK  => JESD204B_REFCLK,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC_N => jesd204b_sync_n
+  );
+
+
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER 1 us;
+
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
+END tb;

applications/disturb2/designs/disturb2_unb2b_station/revisions/disturb2_unb2b_station_full_wg/hdllib.cfg

@@ -8,8 +8,10 @@ hdl_lib_technology = ip_arria10_e1sg
     disturb2_unb2b_station_full_wg.vhd
 
 test_bench_files = 
+    tb_disturb2_unb2b_station_full_wg.vhd
 
 regression_test_vhdl =
+    tb_disturb2_unb2b_station_full_wg.vhd
 
 [modelsim_project_file]
 modelsim_copy_files =

applications/disturb2/designs/disturb2_unb2b_station/revisions/disturb2_unb2b_station_full_wg/tb_disturb2_unb2b_station_full_wg.vhd

+-------------------------------------------------------------------------------
+--
+-- Copyright 2022
+-- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
+-- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
+--
+-- Licensed under the Apache License, Version 2.0 (the "License");
+-- you may not use this file except in compliance with the License.
+-- You may obtain a copy of the License at
+--
+--     http://www.apache.org/licenses/LICENSE-2.0
+--
+-- Unless required by applicable law or agreed to in writing, software
+-- distributed under the License is distributed on an "AS IS" BASIS,
+-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+-- See the License for the specific language governing permissions and
+-- limitations under the License.
+--
+-------------------------------------------------------------------------------
+
+-- Author: Reinier vd Walle
+-- Purpose: Tb to show that disturb2_unb2b_station_full_wg can simulate
+-- Description:
+--   Must use c_sim = TRUE to speed up simulation
+--   This is a compile-only test bench
+-- Usage:
+--   Load sim    # check that design can load in vsim
+--   > as 10     # check that the hierarchy for g_design_name is complete
+--   > run -a    # check that design can simulate some us without error
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, disturb2_unb2b_station_lib;
+USE IEEE.std_logic_1164.ALL;
+USE IEEE.numeric_std.ALL;
+USE common_lib.common_pkg.ALL;
+USE unb2b_board_lib.unb2b_board_pkg.ALL;
+USE common_lib.tb_common_pkg.ALL;
+
+ENTITY tb_disturb2_unb2b_station_full_wg IS
+END tb_disturb2_unb2b_station_full_wg;
+
+ARCHITECTURE tb OF tb_disturb2_unb2b_station_full_wg IS
+
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
+
+  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period  : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_pps_period      : NATURAL := 1000;
+
+  -- Tb
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
+
+  -- DUT
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
+
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
+
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
+
+  -- back transceivers
+  SIGNAL JESD204B_SERIAL_DATA    : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL JESD204B_REFCLK         : STD_LOGIC := '1';
+
+  -- jesd204b syncronization signals
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync_n     : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
+
+BEGIN
+
+
+  ----------------------------------------------------------------------------
+  -- System setup
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+
+  INTA <= 'H';  -- pull up
+  INTB <= 'H';  -- pull up
+
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
+  pmbus_scl <= 'H';  -- pull up
+  pmbus_sda <= 'H';  -- pull up
+
+  ------------------------------------------------------------------------------
+  -- External PPS
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
+  jesd204b_sysref <= pps;
+
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_adc : ENTITY disturb2_unb2b_station_lib.disturb2_unb2b_station
+  GENERIC MAP (
+    g_design_name => "disturb2_unb2b_station_full_wg",
+    g_design_note => "Disturb2 full station design without ADC",
+    g_sim         => c_sim,
+    g_sim_unb_nr  => c_unb_nr,
+    g_sim_node_nr => c_node_nr
+  )
+  PORT MAP (
+    -- GENERAL
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
+
+    -- Others
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
+
+    -- I2C Interface to Sensors
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
+
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
+
+    -- 1GbE Control Interface
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
+
+    -- LEDs
+    QSFP_LED     => open,
+
+    -- back transceivers
+    JESD204B_SERIAL_DATA       => JESD204B_SERIAL_DATA,
+    JESD204B_REFCLK  => JESD204B_REFCLK,
+  
+    -- jesd204b syncronization signals
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC_N => jesd204b_sync_n
+  );
+
+
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER 1 us;
+
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
+
+END tb;

applications/disturb2/designs/disturb2_unb2b_station/tb/vhdl/tb_disturb2_unb2b_station.vhd

 -------------------------------------------------------------------------------
 --
--- Copyright 2020
+-- Copyright 2022
 -- ASTRON (Netherlands Institute for Radio Astronomy) <http://www.astron.nl/>
 -- P.O.Box 2, 7990 AA Dwingeloo, The Netherlands
 --
@@ -17,248 +17,151 @@
 -- limitations under the License.
 --
 -------------------------------------------------------------------------------
--- Test statistics offload with "ethernet packet statistics" in wave window only
+
+-- Author: Reinier vd Walle
+-- Purpose: Tb to show that disturb2_unb2b_station can simulate
+-- Description:
+--   Must use c_sim = TRUE to speed up simulation
+--   This is a compile-only test bench
 -- Usage:
---   > as 7    # default
---   > as 12   # for detailed debugging
---   > run -a  # takes about 250 us --> c_eth_runtime_timeout
---
--- Remark:
--- - Only verify that there is statistics offload.
--- - The statistics data gets undefined, due to that the c_nof_block_per_sync
---   is too short to offload 12 SST packets via 1GbE. This causes that new
---   data is available before the old data has been offloaded. Therefore use
---   c_eth_check_nof_packets = 1 instead of S_pn = 12.
--------------------------------------------------------------------------------
-LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib, mm_lib, dp_lib, diag_lib, disturb_lib, wpfb_lib, eth_lib;
+--   Load sim    # check that design can load in vsim
+--   > as 10     # check that the hierarchy for g_design_name is complete
+--   > run -a    # check that design can simulate some us without error
+
+LIBRARY IEEE, common_lib, unb2b_board_lib, i2c_lib;
 USE IEEE.std_logic_1164.ALL;
 USE IEEE.numeric_std.ALL;
-USE IEEE.MATH_REAL.ALL;
 USE common_lib.common_pkg.ALL;
 USE unb2b_board_lib.unb2b_board_pkg.ALL;
 USE common_lib.tb_common_pkg.ALL;
-USE common_lib.common_str_pkg.ALL;
-USE mm_lib.mm_file_pkg.ALL;
-USE dp_lib.dp_stream_pkg.ALL;
-USE mm_lib.mm_file_unb_pkg.ALL;
-USE diag_lib.diag_pkg.ALL;
-USE wpfb_lib.wpfb_pkg.ALL;
-USE disturb_lib.disturb_pkg.ALL;
-USE eth_lib.eth_pkg.ALL;
 
 ENTITY tb_disturb2_unb2b_station IS
 END tb_disturb2_unb2b_station;
 
 ARCHITECTURE tb OF tb_disturb2_unb2b_station IS
 
-  CONSTANT c_sim                          : BOOLEAN := TRUE;
-  CONSTANT c_unb_nr                       : NATURAL := 0; -- UniBoard 0
-  CONSTANT c_node_nr                      : NATURAL := 0;
-  CONSTANT c_id                           : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
-  CONSTANT c_version                      : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
-
-  CONSTANT c_eth_clk_period               : TIME := 8 ns;  -- 125 MHz XO on UniBoard
-  CONSTANT c_ext_clk_period               : TIME := 5 ns;
-  CONSTANT c_bck_ref_clk_period           : TIME := 5 ns;
+  CONSTANT c_sim             : BOOLEAN := TRUE;
+  CONSTANT c_unb_nr          : NATURAL := 0; -- UniBoard 0
+  CONSTANT c_node_nr         : NATURAL := 0; -- Back node 3
+  CONSTANT c_id              : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
+  CONSTANT c_version         : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00";
+  CONSTANT c_fw_version      : t_unb2b_board_fw_version := (1, 0);
 
-  CONSTANT c_tb_clk_period                : TIME := 100 ps; -- use fast tb_clk to speed up M&C
-
-  CONSTANT c_nof_block_per_sync           : NATURAL := 16;
-  CONSTANT c_nof_clk_per_sync             : NATURAL := c_nof_block_per_sync*c_disturb_N_fft; 
-  CONSTANT c_pps_period                   : NATURAL := c_nof_clk_per_sync;
-  CONSTANT c_wpfb_sim                     : t_wpfb := func_wpfb_set_nof_block_per_sync(c_disturb_wpfb_subbands, c_nof_block_per_sync);
-   
-  -- WG
-  CONSTANT c_full_scale_ampl              : REAL := REAL(2**(18-1) - 1);  -- = full scale of WG
-  CONSTANT c_bsn_start_wg                 : NATURAL := 2;  -- start WG at this BSN to instead of some BSN, to avoid mismatches in exact expected data values
-  CONSTANT c_ampl_sp_0                    : NATURAL := 2**(c_disturb_W_adc-1) / 2;  -- in number of lsb
-  CONSTANT c_wg_subband_freq_unit         : REAL := c_diag_wg_freq_unit / REAL(c_disturb_N_fft);  -- subband freq = Fs/1024 = 200 MSps/1024 = 195312.5 Hz sinus
-  CONSTANT c_wg_freq_offset               : REAL := 0.0 / 11.0; -- in freq_unit
-  CONSTANT c_subband_sp_0                 : REAL := 102.0;  -- Select subband at index 102 = 102/1024 * 200MHz = 19.921875 MHz
-  CONSTANT c_wg_ampl_lsb                  : REAL := c_diag_wg_ampl_unit / c_full_scale_ampl;  -- amplitude in number of LSbit resolution steps
-
--- . 1GbE output
-  CONSTANT c_eth_check_nof_packets        : NATURAL := 1;
-  CONSTANT c_eth_runtime_timeout          : TIME := 300 us;
-  
-  -- MM  
-  CONSTANT c_mm_file_reg_bsn_source_v2    : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SOURCE_V2";
-  CONSTANT c_mm_file_reg_bsn_scheduler_wg : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_BSN_SCHEDULER";
-  CONSTANT c_mm_file_reg_diag_wg          : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_WG";
-  CONSTANT c_mm_file_reg_stat_enable_sst  : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_ENABLE_SST";
-  CONSTANT c_mm_file_reg_stat_hdr_dat_sst : STRING := mmf_unb_file_prefix(c_unb_nr, c_node_nr) & "REG_STAT_HDR_DAT_SST";
+  CONSTANT c_eth_clk_period  : TIME := 8 ns;  -- 125 MHz XO on UniBoard
+  CONSTANT c_ext_clk_period  : TIME := 5 ns;
+  CONSTANT c_bck_ref_clk_period  : TIME := 5 ns;
+  CONSTANT c_pps_period      : NATURAL := 1000;
 
   -- Tb
-  SIGNAL tb_end               : STD_LOGIC := '0';
-  SIGNAL sim_done             : STD_LOGIC := '0';
-  SIGNAL eth_done             : STD_LOGIC := '0';
-  SIGNAL verify_done          : STD_LOGIC := '0';
-  SIGNAL tb_clk               : STD_LOGIC := '0';
-
-  -- WG
-  SIGNAL current_bsn_wg       : STD_LOGIC_VECTOR(c_dp_stream_bsn_w-1 DOWNTO 0);
+  SIGNAL tb_end              : STD_LOGIC := '0';
+  SIGNAL sim_done            : STD_LOGIC := '0';
 
   -- DUT
-  SIGNAL ext_clk              : STD_LOGIC := '0';
-  SIGNAL pps                  : STD_LOGIC := '0';
-  SIGNAL ext_pps              : STD_LOGIC := '0';
-  SIGNAL pps_rst              : STD_LOGIC := '0';
+  SIGNAL ext_clk             : STD_LOGIC := '0';
+  SIGNAL pps                 : STD_LOGIC := '0';
+  SIGNAL pps_rst             : STD_LOGIC := '0';
 
-  SIGNAL WDI                  : STD_LOGIC;
-  SIGNAL INTA                 : STD_LOGIC;
-  SIGNAL INTB                 : STD_LOGIC;
+  SIGNAL WDI                 : STD_LOGIC;
+  SIGNAL INTA                : STD_LOGIC;
+  SIGNAL INTB                : STD_LOGIC;
 
-  SIGNAL eth_clk              : STD_LOGIC := '0';
-  SIGNAL eth_txp              : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
-  SIGNAL eth_rxp              : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_clk             : STD_LOGIC := '0';
+  SIGNAL eth_txp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
+  SIGNAL eth_rxp             : STD_LOGIC_VECTOR(c_unb2b_board_nof_eth-1 downto 0);
 
-  SIGNAL sens_scl             : STD_LOGIC;
-  SIGNAL sens_sda             : STD_LOGIC;
-  SIGNAL pmbus_scl            : STD_LOGIC;
-  SIGNAL pmbus_sda            : STD_LOGIC;
+  SIGNAL sens_scl            : STD_LOGIC;
+  SIGNAL sens_sda            : STD_LOGIC;
+  SIGNAL pmbus_scl           : STD_LOGIC;
+  SIGNAL pmbus_sda           : STD_LOGIC;
 
   -- back transceivers
-  SIGNAL JESD204B_SERIAL_DATA : STD_LOGIC_VECTOR(c_disturb_S_pn-1 downto 0);
-  SIGNAL JESD204B_REFCLK      : STD_LOGIC := '1';
+  SIGNAL JESD204B_SERIAL_DATA    : STD_LOGIC_VECTOR((c_unb2b_board_tr_jesd204b.bus_w * c_unb2b_board_tr_jesd204b.nof_bus)-1 downto 0);
+  SIGNAL JESD204B_REFCLK         : STD_LOGIC := '1';
 
   -- jesd204b syncronization signals
-  SIGNAL jesd204b_sysref      : STD_LOGIC;
-  SIGNAL jesd204b_sync_n      : STD_LOGIC_VECTOR(c_disturb_N_sync_jesd-1 DOWNTO 0);
+  SIGNAL jesd204b_sysref     : STD_LOGIC;
+  SIGNAL jesd204b_sync_n     : STD_LOGIC_VECTOR(c_unb2b_board_nof_sync_jesd204b-1 DOWNTO 0);
+
 
 BEGIN
 
+
+  ----------------------------------------------------------------------------
   -- System setup
-  ext_clk <= (NOT ext_clk) OR tb_end AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
-  eth_clk <= (NOT eth_clk) OR tb_end AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
-  JESD204B_REFCLK <= (NOT JESD204B_REFCLK) OR tb_end AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
+  ----------------------------------------------------------------------------
+  ext_clk <= NOT ext_clk AFTER c_ext_clk_period/2;  -- External clock (200 MHz)
+  eth_clk <= NOT eth_clk AFTER c_eth_clk_period/2;  -- Ethernet ref clock (125 MHz)
+  JESD204B_REFCLK <= NOT JESD204B_REFCLK AFTER c_bck_ref_clk_period/2;  -- JESD sample clock (200MHz) 
 
   INTA <= 'H';  -- pull up
   INTB <= 'H';  -- pull up
 
-  sens_scl  <= 'H';  -- pull up
-  sens_sda  <= 'H';  -- pull up
+  sens_scl <= 'H';  -- pull up
+  sens_sda <= 'H';  -- pull up
   pmbus_scl <= 'H';  -- pull up
   pmbus_sda <= 'H';  -- pull up
 
+  ------------------------------------------------------------------------------
   -- External PPS
-  proc_common_gen_pulse(10, c_pps_period, '1', pps_rst, ext_clk, pps);
+  ------------------------------------------------------------------------------  
+  proc_common_gen_pulse(1, c_pps_period, '1', pps_rst, ext_clk, pps);
   jesd204b_sysref <= pps;
-  ext_pps <= pps;
 
-  -- >> DUT <<
-  u_lofar_unb2b_disturb_station : ENTITY work.disturb2_unb2b_station
+  ------------------------------------------------------------------------------
+  -- DUT
+  ------------------------------------------------------------------------------
+  u_lofar_unb2b_adc : ENTITY work.disturb2_unb2b_station
   GENERIC MAP (
-    g_design_name            => "disturb2_unb2b_station_bf",
-    g_design_note            => "",
-    g_sim                    => c_sim,
-    g_sim_unb_nr             => c_unb_nr,
-    g_sim_node_nr            => c_node_nr,
-    g_wpfb                   => c_wpfb_sim,
-    g_scope_selected_subband => NATURAL(c_subband_sp_0)
+    g_design_name => "disturb2_unb2b_station",
+    g_design_note => "Disturb2 default design",
+    g_sim         => c_sim,
+    g_sim_unb_nr  => c_unb_nr,
+    g_sim_node_nr => c_node_nr
   )
   PORT MAP (
     -- GENERAL
-    CLK                  => ext_clk,
-    PPS                  => pps,
-    WDI                  => WDI,
-    INTA                 => INTA,
-    INTB                 => INTB,
+    CLK          => ext_clk,
+    PPS          => pps,
+    WDI          => WDI,
+    INTA         => INTA,
+    INTB         => INTB,
 
     -- Others
-    VERSION              => c_version,
-    ID                   => c_id,
-    TESTIO               => open,
+    VERSION      => c_version,
+    ID           => c_id,
+    TESTIO       => open,
 
     -- I2C Interface to Sensors
-    SENS_SC              => sens_scl,
-    SENS_SD              => sens_sda,
+    SENS_SC      => sens_scl,
+    SENS_SD      => sens_sda,
 
-    PMBUS_SC             => pmbus_scl,
-    PMBUS_SD             => pmbus_sda,
-    PMBUS_ALERT          => open,
+    PMBUS_SC     => pmbus_scl,
+    PMBUS_SD     => pmbus_sda,
+    PMBUS_ALERT  => open,
 
     -- 1GbE Control Interface
-    ETH_CLK              => eth_clk,
-    ETH_SGIN             => eth_rxp,
-    ETH_SGOUT            => eth_txp,
+    ETH_CLK      => eth_clk,
+    ETH_SGIN     => eth_rxp,
+    ETH_SGOUT    => eth_txp,
 
     -- LEDs
-    QSFP_LED             => open,
+    QSFP_LED     => open,
 
     -- back transceivers
-    JESD204B_SERIAL_DATA => JESD204B_SERIAL_DATA,
-    JESD204B_REFCLK      => JESD204B_REFCLK,
+    JESD204B_SERIAL_DATA       => JESD204B_SERIAL_DATA,
+    JESD204B_REFCLK  => JESD204B_REFCLK,
   
     -- jesd204b syncronization signals
-    JESD204B_SYSREF      => jesd204b_sysref,
-    JESD204B_SYNC_N      => jesd204b_sync_n
+    JESD204B_SYSREF => jesd204b_sysref,
+    JESD204B_SYNC_N => jesd204b_sync_n
   );
 
-  ---------------------------------------------------------------------------------------------------------------------
-  -- Stimuli
-  --   MM slave accesses via file IO
-  tb_clk <= (NOT tb_clk) OR tb_end AFTER c_tb_clk_period/2;    -- Testbench MM clock
-  
-  p_mm_stimuli : PROCESS
-    VARIABLE v_bsn                          : NATURAL;
-  BEGIN
-    -- Wait for DUT power up after reset
-    WAIT FOR 1 us;
-    
-    proc_common_wait_until_hi_lo(ext_clk, ext_pps);
-
-    -- Enable BS
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 3,                   0, tb_clk);
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 2,                   1, tb_clk);  -- Init BSN = 0
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 1,  c_nof_clk_per_sync, tb_clk);  -- nof_block_per_sync
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_source_v2, 0,        16#00000003#, tb_clk);  -- Enable BS at PPS
-    
-    -- Enable WG
-    --   0 : mode[7:0]           --> off=0, calc=1, repeat=2, single=3)
-    --       nof_samples[31:16]  --> <= c_ram_wg_size=1024
-    --   1 : phase[15:0]
-    --   2 : freq[30:0]
-    --   3 : ampl[16:0]
-    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 0,                                                      1024 * 2**16 + 1, tb_clk);  -- nof_samples, mode calc
-    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 1,                                 INTEGER(  0.0 * c_diag_wg_phase_unit), tb_clk);  -- phase offset in degrees
-    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 2, INTEGER((c_subband_sp_0 + c_wg_freq_offset) * c_wg_subband_freq_unit), tb_clk);  -- freq
-    mmf_mm_bus_wr(c_mm_file_reg_diag_wg, 3,                            INTEGER(REAL(c_ampl_sp_0) * c_wg_ampl_lsb), tb_clk);  -- ampl
 
-    -- Read current BSN
-    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 0, current_bsn_wg(31 DOWNTO  0), tb_clk);
-    mmf_mm_bus_rd(c_mm_file_reg_bsn_scheduler_wg, 1, current_bsn_wg(63 DOWNTO 32), tb_clk);
-    proc_common_wait_some_cycles(tb_clk, 1);
-    
-    -- Write scheduler BSN to trigger start of WG at next block
-    v_bsn := TO_UINT(current_bsn_wg) + 2;
-    ASSERT v_bsn <= c_bsn_start_wg REPORT "Too late to start WG: " & int_to_str(v_bsn) & " > " & int_to_str(c_bsn_start_wg) SEVERITY ERROR;
-    v_bsn := c_bsn_start_wg;
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 0, v_bsn, tb_clk);  -- first write low then high part
-    mmf_mm_bus_wr(c_mm_file_reg_bsn_scheduler_wg, 1,     0, tb_clk);  -- assume v_bsn < 2**31-1
-    
-    -- Wait for ADUH monitor to have filled with WG data
-    WAIT FOR c_disturb_T_sub * c_disturb_N_taps;
-    WAIT FOR c_disturb_T_sub * 2;
+  ------------------------------------------------------------------------------
+  -- Simulation end
+  ------------------------------------------------------------------------------
+  sim_done <= '0', '1' AFTER 1 us;
 
-    -- Offload enable
-    mmf_mm_bus_wr(c_mm_file_reg_stat_enable_sst, 0, 1, tb_clk);
-    
-    -- End Simulation
-    proc_common_wait_until_high(ext_clk, eth_done);
-    proc_common_wait_some_cycles(ext_clk, 100);
-    proc_common_stop_simulation(TRUE, ext_clk, eth_done, tb_end);
-    WAIT;
-  END PROCESS;
-
-  -- >> Verify proper DUT output using Ethernet packet statistics <<
-  u_eth_statistics : ENTITY eth_lib.eth_statistics
-  GENERIC MAP (
-    g_runtime_nof_packets => c_eth_check_nof_packets,
-    g_runtime_timeout     => c_eth_runtime_timeout
-  )
-  PORT MAP (  
-    eth_serial_in => eth_txp(0),
-    tb_end        => eth_done
-  );
+  proc_common_stop_simulation(TRUE, ext_clk, sim_done, tb_end);
 
 END tb;