-Added symbol width generics to dp_field_blk and dp_concat_field_blk;

-Set symbol width to 8 (was 1) to dp_concat_field_blk instance used in 
 arts_unb1_sc4_output_tab_i_packetizer.
-Verified OK sim sim (empty field indicated 22, is 6 now).

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd

@@ -455,7 +455,9 @@ BEGIN
     g_nof_streams           => c_nof_offloadstreams,
     g_data_w                => c_data_w,
     g_hdr_field_arr         => c_hdr_field_arr,
-    g_hdr_field_sel         => c_hdr_field_sel
+    g_hdr_field_sel         => c_hdr_field_sel,
+    g_in_symbol_w           => c_byte_w,
+    g_out_symbol_w          => c_byte_w
    )
   PORT MAP (
     mm_rst                => mm_rst,

libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd

@@ -38,7 +38,9 @@ ENTITY dp_concat_field_blk IS
     g_nof_streams    : NATURAL;
     g_data_w         : NATURAL;
     g_hdr_field_arr  : t_common_field_arr; -- User defined header fields
-    g_hdr_field_sel  : STD_LOGIC_VECTOR   -- For each header field, select the source: 0=data path, 1=MM controlled
+    g_hdr_field_sel  : STD_LOGIC_VECTOR;  -- For each header field, select the source: 0=data path, 1=MM controlled
+    g_in_symbol_w    : NATURAL := 1;
+    g_out_symbol_w   : NATURAL := 1
   ); 
   PORT (
     mm_rst               : IN  STD_LOGIC;
@@ -103,7 +105,9 @@ BEGIN
       g_field_arr    => field_arr_set_mode(g_hdr_field_arr , "RW"),
       g_field_sel    => g_hdr_field_sel,
       g_snk_data_w   => c_dp_field_blk_snk_data_w,
-      g_src_data_w  => c_dp_field_blk_src_data_w
+      g_src_data_w   => c_dp_field_blk_src_data_w,
+      g_in_symbol_w  => g_in_symbol_w,
+      g_out_symbol_w => g_out_symbol_w
     )
     PORT MAP (
       dp_clk       => dp_clk,
@@ -134,7 +138,7 @@ BEGIN
     u_dp_concat : ENTITY work.dp_concat
     GENERIC MAP (
       g_data_w    => g_data_w,
-      g_symbol_w  => 1
+      g_symbol_w  => g_out_symbol_w
     )
     PORT MAP (
       rst         => dp_rst,

libraries/base/dp/src/vhdl/dp_field_blk.vhd

@@ -79,7 +79,9 @@ ENTITY dp_field_blk IS
     g_field_arr    : t_common_field_arr;
     g_field_sel    : STD_LOGIC_VECTOR;
     g_snk_data_w   : NATURAL;
-    g_src_data_w  : NATURAL
+    g_src_data_w   : NATURAL;
+    g_in_symbol_w  : NATURAL := 1;
+    g_out_symbol_w : NATURAL := 1
   );
   PORT (
     dp_rst          : IN  STD_LOGIC;
@@ -186,7 +188,9 @@ BEGIN
     g_in_dat_w      => g_snk_data_w,
     g_in_nof_words  => ceil_div(g_src_data_w, g_snk_data_w),
     g_out_dat_w     => g_src_data_w,
-    g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w)
+    g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w),
+    g_in_symbol_w   => g_in_symbol_w,
+    g_out_symbol_w  => g_out_symbol_w
   )
   PORT MAP (
     rst            => dp_rst,