From cad67065ec4b274c39ffbcf721a3bfa263dd6b5f Mon Sep 17 00:00:00 2001
From: Daniel van der Schuur <schuur@astron.nl>
Date: Fri, 14 Jul 2017 13:25:02 +0000
Subject: [PATCH] -Added symbol width generics to dp_field_blk and
dp_concat_field_blk; -Set symbol width to 8 (was 1) to dp_concat_field_blk
instance used in arts_unb1_sc4_output_tab_i_packetizer. -Verified OK sim sim
(empty field indicated 22, is 6 now).
---
.../arts_unb1_sc4_output_tab_i_packetizer.vhd | 4 +++-
.../base/dp/src/vhdl/dp_concat_field_blk.vhd | 16 ++++++++++------
libraries/base/dp/src/vhdl/dp_field_blk.vhd | 12 ++++++++----
3 files changed, 21 insertions(+), 11 deletions(-)
diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
index 5320cbdd27..b1da21e7d3 100644
--- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
+++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd
@@ -455,7 +455,9 @@ BEGIN
g_nof_streams => c_nof_offloadstreams,
g_data_w => c_data_w,
g_hdr_field_arr => c_hdr_field_arr,
- g_hdr_field_sel => c_hdr_field_sel
+ g_hdr_field_sel => c_hdr_field_sel,
+ g_in_symbol_w => c_byte_w,
+ g_out_symbol_w => c_byte_w
)
PORT MAP (
mm_rst => mm_rst,
diff --git a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
index d48f2300c3..18c80f9e1e 100644
--- a/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_concat_field_blk.vhd
@@ -38,7 +38,9 @@ ENTITY dp_concat_field_blk IS
g_nof_streams : NATURAL;
g_data_w : NATURAL;
g_hdr_field_arr : t_common_field_arr; -- User defined header fields
- g_hdr_field_sel : STD_LOGIC_VECTOR -- For each header field, select the source: 0=data path, 1=MM controlled
+ g_hdr_field_sel : STD_LOGIC_VECTOR; -- For each header field, select the source: 0=data path, 1=MM controlled
+ g_in_symbol_w : NATURAL := 1;
+ g_out_symbol_w : NATURAL := 1
);
PORT (
mm_rst : IN STD_LOGIC;
@@ -100,10 +102,12 @@ BEGIN
-- Create multi-cycle header block from single-cycle wide header SLV
u_dp_field_blk : ENTITY work.dp_field_blk
GENERIC MAP (
- g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
- g_field_sel => g_hdr_field_sel,
- g_snk_data_w => c_dp_field_blk_snk_data_w,
- g_src_data_w => c_dp_field_blk_src_data_w
+ g_field_arr => field_arr_set_mode(g_hdr_field_arr , "RW"),
+ g_field_sel => g_hdr_field_sel,
+ g_snk_data_w => c_dp_field_blk_snk_data_w,
+ g_src_data_w => c_dp_field_blk_src_data_w,
+ g_in_symbol_w => g_in_symbol_w,
+ g_out_symbol_w => g_out_symbol_w
)
PORT MAP (
dp_clk => dp_clk,
@@ -134,7 +138,7 @@ BEGIN
u_dp_concat : ENTITY work.dp_concat
GENERIC MAP (
g_data_w => g_data_w,
- g_symbol_w => 1
+ g_symbol_w => g_out_symbol_w
)
PORT MAP (
rst => dp_rst,
diff --git a/libraries/base/dp/src/vhdl/dp_field_blk.vhd b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
index 578ebc75d5..0e93ccca2d 100644
--- a/libraries/base/dp/src/vhdl/dp_field_blk.vhd
+++ b/libraries/base/dp/src/vhdl/dp_field_blk.vhd
@@ -76,10 +76,12 @@ USE work.dp_stream_pkg.ALL;
ENTITY dp_field_blk IS
GENERIC (
- g_field_arr : t_common_field_arr;
+ g_field_arr : t_common_field_arr;
g_field_sel : STD_LOGIC_VECTOR;
- g_snk_data_w : NATURAL;
- g_src_data_w : NATURAL
+ g_snk_data_w : NATURAL;
+ g_src_data_w : NATURAL;
+ g_in_symbol_w : NATURAL := 1;
+ g_out_symbol_w : NATURAL := 1
);
PORT (
dp_rst : IN STD_LOGIC;
@@ -186,7 +188,9 @@ BEGIN
g_in_dat_w => g_snk_data_w,
g_in_nof_words => ceil_div(g_src_data_w, g_snk_data_w),
g_out_dat_w => g_src_data_w,
- g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w)
+ g_out_nof_words => ceil_div(g_snk_data_w, g_src_data_w),
+ g_in_symbol_w => g_in_symbol_w,
+ g_out_symbol_w => g_out_symbol_w
)
PORT MAP (
rst => dp_rst,
--
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