Progress with IQUV output stage

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_iab_i_reorder.vhd

@@ -77,6 +77,8 @@ ARCHITECTURE str OF arts_unb1_sc4_output_iab_i_reorder IS
   SIGNAL dp_fifo_sc_snk_in_arr         : t_dp_sosi_arr(g_nof_frequency_channels-1 DOWNTO 0);
   SIGNAL dp_fifo_sc_src_out_arr        : t_dp_sosi_arr(0 TO g_nof_frequency_channels-1);
   SIGNAL dp_fifo_sc_src_in_arr         : t_dp_siso_arr(0 TO g_nof_frequency_channels-1) := (others => c_dp_siso_rst);
+  SIGNAL dp_pipeline_ready_src_out_arr : t_dp_sosi_arr(0 TO g_nof_frequency_channels-1);
+  SIGNAL dp_pipeline_ready_src_in_arr  : t_dp_siso_arr(0 TO g_nof_frequency_channels-1) := (others => c_dp_siso_rst);
   SIGNAL dp_mux_src_in                 : t_dp_siso := c_dp_siso_rst;
   SIGNAL end_of_packet_delayed         : STD_LOGIC := '0';
   SIGNAL end_of_packet_latched         : STD_LOGIC := '0';
@@ -110,6 +112,7 @@ BEGIN
 
   -----------------------------------------------------------------------------
   -- Feed each channel stream into a dp_fifo_sc
+  -- The pipeline_ready module is needed to alleviate timing errors
   -----------------------------------------------------------------------------
   gen_fifos : FOR i in 0 TO g_nof_frequency_channels-1 GENERATE
     u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
@@ -129,6 +132,19 @@ BEGIN
       src_in      => dp_fifo_sc_src_in_arr(i),
       src_out     => dp_fifo_sc_src_out_arr(i)
     );
+
+    u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
+    PORT MAP(
+      rst         => dp_rst,
+      clk         => dp_clk,
+
+      snk_in      => dp_fifo_sc_src_out_arr(i),
+      snk_out     => dp_fifo_sc_src_in_arr(i),
+
+      src_in      => dp_pipeline_ready_src_in_arr(i),
+      src_out     => dp_pipeline_ready_src_out_arr(i)
+    );
+
   END GENERATE;
 
 
@@ -148,8 +164,8 @@ BEGIN
     rst         => dp_rst,
     clk         => dp_clk,
     -- ST sinks
-    snk_out_arr => dp_fifo_sc_src_in_arr,   -- OUT = request to upstream ST source
-    snk_in_arr  => dp_fifo_sc_src_out_arr,
+    snk_out_arr => dp_pipeline_ready_src_in_arr,   -- OUT = request to upstream ST source
+    snk_in_arr  => dp_pipeline_ready_src_out_arr,
     -- ST source
     src_in      => dp_mux_src_in,  -- IN  = request from downstream ST sink
     src_out     => src_out

applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd

@@ -49,7 +49,7 @@ ENTITY arts_unb1_sc4_output_tab_i_reorder IS
     dp_rst      : IN  STD_LOGIC;
     dp_clk      : IN  STD_LOGIC;  
 
-    snk_in_arr  : IN  t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); -- 12 TAB streams
+    snk_in_arr  : IN  t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- 12 TAB streams
 
     src_out     : OUT t_dp_sosi;
     src_in      : IN  t_dp_siso
@@ -59,47 +59,53 @@ END arts_unb1_sc4_output_tab_i_reorder;
 
 ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_reorder IS
 
-  CONSTANT c_data_w               : NATURAL := c_byte_w;
+  CONSTANT c_indata_w             : NATURAL := c_byte_w;
+  CONSTANT c_data_w               : NATURAL := c_indata_w * 8;
+  CONSTANT c_empty_w              : NATURAL := ceil_log2(c_data_w /c_byte_w);
   CONSTANT c_nof_fifos            : NATURAL := g_nof_tabs * g_nof_frequency_channels;
 
   CONSTANT c_nof_words_per_packet : NATURAL := g_nof_bytes_per_packet/(c_data_w/c_byte_w);
-  CONSTANT c_dp_fifo_sc_size      : NATURAL := 8192; --c_nof_words_per_packet; 6250 not enough?
+  CONSTANT c_dp_fifo_sc_size      : NATURAL := 1024; --8192/8; 
   CONSTANT c_dp_channel_w         : NATURAL := 4*c_byte_w; --4 bytes: TAB, CB, Subband, Channel index.
 
   SIGNAL dp_deinterleave_snk_in_arr       : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); 
+  SIGNAL dp_deinterleave_src_out_arr      : t_dp_sosi_arr(g_nof_tabs*g_nof_frequency_channels-1 DOWNTO 0); 
+  SIGNAL dp_repack_snk_in_arr             : t_dp_sosi_arr(g_nof_tabs*g_nof_frequency_channels-1 DOWNTO 0); 
   SIGNAL dp_fifo_sc_snk_in_arr            : t_dp_sosi_arr(g_nof_tabs*g_nof_frequency_channels-1 DOWNTO 0); 
   SIGNAL dp_fifo_sc_src_out_arr           : t_dp_sosi_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1); 
   SIGNAL dp_fifo_sc_src_in_arr            : t_dp_siso_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1); 
+  SIGNAL dp_pipeline_ready_src_out_arr    : t_dp_sosi_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1); 
+  SIGNAL dp_pipeline_ready_src_in_arr     : t_dp_siso_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1); 
   SIGNAL dp_counter_count_src_out_arr     : t_dp_sosi_arr(1 DOWNTO 0); 
   SIGNAL dp_mux_src_in                    : t_dp_siso; 
 
   SIGNAL end_of_packet                    : STD_LOGIC;
   SIGNAL end_of_packet_latched            : STD_LOGIC;
 
-  SIGNAL dp_demux_snk_in_arr              : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); 
-  SIGNAL dp_demux_inverted_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
-  SIGNAL dp_demux_src_out_2arr_4          : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
-  SIGNAL dp_fifo_sc_src_out_2arr_4        : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
-  SIGNAL dp_fifo_sc_src_in_2arr_4         : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0);
+--  SIGNAL dp_demux_snk_in_arr              : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); 
+--  SIGNAL dp_demux_inverted_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
+--  SIGNAL dp_demux_src_out_2arr_4          : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
+--  SIGNAL dp_fifo_sc_src_out_2arr_4        : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
+--  SIGNAL dp_fifo_sc_src_in_2arr_4         : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0);
 
-  TYPE t_dp_fifo_sc_usedw_arr IS ARRAY(g_nof_frequency_channels-1 DOWNTO 0) OF STD_LOGIC_VECTOR(ceil_log2(c_dp_fifo_sc_size)-1 DOWNTO 0);
-  TYPE t_dp_fifo_sc_usedw_2arr_4 IS ARRAY(g_nof_tabs-1 DOWNTO 0) OF t_dp_fifo_sc_usedw_arr;
-  SIGNAL dp_fifo_sc_usedw_2arr_4      : t_dp_fifo_sc_usedw_2arr_4;
+--  TYPE t_dp_fifo_sc_usedw_arr IS ARRAY(g_nof_frequency_channels-1 DOWNTO 0) OF STD_LOGIC_VECTOR(ceil_log2(c_dp_fifo_sc_size)-1 DOWNTO 0);
+--  TYPE t_dp_fifo_sc_usedw_2arr_4 IS ARRAY(g_nof_tabs-1 DOWNTO 0) OF t_dp_fifo_sc_usedw_arr;
+--  SIGNAL dp_fifo_sc_usedw_2arr_4      : t_dp_fifo_sc_usedw_2arr_4;
 
-  SIGNAL dp_block_gen_src_out_2arr_4      : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
-  SIGNAL dp_block_gen_src_in_2arr_4       : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0);
+--  SIGNAL dp_block_gen_src_out_2arr_4      : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
+--  SIGNAL dp_block_gen_src_in_2arr_4       : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0);
 
   -- dp_mux inputs; 12*4
-  SIGNAL dp_mux_snk_in_2arr_4             : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
-  SIGNAL dp_mux_snk_out_2arr_4            : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0);
-  SIGNAL dp_mux_safe_snk_out_2arr_4       : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0);
+--  SIGNAL dp_mux_snk_in_2arr_4             : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0);
+--  SIGNAL dp_mux_snk_out_2arr_4            : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0);
+--  SIGNAL dp_mux_safe_snk_out_2arr_4       : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0);
   -- dp_mux inputs; 4*12
-  SIGNAL dp_mux_snk_in_2arr_12            : t_dp_sosi_2arr_12(g_nof_frequency_channels-1 DOWNTO 0);
-  SIGNAL dp_mux_reversed_snk_in_2arr_12   : t_dp_sosi_2arr_12(g_nof_frequency_channels-1 DOWNTO 0);
-  SIGNAL dp_mux_snk_out_2arr_12           : t_dp_siso_2arr_12(g_nof_frequency_channels-1 DOWNTO 0);
+--  SIGNAL dp_mux_snk_in_2arr_12            : t_dp_sosi_2arr_12(g_nof_frequency_channels-1 DOWNTO 0);
+--  SIGNAL dp_mux_reversed_snk_in_2arr_12   : t_dp_sosi_2arr_12(g_nof_frequency_channels-1 DOWNTO 0);
+--  SIGNAL dp_mux_snk_out_2arr_12           : t_dp_siso_2arr_12(g_nof_frequency_channels-1 DOWNTO 0);
   -- dp_mux outputs; 12
-  SIGNAL dp_mux_src_out_arr               : t_dp_sosi_arr(g_nof_frequency_channels-1 DOWNTO 0);
-  SIGNAL dp_mux_src_in_arr                : t_dp_siso_arr(g_nof_frequency_channels-1 DOWNTO 0);
+--  SIGNAL dp_mux_src_out_arr               : t_dp_sosi_arr(g_nof_frequency_channels-1 DOWNTO 0);
+--  SIGNAL dp_mux_src_in_arr                : t_dp_siso_arr(g_nof_frequency_channels-1 DOWNTO 0);
 
 BEGIN
 
@@ -153,6 +159,9 @@ BEGIN
 
 
   gen_reordering_fifos : FOR tabno IN 0 TO g_nof_tabs-1 GENERATE
+    dp_deinterleave_snk_in_arr(tabno).empty <= (others => '0');
+    dp_deinterleave_snk_in_arr(tabno).err <= (others => '0');
+
     -----------------------------------------------------------------------------
     -- Deinterleave snk_in into 4 (channel) substreams
     -- . Set the output block size to 6250
@@ -162,7 +171,7 @@ BEGIN
       g_nof_out           => g_nof_frequency_channels,
       g_block_size_int    => 1,
       g_block_size_output => g_nof_bytes_per_packet,
-      g_dat_w             => c_data_w,
+      g_dat_w             => c_indata_w,
       g_use_sync_bsn      => TRUE,
       g_use_ctrl          => TRUE,
       g_use_complex       => FALSE
@@ -172,16 +181,49 @@ BEGIN
       clk        => dp_clk,
   
       snk_in      => dp_deinterleave_snk_in_arr(tabno),
-      src_out_arr => dp_fifo_sc_snk_in_arr(tabno*g_nof_frequency_channels + g_nof_frequency_channels-1 DOWNTO tabno*g_nof_frequency_channels)
+      src_out_arr => dp_deinterleave_src_out_arr(tabno*g_nof_frequency_channels + g_nof_frequency_channels-1 DOWNTO tabno*g_nof_frequency_channels)
     );
 
     -----------------------------------------------------------------------------
     -- Feed each channel stream into a dp_fifo_sc
+    -- The empty fields of the incoming data are cleared
+    -- The data are repacked to 64bit first to speed up data transfer from the FIFOs to the 10GbE port
+    -- The pipeline_ready module is needed to alleviate timing errors
     -----------------------------------------------------------------------------
     gen_fifos : FOR i in 0 TO g_nof_frequency_channels-1 GENERATE
+
+      p_overide_empty : PROCESS(dp_deinterleave_src_out_arr(tabno*g_nof_frequency_channels + i))
+      BEGIN
+        dp_repack_snk_in_arr(tabno*g_nof_frequency_channels + i) <= dp_deinterleave_src_out_arr(tabno*g_nof_frequency_channels + i);
+        dp_repack_snk_in_arr(tabno*g_nof_frequency_channels + i).empty <= (OTHERS => '0');
+      END PROCESS;
+
+
+      u_dp_repack_data : ENTITY dp_lib.dp_repack_data
+      GENERIC MAP (
+        g_in_dat_w      => c_indata_w,  -- 8
+        g_in_nof_words  => 8,
+        g_in_symbol_w   => 8,
+        g_out_dat_w     => c_data_w,    -- 64
+        g_out_nof_words => 1,
+        g_out_symbol_w  => 8
+      )
+      PORT MAP (
+        clk            => dp_clk,
+        rst            => dp_rst,
+
+        snk_in         => dp_repack_snk_in_arr(tabno*g_nof_frequency_channels + i),
+--        snk_out        => dp_mux_src_in,
+                   
+        src_out        => dp_fifo_sc_snk_in_arr(tabno*g_nof_frequency_channels + i),
+        src_in         => c_dp_siso_rdy
+      );
+
       u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc
       GENERIC MAP (
         g_data_w         => c_data_w,
+        g_empty_w        => c_empty_w,
+        g_use_empty      => TRUE,
         g_use_ctrl       => TRUE,
         g_use_bsn        => FALSE,
         g_use_channel    => FALSE,
@@ -196,6 +238,19 @@ BEGIN
         src_in      => dp_fifo_sc_src_in_arr(tabno*g_nof_frequency_channels + i),
         src_out     => dp_fifo_sc_src_out_arr(tabno*g_nof_frequency_channels + i)
       );
+
+      u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready
+      PORT MAP(
+        rst         => dp_rst,
+        clk         => dp_clk,
+  
+        snk_in      => dp_fifo_sc_src_out_arr(tabno*g_nof_frequency_channels + i),
+        snk_out     => dp_fifo_sc_src_in_arr(tabno*g_nof_frequency_channels + i),
+  
+        src_in      => dp_pipeline_ready_src_in_arr(tabno*g_nof_frequency_channels + i),
+        src_out     => dp_pipeline_ready_src_out_arr(tabno*g_nof_frequency_channels + i)
+      );
+
     END GENERATE;
   END GENERATE;
 
@@ -205,6 +260,8 @@ BEGIN
   u_mux : ENTITY dp_lib.dp_mux
   GENERIC MAP (
     g_data_w          => c_data_w,
+    g_empty_w        => c_empty_w,
+    g_use_empty      => TRUE,
     g_error_w         => 1,
     g_mode            => 1, -- forced round robin mode
     g_nof_input       => g_nof_tabs * g_nof_frequency_channels,
@@ -215,8 +272,8 @@ BEGIN
     rst         => dp_rst,
     clk         => dp_clk,
     -- ST sinks
-    snk_out_arr => dp_fifo_sc_src_in_arr,   -- OUT = request to upstream ST source
-    snk_in_arr  => dp_fifo_sc_src_out_arr,
+    snk_out_arr => dp_pipeline_ready_src_in_arr,   -- OUT = request to upstream ST source
+    snk_in_arr  => dp_pipeline_ready_src_out_arr,
     -- ST source
     src_in      => dp_mux_src_in,  -- IN  = request from downstream ST sink
     src_out     => src_out
@@ -355,7 +412,7 @@ BEGIN
   END GENERATE;
 
   -- These FIFOs are flow controlled by the dp_mux stage
-  dp_fifo_sc_src_in_2arr_4 <= dp_mux_safe_snk_out_2arr_4;
+--  dp_fifo_sc_src_in_2arr_4 <= dp_mux_safe_snk_out_2arr_4;
 
   -----------------------------------------------------------------------------
   -- Add 6250 byte SOP,EOP to provide multiplexing boundaries for dp_mux
@@ -385,7 +442,7 @@ BEGIN
 --  END GENERATE;
 
   -- These dp_block_gens are flow controlled by the dp_mux stage
-  dp_block_gen_src_in_2arr_4 <= dp_mux_safe_snk_out_2arr_4;
+--  dp_block_gen_src_in_2arr_4 <= dp_mux_safe_snk_out_2arr_4;
 
   -----------------------------------------------------------------------------
   -- FIXME - Workaround for issue with dp_block_gen

applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4_output.vhd

@@ -52,7 +52,7 @@ ARCHITECTURE tb OF tb_arts_unb1_sc4_output IS
   -- Clocks & reset, general setup
   ----------------------------------------------------------------------------
   CONSTANT c_sim                       : BOOLEAN := TRUE;
-  CONSTANT c_nof_tabs                  : NATURAL := 1;
+  CONSTANT c_nof_tabs                  : NATURAL := 2;
   CONSTANT c_nof_compound_beams        : NATURAL := 1;
   CONSTANT c_nof_bytes_per_iquv_packet : NATURAL := 8500;
   CONSTANT c_nof_bytes_per_i_packet    : NATURAL := 6250;
@@ -170,7 +170,7 @@ BEGIN
     reg_dp_xonoff_iab_i_mosi.wr      <= '0';
   END PROCESS;
 
-  arts_unb1_sc4_output_tab_snk_in_arr(0) <= arts_unb1_sc4_output_iab_snk_in;
+  arts_unb1_sc4_output_tab_snk_in_arr <= (others => arts_unb1_sc4_output_iab_snk_in);
 
   ------------------------------------------------------------------------------
   -- The DUT - ARTS SC4 output module