diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_iab_i_reorder.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_iab_i_reorder.vhd index fe69128d4ad631927c89ba47172b25a100853ca6..91b2e227e3c2edea9e7c73888122ba79e61cba31 100644 --- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_iab_i_reorder.vhd +++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_iab_i_reorder.vhd @@ -77,6 +77,8 @@ ARCHITECTURE str OF arts_unb1_sc4_output_iab_i_reorder IS SIGNAL dp_fifo_sc_snk_in_arr : t_dp_sosi_arr(g_nof_frequency_channels-1 DOWNTO 0); SIGNAL dp_fifo_sc_src_out_arr : t_dp_sosi_arr(0 TO g_nof_frequency_channels-1); SIGNAL dp_fifo_sc_src_in_arr : t_dp_siso_arr(0 TO g_nof_frequency_channels-1) := (others => c_dp_siso_rst); + SIGNAL dp_pipeline_ready_src_out_arr : t_dp_sosi_arr(0 TO g_nof_frequency_channels-1); + SIGNAL dp_pipeline_ready_src_in_arr : t_dp_siso_arr(0 TO g_nof_frequency_channels-1) := (others => c_dp_siso_rst); SIGNAL dp_mux_src_in : t_dp_siso := c_dp_siso_rst; SIGNAL end_of_packet_delayed : STD_LOGIC := '0'; SIGNAL end_of_packet_latched : STD_LOGIC := '0'; @@ -110,6 +112,7 @@ BEGIN ----------------------------------------------------------------------------- -- Feed each channel stream into a dp_fifo_sc + -- The pipeline_ready module is needed to alleviate timing errors ----------------------------------------------------------------------------- gen_fifos : FOR i in 0 TO g_nof_frequency_channels-1 GENERATE u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc @@ -129,6 +132,19 @@ BEGIN src_in => dp_fifo_sc_src_in_arr(i), src_out => dp_fifo_sc_src_out_arr(i) ); + + u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready + PORT MAP( + rst => dp_rst, + clk => dp_clk, + + snk_in => dp_fifo_sc_src_out_arr(i), + snk_out => dp_fifo_sc_src_in_arr(i), + + src_in => dp_pipeline_ready_src_in_arr(i), + src_out => dp_pipeline_ready_src_out_arr(i) + ); + END GENERATE; @@ -148,8 +164,8 @@ BEGIN rst => dp_rst, clk => dp_clk, -- ST sinks - snk_out_arr => dp_fifo_sc_src_in_arr, -- OUT = request to upstream ST source - snk_in_arr => dp_fifo_sc_src_out_arr, + snk_out_arr => dp_pipeline_ready_src_in_arr, -- OUT = request to upstream ST source + snk_in_arr => dp_pipeline_ready_src_out_arr, -- ST source src_in => dp_mux_src_in, -- IN = request from downstream ST sink src_out => src_out diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd index 5fb2a60f7825d8c61a1c08dfee42770fa84c9de1..5320cbdd27a52ea0f794ceff400355b1006dfee5 100644 --- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd +++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_packetizer.vhd @@ -102,14 +102,21 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS TO_UVEC( 0, c_diag_bg_bsn_init_w)); ------------------------------------------------------------------------------- - -- dp_offload_tx + -- Data flow ------------------------------------------------------------------------------- - CONSTANT c_nof_words_per_block : NATURAL := 6250; - CONSTANT c_nof_blocks_per_packet : NATURAL := 1; - - CONSTANT c_nof_hdr_fields : NATURAL := 3 + 12 + 4 + 7 + 8; - CONSTANT c_hdr_field_sel : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "101"&"111111111101"&"1111"&"1100010"&"11111111"; - + CONSTANT c_data_w : NATURAL := 64; + CONSTANT c_empty_w : NATURAL := ceil_log2(c_data_w /c_byte_w); + CONSTANT c_nof_words_per_packet : NATURAL := ceil_div(g_nof_bytes_per_packet, 8); --781.25 The .25 should be indicated by an extra word with empty = 6 + CONSTANT c_nof_words_per_block : NATURAL := 6250; + CONSTANT c_nof_blocks_per_packet : NATURAL := 1; + CONSTANT c_nof_offloadstreams : NATURAL := 5; + CONSTANT c_udp_dst_prt_base : NATURAL := 5000; + CONSTANT c_nof_bytes_per_header : NATURAL := 94; + CONSTANT c_fifo_fill_fill : NATURAL := ceil_div((g_nof_bytes_per_packet + c_nof_bytes_per_header), 8); + CONSTANT c_fifo_fill_size : NATURAL := 1024; + + CONSTANT c_nof_hdr_fields : NATURAL := 1 + 3 + 12 + 4 + 9 + 8; + CONSTANT c_hdr_field_sel : STD_LOGIC_VECTOR(c_nof_hdr_fields-1 DOWNTO 0) := "1" & "101"&"111111111101"&"1011"&"110101001"&"11111111"; -- Make field 'udp_dst_port' an input -- Notes: -- . pre-calculated ip_header_checksum is valid only for UNB0, FN0 targeting IP 10.10.10.10 -- . udp_total_length = 6250B + 24 flag bytes + 16 ID bytes + 8 UDP bytes = B @@ -117,32 +124,36 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS -- . channel = 0 : sb0/ch0,1,2,3 -- . channel = 4 : sb1/ch0,1,2,3 -- . etc. - CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"F452147062F0") ), + + CONSTANT c_hdr_field_arr : t_common_field_arr(c_nof_hdr_fields-1 DOWNTO 0) := ( ( field_name_pad("word_align" ), "RW", 16, field_default(0) ), + ( field_name_pad("eth_dst_mac" ), "RW", 48, field_default(x"7cfe90927c30") ), ( field_name_pad("eth_src_mac" ), "RW", 48, field_default(0) ), ( field_name_pad("eth_type" ), "RW", 16, field_default(x"0800") ), ( field_name_pad("ip_version" ), "RW", 4, field_default(4) ), ( field_name_pad("ip_header_length" ), "RW", 4, field_default(5) ), ( field_name_pad("ip_services" ), "RW", 8, field_default(0) ), - ( field_name_pad("ip_total_length" ), "RW", 16, field_default(6318) ), + ( field_name_pad("ip_total_length" ), "RW", 16, field_default(6326) ), ( field_name_pad("ip_identification" ), "RW", 16, field_default(0) ), ( field_name_pad("ip_flags" ), "RW", 3, field_default(2) ), ( field_name_pad("ip_fragment_offset" ), "RW", 13, field_default(0) ), ( field_name_pad("ip_time_to_live" ), "RW", 8, field_default(127) ), ( field_name_pad("ip_protocol" ), "RW", 8, field_default(17) ), - ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(62104) ), + ( field_name_pad("ip_header_checksum" ), "RW", 16, field_default(0) ), ( field_name_pad("ip_src_addr" ), "RW", 32, field_default(0) ), - ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"0A63D201") ), - ( field_name_pad("udp_src_port" ), "RW", 16, field_default(0) ), - ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(0) ), - ( field_name_pad("udp_total_length" ), "RW", 16, field_default(6298) ), + ( field_name_pad("ip_dst_addr" ), "RW", 32, field_default(x"0A63C801") ), + ( field_name_pad("udp_src_port" ), "RW", 16, field_default(4000) ), + ( field_name_pad("udp_dst_port" ), "RW", 16, field_default(4000) ), + ( field_name_pad("udp_total_length" ), "RW", 16, field_default(6306) ), ( field_name_pad("udp_checksum" ), "RW", 16, field_default(0) ), - ( field_name_pad("id_marker_byte" ), "RW", 8, field_default(65) ), - ( field_name_pad("id_format_version" ), "RW", 8, field_default(0) ), + ( field_name_pad("id_marker_byte" ), "RW", 8, field_default(x"E2") ), + ( field_name_pad("id_format_version" ), "RW", 8, field_default(1) ), ( field_name_pad("id_cb_index" ), "RW", 8, field_default(0) ), ( field_name_pad("id_tab_index" ), "RW", 8, field_default(0) ), ( field_name_pad("id_channel_index" ), "RW", 16, field_default(0) ), - ( field_name_pad("id_nof_samples_per_packet" ), "RW", 16, field_default(0) ), + ( field_name_pad("id_application_payload_size" ), "RW", 16, field_default(6250) ), ( field_name_pad("id_timestamp" ), "RW", 64, field_default(0) ), + ( field_name_pad("id_sequence_number" ), "RW", 8, field_default(0) ), + ( field_name_pad("id_reserved" ), "RW", 72, field_default(0) ), ( field_name_pad("flags_crc_error" ), "RW", 24, field_default(0) ), ( field_name_pad("flags_no_input_present" ), "RW", 24, field_default(0) ), ( field_name_pad("flags_uploading_weights" ), "RW", 24, field_default(0) ), @@ -152,7 +163,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS ( field_name_pad("flags_reserved_0" ), "RW", 24, field_default(0) ), ( field_name_pad("flags_reserved_1" ), "RW", 24, field_default(0) ) ); - SIGNAL hdr_fields_in_arr : t_slv_1024_arr(1-1 DOWNTO 0); + SIGNAL hdr_fields_in_arr : t_slv_1024_arr(c_nof_offloadstreams-1 DOWNTO 0); SIGNAL id_backplane : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0); SIGNAL id_chip : STD_LOGIC_VECTOR(c_byte_w-1 DOWNTO 0); @@ -161,6 +172,7 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS SIGNAL id_cb : STD_LOGIC_VECTOR( c_byte_w-1 DOWNTO 0); SIGNAL id_sequence_number : STD_LOGIC_VECTOR( c_byte_w-1 DOWNTO 0); SIGNAL id_local_channel : STD_LOGIC_VECTOR(6 DOWNTO 0); + SIGNAL id_udp_dst_prt : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL id_cb_offset : NATURAL := 0; SIGNAL id_channel_offset : NATURAL := 0; @@ -187,10 +199,14 @@ ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_packetizer IS SIGNAL arts_unb1_sc4_output_i_framer_src_out : t_dp_sosi; - SIGNAL dp_fifo_fill_sc_src_out : t_dp_sosi; - SIGNAL dp_fifo_fill_sc_src_in : t_dp_siso; - SIGNAL dp_offload_tx_src_out : t_dp_sosi; - SIGNAL dp_offload_tx_src_in : t_dp_siso; + SIGNAL dp_fifo_fill_sc_src_out : t_dp_sosi; + SIGNAL dp_fifo_fill_sc_src_in : t_dp_siso; + SIGNAL dp_demux_inverted_src_out_arr : t_dp_sosi_arr(0 TO c_nof_offloadstreams-1); + SIGNAL dp_demux_inverted_src_in_arr : t_dp_siso_arr(0 TO c_nof_offloadstreams-1); + SIGNAL dp_field_blk_src_out_arr : t_dp_sosi_arr(c_nof_offloadstreams-1 DOWNTO 0); + SIGNAL dp_field_blk_src_in_arr : t_dp_siso_arr(c_nof_offloadstreams-1 DOWNTO 0); +-- SIGNAL dp_mux_src_out : t_dp_sosi; +-- SIGNAL dp_mux_src_in : t_dp_siso; BEGIN @@ -251,7 +267,8 @@ BEGIN -- ); -- ----------------------------------------------------------------------------- - -- dp_counter creates CB,SB,CH,T indices for the IAB stream: + -- dp_counter creates CB,SB,CH,T indices for the stream headers. The counts are + -- . determined by the order in which the fifos are read out -- . [CBxSB 0..87(119)][SEQ 0..3][TAB 0..11][CH 0..3][t 0..6249] -- . c0 = range(0,g_nof_bytes_per_packet,1) t -- . c1 = range(0,4,1) CH @@ -263,7 +280,7 @@ BEGIN GENERIC MAP ( g_nof_counters => 5, -- c3,c2,c1, c0 g_range_start => (0,0,0,0, 0, 0, 0, 0, 0, 0), - g_range_stop => (0,0,0,0, 0, 88, 4, g_nof_tabs, 4, g_nof_bytes_per_packet), + g_range_stop => (0,0,0,0, 0, 88, 4, g_nof_tabs, 4, c_nof_words_per_packet), g_range_step => (0,0,0,0, 0, 1, 1, 1, 1, 1) ) PORT MAP ( @@ -401,49 +418,44 @@ BEGIN dp_rst => dp_rst, dp_clk => dp_clk, - snk_out_arr(0) => dp_xonoff_snk_out, - snk_in_arr(0) => dp_xonoff_snk_in, + snk_out_arr(0) => dp_xonoff_snk_out, + snk_in_arr(0) => dp_xonoff_snk_in, - src_in_arr => (OTHERS => c_dp_siso_rdy), + src_in_arr(0) => dp_xonoff_src_in, src_out_arr(0) => dp_xonoff_src_out ); + ----------------------------------------------------------------------------- - -- Fill FIFO to buffer 8000 Bytes + -- Distribute the packets to the five concat blocks ----------------------------------------------------------------------------- - u_dp_fifo_fill_sc : ENTITY dp_lib.dp_fifo_fill_sc + u_dp_demux : ENTITY dp_lib.dp_demux GENERIC MAP ( - g_use_bsn => TRUE, - g_bsn_w => 16, -- Enough to see 25k timesamples - g_data_w => 8, - g_use_sync => TRUE, - g_use_channel => TRUE, - g_channel_w => 32, - g_use_complex => FALSE, - g_fifo_fill => 6250, - g_fifo_size => 7000 + g_mode => 1, -- Use EOP to select next input + g_combined => FALSE, -- Only the current channel needs to be ready + g_nof_output => c_nof_offloadstreams, + g_remove_channel_lo => FALSE ) PORT MAP ( - rst => dp_rst, clk => dp_clk, + rst => dp_rst, - snk_in => dp_xonoff_src_out, - src_in => dp_fifo_fill_sc_src_in, - src_out => dp_fifo_fill_sc_src_out + snk_in => dp_xonoff_src_out, + snk_out => dp_xonoff_src_in, + + src_out_arr => dp_demux_inverted_src_out_arr, -- output: 5 streams (0 TO 4) + src_in_arr => dp_demux_inverted_src_in_arr -- backpressure input: 5 streams (0 TO 4) ); ----------------------------------------------------------------------------- - -- Header insertion (dp_offload_tx) + -- Header insertion ----------------------------------------------------------------------------- - u_dp_offload_tx : ENTITY dp_lib.dp_offload_tx + u_dp_concat_field_blk : ENTITY dp_lib.dp_concat_field_blk GENERIC MAP ( - g_nof_streams => 1, - g_data_w => 8, - g_use_complex => FALSE, - g_nof_words_per_block => c_nof_words_per_block, - g_nof_blocks_per_packet => c_nof_blocks_per_packet, - g_hdr_field_arr => c_hdr_field_arr, - g_hdr_field_sel => c_hdr_field_sel + g_nof_streams => c_nof_offloadstreams, + g_data_w => c_data_w, + g_hdr_field_arr => c_hdr_field_arr, + g_hdr_field_sel => c_hdr_field_sel ) PORT MAP ( mm_rst => mm_rst, @@ -455,11 +467,11 @@ BEGIN reg_hdr_dat_mosi => reg_dp_offload_tx_hdr_dat_mosi, reg_hdr_dat_miso => reg_dp_offload_tx_hdr_dat_miso, - snk_in_arr(0) => dp_fifo_fill_sc_src_out, - snk_out_arr(0) => dp_fifo_fill_sc_src_in, + snk_in_arr => dp_demux_inverted_src_out_arr, + snk_out_arr => dp_demux_inverted_src_in_arr, - src_out_arr(0) => dp_offload_tx_src_out, - src_in_arr(0) => dp_offload_tx_src_in, + src_out_arr => dp_field_blk_src_out_arr, + src_in_arr => dp_field_blk_src_in_arr, hdr_fields_in_arr => hdr_fields_in_arr ); @@ -469,41 +481,90 @@ BEGIN --------------------------------------------------------------------------------------- id_backplane <= RESIZE_UVEC(ID(7 DOWNTO 3), c_byte_w); id_chip <= RESIZE_UVEC(ID(2 DOWNTO 0), c_byte_w); + id_band <= RESIZE_UVEC(ID(6 DOWNTO 3), c_byte_w); --------------------------------------------------------------------------------------- - -- Wire the hardwired header fields to DP signals and ID + -- Look up tables for the node dependent offsets for various header fields + -- The CB increments by 5 per node + -- The Channel increments by 96 per board --------------------------------------------------------------------------------------- - hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac" )) <= x"00228608" & id_backplane & INCR_UVEC(id_chip, 8); - hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000, 16); - hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "udp_dst_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= TO_UVEC(4000, 16); - hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr" )) <= x"0A63" & id_backplane & INCR_UVEC(id_chip, 9); - - hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "id_timestamp" ) DOWNTO field_lo(c_hdr_field_arr, "id_timestamp" )) <= dp_fifo_fill_sc_src_out.bsn(63 DOWNTO 0); - hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "id_channel_index") DOWNTO field_lo(c_hdr_field_arr, "id_channel_index")) <= SHIFT_UVEC(dp_fifo_fill_sc_src_out.channel(15 DOWNTO 0), -4); --Subband index - hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "id_cb_index" ) DOWNTO field_lo(c_hdr_field_arr, "id_cb_index" )) <= dp_fifo_fill_sc_src_out.channel(23 DOWNTO 16); - hdr_fields_in_arr(0)(field_hi(c_hdr_field_arr, "id_tab_index" ) DOWNTO field_lo(c_hdr_field_arr, "id_tab_index" )) <= dp_fifo_fill_sc_src_out.channel(31 DOWNTO 24); + id_cb_offset <= sel_n(TO_UINT(id_chip) , 0, 5, 10, 15, 20, 25, 30, 35); + -- TODO: See if there is a more elegant way to do this + id_channel_offset <= sel_n(TO_UINT(id_band(2 DOWNTO 0)) , 0, 96, 192, 288, 384, 480, 576, 672) + sel_a_b(TO_UINT(id_band(3 DOWNTO 3)), 768, 0); + + -- Combine local channel index 0..95 with the UniBoard/band ID 0..15 to get global channels 0..1535. + id_channel <= TO_UVEC(id_channel_offset + TO_UINT(dp_xonoff_src_out.channel(8 DOWNTO 2)), 16); + -- Combine local CB index 0..4 with the FPGA ID 0..7 to get global CB indices 0..39. + id_cb <= TO_UVEC(id_cb_offset + TO_UINT(dp_xonoff_src_out.channel(11 DOWNTO 9)), 8); + -- The sequence number 0..3 + id_sequence_number <= RESIZE_UVEC(dp_xonoff_src_out.channel(1 DOWNTO 0), c_byte_w); + id_udp_dst_prt <= TO_UVEC(c_udp_dst_prt_base + TO_UINT(id_cb), 16); --------------------------------------------------------------------------------------- - -- Repack to 64b + -- Wire the hardwired header fields to DP signals and ID --------------------------------------------------------------------------------------- - u_dp_repack_data : ENTITY dp_lib.dp_repack_data + gen_wire_headers : FOR i IN 0 TO c_nof_offloadstreams-1 GENERATE + hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "eth_src_mac" ) DOWNTO field_lo(c_hdr_field_arr, "eth_src_mac" )) <= x"00228608" & id_backplane & id_chip; + hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "ip_src_addr" ) DOWNTO field_lo(c_hdr_field_arr, "ip_src_addr" )) <= x"0A63" & id_backplane & INCR_UVEC(id_chip, 1); + hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_src_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_src_port" )) <= TO_UVEC(4000, 16); + hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "udp_dst_port" ) DOWNTO field_lo(c_hdr_field_arr, "udp_dst_port" )) <= id_udp_dst_prt; + + hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_timestamp" ) DOWNTO field_lo(c_hdr_field_arr, "id_timestamp" )) <= general_bsn_latched(63 DOWNTO 0); + hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_channel_index" ) DOWNTO field_lo(c_hdr_field_arr, "id_channel_index" )) <= id_channel; + hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_cb_index" ) DOWNTO field_lo(c_hdr_field_arr, "id_cb_index" )) <= id_cb; + hdr_fields_in_arr(i)(field_hi(c_hdr_field_arr, "id_sequence_number") DOWNTO field_lo(c_hdr_field_arr, "id_sequence_number")) <= id_sequence_number; + END GENERATE; + + ----------------------------------------------------------------------------- + -- dp_mux the 5 streams into a single stream again + ----------------------------------------------------------------------------- + u_mux : ENTITY dp_lib.dp_mux GENERIC MAP ( - g_in_dat_w => 8, - g_in_nof_words => 8, --- g_in_symbol_w => 8, - g_out_dat_w => 64, - g_out_nof_words => 1 --- g_out_symbol_w => 8 + g_data_w => c_data_w, + g_empty_w => c_empty_w, + g_use_empty => TRUE, + g_error_w => 1, + g_mode => 1, -- forced round robin mode + g_nof_input => c_nof_offloadstreams, + g_fifo_size => array_init(1024, c_nof_offloadstreams), -- FIFO is not used, but generic must match g_nof_input + g_fifo_fill => array_init(0, c_nof_offloadstreams) -- FIFO is not used, but generic must match g_nof_input ) PORT MAP ( - clk => dp_clk, - rst => dp_rst, - - snk_in => dp_offload_tx_src_out, - snk_out => dp_offload_tx_src_in, - - src_out => src_out, - src_in => src_in + rst => dp_rst, + clk => dp_clk, + -- ST sinks + snk_out_arr => dp_field_blk_src_in_arr, + snk_in_arr => dp_field_blk_src_out_arr, + -- ST source + src_in => dp_fifo_fill_sc_src_in, + src_out => dp_fifo_fill_sc_src_out + ); + + ----------------------------------------------------------------------------- + -- Fill FIFO to buffer 8000 Bytes + ----------------------------------------------------------------------------- + u_dp_fifo_fill_sc : ENTITY dp_lib.dp_fifo_fill_sc + GENERIC MAP ( + g_use_bsn => TRUE, + g_bsn_w => 16, -- Enough to see 25k timesamples + g_data_w => c_data_w, + g_empty_w => c_empty_w, + g_use_empty => TRUE, + g_use_sync => TRUE, + g_use_channel => TRUE, + g_channel_w => 32, + g_use_complex => FALSE, + g_fifo_fill => c_fifo_fill_fill, + g_fifo_size => c_fifo_fill_size + ) + PORT MAP ( + rst => dp_rst, + clk => dp_clk, + + snk_out => dp_fifo_fill_sc_src_in, + snk_in => dp_fifo_fill_sc_src_out, + src_in => src_in, + src_out => src_out ); diff --git a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd index 19cec82339621c27f2d8020e6b90a5a433198b0d..013f12a994cdbedbc9f6b78e588572c2de0e540b 100644 --- a/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd +++ b/applications/arts/designs/arts_unb1_sc4/src/vhdl/arts_unb1_sc4_output_tab_i_reorder.vhd @@ -49,7 +49,7 @@ ENTITY arts_unb1_sc4_output_tab_i_reorder IS dp_rst : IN STD_LOGIC; dp_clk : IN STD_LOGIC; - snk_in_arr : IN t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); -- 12 TAB streams + snk_in_arr : IN t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0) := (OTHERS => c_dp_sosi_rst); -- 12 TAB streams src_out : OUT t_dp_sosi; src_in : IN t_dp_siso @@ -59,47 +59,53 @@ END arts_unb1_sc4_output_tab_i_reorder; ARCHITECTURE str OF arts_unb1_sc4_output_tab_i_reorder IS - CONSTANT c_data_w : NATURAL := c_byte_w; + CONSTANT c_indata_w : NATURAL := c_byte_w; + CONSTANT c_data_w : NATURAL := c_indata_w * 8; + CONSTANT c_empty_w : NATURAL := ceil_log2(c_data_w /c_byte_w); CONSTANT c_nof_fifos : NATURAL := g_nof_tabs * g_nof_frequency_channels; CONSTANT c_nof_words_per_packet : NATURAL := g_nof_bytes_per_packet/(c_data_w/c_byte_w); - CONSTANT c_dp_fifo_sc_size : NATURAL := 8192; --c_nof_words_per_packet; 6250 not enough? + CONSTANT c_dp_fifo_sc_size : NATURAL := 1024; --8192/8; CONSTANT c_dp_channel_w : NATURAL := 4*c_byte_w; --4 bytes: TAB, CB, Subband, Channel index. SIGNAL dp_deinterleave_snk_in_arr : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); + SIGNAL dp_deinterleave_src_out_arr : t_dp_sosi_arr(g_nof_tabs*g_nof_frequency_channels-1 DOWNTO 0); + SIGNAL dp_repack_snk_in_arr : t_dp_sosi_arr(g_nof_tabs*g_nof_frequency_channels-1 DOWNTO 0); SIGNAL dp_fifo_sc_snk_in_arr : t_dp_sosi_arr(g_nof_tabs*g_nof_frequency_channels-1 DOWNTO 0); SIGNAL dp_fifo_sc_src_out_arr : t_dp_sosi_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1); SIGNAL dp_fifo_sc_src_in_arr : t_dp_siso_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1); + SIGNAL dp_pipeline_ready_src_out_arr : t_dp_sosi_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1); + SIGNAL dp_pipeline_ready_src_in_arr : t_dp_siso_arr(0 TO g_nof_tabs*g_nof_frequency_channels-1); SIGNAL dp_counter_count_src_out_arr : t_dp_sosi_arr(1 DOWNTO 0); SIGNAL dp_mux_src_in : t_dp_siso; SIGNAL end_of_packet : STD_LOGIC; SIGNAL end_of_packet_latched : STD_LOGIC; - SIGNAL dp_demux_snk_in_arr : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); - SIGNAL dp_demux_inverted_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); - SIGNAL dp_demux_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); - SIGNAL dp_fifo_sc_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); - SIGNAL dp_fifo_sc_src_in_2arr_4 : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_demux_snk_in_arr : t_dp_sosi_arr(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_demux_inverted_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_demux_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_fifo_sc_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_fifo_sc_src_in_2arr_4 : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0); - TYPE t_dp_fifo_sc_usedw_arr IS ARRAY(g_nof_frequency_channels-1 DOWNTO 0) OF STD_LOGIC_VECTOR(ceil_log2(c_dp_fifo_sc_size)-1 DOWNTO 0); - TYPE t_dp_fifo_sc_usedw_2arr_4 IS ARRAY(g_nof_tabs-1 DOWNTO 0) OF t_dp_fifo_sc_usedw_arr; - SIGNAL dp_fifo_sc_usedw_2arr_4 : t_dp_fifo_sc_usedw_2arr_4; +-- TYPE t_dp_fifo_sc_usedw_arr IS ARRAY(g_nof_frequency_channels-1 DOWNTO 0) OF STD_LOGIC_VECTOR(ceil_log2(c_dp_fifo_sc_size)-1 DOWNTO 0); +-- TYPE t_dp_fifo_sc_usedw_2arr_4 IS ARRAY(g_nof_tabs-1 DOWNTO 0) OF t_dp_fifo_sc_usedw_arr; +-- SIGNAL dp_fifo_sc_usedw_2arr_4 : t_dp_fifo_sc_usedw_2arr_4; - SIGNAL dp_block_gen_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); - SIGNAL dp_block_gen_src_in_2arr_4 : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_block_gen_src_out_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_block_gen_src_in_2arr_4 : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0); -- dp_mux inputs; 12*4 - SIGNAL dp_mux_snk_in_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); - SIGNAL dp_mux_snk_out_2arr_4 : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0); - SIGNAL dp_mux_safe_snk_out_2arr_4 : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_mux_snk_in_2arr_4 : t_dp_sosi_2arr_4(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_mux_snk_out_2arr_4 : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0); +-- SIGNAL dp_mux_safe_snk_out_2arr_4 : t_dp_siso_2arr_4(g_nof_tabs-1 DOWNTO 0); -- dp_mux inputs; 4*12 - SIGNAL dp_mux_snk_in_2arr_12 : t_dp_sosi_2arr_12(g_nof_frequency_channels-1 DOWNTO 0); - SIGNAL dp_mux_reversed_snk_in_2arr_12 : t_dp_sosi_2arr_12(g_nof_frequency_channels-1 DOWNTO 0); - SIGNAL dp_mux_snk_out_2arr_12 : t_dp_siso_2arr_12(g_nof_frequency_channels-1 DOWNTO 0); +-- SIGNAL dp_mux_snk_in_2arr_12 : t_dp_sosi_2arr_12(g_nof_frequency_channels-1 DOWNTO 0); +-- SIGNAL dp_mux_reversed_snk_in_2arr_12 : t_dp_sosi_2arr_12(g_nof_frequency_channels-1 DOWNTO 0); +-- SIGNAL dp_mux_snk_out_2arr_12 : t_dp_siso_2arr_12(g_nof_frequency_channels-1 DOWNTO 0); -- dp_mux outputs; 12 - SIGNAL dp_mux_src_out_arr : t_dp_sosi_arr(g_nof_frequency_channels-1 DOWNTO 0); - SIGNAL dp_mux_src_in_arr : t_dp_siso_arr(g_nof_frequency_channels-1 DOWNTO 0); +-- SIGNAL dp_mux_src_out_arr : t_dp_sosi_arr(g_nof_frequency_channels-1 DOWNTO 0); +-- SIGNAL dp_mux_src_in_arr : t_dp_siso_arr(g_nof_frequency_channels-1 DOWNTO 0); BEGIN @@ -153,6 +159,9 @@ BEGIN gen_reordering_fifos : FOR tabno IN 0 TO g_nof_tabs-1 GENERATE + dp_deinterleave_snk_in_arr(tabno).empty <= (others => '0'); + dp_deinterleave_snk_in_arr(tabno).err <= (others => '0'); + ----------------------------------------------------------------------------- -- Deinterleave snk_in into 4 (channel) substreams -- . Set the output block size to 6250 @@ -162,7 +171,7 @@ BEGIN g_nof_out => g_nof_frequency_channels, g_block_size_int => 1, g_block_size_output => g_nof_bytes_per_packet, - g_dat_w => c_data_w, + g_dat_w => c_indata_w, g_use_sync_bsn => TRUE, g_use_ctrl => TRUE, g_use_complex => FALSE @@ -172,16 +181,49 @@ BEGIN clk => dp_clk, snk_in => dp_deinterleave_snk_in_arr(tabno), - src_out_arr => dp_fifo_sc_snk_in_arr(tabno*g_nof_frequency_channels + g_nof_frequency_channels-1 DOWNTO tabno*g_nof_frequency_channels) + src_out_arr => dp_deinterleave_src_out_arr(tabno*g_nof_frequency_channels + g_nof_frequency_channels-1 DOWNTO tabno*g_nof_frequency_channels) ); ----------------------------------------------------------------------------- -- Feed each channel stream into a dp_fifo_sc + -- The empty fields of the incoming data are cleared + -- The data are repacked to 64bit first to speed up data transfer from the FIFOs to the 10GbE port + -- The pipeline_ready module is needed to alleviate timing errors ----------------------------------------------------------------------------- gen_fifos : FOR i in 0 TO g_nof_frequency_channels-1 GENERATE + + p_overide_empty : PROCESS(dp_deinterleave_src_out_arr(tabno*g_nof_frequency_channels + i)) + BEGIN + dp_repack_snk_in_arr(tabno*g_nof_frequency_channels + i) <= dp_deinterleave_src_out_arr(tabno*g_nof_frequency_channels + i); + dp_repack_snk_in_arr(tabno*g_nof_frequency_channels + i).empty <= (OTHERS => '0'); + END PROCESS; + + + u_dp_repack_data : ENTITY dp_lib.dp_repack_data + GENERIC MAP ( + g_in_dat_w => c_indata_w, -- 8 + g_in_nof_words => 8, + g_in_symbol_w => 8, + g_out_dat_w => c_data_w, -- 64 + g_out_nof_words => 1, + g_out_symbol_w => 8 + ) + PORT MAP ( + clk => dp_clk, + rst => dp_rst, + + snk_in => dp_repack_snk_in_arr(tabno*g_nof_frequency_channels + i), +-- snk_out => dp_mux_src_in, + + src_out => dp_fifo_sc_snk_in_arr(tabno*g_nof_frequency_channels + i), + src_in => c_dp_siso_rdy + ); + u_dp_fifo_sc : ENTITY dp_lib.dp_fifo_sc GENERIC MAP ( g_data_w => c_data_w, + g_empty_w => c_empty_w, + g_use_empty => TRUE, g_use_ctrl => TRUE, g_use_bsn => FALSE, g_use_channel => FALSE, @@ -196,6 +238,19 @@ BEGIN src_in => dp_fifo_sc_src_in_arr(tabno*g_nof_frequency_channels + i), src_out => dp_fifo_sc_src_out_arr(tabno*g_nof_frequency_channels + i) ); + + u_dp_pipeline_ready : ENTITY dp_lib.dp_pipeline_ready + PORT MAP( + rst => dp_rst, + clk => dp_clk, + + snk_in => dp_fifo_sc_src_out_arr(tabno*g_nof_frequency_channels + i), + snk_out => dp_fifo_sc_src_in_arr(tabno*g_nof_frequency_channels + i), + + src_in => dp_pipeline_ready_src_in_arr(tabno*g_nof_frequency_channels + i), + src_out => dp_pipeline_ready_src_out_arr(tabno*g_nof_frequency_channels + i) + ); + END GENERATE; END GENERATE; @@ -205,6 +260,8 @@ BEGIN u_mux : ENTITY dp_lib.dp_mux GENERIC MAP ( g_data_w => c_data_w, + g_empty_w => c_empty_w, + g_use_empty => TRUE, g_error_w => 1, g_mode => 1, -- forced round robin mode g_nof_input => g_nof_tabs * g_nof_frequency_channels, @@ -215,8 +272,8 @@ BEGIN rst => dp_rst, clk => dp_clk, -- ST sinks - snk_out_arr => dp_fifo_sc_src_in_arr, -- OUT = request to upstream ST source - snk_in_arr => dp_fifo_sc_src_out_arr, + snk_out_arr => dp_pipeline_ready_src_in_arr, -- OUT = request to upstream ST source + snk_in_arr => dp_pipeline_ready_src_out_arr, -- ST source src_in => dp_mux_src_in, -- IN = request from downstream ST sink src_out => src_out @@ -355,7 +412,7 @@ BEGIN END GENERATE; -- These FIFOs are flow controlled by the dp_mux stage - dp_fifo_sc_src_in_2arr_4 <= dp_mux_safe_snk_out_2arr_4; +-- dp_fifo_sc_src_in_2arr_4 <= dp_mux_safe_snk_out_2arr_4; ----------------------------------------------------------------------------- -- Add 6250 byte SOP,EOP to provide multiplexing boundaries for dp_mux @@ -385,7 +442,7 @@ BEGIN -- END GENERATE; -- These dp_block_gens are flow controlled by the dp_mux stage - dp_block_gen_src_in_2arr_4 <= dp_mux_safe_snk_out_2arr_4; +-- dp_block_gen_src_in_2arr_4 <= dp_mux_safe_snk_out_2arr_4; ----------------------------------------------------------------------------- -- FIXME - Workaround for issue with dp_block_gen diff --git a/applications/arts/designs/arts_unb1_sc4/tb/data/wave_output.do b/applications/arts/designs/arts_unb1_sc4/tb/data/wave_output.do index add072934316e7b1ed47285563efb236725ac95f..cb3b5fe09e79ded28222fdb1dec731cb89e322d8 100644 --- a/applications/arts/designs/arts_unb1_sc4/tb/data/wave_output.do +++ b/applications/arts/designs/arts_unb1_sc4/tb/data/wave_output.do @@ -65,6 +65,8 @@ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_snk_in_arr add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(0).err {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr(3) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_out_arr add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_in_arr(0) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_in_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_in_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_in_arr(3) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_fifo_sc_src_in_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(0).err {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr(3) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_out_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_in_arr(0) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_in_arr(0).ready {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_in_arr(0).xon {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_in_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_in_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_in_arr(3) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_pipeline_ready_src_in_arr add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_mux_src_in.ready {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_mux_src_in.xon {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/dp_mux_src_in add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/stagger_endcount add wave -noupdate -height 15 -radix unsigned /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_reorder/pulse_delay @@ -101,10 +103,12 @@ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/id_backplane add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/id_chip add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/id_band +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/id_channel_offset add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/id_channel add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/id_cb_offset add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/id_cb add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/id_sequence_number +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/id_udp_dst_prt add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/mms_diag_block_gen_src_out add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/mms_diag_block_gen_src_in add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_fifo_sc_snk_in @@ -113,7 +117,7 @@ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_snk_out add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_src_out add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_src_in -add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(3).err {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(2).err {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(1).err {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr(0).err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_count_src_out_arr add wave -noupdate -height 15 -radix unsigned /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_src_out_cb add wave -noupdate -height 15 -radix unsigned /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_src_out_sb add wave -noupdate -height 15 -radix unsigned /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_counter_src_out_seq @@ -123,10 +127,10 @@ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_snk_in add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_snk_out add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out.err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_out -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_in +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_in.ready {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_in.xon {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_xonoff_src_in add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_field_blk_src_out add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_field_blk_src_in -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out.err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_out add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_iab/u_arts_unb1_sc4_output_iab_i_packetizer/dp_repack_data_src_in add wave -noupdate -divider TABS add wave -noupdate -divider output_tab @@ -165,20 +169,20 @@ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/g_nof_bytes_per_packet add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_rst add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_clk -add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0).err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr(0) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/snk_in_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out.err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_out add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/src_in -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_deinterleave_snk_in_arr -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr -add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3).err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr -add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_in_arr(0) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_in_arr(0).ready {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_in_arr(0).xon {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_in_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_in_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_in_arr(3) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_in_arr -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_counter_count_src_out_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_deinterleave_snk_in_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_deinterleave_snk_in_arr(0) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_deinterleave_snk_in_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(7) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(6) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(5) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(4) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(3) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr(0).err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_repack_snk_in_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(7) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(6) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(5) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(4) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(3) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr(0).err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_snk_in_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(0).err {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1) {-height 15 -expand} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(1).err {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(3) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(4) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(5) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(6) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr(7) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_out_arr +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_fifo_sc_src_in_arr +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_pipeline_ready_src_out_arr +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_pipeline_ready_src_in_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_counter_count_src_out_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_counter_count_src_out_arr(0) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_counter_count_src_out_arr add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_mux_src_in.ready {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_mux_src_in.xon {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_mux_src_in add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/end_of_packet add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/end_of_packet_latched -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_demux_snk_in_arr -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_mux_src_out_arr -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/dp_mux_src_in_arr add wave -noupdate -divider {reordering fifos} add wave -noupdate -height 15 -radix unsigned /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/gen_reordering_fifos(0)/gen_fifos(0)/u_dp_fifo_sc/usedw add wave -noupdate -height 15 -radix unsigned /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_reorder/gen_reordering_fifos(0)/gen_fifos(1)/u_dp_fifo_sc/usedw @@ -191,22 +195,35 @@ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_ add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/mm_clk add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_rst add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_clk +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/snk_out add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/snk_in -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_in add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/hdr_fields_in_arr add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_backplane add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_chip -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/mms_diag_block_gen_src_out_arr +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_band +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_channel +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_cb +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_sequence_number +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_local_channel +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_udp_dst_prt +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_cb_offset +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/id_channel_offset add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/arts_unb1_sc4_output_i_framer_src_out +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in.err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_in +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_snk_out add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_src_out +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_src_in.ready {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_src_in.xon {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_xonoff_src_in +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_demux_inverted_src_out_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_demux_inverted_src_in_arr(0) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_demux_inverted_src_in_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_demux_inverted_src_in_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_demux_inverted_src_in_arr(3) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_demux_inverted_src_in_arr(4) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_demux_inverted_src_in_arr +add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_field_blk_src_out_arr +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_field_blk_src_in_arr(4) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_field_blk_src_in_arr(3) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_field_blk_src_in_arr(2) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_field_blk_src_in_arr(1) {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_field_blk_src_in_arr(0) {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_field_blk_src_in_arr add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_fifo_fill_sc_src_out add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_fifo_fill_sc_src_in -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_offload_tx_src_out -add wave -noupdate -height 15 /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/dp_offload_tx_src_in +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.sync {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.bsn {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.data {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.re {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.im {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.valid {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.sop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.eop {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.empty {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.channel {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out.err {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_out +add wave -noupdate -height 15 -expand -subitemconfig {/tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_in.ready {-height 15} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_in.xon {-height 15}} /tb_arts_unb1_sc4_output/u_arts_unb1_sc4_output/u_arts_unb1_sc4_output_tab/u_arts_unb1_sc4_output_tab_i_packetizer/src_in TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {2896667500000 fs} 0} +WaveRestoreCursors {{Cursor 1} {2866022500000 fs} 0} configure wave -namecolwidth 367 configure wave -valuecolwidth 170 configure wave -justifyvalue left @@ -221,4 +238,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits fs update -WaveRestoreZoom {2701945 ns} {3030070 ns} +WaveRestoreZoom {2767585 ns} {2964460 ns} diff --git a/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4_output.vhd b/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4_output.vhd index 4d2c55140dc3059cd689a821ae657995edd003c5..0a92ee564573308e4060915fa3c127359c9710fb 100644 --- a/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4_output.vhd +++ b/applications/arts/designs/arts_unb1_sc4/tb/vhdl/tb_arts_unb1_sc4_output.vhd @@ -52,7 +52,7 @@ ARCHITECTURE tb OF tb_arts_unb1_sc4_output IS -- Clocks & reset, general setup ---------------------------------------------------------------------------- CONSTANT c_sim : BOOLEAN := TRUE; - CONSTANT c_nof_tabs : NATURAL := 1; + CONSTANT c_nof_tabs : NATURAL := 2; CONSTANT c_nof_compound_beams : NATURAL := 1; CONSTANT c_nof_bytes_per_iquv_packet : NATURAL := 8500; CONSTANT c_nof_bytes_per_i_packet : NATURAL := 6250; @@ -170,7 +170,7 @@ BEGIN reg_dp_xonoff_iab_i_mosi.wr <= '0'; END PROCESS; - arts_unb1_sc4_output_tab_snk_in_arr(0) <= arts_unb1_sc4_output_iab_snk_in; + arts_unb1_sc4_output_tab_snk_in_arr <= (others => arts_unb1_sc4_output_iab_snk_in); ------------------------------------------------------------------------------ -- The DUT - ARTS SC4 output module