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Commit ca7a51d1 authored by Eric Kooistra's avatar Eric Kooistra
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Added Arria10 DDIO IP from ip_arria10_ddio library to tech_iobuf.

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hdl_lib_name = tech_iobuf hdl_lib_name = tech_iobuf
hdl_library_clause_name = tech_iobuf_lib hdl_library_clause_name = tech_iobuf_lib
hdl_lib_uses = technology ip_stratixiv hdl_lib_uses = technology ip_stratixiv ip_arria10_ddio
hdl_lib_technology = hdl_lib_technology =
build_dir_sim = $HDL_BUILD_DIR build_dir_sim = $HDL_BUILD_DIR
......
...@@ -60,4 +60,37 @@ PACKAGE tech_iobuf_component_pkg IS ...@@ -60,4 +60,37 @@ PACKAGE tech_iobuf_component_pkg IS
); );
END COMPONENT; END COMPONENT;
-----------------------------------------------------------------------------
-- ip_arria10
-----------------------------------------------------------------------------
COMPONENT ip_arria10_ddio_in IS
GENERIC (
g_width : NATURAL := 1
);
PORT (
in_dat : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
in_clk : IN STD_LOGIC;
in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
rst : IN STD_LOGIC := '0';
out_dat_hi : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
out_dat_lo : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
END COMPONENT;
COMPONENT ip_arria10_ddio_out IS
GENERIC(
g_width : NATURAL := 1
);
PORT (
rst : IN STD_LOGIC := '0';
in_clk : IN STD_LOGIC;
in_clk_en : IN STD_LOGIC := '1'; -- Not Connected
in_dat_hi : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
in_dat_lo : IN STD_LOGIC_VECTOR(g_width-1 DOWNTO 0);
out_dat : OUT STD_LOGIC_VECTOR(g_width-1 DOWNTO 0)
);
END COMPONENT;
END tech_iobuf_component_pkg; END tech_iobuf_component_pkg;
...@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL; ...@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib; LIBRARY ip_stratixiv_lib;
LIBRARY ip_arria10_ddio_lib;
ENTITY tech_iobuf_ddio_in IS ENTITY tech_iobuf_ddio_in IS
GENERIC ( GENERIC (
...@@ -54,4 +55,10 @@ BEGIN ...@@ -54,4 +55,10 @@ BEGIN
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo); PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
END GENERATE; END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_ddio_in
GENERIC MAP (g_width)
PORT MAP (in_dat, in_clk, in_clk_en, rst, out_dat_hi, out_dat_lo);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
\ No newline at end of file
...@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL; ...@@ -27,6 +27,7 @@ USE technology_lib.technology_select_pkg.ALL;
-- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis. -- Declare IP libraries to ensure default binding in simulation. The IP library clause is ignored by synthesis.
LIBRARY ip_stratixiv_lib; LIBRARY ip_stratixiv_lib;
LIBRARY ip_arria10_ddio_lib;
ENTITY tech_iobuf_ddio_out IS ENTITY tech_iobuf_ddio_out IS
GENERIC ( GENERIC (
...@@ -53,5 +54,11 @@ BEGIN ...@@ -53,5 +54,11 @@ BEGIN
GENERIC MAP ("Stratix IV", g_width) GENERIC MAP ("Stratix IV", g_width)
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat); PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
END GENERATE; END GENERATE;
gen_ip_arria10 : IF g_technology=c_tech_arria10 GENERATE
u0 : ip_arria10_ddio_out
GENERIC MAP (g_width)
PORT MAP (rst, in_clk, in_clk_en, in_dat_hi, in_dat_lo, out_dat);
END GENERATE;
END ARCHITECTURE; END ARCHITECTURE;
\ No newline at end of file
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